CN108683329B - Real-time detection system for load current - Google Patents

Real-time detection system for load current Download PDF

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Publication number
CN108683329B
CN108683329B CN201810619848.0A CN201810619848A CN108683329B CN 108683329 B CN108683329 B CN 108683329B CN 201810619848 A CN201810619848 A CN 201810619848A CN 108683329 B CN108683329 B CN 108683329B
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load current
pull
signal out
load
output
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CN108683329A (en
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李丹
潘扬
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Giantec Semiconductor Corp
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Giantec Semiconductor Corp
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

Abstract

The invention discloses a real-time detection system of load current, comprising: the device comprises a switch system with a pull-up driving stage and a pull-down driving stage with adjustable gears, a load current detection module, a processor and an analog-to-digital converter; the load current detection module is respectively connected with the output end of the switch system, the pull-up driving stage and the pull-down driving stage, and is used for detecting the load current of the switch system in real time and transmitting the load current to the analog-to-digital converter; the analog-to-digital converter is connected with the load current detection module and used for receiving the load current and converting the load current into a digital signal; the processor is connected with the analog-to-digital converter and used for receiving the digital signal of the load current output by the analog-to-digital converter, calculating the digital signal to obtain a gear adjusting signal, and receiving and executing the gear adjusting signal output by the processor by the pull-up driving stage or the pull-down driving stage. The invention dynamically adjusts the output voltage slew rate of the power tube by using the result obtained by real-time detection, thereby protecting the power tube from being punctured.

Description

Real-time detection system for load current
Technical Field
The invention relates to the field of switch systems, in particular to a load current real-time detection system suitable for monitoring output power and realizing dynamic adjustment of the output voltage slew rate of a power tube.
Background
In switching systems with high power output, such as class d power amplifiers or dc-dc voltage converters, efficiency and electromagnetic interference are two major performance indicators that need special attention. However, these two methods are contradictory.
If the edges of the output voltage of the switching system are steeper, the less energy is lost on the switches and the efficiency of the system is naturally higher.
The output of the switching system contains not only the fundamental frequency energy but also the high frequency carrier energy. High frequency signals are just the origin of the electromagnetic interference. The steeper the edges of the output signal, the greater the overshoot and the more severe the resulting electromagnetic interference.
Therefore, how to choose the optimal combination between efficiency and electromagnetic interference has always been a re-used issue in switching systems.
Another troublesome problem of switching systems is the voltage spike, i.e. the overshoot mentioned above, caused by the switching of the power switch at the source and drain terminals of the switching tube. Once the overshoot is too large and exceeds the tolerance range of the source-drain voltage of the switch tube, avalanche breakdown of the switch tube occurs to cause unrecoverable device damage. The overshoot is not fixed, but depends on many factors, such as the wire diameter and length of the connection wire during packaging, the output power, the output voltage slew rate, etc. Efficiency is often wasted if there is a large margin left in the design to avoid punch-through. But too small may increase the probability of device failure.
Electromagnetic interference is caused by electromagnetic wave radiation caused when high frequency signals are conducted through the transmission line. The larger the signal energy on the transmission line, the stronger the resulting radiation and the more severe the electromagnetic interference.
As shown in fig. 1a, a parasitic inductance Lp introduced by a chip package wire bonding, when a power tube is switched to cause a large current sudden change, a large peak voltage V is seen at two ends of the parasitic inductance Lp of a lead connecting the power tubespike：
Vspike＝L*(di/dt)
In the formula, L is the inductance value of the parasitic inductance, and di/dt is the change rate of the current on the power tube.
The longer the package wire bond, the greater the parasitic inductance value introduced. When the output stage OUT is edge-switched, the power transistor is switched between on and off, and the current change rate caused by the switching is the largest, so that the voltage difference introduced between the two ends of the parasitic inductor is also the largest. In addition, the parasitic diode Dp of the switching tube is in a forward conducting state during switching, and the parasitic diode Dp are superimposed, as shown in the left diagram of fig. 1b, a very high voltage spike is often seen at the output stage out, and thus the power tube breakdown effect is sometimes even caused by aggravated electromagnetic interference.
The magnitude of the parasitic inductance of a package line is limited by such factors as the material and the type and size of the package. This is difficult to optimize in circuit design. But the reduction of spikes and emi can be achieved by controlling the rate of change of the current. The speed of the current speed is determined by the magnitude of the load current and the driving capability of the power tube.
In many switching systems, the drive stage of the power transistor is designed to have a plurality of gear positions. If the EMI is too severe, the weaker drive at the expense of efficiency selection reduces the slew rate of the output edge, making it less steep as shown in the right diagram of FIG. 1 b. If the electromagnetic interference is still within an acceptable range, the drive range is selected to be as strong as possible to improve efficiency. However, such gear selection is often fixed and cannot be adjusted in real time.
Disclosure of Invention
The invention aims to provide a load current real-time detection system, and the output voltage slew rate of a power tube is dynamically adjusted by using the result obtained by real-time detection. The real-time slew rate adjustment can effectively restrain transient high-voltage spikes borne by the power tube during output turnover and protect the power tube from being broken down. The invention adopts a method for realizing full digital time sequence detection, can realize the purpose of automatically selecting the optimal combination by considering both important and contradictory parameter indexes of output efficiency and electromagnetic interference.
In order to achieve the above purpose, the invention is realized by the following technical scheme:
a load current real-time detection system, comprising: the device comprises a switch system with a pull-up driving stage and a pull-down driving stage with adjustable gears, a load current detection module, a processor and an analog-to-digital converter;
the load current detection module is respectively connected with the output end of the switch system, the pull-up driving stage and the pull-down driving stage, and is used for detecting the load current of the switch system in real time and transmitting the load current to the analog-to-digital converter.
The analog-to-digital converter is connected with the load current detection module and used for receiving the load current and converting the load current into a digital signal.
The processor is connected with the analog-to-digital converter and used for receiving the digital signal of the load current output by the analog-to-digital converter and calculating the digital signal to obtain a gear adjusting signal.
And the pull-up driving stage or the pull-down driving stage receives and executes the gear adjusting signal output by the processor.
The load current detection module detects load current, which refers to the load current and the direction of the load current at the moment of level inversion of a voltage signal OUT at the output end of the switch system.
When the load current flows from the load to the output terminal, the load current detection module detects a time signal OUT _ sense _ r when the output terminal voltage signal OUT is inverted from a logic low level to a high level.
When the voltage signal OUT at the output end is less than or equal to Vth,HWhen the signal OUT _ sense _ r is 1, the voltage signal OUT > Vt is outputh,HWhen the signal out _ sense _ r is 0.
When the load current flows from the output end to the load, the load current detection module detects the signal OUT _ sense _ f at the moment when the voltage signal OUT at the output end is inverted from the logic high level to the low level.
When the voltage signal OUT of the output end is more than or equal to Vth,LWhen the signal OUT _ sense _ f is 1, the output terminal voltage signal OUT < Vth,LWhen the signal out _ sense _ f is 0.
The analog-to-digital conversion module comprises: a plurality of digital logic delay units and registers connected in series; each register is connected with the load current detection module, and each register is used for receiving the signal out _ sense _ f or the signal out _ sense _ r detected by the load current detection module.
Each digital logic delay unit is used as a timing unit.
When the load current flows from the output end to the load, the signal out _ sense _ f is a clock signal common to all the registers; when the load current flows from the load to the output, the signal out _ sense _ r is a clock signal common to all registers.
When the clock signal of each register generates lower edge turnover or upper edge turnover, each register samples and stores the output level of the corresponding digital logic delay unit at the moment, each register performs logic operation on the output level to obtain corresponding digital information, each register transmits the obtained digital information to a processor, and the processor obtains a digital information group Q < m:0 >.
The processor stores a corresponding table of the gear positions of the pull-up and pull-down driving stages, the load current and the number k of 1 in the digital information group Q < m:0 >. The processor determines the number k range of 1's in the set of digital information Q < m:0> by looking up a table,
when k is less than a first preset threshold value mLAccording to the corresponding tableSelecting a gear corresponding to the current load current and sending a gear adjusting signal to a corresponding upper or lower pull-down driving stage, so that dead time is shortened;
when k is higher than a second preset threshold value mhSelecting a gear corresponding to the current load current according to the corresponding table and sending a gear adjusting signal to a corresponding upper or lower pull-down driving stage so as to prolong the dead time; when m isL<k<mhThe processor does not adjust the current up and down drive stage gear.
Compared with the prior art, the invention has the following advantages:
the invention dynamically adjusts the output voltage slew rate of the power tube by using the result obtained by real-time detection. The real-time slew rate adjustment can effectively restrain transient high-voltage spikes borne by the power tube during output turnover and protect the power tube from being broken down. The invention adopts the realization method of full digital time sequence detection, can give consideration to two very important but contradictory parameter indexes of output efficiency and electromagnetic interference, and automatically selects the optimal combination of the output efficiency and the electromagnetic interference.
Compared with the conventional current detection mode in the prior art, the method for realizing the all-digital time sequence detection has the advantages of much higher response speed and much smaller consumed current and area.
Drawings
FIG. 1a is a schematic diagram of a switching system output power transistor and associated parasitic devices in the prior art;
FIG. 1b is a schematic diagram illustrating the effect of electromagnetic interference and output efficiency on the power transistor driving stage gear adjustment in the prior art;
FIG. 2 is a schematic diagram of a load current real-time detection circuit according to the present invention;
FIG. 3 is a schematic structural diagram of a driving stage with adjustable gears of the real-time load current detection circuit according to the present invention;
FIG. 4 is a schematic diagram illustrating dead zone control of a gear-adjustable driver stage of a load current real-time detection circuit according to the present invention;
FIG. 5a is a schematic diagram illustrating a state of a load current flowing from a load to an output terminal in a real-time load current detection circuit according to the present invention;
FIG. 5b is a diagram showing the relationship between the output voltage and the pull-down switch voltage when the load current flows from the load to the output terminal in the real-time load current detection circuit of the present invention;
fig. 5c is a graph illustrating a relationship between a level inversion time and an output voltage of the detection output terminal when the load current flows from the load to the output terminal in the real-time load current detection circuit according to the present invention;
FIG. 6a is a schematic diagram illustrating a state of a load current flowing from an output terminal to a load in a real-time load current detection circuit according to the present invention;
FIG. 6b is a diagram showing the relationship between the output voltage and the pull-down switch voltage when the load current flows from the output terminal to the load in the real-time load current detection circuit of the present invention;
fig. 6c is a diagram illustrating a relationship between a level inversion time and an output voltage of a detection output terminal when a load current flows from the output terminal to a load in the real-time load current detection circuit according to the present invention;
FIG. 7 is a schematic diagram of a timing detection module in a real-time load current detection circuit according to the present invention;
fig. 8 is a schematic diagram illustrating a timing relationship between each clock signal and an output voltage of each delay unit in the load current real-time detection circuit according to the present invention.
Detailed Description
The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
As shown in fig. 2, the present invention provides a real-time load current detection circuit, which comprises: the system comprises a pull-up driving stage gh, a pull-down driving stage gl, a load current detection module, a processor and an analog-to-digital converter, wherein the gears of the pull-up driving stage gh and the pull-down driving stage gl are adjustable; the pull-up driving stage gh is respectively connected with a pull-up switch S1 in the switch system, the input end of the load current detection module and the processor, and one end of the pull-down driving stage gl is connected with a pull-down switch S2 in the circuit of the power tube, the input end of the load current detection module and the processor. The input end of the analog-to-digital converter is connected with the output end of the load current detection module, and the output end of the analog-to-digital converter is connected with the processor.
Load current detection module detects a current flowing to an output load ZLThe detected output current is converted into a digital signal through an analog-to-digital converter (ADC), and then a proper driving level gear is calculated through a processor (processor), so that the output slew rate is automatically adjusted. When the output current is detected to be lower, a stronger driving stage gear is automatically selected, because the currents on the switching tube and the transmission line T are smaller at the moment, too high voltage overshoot and electromagnetic radiation cannot be introduced even if the voltage of the output end is overturned. Therefore, it is preferable to improve the efficiency as much as possible. When the output current is detected to be high, a weaker driving level gear is automatically selected to reduce the output slew rate and output overshoot to reduce the electromagnetic radiation as priority.
When outputting the load current I as shown in connection with FIGS. 5a and 5bloadIs directed from the load ZLWhen the current flows to the output end, the load current I is in the dead time period when the pull-down switch S2 of the output stage is turned off and the pull-up switch S1 is not turned onloadThe voltage cannot suddenly change, and the voltage flows to the power supply VDD through the parasitic diode Dp1 of the pull-up tube. Therefore, the voltage signal OUT at the output end is not pulled up by the pull-up tube but depends on the load current IloadThe charging is pulled high. Load current IloadThe larger the output voltage signal OUT rises, the faster the output voltage signal OUT rises, i.e. the slew rate of the rising edge of the output voltage signal OUT depends on the load current Iload。
As shown in fig. 5c, the load current detection module detects the current, and actually detects the load current and the direction of the load current at the time when the level of the voltage signal OUT at the output terminal is inverted. The signal OUT _ sense _ r detects when the voltage signal OUT is switched from a logic high level to a logic low level in time, and the signal OUT _ sense _ f detects when the voltage signal OUT is switched from a logic low level to a high level in time. When the voltage signal OUT level at the output end is lower than Vth,HRises above Vth,HAt this time, the out _ sense _ r signal rapidly changes from 1 to 0The delay between the two signals is negligibly short, and the OUT _ sense _ f signal is changed from 0 to 1 later, but the delay between the signal completing the inversion and the inversion of the rising edge of the output terminal voltage signal OUT is longer. Vice versa, when the output terminal voltage signal OUT is higher than Vth,LBecomes lower than Vth,LOut _ sense _ f rapidly changes from 1 to 0, with negligible delay difference. And the delay between the time when OUT _ sense _ r changes from 0 to 1 and the falling edge of the output terminal voltage signal OUT is long.
When the load current IloadFrom the load ZLWhen the current flows to the output terminal, the load current detection module is configured to detect that a signal at a time when the output terminal voltage signal OUT is inverted from a logic low level to a logic high level is OUT _ sense _ r. When the voltage signal OUT at the output end is less than or equal to Vth,HWhen OUT _ sense _ r is 1, the output terminal voltage signal OUT > Vth,HWhen out _ sense _ r is 0.
When outputting the load current I as shown in FIGS. 6a and 6bloadIs flowing from the output to the load ZLDuring the dead time when the pull-up switch S1 of the output stage is turned off and the pull-down switch S2 is not turned on, the load current IloadCan not suddenly change, the current flows from the ground GND to the load Z through the parasitic diode DP2 of the pull-down tubeLTherefore, the voltage signal OUT at the output end is changed from high to low not by the pull-down tube but by the load current IloadThe pumping charge is pulled low. Load current IloadThe larger the output voltage signal OUT is, the faster the output voltage signal OUT falls, i.e. the slew rate of the falling edge of the output voltage signal OUT depends on the load current Iload。
As shown in fig. 6c, the load current detection module detects the load current and the direction of the load current at the time of level inversion of the output terminal. When the load current flows from the output terminal to the load, the load current detection module detects that the signal at the moment when the voltage signal OUT at the output terminal is inverted from the logic high level to the low level is OUT _ sense _ f. When the voltage signal OUT of the output end is more than or equal to Vth,LWhen OUT _ sense _ f is 1, the output terminal voltage signal OUT < Vth,LWhen out _ sense _ f is 0.
Load current detection module detectionTo the output load ZLThe detected output current is converted into a digital signal through an analog-to-digital converter (ADC), and then a proper driving level gear is calculated through a processor (processor), so that the output slew rate is automatically adjusted.
As shown in fig. 7, the analog-to-digital converter includes: m +1 digital logic delay units d connected in series0～dmAnd a register Q0～Qm. The load detector is coupled to each register for providing each register with its detected out _ sense _ f/r signal. Each digital logic delay cell may act as a timing cell.
According to load current IloadAnd one of the signal OUT _ sense _ f for detecting the falling edge inversion moment of the voltage signal OUT at the output end and the signal OUT _ sense _ r for detecting the rising edge inversion moment is selected as a clock common to all the registers. When the load current IloadFrom the output to the load ZLThen, the signal out _ sense _ f is selected as a clock common to all registers; when the load current IloadFrom the load ZLWhen the signal flows to the output, the signal out _ sense _ r is selected as a clock signal common to all registers.
When the clock of each register is turned over at the lower edge or turned over at the upper edge, each register samples and stores the output level of the time delay unit to obtain a digital information group Q < m:0 >.
As shown in fig. 8, when the load current IloadFrom the load ZLWhen the signal flows to the output, the signal out _ sense _ r is selected as a clock signal common to all registers. That is, the signal out _ sense _ r is selected as the effective clock edge, and the rising edge of the signal out _ sense _ r occurs at the i-1 th delay unit di-1After the rising edge of (c), the ith delay unit diBefore the rising edge. The delay time (delay time) is in the range of i x td<delay time<(i+)*tdThen Q is obtained<m:0>In the data, Q<m:i>All are 0, Q<i-1:0>All are 1.
When the number of 0 in the digital information group Q < m: i > is larger than the number of 1 in the digital information group Q < i-1:0>, the processor outputs a gear degradation adjusting signal to the pull-up driving stage;
the pull-up driving stage performs an operation of reducing the first gear based on the current gear according to the signal.
When the number of 0 in the digital information group Q < m: i > is less than the number of 1 in the digital information group Q < i-1:0>, the processor outputs a gear upgrading adjustment signal to the pull-up driving stage; the pull-up driving stage performs an operation of increasing the first gear based on the current gear according to the signal.
The analog-to-digital converter transmits the digital information group Q < m:0> to the processor. In this embodiment, the operation of the processor is as follows:
during the circuit design process, different load currents I can be obtained through simulationloadDesired digital information group Q under the condition of direction<m:0>Number (k) range (m) of 1L<k<mh) And k is in a set range, which indicates that the edge turning time of the voltage signal OUT at the output end is more reasonable. If the gear is not in the set range, the gear of the driving stage needs to be readjusted.
When the circuit is actually working, the load current IloadThe larger the edge transition speed of the output voltage signal OUT, the earlier the register sampling clock OUT _ sense _ f/r transitions.
When the load current IloadDirection from load ZLDigital information group Q obtained when flowing to the output<m:0>The number of 1 s in (1) is small and the number of 0 s is large. When the processor finds Q in the table look-up mode<m:0>The number k of the line 1 is less than a first preset threshold value mLAnd reducing the number of circuit delay units for controlling the dead time on the basis of the current dead time delay circuit, so that the dead time is shortened a little. Therefore, the purposes of reducing the turning speed of the OUT section and optimizing electromagnetic interference (EMI) by overshoot are achieved.
Conversely, when the processor finds Q by looking up the table<m:0>The number k of the Lily 1 is higher than a second preset threshold value mhDescription output terminalThe slew rate of the voltage signal OUT is too low, and at the moment, the number of the delay units can be increased on the basis of the current dead zone delay circuit, so that the purpose of increasing dead zone time and improving the OUT slew rate optimization efficiency is achieved.
In addition, the current I of different gears at different loads can be obtained through simulationloadQ in case of<m:0>And 1, a corresponding table of the number k of the cells. The processor stores the information of this table. In actual operation, the processor obtains Q according to the current gear information<m:0>The current load current I can be calculated by a table look-up modeloadAutomatically selecting and loading current IloadAnd selecting the corresponding drive stage gear, namely selecting the size of the corresponding drive stage device.
When the load current direction is from the load to the output end and the gear of the drive stage needs to be adjusted, the processor outputs an adjustment gear signal to the pull-up drive stage, and the pull-up drive stage executes the adjustment;
when the load current direction is from the ground to the load and the gear of the drive stage needs to be adjusted, the processor outputs an adjustment gear signal to the pull-down drive stage, and the pull-down drive stage executes the adjustment.
Through the self-adaptive dynamic slew rate adjustment, the voltage turnover speed of the OUT end can be maintained in an ideal state, and the influence of load current change on the voltage turnover speed can be effectively reduced.
As shown in fig. 3, the pull-up driving stage gh and the pull-down driving stage gl respectively include n driving steps, and the sources of the MOS transistors Q10 to Qn0 and the pull-up transistor Q1 in the n steps of the pull-up driving stage gh are connected to the power supply VDD. The drains of the MOS transistors Q10-Qn 0 are correspondingly connected with the sources of the MOS transistors Q11-Qn 1 in the n levels of the pull-up driving level gh.
The sources of the MOS transistors Q13-Qn 3 and the pull-down transistor Q2 in the n levels of the pull-down driving stage gl are connected to the ground GND. The drains of the MOS transistors Q11-Qn 1 are correspondingly connected with the drains of the MOS transistors Q12-Qn 2 in the n steps of the pull-down driving stage gl respectively. The gates of the MOS transistors Q11-Qn 1 and the gates of the MOS transistors Q12-Qn 2 are connected with the gates of the pull-up transistor Q1 and the pull-down transistor Q2. The drain electrode of the pull-up tube Q1 and the drain electrode of the pull-down tube Q2 are connected as an output end.
Selecting a higher drive range means that the pull-up tube Q1 and pull-down tube Q2 inside the drive stage will be larger in size and the output pull-up/pull-down capability of the drive stage will be stronger.
As shown in fig. 4, the faster the on and off speed of the switch controlled by the output of the driving stage, the higher the output slew rate of the switch control.
In addition to the pull-up/pull-down tube size of the driver stage, the step adjustment of the dead time of the pull-up and pull-down driver stage gh, gl outputs in fig. 4 can also affect the slew rate of the output. When neither the pull-up switch S1 nor the pull-down switch S2 of the switching system is open (i.e., dead band), the load current IloadEither to the power supply or from the ground through the parasitic diode of the switch. In this process, the voltage drop of the parasitic diode and the parasitic inductance of the wire bonding both contribute to overshoot at the output terminal, which affects the EMI performance.
However, if enough dead time is not reserved when the pull-up switch and the pull-down switch are switched, an instant short circuit from a power supply to the ground may be caused, the efficiency of the system is affected, and even a switch tube may be burned out.
The dead band control architecture with adjustable gears is shown in fig. 4. Whether the pull-up switch and the pull-down switch are turned off or not is judged through the output level of the driving stage. The pull-down switch S2 is allowed to open when the pull-up switch S1 is closed. And vice versa. The dead time is controlled by the delay unit described above between the decision to switch off and the permission to switch on. When the load current IloadIn the weaker, a longer dead time may be selected. Because even though the pull-up and pull-down tubes Q1 and Q2 are both off at this time, the load current I is weakerloadToo high overshoot at the output end cannot be caused, and the energy on the transmission line is not large, so that the influence on EMI is not large, and the efficiency is considered preferentially. When the load current IloadWhen stronger, a shorter dead time may be selected to reduce overshoot optimization EMI. At this time, even if the pull-up and pull-down tubes Q1, Q2 are instantaneously and simultaneously conducted, the current is used as the load current I by the output endloadAnd the pumping-out can not cause the short-circuit large current from the power supply to the ground.
In summary, the method for dynamically adjusting the output slew rate by monitoring the output power through time sequence detection can achieve the purpose of multi-gear automatic adjustment with very low cost, and obtain the optimal combination in the game of system efficiency and electromagnetic radiation.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims (5)

1. A system for real-time detection of load current, comprising: the device comprises a switch system with a pull-up driving stage and a pull-down driving stage with adjustable gears, a load current detection module, a processor and an analog-to-digital converter;
the load current detection module is respectively connected with the output end of the switch system, the pull-up driving stage and the pull-down driving stage, and is used for detecting the load current of the switch system in real time and transmitting the load current to the analog-to-digital converter;
the analog-to-digital converter is connected with the load current detection module and used for receiving the load current and converting the load current into a digital signal;
the processor is connected with the analog-to-digital converter and used for receiving the digital signal of the load current output by the analog-to-digital converter and calculating the digital signal to obtain a gear adjusting signal,
the pull-up driving stage or the pull-down driving stage receives and executes the gear adjusting signal output by the processor;
the load current detection module detects load current, which refers to the load current and the direction of the load current at the level overturning moment of a voltage signal OUT at the output end of the switch system;
when a load current flows from a load to an output end, the load current detection module detects a moment signal OUT _ sense _ r when the voltage signal OUT at the output end is inverted from a logic low level to a high level;
when the voltage signal OUT at the output end is less than or equal to Vth,HWhen the signal OUT _ sense _ r =1, when the output terminal voltage signal OUT > Vth,HWhen, signal out _ sense _ r = 0;
when a load current flows from the output end to the load, the load current detection module detects a signal OUT _ sense _ f at the moment when the voltage signal OUT at the output end is inverted from a logic high level to a low level;
when the voltage signal OUT of the output end is more than or equal to Vth,LWhen the signal OUT _ sense _ f =1, the voltage signal OUT < V at the output terminalth,LWhen, signal out _ sense _ f = 0.
2. The real-time load current detection system according to claim 1, wherein the analog-to-digital conversion module comprises: a plurality of digital logic delay units and registers connected in series; each register is connected with the load current detection module, and each register is used for receiving the signal out _ sense _ f or the signal out _ sense _ r detected by the load current detection module.
3. The real-time load current detection system according to claim 2,
each digital logic delay unit is used as a timing unit.
4. The real-time load current detection system according to claim 2,
when the load current flows from the output end to the load, the signal out _ sense _ f is a clock signal common to all the registers; when the load current flows from the load to the output end, the signal out _ sense _ r is a clock signal common to all the registers;
when the clock signal of each register generates lower edge turnover or upper edge turnover, each register samples and stores the output level of the corresponding digital logic delay unit at the moment, each register performs logic operation on the output level to obtain corresponding digital information, each register transmits the obtained digital information to a processor, and the processor obtains a digital information group Q < m:0 >.
5. The real-time load current detection system according to claim 4,
the processor stores a corresponding table of the gear positions of the pull-up driving stage and the pull-down driving stage, the load current and the number k of 1 in the digital information group Q < m:0 >;
the processor determines the number k range of 1's in the set of digital information Q < m:0> by looking up a table,
when k is less than a first preset threshold value mLSelecting a gear corresponding to the current load current according to the corresponding table and sending a gear adjusting signal to a corresponding upper or lower pull-down driving stage, so that the dead time is shortened;
when k is higher than a second preset threshold value mhSelecting a gear corresponding to the current load current according to the corresponding table and sending a gear adjusting signal to a corresponding upper or lower pull-down driving stage so as to prolong the dead time;
when m isL<k<mhThe processor does not adjust the current up and down drive stage gear.
CN201810619848.0A 2018-06-14 2018-06-14 Real-time detection system for load current Active CN108683329B (en)

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