CN107656123B - Buck load current detection circuit with compensation circuit and method - Google Patents
Buck load current detection circuit with compensation circuit and method Download PDFInfo
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- CN107656123B CN107656123B CN201710271314.9A CN201710271314A CN107656123B CN 107656123 B CN107656123 B CN 107656123B CN 201710271314 A CN201710271314 A CN 201710271314A CN 107656123 B CN107656123 B CN 107656123B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The Buck converter load current detection circuit with the compensation circuit comprises an image current sampling tube, a fourth MOS tube, a primary operational amplifier, a Buck converter output power tube, a sample hold circuit, a compensation circuit and an internal current sampling resistor. The sampling hold circuit samples and holds the current when the Buck converter output power tube is conducted, and when the Buck converter output power tube is closed, the sampling hold voltage obtained by the sampling hold circuit and the compensation circuit are utilized to simulate the load current when the shunt tube Q2 is conducted. The current sampling tube Q3 has current flowing through Rs in the whole period, the voltage Vsa of the current sampling tube Q is proportional to the load current, and the current is fed back to the control end after low-pass filtering, so that the load current detection of an external sampling resistor is not needed outside the chip, and the pins of the chip and peripheral circuits applied by the chip are reduced; the energy loss caused by the external sampling resistor is reduced, and the conversion efficiency is improved.
Description
Technical Field
The invention relates to a direct current electric energy conversion circuit or a control device; in particular, to a Buck-conversion dc power conversion circuit, and more particularly, to a Buck-conversion dc power conversion device and method with load current detection.
Background
In a switching power supply circuit, i.e. SWITCHING REGULATOR, used in a DC-to-DC power conversion circuit or a control device in the prior art, a Buck converter is an important type of DC/DC (direct current to direct current) converter, and is mainly suitable for situations that an input voltage is higher than an output voltage, in order to realize constant current output of the Buck converter under different load conditions, load current needs to be detected, that is, the load current of the Buck converter needs to be detected accurately, and is fed back to a control end of the Buck converter to control the Buck converter so as to maintain constant current output of the Buck converter.
The Buck load current detection circuit commonly used in the existing power supply chip is usually to connect a small off-chip sampling resistor in series between the inductor and the output signal for detection. Fig. 1 is a block diagram of a circuit structure for realizing Buck load current detection in the prior art. In fig. 1, an external current detecting resistor Rsen and an external inductor are connected in series, the current of the inductor flows through the external current detecting resistor Rsen to generate a voltage drop, the voltage at two ends of the current detecting resistor Rsen is fed back to an operational amplifier in a chip through two pins, namely a terminal RN and a terminal RP, and the chip calculates real-time inductor current according to the resistance value of the current detecting resistor Rsen and the voltage at two ends, wherein the average current of the inductor current is the load current.
In the existing Buck load current detection circuit chip design, two pins are reserved for the current detection resistor by the circuit chip, so that the complexity of the chip is increased, and the integration level of the chip is reduced and the cost is increased; in the application requiring load current detection, not only the power consumption is increased due to the external resistor, but also the system cost for applying the DCDC chip is increased due to high requirements on the precision of the external resistor.
Noun interpretation:
DCDC is an abbreviation of english Direct current Direct current, and chinese means that dc voltage is converted into dc voltage;
buck Buck converter means in this application a Buck DC/DC conversion circuit employing the Buck converter mode, i.e. the Buck converter is also referred to as a Buck converter;
CC is herein defined as constant current, i.e. constant current
NMOS is an abbreviation of Negative channel-Metal-Oxide-Semiconductor, i.e., N-type Metal Oxide Semiconductor;
PMOS is an abbreviation for Positive channel-Metal-Oxide-Semiconductor, i.e., P-type Metal Oxide Semiconductor;
PWM is an abbreviation for english Pulse Width Modulation, chinese meaning pulse width modulation; the Pulse Width Modulation (PWM) switch type voltage stabilizing circuit achieves the purpose of stabilizing output voltage by adjusting the duty ratio of the PWM switch type voltage stabilizing circuit under the condition that the output frequency of the control circuit is unchanged.
Disclosure of Invention
The invention aims to solve the technical problems of avoiding the defects of the prior art and providing a Buck converter load current detection circuit and a Buck converter load current detection method provided with a compensation circuit, which realize high-precision load current detection without an external sampling resistor in a Buck Buck conversion circuit needing constant current control, reduce chip pins and save energy consumption and cost caused by external resistors in chip application. The technical scheme adopted for solving the technical problems is that the Buck converter load current detection circuit with the compensation circuit comprises an image current sampling tube and a fourth MOS tube, a primary operational amplifier, a sampling and holding circuit, a compensation circuit and an internal current sampling resistor, wherein the image current sampling tube and the fourth MOS tube are used for current image of an output power tube of the Buck converter, the primary operational amplifier is used for amplifying current signals, the sampling and holding circuit is used for sampling and holding peak voltage on a holding capacitor at the closing moment of the output power tube of the Buck converter, the compensation circuit is used for outputting compensation current in the conduction period of the freewheel tube of the Buck converter, and the internal current sampling resistor is used for converting sampled and amplified load current signals into voltage signals; the circuit function of the compensation circuit is equivalent to a compensation current source; the input terminal of the sampling hold circuit is electrically connected with the source electrode of the output power tube of the Buck converter and the source electrode of the freewheel tube of the Buck converter at the same time; meanwhile, the input terminal of the sample hold circuit is also used for electrically connecting the Buck converter load current detection circuit with an external inductor and is used for sampling and obtaining the current of the external inductor, namely, the input terminal of the sample hold circuit is used as the input terminal of the Buck converter load current detection circuit; the output terminal of the sampling hold circuit is electrically connected with the negative electrode of the compensation current source and the positive electrode input terminal of the primary operational amplifier at the same time; the positive electrode of the compensation current source is electrically connected with an external input voltage source; the source electrode of the mirror current sampling tube is electrically connected with an external input voltage source, the grid electrode of the mirror current sampling tube is grounded, and the drain electrode of the mirror current sampling tube is electrically connected with the negative input terminal of the primary operational amplifier; the drain electrode of the mirror current sampling tube is also electrically connected with the drain electrode of the fourth MOS tube, namely the drain electrode of the fourth MOS tube is also electrically connected with the negative electrode input terminal of the primary operational amplifier; the grid electrode of the fourth MOS tube is electrically connected with the output terminal of the primary operational amplifier, and the source electrode of the fourth MOS tube is electrically connected with the voltage output terminal of the internal current sampling resistor, namely, the source electrode of the fourth MOS tube is used as the output terminal of the Buck converter load current detection circuit.
The sample-hold circuit comprises a first switch and a sample-hold capacitor, wherein the first switch receives a non-signal of a first control signalIs controlled by (a); the first control signal is a switch control signal which is generated in the Buck converter and used for an output power tube of the Buck converter; one end of the first switch is used as an input terminal of the sample hold circuit and is electrically connected with one end of an external inductor to obtain external load current; the other end of the first switch is used as an output terminal of the sample hold circuit and is used for being electrically connected with the positive plate of the sample hold capacitor and the negative electrode of the compensation current source; and the negative plate of the sampling holding capacitor is grounded.
The compensation circuit comprises an eleventh resistor, a twelfth resistor, a thirteenth resistor, a compensation amplifier, a fifth MOS tube and a sixth MOS tube; one end of the twelfth resistor is electrically connected with an external input voltage source and used as a positive electrode input terminal of an equivalent compensation current source; the other end of the twelfth resistor is electrically connected with the positive electrode input terminal of the compensation amplifier; one end of the thirteenth resistor is electrically connected with the positive electrode input end of the compensation amplifier; the other end of the thirteenth resistor is grounded; one end of the eleventh resistor is electrically connected with the negative electrode input end of the compensation amplifier; the other end of the eleventh resistor is grounded; the output end of the compensation amplifier is electrically connected with the gates of the fifth MOS tube and the sixth MOS tube; the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are electrically connected with an external input voltage source; the source electrode of the fifth MOS tube is electrically connected with the non-grounding end of the eleventh resistor, and the source electrode of the sixth MOS tube is used as a negative electrode output terminal of the equivalent compensation current source.
The primary operational amplifier comprises a low-error operational amplifier, a chopper-type operational amplifier and an auto-zeroing operational amplifier.
The Buck converter load current detection circuit with the compensation circuit further comprises a low-pass filter for low-pass filtering of the voltage signal output by the internal current sampling resistor; the low-pass filter comprises a low-pass filter resistor and a low-pass filter capacitor, and one end of the low-pass filter resistor is used as an input terminal of the low-pass filter and is electrically connected with a voltage output terminal of the internal current sampling resistor; the other end of the low-pass filter resistor is used as an output terminal of the low-pass filter and is electrically connected with one end of the low-pass filter capacitor, and the other end of the low-pass filter capacitor is grounded; the output terminal of the low-pass filter is used as the output terminal of the Buck converter load current detection circuit, i.e. the output signal of the low-pass filter is used as the load current sampling signal of the Buck converter.
The Buck converter load current detection circuit with the compensation circuit further comprises a reference voltage generation circuit; the reference voltage generating circuit comprises a current source and a reference voltage circuit resistor; the positive electrode of the current source is electrically connected with an external input voltage source, and the negative electrode of the current source is used as an output terminal of the reference voltage generating circuit; the negative electrode of the current source is also electrically connected with one end of the reference voltage circuit resistor, and the other end of the reference voltage circuit resistor is grounded.
The Buck converter load current detection circuit with the compensation circuit further comprises an error amplifier for comparing the detected voltage signal representing the load current with a reference voltage, and the negative input terminal of the error amplifier is electrically connected with the output terminal of the reference voltage generation circuit; the positive input terminal of the error amplifier is electrically connected to the output terminal of the low pass filter.
The technical scheme adopted for solving the technical problems can also be a Buck load current detection method of a Buck converter load current detection circuit with a compensation circuit, which comprises the following steps of 1: the mirror image current sampling tube and the Buck converter output power tube form a mirror image pair tube, and when the Buck converter output power tube is conducted and the Buck converter freewheel tube is closed, the mirror image current sampling tube acquires and obtains the conducting current of the first Buck converter output power tube, namely load current; the sampling and holding circuit samples the mirror image current sampling tube; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube is conducted and the Buck converter freewheel tube is in a closed state; step 2: when the Buck converter output power tube is switched from a conducting state to a closing state, the sampling hold circuit keeps the voltage at the current moment, and the Buck converter output power tube is closed through the sampling hold circuit and the compensation circuit, and the follow current, namely the load current, when the Buck converter follow current tube is conducted; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube is closed and the Buck converter freewheel tube is in a conducting state.
The technical scheme adopted for solving the technical problems can be that the Buck load current detection method of the Buck converter load current detection circuit with the compensation circuit comprises the following steps: step 1: the mirror image current sampling tube and the Buck converter output power tube form a mirror image pair tube, and when the Buck converter output power tube is conducted and the Buck converter freewheel tube is closed, the mirror image current sampling tube acquires and obtains the conducting current of the first Buck converter output power tube, namely load current; the sampling and holding circuit samples the mirror image current sampling tube; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube is conducted and the Buck converter freewheel tube is in a closed state; step 2: when the Buck converter output power tube is switched from a conducting state to a closing state, the sampling hold circuit keeps the voltage at the current moment, and the Buck converter output power tube is closed through the sampling hold circuit and the compensation circuit, and the follow current, namely the load current, when the Buck converter follow current tube is conducted; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube is closed and the Buck converter freewheel tube is in a conducting state; step 3 is included after both steps 1 and 2: the step of low-pass filtering is further arranged on the output signal of the Buck converter load current detection circuit in the steps 1 and 2, namely the low-pass filtering is further performed on the voltage signal of the reactive load current output by the internal current sampling resistor by adopting a low-pass filter, and the low-pass filtered signal is used as the output signal of the Buck converter load current detection circuit.
Compared with the prior art, the invention has the beneficial effects that: 1. in the chip applying the design circuit scheme of the invention, the load current detection can be realized without connecting a sampling resistor again; 2. chip pins are saved, so that load current detection can be realized in chip application with small space and few pins, and Buck constant current control is realized; 3. the sampling resistor is not required to be externally connected again, so that the power consumption and the cost caused by an external resistor when the chip is applied are also saved; 4. through the combination of the sample hold circuit and the compensation circuit at the front end of current sampling, a buck freewheeling tube detection circuit is omitted, more accurate actual load current can be better obtained, higher sensitivity and higher precision are achieved, the load current detection precision is improved, and the circuits in the chip are simplified.
Drawings
FIG. 1 is a circuit schematic of a prior art load current detection implementation of a Buck converter circuit;
FIG. 2 is a block diagram of the circuit configuration of a Buck converter applied to one of the preferred embodiments of the present invention;
FIG. 3 is a schematic circuit diagram of one of the preferred embodiments of the present invention;
FIG. 4 is a waveform timing diagram of one of the preferred embodiments of the present invention;
fig. 5 is an electrical schematic diagram of the compensation circuit 34 in a preferred embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the drawings.
As shown in FIG. 2, one of the circuit blocks of the battery charging application of the Buck converter according to the preferred embodiment of the present invention is a circuit block diagram of the Buck converter, which includes a circuit block diagram for detecting and obtaining a voltage feedback signalIs used for detecting and obtaining the current feedback signal +.>Feedback current detection module 130 of (1) for detecting and obtaining an input voltage feedback signal +.>Input voltage detection module 150 of (c) for detecting the obtained temperature feedback signal +.>Temperature detection module 160 of (1) for calculating various feedback signals and outputting feedback control signalsIs used for feedback control signal +.>The integrated amplification module 300 for amplification and the PWM switch control power output module 900 for output power control of the hybrid direct current power conversion device; the voltage feedback signal +.>And a current feedback signal of said feedback current detection module 130 +.>To the feedback control module 200; the feedback control module 200 calculates a voltage feedback signal +.>Deviation from the set voltage feedback signal threshold forms a first voltage difference signal, calculating the current feedback signal +.>Forming a second current difference signal from the deviation of the set current feedback signal threshold; the feedback control module 200 is configured to control the voltage from the first voltageThe larger one of the difference signal and the second current difference signal is selected as feedback control signal +.>And feedback control signal +.>Amplified to control signal +.>And transmits a control signal +>And the PWM switch control power output module is used for adjusting the output power of the hybrid direct-current electric energy conversion device, so that the Buck type conversion device keeps constant current output in a constant current charging stage, and the current can be automatically reduced in the constant voltage charging stage.
The purpose of the present invention is to design a Buck converter load current detection circuit with a compensation circuit, so that the feedback current detection module 130 can be more optimized and used conveniently.
Referring to fig. 3, a schematic circuit diagram of one of the preferred embodiments of the present invention is shown, in which a specific embodiment of a Buck converter load current detection circuit shown in the figure includes a mirror current sampling tube Q3 and a fourth MOS tube for current mirror of a Buck converter output power tube Q1, a primary operational amplifier 35 for amplifying a current signal, a sample-and-hold circuit 33 for sampling and holding a peak voltage on a sample-and-hold capacitor C1 at a closing time of the Buck converter output power tube Q1, a compensation circuit 34 for outputting a compensation current during an on period of the Buck converter freewheeling tube Q2, and an internal current sampling resistor Rs for converting the sampled and amplified load current signal into a voltage signal; the circuit function of the compensation circuit 34 is equivalent to a compensation current source L1; the input terminal of the sample hold circuit 33 is electrically connected with the source electrode of the Buck converter output power tube Q1 and the source electrode of the Buck converter freewheel tube Q2 at the same time; while the input terminal of the sample-and-hold circuit 33 is also used for the Buck converter negativeThe current-carrying detection circuit is electrically connected with the external inductor and is used for sampling and obtaining the current of the external inductor, namely, the input terminal of the sample-and-hold circuit 33 is used as the input terminal of the Buck converter load current detection circuit; an output terminal of the sample-and-hold circuit 33 is electrically connected to both the negative electrode of the compensation current source L1 and the positive input terminal of the primary operational amplifier 35; the positive electrode of the compensation current source L1 is electrically connected with an external input voltage source VIN; the source electrode of the mirror current sampling tube Q3 is electrically connected with an external input voltage source VIN, the grid electrode of the mirror current sampling tube Q3 is grounded, and the drain electrode of the mirror current sampling tube Q3 is electrically connected with the negative input terminal of the primary operational amplifier 35; the drain electrode of the mirror current sampling tube Q3 is further electrically connected to the drain electrode of the fourth MOS tube Q4, that is, the drain electrode of the fourth MOS tube Q4 is also electrically connected to the negative input terminal of the primary operational amplifier 35; the gate of the fourth MOS transistor Q4 is electrically connected to the output terminal of the primary operational amplifier 35, and the source of the fourth MOS transistor Q4 is electrically connected to the voltage output terminal of the internal current sampling resistor Rs, that is, the source of the fourth MOS transistor Q4 is used as the output terminal of the Buck converter load current detection circuit. Wherein the Buck converter follow-up tube Q2 receives the second control signalIs controlled by the control system. The fourth MOS transistor Q4 has an effect of making the potential difference between the drain and the source of the mirror current sampling transistor Q3 more approximate to the potential difference between the drain and the source of the Buck converter output power transistor Q1, thereby improving the detection accuracy of the load current. The mirror current sampling tube Q3 and the fourth MOS tube Q4 are PMOS tubes, and the Buck converter freewheel tube Q2 is an NMOS tube, although the disclosure of the present invention is not limited to the specific types of these tubes, and any tube or circuit that can implement the corresponding switch and function may be used.
When the first control signalWhen the output power tube Q1 of the Buck converter is opened for low level, the mirror image current sampling tube Q3 is the mirror image tube of the output power tube Q1 of the Buck converter, and the mirror image current sampling tube Q3 is currentThe size of the resistor is 1/K of the current of the output power tube Q1 of the Buck converter, and K is the size proportion of the on-resistance of the output power tube Q1 of the Buck converter and the on-resistance of the mirror current sampling tube Q3; meanwhile, the sample-hold circuit is turned on, and the ground potential of the positive input terminal of the primary operational amplifier 35, i.e., the VSH node, becomes lower as the current of the Buck converter output power transistor Q1 increases. When the first control signal phi 1 changes from low level to high level, the switch K1 is turned off after the second control signal phi 2 changes to high level, the charge stored on the sample-and-hold capacitor C1 is slowly charged by the compensation current source L1, and the process of reducing the inductance current is simulated. The voltage Vsa across the internal sense resistor Rs is proportional to the average value of the inductor current, vsa and Vref generated by the reference current source are controlled by the output current of the error amplifier to ufb_i. UFB_I is input into a loop to control the pulse width of PWM, so that the constant output current of the BUCK-type voltage converter is realized, and the circuit is particularly suitable for a circuit of a battery charging management chip.
In the preferred embodiment shown in fig. 3, the sample-and-hold circuit 33 includes a first switch K1 and a sample-and-hold capacitor C1, the first switch K1 receiving a first control signalIs not signal->Is controlled by (a); said first control signal->The switching control signal is generated in a Buck converter load current detection circuit and used for a Buck converter output power tube Q1; one end of the first switch K1 is used as an input terminal of the sample-hold circuit 33, and is used for being electrically connected with a source electrode of the Buck converter output power tube Q1 and a source electrode of the Buck converter freewheel tube Q2, and the other end of the first switch K1 is also used as an input terminal of the sample-hold circuit 33, and is used for being electrically connected with one end of an external inductor to obtain an external load current; the other end of the first switch K1 is used as an output terminal of the sample-and-hold circuit 33 for the same as the samplingThe positive plate of the sample holding capacitor C1 is electrically connected with the negative electrode of the compensation current source L1; and the negative plate of the sample-hold capacitor C1 is grounded.
In the preferred embodiment shown in fig. 3, the primary operational amplifier 35 comprises a low error operational amplifier, a chopper type operational amplifier, and an auto-zeroed operational amplifier. The low error op-amp, low offset operation amplifier, may be a chopper op-amp, chopping operation amplifier, or Auto-zeroed op-amp, auto-Zeroing operation amplifier. Whatever the operational amplifier implementation and its equivalent transformation form, it is within the scope of protection of this patent.
In the preferred embodiment shown in fig. 3, a low pass filter 32 is also included for low pass filtering the voltage signal output by the internal current sampling resistor Rs; the low-pass filter 32 includes a low-pass filter resistor Rf and a low-pass filter capacitor Cf, one end of the low-pass filter resistor Rf serving as an input terminal of the low-pass filter 32 being electrically connected to a voltage output terminal of the internal current sampling resistor Rs; the other end of the low-pass filter resistor Rf is used as an output terminal of the low-pass filter 32 and is electrically connected to one end of the low-pass filter capacitor Cf, and the other end of the low-pass filter capacitor Cf is grounded; the output terminal of the low pass filter 32 is used as the output terminal of the Buck converter load current detection circuit, i.e. the output signal of the low pass filter 32 is used as the load current sampling signal of the Buck converter.
In the preferred embodiment shown in fig. 3, reference voltage generation circuit 90 is also included; the reference voltage generating circuit 90 includes a current source Iref and a reference voltage circuit resistor RL; the positive electrode of the current source Iref is electrically connected to an external input voltage source VIN, and the negative electrode of the current source Iref is used as an output terminal of the reference voltage generating circuit 90; the negative electrode of the current source Iref is also electrically connected with one end of the reference voltage circuit resistor RL, and the other end of the reference voltage circuit resistor RL is grounded.
In the preferred embodiment shown in fig. 3, an error amplifier 38 is further included for comparing the detected voltage signal indicative of the magnitude of the load current with a reference voltage, a first input terminal of the error amplifier 38 being electrically connected to an output terminal of the reference voltage generating circuit 90; a second input terminal of the error amplifier 38 is electrically connected to an output terminal of the low pass filter 32.
When the first control signalFor low level, the Buck converter output power tube Q1 is turned on, the mirror current sampling tube Q3 is a mirror tube of the Buck converter output power tube Q1, and due to the virtual short characteristics of the positive input end and the negative input end of the primary operational amplifier 35, the drain voltages of the mirror current sampling tube Q3 and the Buck converter output power tube Q1 are consistent. The on-current of the mirror current sampling tube Q3 is 1/K of the on-current of the output power tube Q1 of the Buck converter, and K is the size proportion of the equivalent on-resistance of the Q1 and the Q3 or the scaling ratio of a current mirror formed by the Q3 and the Q1 tube.
When the first control signalAt low level, the Buck converter output power transistor Q1 is turned on and the first control signal +.>Is not signal->The first switch K1 is controlled to be turned on, so that the sample-and-hold circuit 33 is turned on, sample-and-hold is started, and the voltage signal Vsa at the voltage output terminal Vsa of the internal current sampling resistor Rs becomes higher as the current of the Buck converter output power transistor Q1 increases.
On-current of Buck converter output power tube Q1And the on-current of the mirror current sampling tube Q3 +.>The relation between the two is: />。
When the first control signalAt low level, the first control signal +.>Is not signal->The first switch K1 is controlled to be opened, and the sampling holding capacitor C1 is in a charging process; when the first control signal->At high level, the first control signal +.>Is not signal->The moment when the first switch K1 is controlled to be turned off, the voltage value stored by the sampling and holding capacitor C1 represents the peak current value when the mirror current sampling tube Q3 is turned on, and at the moment, the ground potential on the internal current sampling resistor Rs is as follows: />. Wherein D is the first control signal +.>T is the first control signal +.>Is a periodic one.
When the first control signalAt high level, the first control signal +.>Is not signal->After the first switch K1 is controlled to be turned off, the sampling holding capacitor C1 is slowly discharged through the compensation current source L1 to simulate the process of the current drop of the inductor, namely, the internal current sampling resistor Rs has the ground potential of +.>。
This makes the ground potential across the internal current sampling resistor Rs the following over the control signal period T:that is, the ground potential across the internal current sampling resistor Rs is proportional to the average value of the inductor current throughout the control signal period T. Therefore, the Buck converter is capable of detecting load current without an external resistor, and is particularly suitable for a circuit of a battery charging management chip.
As shown in fig. 4, a waveform diagram of the timing of each signal of the circuit simulation shown in the preferred embodiment of fig. 3 is shown. When the Buck converter is in the continuous operation mode, the voltage signal VSH input at the positive input terminal of the primary operational amplifier 35, i.e., the node VSH, falls along with the rise of the inductor current or the load current due to the fact that the Buck converter output power transistor Q1 and the mirror current sampling tube Q3 are mirror tubes during the rise of the inductor current. After the inductor current or the load current reaches the peak, the first switch K1 is turned off, the voltage of the peak of the inductor current or the load current is maintained on the sample-hold capacitor C1, and if the compensation circuit is not provided, the voltage signal VSH input at the positive input end of the primary operational amplifier 35 is a line parallel to the X axis during the period of decreasing the inductor current. When the Buck converter is in the continuous working mode, the detected feedback current in the period of the inductor current falling is more similar to the actual load current due to the fact that the compensation circuit, namely the compensation current source, is arranged.
The shaded portion as shown in fig. 4 is an error of load current detection in which the compensation circuit is not provided. As can be seen from fig. 4, the detection of the load current by the compensation circuit is provided to reduce the error of the feedback current, both in the continuous operation mode and in the discontinuous operation mode, the specific degree of error reduction being the triangular hatched portion shown on the left side of fig. 5. After the compensation circuit is arranged, the accuracy of load current detection in the whole period can be improved through the combined action of the sample and hold circuit and the compensation circuit in a period after the output power tube Q1 of the Buck converter is closed, and particularly in a continuous working mode, the detection accuracy is higher than that in a discontinuous working mode.
In a preferred embodiment of the compensation circuit 34 shown in fig. 5, the compensation circuit 34 includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a compensation amplifier 345, a fifth MOS transistor Q5, and a sixth MOS transistor Q6; the fifth MOS tube Q5 and the sixth MOS tube Q6 are PMOS tubes; one end of the twelfth resistor R12 is electrically connected with an external input voltage source VIN and is used as a positive electrode input terminal of the equivalent compensation current source L1; the other end of the twelfth resistor R12 is electrically connected to the positive input terminal of the compensation amplifier 345; one end of the thirteenth resistor R13 is electrically connected to the positive input terminal of the compensation amplifier 345; the other end of the thirteenth resistor R13 is grounded; one end of the eleventh resistor R11 is electrically connected to the negative input terminal of the compensation amplifier 345; the other end of the eleventh resistor R11 is grounded; the output end of the compensation amplifier 345 is electrically connected with the gates of the fifth MOS transistor Q5 and the sixth MOS transistor Q6; the drains of the fifth MOS transistor Q5 and the sixth MOS transistor Q6 are electrically connected with an external input voltage source VIN; the source electrode of the fifth MOS transistor Q5 is electrically connected to the non-grounded end of the eleventh resistor R11, and the source electrode of the sixth MOS transistor Q6 is used as a negative output terminal of the equivalent compensation current source L1. Combined drawing5 and fig. 3, it can be seen that the magnitude of the compensation current outputted by the compensation current source is:. For Buck converter, the current peak to peak value of its external inductance Lx is +.>The method comprises the steps of carrying out a first treatment on the surface of the If the Buck converter is in continuous operation mode, the current peak-to-peak value of the external inductance Lx is reflected in the voltage variation on the sampling capacitance C1 as +.>The method comprises the steps of carrying out a first treatment on the surface of the The compensation current should meet the following conditions: />The relation among the sampling capacitor C1, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13 is properly selected, so that the compensated current is consistent with the actual load current, namely the inductance current, in the conduction period of the NMOS tube, and even the compensation circuit can be set as a constant current source when the variation range of the output voltage Vo is smaller, and the analog detection and feedback of the load current can be realized in the simplest mode within a certain precision range.
The technical scheme of the invention also comprises a Buck load current detection method based on the Buck converter load current detection circuit with the compensation circuit, which comprises the following steps: step 1: the mirror image current sampling tube Q3 and the Buck converter output power tube Q1 form a mirror image pair tube, and when the Buck converter output power tube Q1 is conducted and the Buck converter freewheel tube Q2 is closed, the mirror image current sampling tube Q3 acquires and obtains the conduction current of the first Buck converter output power tube Q1, namely load current; the sample-and-hold circuit 33 samples the mirror current sampling tube Q3; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube Q1 is conducted and the Buck converter freewheel tube Q2 is in a closed state; step 2: when the Buck converter output power tube Q1 is switched from the on state to the off state, the sample-hold circuit 33 holds the voltage at the current moment, and the Buck converter output power tube Q1 is jointly simulated to be turned off by the sample-hold circuit 33 and the compensation circuit 34, and the freewheeling current, namely the load current, when the Buck converter continuous tube Q2 is turned on; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube Q1 is closed and the Buck converter follow-up tube Q2 is in a conducting state; step 3 is included after both steps 1 and 2: the step of low-pass filtering is further provided for the output signal of the Buck converter load current detection circuit in steps 1 and 2, that is, the low-pass filtering is further performed for the voltage signal of the reactive load current output by the internal current sampling resistor Rs by using the low-pass filter 32 to average the inductor current, and the low-pass filtered signal is used as the output signal of the Buck converter load current detection circuit.
When the Buck converter output power tube Q1 is closed, the sample hold voltage obtained by the sample hold circuit and the compensation circuit are utilized to simulate the load current when the follow-up tube Q2 is conducted. The current sampling tube Q3 has current flowing through Rs in the whole period, the voltage Vsa of the current sampling tube Q is proportional to the load current, and the current is fed back to the control end after passing through the low-pass filter 32, so that the load current detection of an external sampling resistor is not needed outside the chip, and the pins of the chip and peripheral circuits applied to the chip are reduced; the energy loss caused by the external sampling resistor is reduced, and the conversion efficiency is improved. Compared with the prior art, the invention has the beneficial effects that: 1. no extra external sampling resistor is needed, no extra pins are needed, and the periphery is simplified; 2. the energy loss caused by the sampling resistor is reduced, and the overall efficiency is improved; 3. the inductance current estimation circuit simulates an inductance current sampling signal, so that a sampling circuit is simplified, and the sampling precision is improved; 4. the sampling operational amplifier adopts a loop structure, so that sampling offset is reduced, and the sampling precision can be further improved.
In addition, for convenience of description, the electronic components such as the NMOS transistor, the PMOS transistor, the resistor, the capacitor and the like are all numbered in the first order and the second order, and the order numbers do not represent the position or the order limitation, but are only for convenience of description. The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the contents of the specification and drawings, or direct or indirect application in other related technical fields, are included in the scope of the invention.
Claims (8)
1. A Buck converter load current detection circuit with compensation circuit, comprising: the power supply circuit comprises an image current sampling tube (Q3) for current image of a Buck converter output power tube (Q1), a primary operational amplifier (35) and a fourth MOS tube (Q4) for current signal amplification, a sample-hold circuit (33) for sampling and holding peak voltage on a sample-hold capacitor (C1) at the closing moment of the Buck converter output power tube (Q1), a compensation circuit (34) for outputting compensation current in the conduction period of the Buck converter freewheel tube (Q2) and an internal current sampling resistor (Rs) for converting a sampled and amplified load current signal into a voltage signal; the circuit function of the compensation circuit (34) is equivalent to a compensation current source (L1); an input terminal of the sample hold circuit (33) is electrically connected with a source electrode of an output power tube (Q1) of the Buck converter and a source electrode of a follow current tube (Q2) of the Buck converter at the same time; meanwhile, an input terminal of the sample hold circuit (33) is also used for electrically connecting the Buck converter load current detection circuit with an external inductor and is used for sampling and obtaining the current of the external inductor, namely, the input terminal of the sample hold circuit (33) is used as the input terminal of the Buck converter load current detection circuit; an output terminal of the sample-and-hold circuit (33) is electrically connected to both the negative electrode of the compensation current source (L1) and the positive input terminal of the primary operational amplifier (35); the positive electrode of the compensation current source (L1) is electrically connected with an external input voltage source (VIN); the source electrode of the mirror current sampling tube (Q3) is electrically connected with an external input voltage source (VIN), the grid electrode of the mirror current sampling tube (Q3) is grounded, and the drain electrode of the mirror current sampling tube (Q3) is electrically connected with the negative electrode input terminal of the primary operational amplifier (35); the drain electrode of the mirror image current sampling tube (Q3) is also electrically connected with the drain electrode of the fourth MOS tube (Q4), namely the drain electrode of the fourth MOS tube (Q4) is also electrically connected with the negative electrode input terminal of the primary operational amplifier (35); the grid electrode of the fourth MOS tube (Q4) is electrically connected with the output terminal of the primary operational amplifier (35), and the source electrode of the fourth MOS tube (Q4) is electrically connected with the voltage output terminal of the internal current sampling resistor (Rs), namely the source electrode of the fourth MOS tube (Q4) is used as the output terminal of the Buck converter load current detection circuit;
the compensation circuit (34) comprises an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a compensation amplifier (345), a fifth MOS tube (Q5) and a sixth MOS tube (Q6); one end of the twelfth resistor (R12) is electrically connected with an external input voltage source (VIN) and is used as a positive electrode input terminal of an equivalent compensation current source (L1); the other end of the twelfth resistor (R12) is electrically connected with the positive electrode input terminal of the compensation amplifier (345); one end of the thirteenth resistor (R13) is electrically connected with the positive electrode input end of the compensation amplifier (345); the other end of the thirteenth resistor (R13) is grounded; one end of the eleventh resistor (R11) is electrically connected with the negative electrode input end of the compensation amplifier (345); the other end of the eleventh resistor (R11) is grounded; the output end of the compensation amplifier (345) is electrically connected with the gates of the fifth MOS tube (Q5) and the sixth MOS tube (Q6); the drain electrode of the fifth MOS tube (Q5) and the drain electrode of the sixth MOS tube (Q6) are electrically connected with an external input voltage source (VIN); the source electrode of the fifth MOS tube (Q5) is electrically connected with the non-grounding end of the eleventh resistor (R11), and the source electrode of the sixth MOS tube (Q6) is used as a negative electrode output terminal of the equivalent compensation current source (L1).
2. The Buck converter load current detection circuit with compensation circuit according to claim 1, wherein the sample-and-hold circuit (33) comprises a first switch (K1) and a sample-and-hold capacitor (C1), the first switch (K1) receiving a non-signal of the first control signal (Φ1)Is controlled by (a); the first control signal (phi 1) is a switch control signal generated in the Buck converter and used for an output power tube (Q1) of the Buck converter; one end of the first switch (K1) is used as an input terminal of the sample-and-hold circuit (33) for connecting with the outsideOne end of the inductor is electrically connected to obtain external load current; the other end of the first switch (K1) is used as an output terminal of the sampling hold circuit (33) and is used for being electrically connected with a positive plate of the sampling hold capacitor (C1) and a negative electrode of the compensation current source (L1); the negative plate of the sample-and-hold capacitor (C1) is grounded.
3. The Buck converter load current detection circuit with compensation circuit of claim 1, wherein the primary operational amplifier (35) comprises a low error operational amplifier, a chopper operational amplifier, and an auto-zero operational amplifier.
4. The Buck converter load current detection circuit with compensation circuit of claim 1, further comprising a low pass filter (32) for low pass filtering the voltage signal output by the internal current sampling resistor (Rs); the low-pass filter (32) comprises a low-pass filter resistor (Rf) and a low-pass filter capacitor (Cf), wherein one end of the low-pass filter resistor (Rf) is used as an input terminal of the low-pass filter (32) and is electrically connected with a voltage output terminal of the internal current sampling resistor (Rs); the other end of the low-pass filter resistor (Rf) is used as an output terminal of the low-pass filter (32) and is electrically connected with one end of the low-pass filter capacitor (Cf), and the other end of the low-pass filter capacitor (Cf) is grounded; the output terminal of the low-pass filter (32) is used as the output terminal of the Buck converter load current detection circuit, i.e. the output signal of the low-pass filter (32) is used as the load current sampling signal of the Buck converter.
5. The Buck converter load current detection circuit with compensation circuit of claim 4, further comprising a reference voltage generation circuit (90); the reference voltage generating circuit (90) comprises a current source (Iref) and a reference voltage circuit Resistor (RL); the positive electrode of the current source (Iref) is electrically connected to an external input voltage source (VIN), and the negative electrode of the current source (Iref) is used as an output terminal of the reference voltage generating circuit (90); the negative electrode of the current source (Iref) is also electrically connected with one end of the reference voltage circuit Resistor (RL), and the other end of the reference voltage circuit Resistor (RL) is grounded.
6. The Buck converter load current detection circuit with compensation circuit of claim 5, further comprising an error amplifier (38) for detecting a voltage signal indicative of the magnitude of the load current and a reference voltage comparison operation, a negative input terminal of the error amplifier (38) being electrically connected to an output terminal of the reference voltage generation circuit (90); a positive input terminal of the error amplifier (38) is electrically connected to an output terminal of the low-pass filter (32).
7. A Buck load current detection method based on the Buck converter load current detection circuit with compensation circuit as claimed in any one of claims 1 to 3,
comprising the following steps: step 1: the mirror current sampling tube (Q3) and the Buck converter output power tube (Q1) form a mirror pair tube, and when the Buck converter output power tube (Q1) is conducted and the Buck converter follow-up tube (Q2) is closed, the mirror current sampling tube (Q3) acquires the conduction current of the Buck converter output power tube (Q1), namely load current; the sample-and-hold circuit (33) samples the mirror current sampling tube (Q3); the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube (Q1) is conducted and the Buck converter current-sustaining tube (Q2) is in a closed state; step 2: when the Buck converter output power tube (Q1) is switched from a conducting state to a closing state, the sampling hold circuit (33) keeps the voltage at the current moment, and the Buck converter output power tube (Q1) is closed through the sampling hold circuit (33) and the compensation circuit (34) together, and the follow current, namely the load current, when the Buck converter follow current tube (Q2) is conducted; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube (Q1) is closed and the Buck converter current-continuing tube (Q2) is in a conducting state.
8. A Buck load current detection method based on the Buck converter load current detection circuit with compensation circuit of any one of claims 4 to 6, comprising: step 1: the mirror current sampling tube (Q3) and the Buck converter output power tube (Q1) form a mirror pair tube, and when the Buck converter output power tube (Q1) is conducted and the Buck converter follow-up tube (Q2) is closed, the mirror current sampling tube (Q3) acquires the conduction current of the Buck converter output power tube (Q1), namely load current; the sample-and-hold circuit (33) samples the mirror current sampling tube (Q3); the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube (Q1) is conducted and the Buck converter current-sustaining tube (Q2) is in a closed state; step 2: when the Buck converter output power tube (Q1) is switched from a conducting state to a closing state, the sampling hold circuit (33) keeps the voltage at the current moment, and the Buck converter output power tube (Q1) is closed through the sampling hold circuit (33) and the compensation circuit (34) together, and the follow current, namely the load current, when the Buck converter follow current tube (Q2) is conducted; the output current of the Buck converter load current detection circuit represents the load current when the Buck converter output power tube (Q1) is closed and the Buck converter current-sustaining tube (Q2) is in a conducting state; step 3 is included after both steps 1 and 2: namely, the step of low-pass filtering is further arranged on the output signal of the Buck converter load current detection circuit in the steps 1 and 2, namely, the low-pass filtering is further carried out on the voltage signal of the reaction load current output by the internal current sampling resistor (Rs) by adopting a low-pass filter (32), and the low-pass filtered signal is used as the output signal of the Buck converter load current detection circuit.
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| TWI665865B (en) * | 2018-12-05 | 2019-07-11 | Hycon Technology Corp. | Bias switch circuit for compensating frontend offset of high accuracy measurement circuit |
| CN110311380B (en) * | 2019-07-19 | 2023-05-23 | 云南电网有限责任公司电力科学研究院 | Active grounding compensator control method |
| CN111999545B (en) * | 2020-08-14 | 2023-03-21 | Oppo广东移动通信有限公司 | Current measurement method, power supply device and power supply chip |
| CN112798882A (en) * | 2020-12-04 | 2021-05-14 | 上海芯导电子科技股份有限公司 | Improved light load detection circuit |
| CN113252949B (en) * | 2021-05-13 | 2021-11-05 | 北京芯格诺微电子有限公司 | High-precision current sampling circuit with on-chip real-time calibration |
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