CN111208337A - Current sampling circuit and current detection system - Google Patents
Current sampling circuit and current detection system Download PDFInfo
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- CN111208337A CN111208337A CN202010027351.7A CN202010027351A CN111208337A CN 111208337 A CN111208337 A CN 111208337A CN 202010027351 A CN202010027351 A CN 202010027351A CN 111208337 A CN111208337 A CN 111208337A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
Abstract
The embodiment of the invention discloses a current sampling circuit and a current detection system, wherein the current sampling circuit comprises a current sampling module and a current compensation module; the current sampling module comprises a power unit, a sampling unit, a first current mirror image unit and a second current mirror image unit, wherein the second current mirror image unit comprises a first transistor; the current compensation module comprises a third current mirror unit and a second transistor; the third current mirror unit comprises a current release tube; the second transistor and the first transistor form a fourth current mirror unit; the power unit, the first current mirror image unit and the element to be sampled are electrically connected at a first node; the sampling unit is electrically connected with the first current mirror image unit at a second node; the current release tube is electrically connected with the first current mirror unit at a third node; the first current mirror cell and the second current mirror cell are electrically connected. According to the technical scheme, the compensation current is provided by additionally arranging the current compensation module, and the sampling precision is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of power electronics, in particular to a current sampling circuit and a current detection system.
Background
In an electronic device, it is generally necessary to detect a current of an electronic element to obtain an operating state of the electronic device, and a current sampling circuit is used at this time.
The conventional current sampling circuit generally adopts an operational amplifier to provide a certain gain, but the circuit structure of an operational amplifier is generally complex, the internal bandwidth is limited by a load, and although the accuracy can be designed to be high, the sampling rate is slow. On the contrary, if a faster sampling speed is adopted, the accuracy is affected.
Therefore, a current sampling circuit with high sampling precision and high sampling speed becomes a hot point of research.
Disclosure of Invention
In view of this, embodiments of the present invention provide a current sampling circuit and a current detection system, where the current sampling circuit has higher sampling precision and faster sampling speed.
In a first aspect, an embodiment of the present invention provides a current sampling circuit, including a current sampling module and a current compensation module;
the current sampling module comprises a power unit, a sampling unit, a first current mirror image unit and a second current mirror image unit, wherein the second current mirror image unit comprises a first transistor;
the current compensation module comprises a third current mirror unit and a second transistor; the third current mirror unit comprises a current release tube;
the second transistor and the first transistor form a fourth current mirror unit;
the power unit, the first current mirror unit and the element to be sampled are electrically connected at a first node;
the sampling unit is electrically connected with the first current mirror unit at a second node;
the current release tube and the first current mirror unit are electrically connected at a third node;
the first current mirror cell and the second current mirror cell are electrically connected.
Optionally, the first current mirror unit includes a third transistor and a fourth transistor, the second current mirror unit further includes a fifth transistor and a sixth transistor, and the third current mirror unit further includes a seventh transistor and an eighth transistor;
the channel width-length ratios of the third transistor and the fourth transistor are the same;
the channel width-to-length ratios of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are the same;
the channel width-length ratios of the current release tube, the seventh transistor and the eighth transistor are the same;
the power unit comprises a power transistor, and the sampling unit comprises a sampling transistor;
the channel width-to-length ratio of the power transistor and the sampling transistor is M:1, wherein M > 1.
Optionally, the current sampling circuit further includes a voltage signal output terminal electrically connected to the first transistor for providing a reference current to the first transistor;
and the compensation current output by the current compensation module is the same as the reference current.
Optionally, the current sampling circuit further includes a sampling current output unit, and the sampling current output unit is electrically connected to the sampling unit and the first current mirror unit at the second node.
Optionally, the sampling current output unit includes a sampling current output control transistor and a sampling resistor;
the input of sampling current output control transistor with the unit of sampling with first current mirror image unit is in the second node electricity is connected, sampling current output control transistor's output with the first end of sampling resistor is connected, the second end ground connection of sampling resistor.
Optionally, the current sampling circuit further includes a voltage signal output terminal, and the voltage signal input terminal is electrically connected to the power unit, the sampling unit, and the third current mirror unit, respectively.
Optionally, the current collection module further includes a first switch state tube and a second switch state tube, and the current compensation module further includes a third switch state tube;
the first switch state tube is arranged between the first node and the third node in series;
the second switch state tube is arranged between the voltage signal output terminal and the first current mirror unit in series;
the third switch state tube is arranged between the current release tube and the third node in series;
and the source-drain voltage difference when the first switch state tube, the second switch state tube and the third switch state tube are conducted is zero.
Optionally, the current sampling module further includes a synchronous rectification unit, one end of the synchronous rectification unit is electrically connected to the element to be sampled at the first node, and the other end of the synchronous rectification unit is grounded.
Optionally, the power transistor, the sampling transistor, the third transistor, the fourth transistor, the current release transistor, the seventh transistor, and the eighth transistor are PMOS transistors; the first transistor, the second transistor, the fifth transistor, and the sixth transistor are NMOS transistors.
In a second aspect, an embodiment of the present invention further provides a current detection system, including the current sampling circuit in the first aspect, further including an oscillator, a logic control circuit, a driving circuit, a PWM comparator, an error amplifier, an element to be sampled, and a driving transistor;
the current sampling circuit is respectively and electrically connected with the element to be sampled and the first input end of the PWM comparator;
the error amplifier is electrically connected with the second input end of the PWM comparator;
the logic control circuit is respectively connected with the output end of the PWM comparator, the oscillator and the driving circuit and is used for generating driving signals according to signals output by the PWM comparator and logic control clock signals output by the oscillator;
the driving circuit is connected with the driving transistor and used for driving the driving transistor to be conducted.
According to the current sampling circuit and the current detection system provided by the embodiment of the invention, the current sampling circuit comprises a current sampling module and a current compensation module; the current of an element to be sampled is collected through the current sampling module, the current collected by the current sampling module is compensated through the current compensation module, errors caused by the device structure of the current sampling module are made up, and the sampling current precision collected by the current sampling circuit is guaranteed to be high; meanwhile, the channel width-length ratio of each transistor in each current mirror image unit is reasonably set, so that the mirror relationship between the current and the channel width-length ratio is realized, the sampling error caused by the structure of the current sampling circuit is fully reduced or completely eliminated, and the sampling precision is improved; meanwhile, the current compensation module is simple in structure, so that the whole current sampling circuit is simple in structure, and the sampling rate is high.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic structural diagram of a current mirror unit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a current sampling circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a current detection system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a current mirror unit according to an embodiment of the present invention, and as shown in fig. 1, a current mirror unit 10 according to an embodiment of the present invention includes a first mirror transistor 11 and a second mirror transistor 12, where channel width-length ratios of the first mirror transistor 11 and the second mirror transistor 12 are different, specifically, channel lengths of the first mirror transistor 11 and the second mirror transistor 12 may be the same, and channel widths are different, for example, a ratio of the channel widths may be M:1, where M > 1. Assuming that VA is VB, the ratio between the driving current IP flowing through the first mirror transistor 11 and the driving current IPs flowing through the second mirror transistor is also M: 1. The current mirror image method is simple and convenient, almost has no sampling resistor, reduces the power consumption of the circuit and improves the precision.
Based on the above concept, an embodiment of the present invention provides a current sampling circuit, and specifically, fig. 2 is a schematic structural diagram of the current sampling circuit provided in the embodiment of the present invention, as shown in fig. 2, the current sampling circuit provided in the embodiment of the present invention includes a current sampling module 21 and a current compensation module 22; the current sampling module 21 includes a power unit 211, a sampling unit 212, a first current mirror unit 213, and a second current mirror unit 214, the second current mirror unit 214 including a first transistor MN 1; the current compensation module 22 includes a third current mirror unit 221 and a second transistor MN 4; the third current mirror 221 unit includes a current release pipe MP 6; the second transistor MN4 and the first transistor MN1 form a fourth current mirror unit 23; the power unit 211, the first current mirror unit 213, and the element to be sampled 24 are electrically connected at a first node N1; the sampling unit 212 and the first current mirror unit 213 are electrically connected at a second node N2; the current release tube MP6 and the first current mirror unit 213 are electrically connected at the third node N3; the first current mirror unit 213 and the second current mirror unit 214 are electrically connected.
For example, as shown in fig. 2, the current sampling module 21 is electrically connected to the element to be sampled 24, and is configured to collect a current flowing through the element to be sampled 24, where the element to be sampled 24 provided in the embodiment of the present invention may be an inductor L. The current compensation module 22 is electrically connected to the current sampling module 21, and is configured to provide a compensation current to the current sampling module 21, compensate for an error caused by a device structure of the current sampling module 21, and ensure that the sampling current acquired by the current sampling circuit 20 has a high accuracy. Further, the current compensation module 22 provided by the embodiment of the present invention has a simple structure, has a small influence on the sampling rate, ensures that the sampling rate of the current sampling circuit 20 is fast, and provides a current sampling circuit with both high sampling precision and high sampling rate.
Specifically, as shown in fig. 2, the current sampling module 21 includes a power unit 211, a sampling unit 212, a first current mirror unit 213, and a second current mirror unit 214, where the second current mirror unit 214 includes a first transistor MN 1; the current compensation module 22 includes a third current mirror unit 221 and a second transistor MN 4; the third current mirror 221 unit includes a current release pipe MP 6; the second transistor MN4 and the first transistor MN1 form a fourth current mirror unit 23. The power unit 211, the first current mirror unit 213 and the element 24 to be sampled are electrically connected at a first node N1, the sampling unit 212 and the first current mirror unit 213 are electrically connected at a second node N2, and the sampling unit 212 performs current sampling on the element 24 to be sampled by controlling the power unit 211 and the first current mirror unit 213 to be turned on. Meanwhile, the current release tube MP6 and the first current mirror unit 213 are electrically connected at the third node N3, and the current release tube MP6 compensates the compensation current provided by the current compensation module 22 to the third node N3, so as to compensate for an error caused by the device structure of the current sampling module 21 itself, and ensure that the sampling current precision acquired by the current sampling circuit 20 is relatively high. Furthermore, by reasonably setting the channel width-length ratio of each transistor in each current mirror unit, the mirror relation between the current and the channel width-length ratio is realized, and different sampling precision is guaranteed.
In summary, the current sampling circuit provided in the embodiment of the present invention is configured to include a current sampling module and a current compensation module; the current of an element to be sampled is collected through the current sampling module, the current collected by the current sampling module is compensated through the current compensation module, errors caused by the device structure of the current sampling module are made up, and the sampling current precision collected by the current sampling circuit is guaranteed to be high; meanwhile, the channel width-length ratio of each transistor in each current mirror image unit is reasonably set, so that the mirror relationship between the current and the channel width-length ratio is realized, the sampling error caused by the structure of the current sampling circuit is fully reduced or completely eliminated, and the sampling precision is improved; meanwhile, the current compensation module is simple in structure, so that the whole current sampling circuit is simple in structure, and the sampling rate is high.
Optionally, with continuing reference to fig. 2, the current sampling circuit 20 provided in the embodiment of the present invention may further include a voltage signal input terminal VDD, where the voltage signal input terminal VDD is electrically connected to the power unit 211, the sampling unit 212, and the third current mirror unit 221, respectively, to provide voltage signals for the power unit 211, the sampling unit 212, and the third current mirror unit 221, so as to ensure that the power unit 211, the sampling unit 212, and the third current mirror unit 221 operate normally.
Further, with continued reference to fig. 2, the current collection module 21 may further include a first switch state tube MS1 and a second switch state tube MS2, and the current compensation module 22 may further include a third switch state tube MS 3; the first switch state tube MS1 is arranged in series between the first node N1 and the third node N3; the second switch state tube MS2 is serially disposed between the voltage signal output terminal VDD and the first current mirror unit 213; the third switch state tube MS3 is arranged in series between the current release tube MP6 and the third node N3; the source-drain voltage difference when the first switch state tube MS1, the second switch state tube MS2 and the third switch state tube MS3 are turned on is zero.
Illustratively, a first switch state tube MS1 is disposed between the first node N1 and the third node N3, a second switch state tube MS2 is disposed between the voltage signal output terminal VDD and the first current mirror unit 213, and a third switch state tube MS3 is disposed between the current release tube MP6 and the third node N3, so that the working processes of the current sampling module 21 and the current compensation module 22 are flexibly set through the on and off of the first switch state tube MS1, the second switch state tube MS2 and the third switch state tube MS3, the current sampling and current compensation processes are controlled, and the controllability of the whole current sampling circuit is provided. Furthermore, the source-drain voltage difference when the first switch state tube MS1, the second switch state tube MS2 and the third switch state tube MS3 are turned on is zero, so that the sampling current is not affected by the arrangement of the first switch state tube MS1, the second switch state tube MS2 and the third switch state tube MS3, and the sampling current collection precision is high.
The following is a detailed description of how to set the channel width-to-length ratio of each transistor in each current mirror unit, to achieve sufficient reduction or complete elimination of the sampling error caused by the structure of the current sampling circuit itself, and to improve the sampling accuracy.
Optionally, with continued reference to fig. 2, the first current mirror unit 213 includes a third transistor MP2 and a fourth transistor MP3, the second current mirror unit 214 further includes a fifth transistor MN2 and a sixth transistor MN3, and the third current mirror unit 221 further includes a seventh transistor MP4 and an eighth transistor MP 5;
the channel width-to-length ratios of the third transistor MP2 and the fourth transistor MP3 are the same;
the channel width-to-length ratios of the first transistor MN1, the second transistor MN4, the fifth transistor MN2, and the sixth transistor MN3 are the same;
the channel width-to-length ratios of the current release pipe MP6, the seventh transistor MP4 and the eighth transistor MP5 are the same;
the power unit 211 includes a power transistor MP, and the sampling unit 212 includes a sampling transistor MP 1;
the channel width-to-length ratio of the power transistor MP and the sampling transistor MP1 is M:1, wherein M > 1.
Illustratively, as shown in fig. 2, when Q is low, MP is turned on, and it can be known from kirchhoff's law that the current flowing through the power transistor MP is equal to the current flowing through the element to be sampled 24 and the first switch state transistor MS1, that is:
IMP＝IMS1+IL(1)
further, it can be known from kirchhoff's law that the current flowing through the fourth transistor MP3 is equal to the current flowing through the first switch-state transistor MS1 and the third switch-state transistor MS3, that is:
IMP3＝IMS1+IMS3(2)
further, the potentials of the first node N1, the second node N2 and the third node N3 are set to be the same, that is:
VN1＝VN2＝VN3(3)
since the third transistor MP2 and the fourth transistor MP3 constitute the first current mirror unit 213, and the channel width-to-length ratios of the third transistor MP2 and the fourth transistor MP3 are the same, the first transistor MN1, the fifth transistor MN2, and the sixth transistor MN3 constitute the second current mirror unit 214, and the channel width-to-length ratios of the first transistor MN1, the fifth transistor MN2, and the sixth transistor MN3 are the same, the current flowing through the first transistor is IrefThus:
IMP2＝IMP3＝Iref(4)
from equations (2), (3) and (4) we can obtain:
Iref＝IMS1+IMS3(5)
since the channel width-to-length ratio of the sampling transistor MP1 to the channel width-to-length ratio of the power transistor MP is 1: m, so there are:
from equation (1), equation (2), equation (5) and equation (6) we can obtain:
IL＝M×IMP1-Iref+IMS3(7)
the first transistor MN1 and the second transistor MN4 form the fourth current mirror unit 23, and the channel width-to-length ratios of the first transistor MN1 and the second transistor MN4 are the same; the current release transistor MP6, the seventh transistor MP4, and the eighth transistor MP5 form the third current mirror unit 221, and the channel width-to-length ratios of the current release transistor MP6, the seventh transistor MP4, and the eighth transistor MP5 are the same, so that there are:
IMS3＝Iref(8)
thus, equation (7) can be rewritten as:
IL＝M×IMP1(9)
with continued reference to fig. 2, again because:
IMP5+Iusen＝Isen(10)
IMP1＝Iusen+Iref(11)
from equation (9), equation (10) and equation (11), we can obtain:
further, the expressions of the sampling error and the sampling precision are respectively:
AS＝1-RE＝100％ (14)
as can be known from the formulas (13) and (14), by appropriately setting the channel width-to-length ratios of the transistors in the current mirror units, the sampling error caused by the structure of the current sampling circuit itself can be substantially reduced or completely eliminated, for example, by setting the channel width-to-length ratios of the third transistor MP2 and the fourth transistor MP3 to be the same; the channel width-to-length ratios of the first transistor MN1, the second transistor MN4, the fifth transistor MN2, and the sixth transistor MN3 are the same; the channel width-to-length ratios of the current release pipe MP6, the seventh transistor MP4 and the eighth transistor MP5 are the same; the channel width-to-length ratio of the power transistor MP and the sampling transistor MP1 is M:1, introducing a compensation current IMS3 into a current sampling circuit, and proving through theoretical calculation that the method can completely eliminate the sampling error caused by the structure of the current sampling circuit and ensure that the sampling precision is 100%.
Optionally, with continued reference to fig. 2, in the embodiment of the present invention, the power transistor MP, the sampling transistor MP1, the third transistor MP2, the fourth transistor MP3, the current release transistor MP6, the seventh transistor MP4, and the eighth transistor MP5 are PMOS transistors; the first transistor MN1, the second transistor MN4, the fifth transistor MN2, and the sixth transistor MN3 are NMOS transistors for example, so that the first current mirror unit 213 can be a PMOS current mirror unit, the second current mirror unit 214 can be an NMOS current mirror unit, the third current mirror unit 221 can be a PMOS current mirror unit, and the fourth current mirror unit 23 can be an NMOS current mirror unit.
It should be noted that the type of each transistor is not limited in the embodiment of the present invention, fig. 2 is only illustrated as one possible implementation manner, and is not limited, and other types of transistors are also within the protection scope of the embodiment of the present invention.
Optionally, with continued reference to fig. 2, the current sampling circuit 20 may further include a voltage signal output terminal VDD, which is electrically connected to the first transistor MN1, and is configured to provide a reference current Iref to the first transistor MN 1; the compensation current output by the current compensation module 21 is the same as the reference current Iref.
For example, as can be known from fig. 2, Iref provides bias currents for the first transistor MN1, the fifth transistor MN2, and the sixth transistor MN3, and since the final induced current is obtained by subtracting the bias current from the sampling current, by reasonably setting the channel width-to-length ratio of each transistor in each current mirror unit, the compensation current output by the current compensation module 22 can be ensured to be the same as the reference current Iref (i.e., the bias current), and it is ensured that the sampling error caused by the structure of the current sampling circuit itself can be completely eliminated, and the sampling accuracy is ensured to be 100%.
Optionally, as shown in fig. 2, the current sampling module 21 according to the embodiment of the present invention may further include a sampling current output unit 215, where the sampling current output unit 215 is electrically connected to the sampling unit 212 and the first current mirror unit 213 at a second node, and the sampling current output unit 215 is arranged to ensure that the output of the sampling current can be flexibly controlled, and the output process of the sampling current is flexible and controllable.
Specifically, the sampling current output unit 215 includes a sampling current output control transistor MS and a sampling resistor Rsen, an input end of the sampling current output control transistor MS is electrically connected to the sampling unit 212 and the first current mirror unit 213 at the second node N2, an output end of the sampling current output control transistor MS is connected to a first end of the sampling resistor Rsen, and a second end of the sampling resistor Rsen is grounded. The output of the sampling current is flexibly controlled by setting the sampling current output control transistor MS, so that the output process of the sampling current is flexible and controllable; the sampling resistor Rsen is arranged to protect the sampling current output branch circuit, and the phenomenon that the sampling current is too large to burn out a device is avoided.
Optionally, with continuing reference to fig. 2, the current sampling module 21 according to the embodiment of the present invention may further include a synchronous rectification unit 216, where one end of the synchronous rectification unit 216 is electrically connected to the to-be-sampled element 24 at the first node N1, the other end of the synchronous rectification unit 216 is grounded, and the synchronous rectification unit 216 is configured to perform synchronous rectification on the sampling current of the to-be-sampled element 24. Alternatively, the synchronous rectification unit 216 may be a synchronous rectification transistor MN, and the synchronous rectification transistor MN may be an NMOS transistor.
On the basis of the foregoing embodiment, an embodiment of the present invention further provides a current detection system, specifically, fig. 3 is a schematic structural diagram of the current detection system provided in the embodiment of the present invention, and as shown in fig. 3, a current detection system 30 provided in the embodiment of the present invention includes the current sampling circuit 20 described in the foregoing embodiment, and further includes an oscillator 31, a logic control circuit 32, a driving circuit 33, a PWM comparator 34, an error amplifier 35, an element to be sampled 24, and a driving transistor 36; the current sampling circuit 20 is electrically connected with the element to be sampled 24 and a first input end of the PWM comparator 24 respectively; the error amplifier is electrically connected to a second input terminal of the PWM comparator 34; the logic control circuit 32 is respectively connected with the output end of the PWM comparator 34, the oscillator 31 and the driving circuit 33, and is configured to generate a driving signal according to a signal output by the PWM comparator and a logic control clock signal output by the oscillator; the driving circuit 33 is connected to the driving transistor 36 for driving the driving transistor 36 to be conductive.
Illustratively, the current detection circuit 20 is configured to generate a suitable ramp signal according to the sampled current of the element 24 to be sampled, and send the ramp signal and the output of the error amplifier 35 to the PWM comparator 34 for comparison; the oscillator 31 is used for generating a logic control clock; the logic control circuit 32 is respectively connected with the output end of the PWM comparator 34, the oscillator 31 and the driving circuit 33, and is used for performing combinational logic control on the signal output by the PWM comparator and the logic control clock signal output by the oscillator, generating and transmitting the driving circuit 33; the driving circuit 33 is connected to the driving transistor 36 for driving the driving transistor 36 to be turned on; and realizing the current detection function.
Optionally, as shown in fig. 3, the current detection system 30 provided in the embodiment of the present invention may further include a resistor or a capacitor element, such as a capacitor C, a resistor R1, and a resistor R2, which is not described again in the embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that the features of the various embodiments of the invention may be partially or fully coupled to each other or combined and may be capable of cooperating with each other in various ways and of being technically driven. Numerous variations, rearrangements, combinations, and substitutions will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A current sampling circuit is characterized by comprising a current sampling module and a current compensation module;
the current sampling module comprises a power unit, a sampling unit, a first current mirror image unit and a second current mirror image unit, wherein the second current mirror image unit comprises a first transistor;
the current compensation module comprises a third current mirror unit and a second transistor; the third current mirror unit comprises a current release tube;
the second transistor and the first transistor form a fourth current mirror unit;
the power unit, the first current mirror unit and the element to be sampled are electrically connected at a first node;
the sampling unit is electrically connected with the first current mirror unit at a second node;
the current release tube and the first current mirror unit are electrically connected at a third node;
the first current mirror cell and the second current mirror cell are electrically connected.
2. The current sampling circuit of claim 1, wherein the first current mirror cell comprises a third transistor and a fourth transistor, the second current mirror cell further comprises a fifth transistor and a sixth transistor, and the third current mirror cell further comprises a seventh transistor and an eighth transistor;
the channel width-length ratios of the third transistor and the fourth transistor are the same;
the channel width-to-length ratios of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are the same;
the channel width-length ratios of the current release tube, the seventh transistor and the eighth transistor are the same;
the power unit comprises a power transistor, and the sampling unit comprises a sampling transistor;
the channel width-to-length ratio of the power transistor and the sampling transistor is M:1, wherein M > 1.
3. The current sampling circuit of claim 2, further comprising a voltage signal output terminal electrically connected to the first transistor for providing a reference current to the first transistor;
and the compensation current output by the current compensation module is the same as the reference current.
4. The current sampling circuit of claim 1, wherein the current sampling module further comprises a sampling current output unit electrically connected to the sampling unit and the first current mirror unit at the second node.
5. The current sampling circuit according to claim 4, wherein the sampling current output unit includes a sampling current output control transistor and a sampling resistor;
the input of sampling current output control transistor with the unit of sampling with first current mirror image unit is in the second node electricity is connected, sampling current output control transistor's output with the first end of sampling resistor is connected, the second end ground connection of sampling resistor.
6. The current sampling circuit of claim 1, further comprising voltage signal output terminals electrically connected to the power unit, the sampling unit, and the third current mirror unit, respectively.
7. The current sampling circuit of claim 6, wherein the current collection module further comprises a first switch state transistor and a second switch state transistor, and the current compensation module further comprises a third switch state transistor;
the first switch state tube is arranged between the first node and the third node in series;
the second switch state tube is arranged between the voltage signal output terminal and the first current mirror unit in series;
the third switch state tube is arranged between the current release tube and the third node in series;
and the source-drain voltage difference when the first switch state tube, the second switch state tube and the third switch state tube are conducted is zero.
8. The current sampling circuit according to claim 1, wherein the current sampling module further comprises a synchronous rectification unit, one end of the synchronous rectification unit is electrically connected to the element to be sampled at the first node, and the other end of the synchronous rectification unit is grounded.
9. The current sampling circuit according to claim 2, wherein the power transistor, the sampling transistor, the third transistor, the fourth transistor, the current release tube, the seventh transistor, and the eighth transistor are PMOS transistors; the first transistor, the second transistor, the fifth transistor, and the sixth transistor are NMOS transistors.
10. A current detection system comprising the current sampling circuit according to any one of claims 1 to 9, further comprising an oscillator, a logic control circuit, a drive circuit, a PWM comparator, an error amplifier, an element to be sampled, and a drive transistor;
the current sampling circuit is respectively and electrically connected with the element to be sampled and the first input end of the PWM comparator;
the error amplifier is electrically connected with the second input end of the PWM comparator;
the logic control circuit is respectively connected with the output end of the PWM comparator, the oscillator and the driving circuit and is used for generating driving signals according to signals output by the PWM comparator and logic control clock signals output by the oscillator;
the driving circuit is connected with the driving transistor and used for driving the driving transistor to be conducted.
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