CN102545849A - Self-adaptive input hysteresis comparator - Google Patents

Self-adaptive input hysteresis comparator Download PDF

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CN102545849A
CN102545849A CN2010105807447A CN201010580744A CN102545849A CN 102545849 A CN102545849 A CN 102545849A CN 2010105807447 A CN2010105807447 A CN 2010105807447A CN 201010580744 A CN201010580744 A CN 201010580744A CN 102545849 A CN102545849 A CN 102545849A
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CN102545849B (en
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马和良
景一欧
倪昊
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Shanghai Huahong Integrated Circuit Co Ltd
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Abstract

The invention discloses a self-adaptive input hysteresis comparator which comprises a first-stage amplification module, a positive feedback module, a differential input-single-ended output conversion module and an output driving module. Compared with the traditional hysteresis comparator, the hysteresis comparator disclosed by the invention is provided with an NMOS (negative-channel metal oxide semiconductor) input pair and a PMOS (positive-channel metal oxide semiconductor) input pair in the first-stage amplification module, so that a larger input range is realized, the amplitude of front-stage signals does not need to be limited excessively, the integrity of the front-stage signals is further ensured, and the hysteresis comparator is also conductive to demodulation and stable work of a system.

Description

The hysteresis comparator of self adaptation input
Technical field
The present invention relates to the hysteresis comparator in a kind of analog integrated circuit.
Background technology
See also Fig. 1, this is a kind of concrete realization circuit of existing hysteresis comparator, comprises first order amplification module, positive feedback module, the single-ended output module of both-end input commentaries on classics, output driver module.Its particular circuit configurations is following:
The grid of transistor one N1 connects bias voltage one VB1, source ground;
The grid of transistor two N2 meets positive input terminal IN+, and source electrode connects the drain electrode of transistor one N1;
The grid of transistor three N3 meets negative input end IN-, and source electrode connects the drain electrode of transistor one N1;
The grid of transistor four N4 links to each other and links to each other with the drain electrode of transistor two N2 with drain electrode, and the source electrode of transistor four N4 meets operating voltage VDD;
The grid of transistor five N5 links to each other and links to each other with the drain electrode of transistor three N3 with drain electrode, and the source electrode of transistor five N5 meets operating voltage VDD;
The grid of transistor six N6 links to each other source ground with drain electrode;
The drain electrode of transistor seven N7 links to each other with the grid of transistor six N6, the source ground of transistor seven N7;
The grid of transistor eight N8 links to each other with the grid of transistor six N6, and the drain electrode of transistor eight N8 links to each other with the grid of transistor seven N7, the source ground of transistor eight N8;
The grid of transistor nine N9 links to each other with drain electrode and links to each other the source ground of transistor nine N9 with the grid of transistor seven N7;
The grid of transistor ten N10 links to each other with the drain electrode of transistor two N2, and the drain electrode of transistor ten N10 links to each other with the grid of transistor six N6, and the source electrode of transistor ten N10 meets operating voltage VDD;
The grid of transistor 11 N11 links to each other with the drain electrode of transistor three N3, and the drain electrode of transistor 11 N11 links to each other with the grid of transistor seven N7, and the source electrode of transistor 11 N11 meets operating voltage VDD;
The grid of transistor 12 N12 connects bias voltage two VB2, source ground;
The grid of transistor 13 N13 links to each other with the grid of transistor six N6, and the source electrode of transistor 13 N13 links to each other with the drain electrode of transistor 12 N12;
The grid of transistor 14 N14 links to each other with the grid of transistor seven N7, and the source electrode of transistor 14 N14 links to each other with the drain electrode of transistor 12 N12;
The grid of transistor 15 N15 links to each other and links to each other with the drain electrode of transistor 13 N13 with drain electrode, and the source electrode of transistor 15 N15 meets operating voltage VDD;
The grid of transistor 16 N16 links to each other with the drain electrode of transistor 13 N13, and the drain electrode of transistor 16 N16 links to each other with the drain electrode of transistor 14 N14, and the source electrode of transistor 16 N16 meets operating voltage VDD;
The grid of transistor 17 N17 links to each other with the drain electrode of transistor 14 N14, the source ground of transistor 17 N17;
The grid of transistor 18 N18 links to each other with the drain electrode of transistor 14 N14, and the drain electrode of transistor 18 N18 links to each other with the drain electrode of transistor 17 N17, and the source electrode of transistor 18 N18 meets operating voltage VDD;
The grid of transistor 19 N19 links to each other with the drain electrode of transistor 17 N17, the source ground of transistor 19 N19;
The grid of transistor 20 N20 links to each other with the drain electrode of transistor 17 N17, and the drain electrode of the drain electrode of transistor 20 N20 and transistor 19 N19 links to each other and as signal output part OUT, the source electrode of transistor 20 N20 meets operating voltage VDD.
Wherein, First order amplification module comprises that transistor one N1 is to transistor five N5; The positive feedback module comprises that transistor six N6 are to transistor 11 N11; The both-end input is changeed single-ended output module and is comprised transistor 12 N12 to transistor 16 N16, and the output driver module comprises that transistor 17 N17 are to transistor 20 N20.
Wherein, transistor one N1, transistor two N2, transistor three N3, transistor six N6, transistor seven N7, transistor eight N8, transistor nine N9, transistor 12 N12, transistor 13 N13, transistor 14 N14, transistor 17 N17, transistor 19 N19 are the NNOS transistor.
Wherein, transistor four N4, transistor five N5, transistor ten N10, transistor 11 N11, transistor 15 N15, transistor 16 N16, transistor 18 N18, transistor 20 N20 are the PNOS transistor.
Hysteresis comparator shown in Figure 1 is in amplifying return circuit, to add positive feedback, makes the threshold value of input voltage to change according to input signal, thereby has the function of filtering noise, i.e. lag function.Yet this hysteresis comparator has certain requirement for the amplitude of the input signal of differential input end IN+, IN-, handles and at first need carry out the range of decrease for the input signal that does not meet the demands, and this will influence the integrality of input signal to a certain extent.
Summary of the invention
Technical problem to be solved by this invention provides a kind of hysteresis comparator of self adaptation input, has improved the scope of application of input signal, thereby has not needed excessively to limit the integrality that input signal has guaranteed input signal.
For solving the problems of the technologies described above, the hysteresis comparator of self adaptation input of the present invention comprises first order amplification module, positive feedback module, the single-ended output module of both-end input commentaries on classics, output driver module, and its particular circuit configurations is:
The grid of transistor one connects bias voltage one, source ground;
The grid of transistor two connects bias voltage two, and source electrode connects operating voltage;
The grid of transistor three connects positive input terminal, and source electrode connects the drain electrode of transistor one;
The grid of transistor four connects positive input terminal, and source electrode connects the drain electrode of transistor two;
The grid of transistor five connects negative input end, and source electrode connects the drain electrode of transistor two;
The grid of transistor six connects negative input end, and source electrode connects the drain electrode of transistor one;
The grid of transistor seven connects the drain electrode of transistor four M4, the source ground of transistor seven;
The grid of transistor eight and the drain electrode that drains and link to each other and meet transistor four M4, the source ground of transistor eight;
The grid of transistor nine and the drain electrode that drains and link to each other and meet transistor five M5, the source ground of transistor nine;
The grid of transistor ten connects the drain electrode of transistor five M5, the source ground of transistor ten;
The grid of transistor 11 links to each other with drain electrode and connects the drain electrode of transistor three and the drain electrode of transistor ten, and the source electrode of transistor 11 connects operating voltage;
The grid of transistor 12 links to each other with drain electrode and connects the drain electrode of transistor six and the drain electrode of transistor seven, and the source electrode of transistor 12 connects operating voltage;
The grid of transistor 13 links to each other source ground with drain electrode;
The drain electrode of transistor 14 links to each other with the grid of transistor 13, the source ground of transistor 14;
The grid of transistor 15 links to each other with the grid of transistor 13, and the drain electrode of transistor 15 links to each other with the grid of transistor 14, the source ground of transistor 15;
The grid of transistor 16 links to each other with drain electrode and links to each other the source ground of transistor 16 with the grid of transistor 14;
The grid of transistor 17 links to each other with the drain electrode of transistor three, and the drain electrode of transistor 17 links to each other with the grid of transistor 13, and the source electrode of transistor 17 connects operating voltage;
The grid of transistor 18 links to each other with the drain electrode of transistor six, and the drain electrode of transistor 18 links to each other with the grid of transistor 14, and the source electrode of transistor 18 connects operating voltage;
The grid of transistor 19 connects bias voltage three, source ground;
The grid of transistor 20 links to each other with the grid of transistor 13, and the source electrode of transistor 20 links to each other with the drain electrode of transistor 19;
The grid of transistor 21 links to each other with the grid of transistor 14, and the source electrode of transistor 21 links to each other with the drain electrode of transistor 19;
The grid of transistor 22 links to each other and links to each other with the drain electrode of transistor 20 with drain electrode, and the source electrode of transistor 22 connects operating voltage;
The grid of transistor 23 links to each other with the drain electrode of transistor 20, and the drain electrode of transistor 23 links to each other with the drain electrode of transistor 21, and the source electrode of transistor 23 connects operating voltage;
The grid of transistor 24 links to each other with the drain electrode of transistor 21, the source ground of transistor 24;
The grid of transistor 25 links to each other with the drain electrode of transistor 21, and the drain electrode of transistor 25 links to each other with the drain electrode of transistor 24, and the source electrode of transistor 25 connects operating voltage;
The grid of transistor 26 links to each other with the drain electrode of transistor 24, the source ground of transistor 26;
The grid of transistor 27 links to each other with the drain electrode of transistor 24, and the drain electrode of the drain electrode of transistor 27 and transistor 26 links to each other and as signal output part, the source electrode of transistor 27 connects operating voltage;
Said first order amplification module comprises transistor one to transistor 12; The positive feedback module comprises transistor 13 to transistor 18; The both-end input is changeed single-ended output module and is comprised transistor 19 to transistor 23, and the output driver module comprises transistor 24 to transistor 27.
Hysteresis comparator of the present invention is compared with traditional hysteresis comparator; In first order amplification module, being provided with the NMOS input imports (being made up of two PMOS) (being made up of two NMOS) and PMOS; Thereby has a bigger input range; Do not need excessively to limit the signal amplitude of prime, thereby guaranteed the integrality of prime signal, help the steady operation that demodulation also helps system.
Description of drawings
Fig. 1 is the concrete realization circuit of existing hysteresis comparator;
Fig. 2 is the concrete realization circuit of hysteresis comparator of the present invention.
Description of reference numerals among the figure:
N1～N20 is respectively transistor one a to transistor 20; M1～M27 is respectively transistor one to transistor 27; IN+, IN-are the input of a pair of differential signal; OUT is a signal output part; VB1～VB3 is respectively bias voltage one to bias voltage three.
Embodiment
See also Fig. 2, the hysteresis comparator of self adaptation input of the present invention comprises first order amplification module, positive feedback module, the single-ended output module of both-end input commentaries on classics, output driver module, and its particular circuit configurations is:
The grid of transistor one M1 connects bias voltage one VB1, source ground;
The grid of transistor two M2 meets bias voltage two VB2, and source electrode meets operating voltage VDD;
The grid of transistor three M3 meets positive input terminal IN+, and source electrode connects the drain electrode of transistor one M1;
The grid of transistor four M4 meets positive input terminal IN+, and source electrode connects the drain electrode of transistor two M2;
The grid of transistor five M5 meets negative input end IN-, and source electrode connects the drain electrode of transistor two M2;
The grid of transistor six M6 meets negative input end IN-, and source electrode connects the drain electrode of transistor one M1;
The grid of transistor seven M7 connects the drain electrode of transistor four M4, the source ground of transistor seven M7;
The grid of transistor eight M8 and the drain electrode that drains and link to each other and meet transistor four M4, the source ground of transistor eight M8;
The grid of transistor nine M9 and the drain electrode that drains and link to each other and meet transistor five M5, the source ground of transistor nine M9;
The grid of transistor ten M10 connects the drain electrode of transistor five M5, the source ground of transistor ten M10;
The grid of transistor 11 M11 links to each other with drain electrode and connects the drain electrode of transistor three M3 and the drain electrode of transistor ten M10, and the source electrode of transistor 11 M11 meets operating voltage VDD;
The grid of transistor 12 M12 links to each other with drain electrode and connects the drain electrode of transistor six M6 and the drain electrode of transistor seven M7, and the source electrode of transistor 12 M12 meets operating voltage VDD;
The grid of transistor 13 M13 links to each other source ground with drain electrode;
The drain electrode of transistor 14 M14 links to each other with the grid of transistor 13 M13, the source ground of transistor 14 M14;
The grid of transistor 15 M15 links to each other with the grid of transistor 13 M13, and the drain electrode of transistor 15 M15 links to each other with the grid of transistor 14 M14, the source ground of transistor 15 M15;
The grid of transistor 16 M16 links to each other with drain electrode and links to each other the source ground of transistor 16 M16 with the grid of transistor 14 M14;
The grid of transistor 17 M17 links to each other with the drain electrode of transistor three M3, and the drain electrode of transistor 17 M17 links to each other with the grid of transistor 13 M13, and the source electrode of transistor 17 M17 meets operating voltage VDD;
The grid of transistor 18 M18 links to each other with the drain electrode of transistor six M6, and the drain electrode of transistor 18 M18 links to each other with the grid of transistor 14 M14, and the source electrode of transistor 18 M18 meets operating voltage VDD;
The grid of transistor 19 M19 connects bias voltage three VB3, source ground;
The grid of transistor 20 M20 links to each other with the grid of transistor 13 M13, and the source electrode of transistor 20 M20 links to each other with the drain electrode of transistor 19 M19;
The grid of transistor 21 M21 links to each other with the grid of transistor 14 M14, and the source electrode of transistor 21 M21 links to each other with the drain electrode of transistor 19 M19;
The grid of transistor 22 M22 links to each other and links to each other with the drain electrode of transistor 20 M20 with drain electrode, and the source electrode of transistor 22 M22 meets operating voltage VDD;
The grid of transistor 23 M23 links to each other with the drain electrode of transistor 20 M20, and the drain electrode of transistor 23 M23 links to each other with the drain electrode of transistor 21 M21, and the source electrode of transistor 23 M23 meets operating voltage VDD;
The grid of transistor 24 M24 links to each other with the drain electrode of transistor 21 M21, the source ground of transistor 24 M24;
The grid of transistor 25 M25 links to each other with the drain electrode of transistor 21 M21, and the drain electrode of transistor 25 M25 links to each other with the drain electrode of transistor 24 M24, and the source electrode of transistor 25 M25 meets operating voltage VDD;
The grid of transistor 26 M26 links to each other with the drain electrode of transistor 24 M24, the source ground of transistor 26 M26;
The grid of transistor 27 M27 links to each other with the drain electrode of transistor 24 M24, and the drain electrode of the drain electrode of transistor 27 M27 and transistor 26 M26 links to each other and as signal output part OUT, the source electrode of transistor 27 M27 meets operating voltage VDD.
Wherein, First order amplification module comprises that transistor one M1 is to transistor 12 M12; The positive feedback module comprises that transistor 13 M13 are to transistor 18 M18; The both-end input is changeed single-ended output module and is comprised transistor 19 M19 to transistor 23 M23, and the output driver module comprises that transistor 24 M24 are to transistor 27 M27.
Wherein, transistor one M1, transistor three M3, transistor six M6, transistor seven M7, transistor eight M8, transistor nine M9, transistor ten M10, transistor 13 M13, transistor 14 M14, transistor 15 M15, transistor 16 M16, transistor 19 M19, transistor 20 M20, transistor 21 M21, transistor 24 M24, transistor 26 M26 are nmos pass transistor.
Wherein, transistor two M2, transistor four M4, transistor five M5, transistor 11 M11, transistor 12 M12, transistor 17 M17, transistor 18 M18, transistor 22 M22, transistor 23 M23, transistor 25 M25, transistor 27 M27 are the PMOS transistor.
The operation principle of hysteresis comparator according to the invention is following: first order amplification module amplifies a pair of differential input signal, and its output voltage is input in the positive feedback module.The positive feedback module is handled signal, produces sluggish effect, and its output is input to the both-end input to be changeed in the single-ended output module.Two conversion of signals that the single-ended output module of both-end input commentaries on classics will be imported become single-ended output signal, deliver at last in the output driver module.Last comparison signal is by the output of output driver module.
Particularly, in the first order amplification module, bias voltage one VB1, bias voltage two VB2 are respectively from transistor one M1 (NMOS), transistor two M2 (PMOS) input, thereby stable operating current are provided for this module.Input adopts the NMOS input to importing common input with PMOS, and said NMOS input is to being made up of transistor three M3 and transistor six M6, and said PMOS input is to being made up of transistor four M4 and transistor five M5.When input signal is big mainly by the NMOS input to handling, when running into less signal mainly by the PMOS input to handling, when signal amplitude is moderate by the NMOS input to the PMOS input to common processing.The NMOS input is to offering load (transistor 11 M11 and transistor 13 M13 that diode connects for the signal of handling; Said diode connects and refers to that transistorized grid links to each other with drain electrode); And the PMOS input has so just been integrated two inputs and has been handled the back signal for offering load transistor eight M8 and transistor nine M9 that diode is connected equally behind the signal process current mirror of handling (transistor seven M7 and transistor ten M10).As the drain terminal of transistor 11 M11 of load and transistor 13 M13 as output.
In the positive feedback module with transistor 17 M17, transistor 18 M18 (being PMOS) as input; Transistor 13 M13 of employing diode connected mode and transistor 16 M16 are as load, and the grid interconnection of transistor 14 M14 and transistor 15 M15 is as positive feedback.The breadth length ratio of transistor 14 M14 and transistor 15 M15 is greater than the breadth length ratio of transistor 13 M13 and transistor 16 M16 in the concrete design process, can produce sluggish effect preferably like this.The input signal of single-ended output module is imported in the drain electrode of transistor 13 M13 and transistor 16 M16 as both-end.Both-end input is changeed single-ended output module and is converted two input signals to single-ended output signal and be input in the output driver module, through being exactly the output of whole hysteresis comparator behind the output driver module.
In hysteresis comparator circuit, we suppose that operating voltage VDD is 2V, threshold voltage V ThBe 0.5V, overdrive voltage V OdBe 0.2V, in so traditional hysteresis comparator circuit, the scope of input signal is exactly 0.9-1.8V, too too small signal, and NMOS imports intractable.And in the circuit of hysteresis comparator of the present invention; The right input reference signal of NMOS input remains 0.9-1.8V; And the right input reference signal of PMOS input is 0.2-1.1V; So the scope of the input signal of whole hysteresis comparator is 0.2-1.8V, effectively increased the scope of input signal, solved prime signal problem bigger than normal to a certain extent.
The electric current that the hesitation of following surface analysis positive feedback module, let flow are crossed transistor 17 M17 is I 17, the drain terminal voltage of transistor 17 M17 is V+, the electric current that flows through transistor 18 M18 is I 18, the drain terminal voltage of transistor 18 M18 is V-.If I 17Much larger than I 18, transistor 13 M13 and transistor 15 M15 conductings, transistor 14 M14 and transistor 16 M16 end, then I 17=I 13+ I 15, I 18=I 14+ I 16, this moment, V-was approximately 0, and the voltage of V+ is by the grid voltage V of transistor 13 M13 Gs13Decision:
Figure BDA0000037103890000111
Work as I 18Electric current increases and I 17Electric current when reducing, I 17The reduction that reduces to cause V+, the reduction of V+ finally can cause the output state of circuit to change, and makes transistor 15 M15 end, critical current is following when occurring in critical transition status:
Figure BDA0000037103890000112
So obtain:
Figure BDA0000037103890000121
When deriving conversely,
Figure BDA0000037103890000122
And β 14=β 15, β 13=β 16If β 15Be not equal to β 13, comparator just has hesitation so.
Though the present invention utilizes concrete embodiment to describe, the explanation of embodiment is not limit the scope of the invention.The one skilled in the art, carries out various modifications easily and perhaps can make up embodiment under the situation that does not deviate from the spirit and scope of the present invention through with reference to explanation of the present invention.

Claims (3)

1. the hysteresis comparator of a self adaptation input is characterized in that, comprises first order amplification module, positive feedback module, the single-ended output module of both-end input commentaries on classics, output driver module, and its particular circuit configurations is:
The grid of transistor one connects bias voltage one, source ground;
The grid of transistor two connects bias voltage two, and source electrode connects operating voltage;
The grid of transistor three connects positive input terminal, and source electrode connects the drain electrode of transistor one;
The grid of transistor four connects positive input terminal, and source electrode connects the drain electrode of transistor two;
The grid of transistor five connects negative input end, and source electrode connects the drain electrode of transistor two;
The grid of transistor six connects negative input end, and source electrode connects the drain electrode of transistor one;
The grid of transistor seven connects the drain electrode of transistor four M4, the source ground of transistor seven;
The grid of transistor eight and the drain electrode that drains and link to each other and meet transistor four M4, the source ground of transistor eight;
The grid of transistor nine and the drain electrode that drains and link to each other and meet transistor five M5, the source ground of transistor nine;
The grid of transistor ten connects the drain electrode of transistor five M5, the source ground of transistor ten;
The grid of transistor 11 links to each other with drain electrode and connects the drain electrode of transistor three and the drain electrode of transistor ten, and the source electrode of transistor 11 connects operating voltage;
The grid of transistor 12 links to each other with drain electrode and connects the drain electrode of transistor six and the drain electrode of transistor seven, and the source electrode of transistor 12 connects operating voltage;
The grid of transistor 13 links to each other source ground with drain electrode;
The drain electrode of transistor 14 links to each other with the grid of transistor 13, the source ground of transistor 14;
The grid of transistor 15 links to each other with the grid of transistor 13, and the drain electrode of transistor 15 links to each other with the grid of transistor 14, the source ground of transistor 15;
The grid of transistor 16 links to each other with drain electrode and links to each other the source ground of transistor 16 with the grid of transistor 14;
The grid of transistor 17 links to each other with the drain electrode of transistor three, and the drain electrode of transistor 17 links to each other with the grid of transistor 13, and the source electrode of transistor 17 connects operating voltage;
The grid of transistor 18 links to each other with the drain electrode of transistor six, and the drain electrode of transistor 18 links to each other with the grid of transistor 14, and the source electrode of transistor 18 connects operating voltage;
The grid of transistor 19 connects bias voltage three, source ground;
The grid of transistor 20 links to each other with the grid of transistor 13, and the source electrode of transistor 20 links to each other with the drain electrode of transistor 19;
The grid of transistor 21 links to each other with the grid of transistor 14, and the source electrode of transistor 21 links to each other with the drain electrode of transistor 19;
The grid of transistor 22 links to each other and links to each other with the drain electrode of transistor 20 with drain electrode, and the source electrode of transistor 22 connects operating voltage;
The grid of transistor 23 links to each other with the drain electrode of transistor 20, and the drain electrode of transistor 23 links to each other with the drain electrode of transistor 21, and the source electrode of transistor 23 connects operating voltage;
The grid of transistor 24 links to each other with the drain electrode of transistor 21, the source ground of transistor 24;
The grid of transistor 25 links to each other with the drain electrode of transistor 21, and the drain electrode of transistor 25 links to each other with the drain electrode of transistor 24, and the source electrode of transistor 25 connects operating voltage;
The grid of transistor 26 links to each other with the drain electrode of transistor 24, the source ground of transistor 26;
The grid of transistor 27 links to each other with the drain electrode of transistor 24, and the drain electrode of the drain electrode of transistor 27 and transistor 26 links to each other and as signal output part, the source electrode of transistor 27 connects operating voltage;
Said first order amplification module comprises transistor one to transistor 12; The positive feedback module comprises transistor 13 to transistor 18; The both-end input is changeed single-ended output module and is comprised transistor 19 to transistor 23, and the output driver module comprises transistor 24 to transistor 27.
2. the hysteresis comparator of self adaptation input according to claim 1; It is characterized in that said transistor one, transistor three, transistor six, transistor seven, transistor eight, transistor nine, transistor ten, transistor 13, transistor 14, transistor 15, transistor 16, transistor 19, transistor 20, transistor 21, transistor 24, transistor 26 are nmos pass transistor;
Said transistor two, transistor four, transistor five, transistor 11, transistor 12, transistor 17, transistor 18, transistor 22, transistor 23, transistor 25, transistor 27 are the PMOS transistor.
3. the hysteresis comparator of self adaptation input according to claim 2; It is characterized in that; Comprise the NMOS input in the said first order amplification module to right with the PMOS input, said NMOS input is to being made up of transistor three and transistor six, and said PMOS input is to being made up of transistor four and transistor five.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104579202A (en) * 2014-12-30 2015-04-29 上海贝岭股份有限公司 Triangular wave comparator circuit
CN104935310A (en) * 2015-06-03 2015-09-23 湖南进芯电子科技有限公司 Novel hysteresis comparator applied to multivibrator
CN105958983A (en) * 2016-04-25 2016-09-21 华中科技大学 Voltage comparator suitable for blood oxygen saturation detection
CN110635790A (en) * 2019-11-13 2019-12-31 中国电子科技集团公司第五十八研究所 Voltage type hysteresis comparator

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CN1949668A (en) * 2006-10-25 2007-04-18 华中科技大学 Retarding comparator circuit of single terminal input
CN101013884A (en) * 2006-11-24 2007-08-08 华中科技大学 Unilateral hysteresis comparator
CN201018463Y (en) * 2006-11-24 2008-02-06 华中科技大学 Single side lagging comparators

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US6133764A (en) * 1999-01-27 2000-10-17 Motorola, Inc. Comparator circuit and method
CN1949668A (en) * 2006-10-25 2007-04-18 华中科技大学 Retarding comparator circuit of single terminal input
CN101013884A (en) * 2006-11-24 2007-08-08 华中科技大学 Unilateral hysteresis comparator
CN201018463Y (en) * 2006-11-24 2008-02-06 华中科技大学 Single side lagging comparators

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104579202A (en) * 2014-12-30 2015-04-29 上海贝岭股份有限公司 Triangular wave comparator circuit
CN104935310A (en) * 2015-06-03 2015-09-23 湖南进芯电子科技有限公司 Novel hysteresis comparator applied to multivibrator
CN104935310B (en) * 2015-06-03 2018-05-18 湖南进芯电子科技有限公司 New hysteresis comparator applied to multivibrator
CN105958983A (en) * 2016-04-25 2016-09-21 华中科技大学 Voltage comparator suitable for blood oxygen saturation detection
CN105958983B (en) * 2016-04-25 2018-11-30 华中科技大学 A kind of voltage comparator suitable for blood oxygen saturation detection
CN110635790A (en) * 2019-11-13 2019-12-31 中国电子科技集团公司第五十八研究所 Voltage type hysteresis comparator
CN110635790B (en) * 2019-11-13 2021-12-14 中国电子科技集团公司第五十八研究所 Voltage type hysteresis comparator

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