CN111679710A - Voltage difference detection circuit and low voltage difference linear voltage stabilizer - Google Patents
Voltage difference detection circuit and low voltage difference linear voltage stabilizer Download PDFInfo
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention provides a pressure difference detection circuit and a low-dropout linear regulator, wherein the pressure difference detection circuit utilizes an inherent error amplifier in the structure of the low-dropout linear regulator, combines a detection branch consisting of a few additionally added components, and can judge the difference change of the input voltage of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator according to the level change of a detection signal output by the detection branch, thereby realizing the abnormal monitoring of the input voltage of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator, abandoning a sampling circuit and a comparison circuit required in the prior art, having simple circuit structure and reducing the power consumption and the cost; meanwhile, the difference value between the input voltage of the low dropout linear regulator and the output voltage of the low dropout linear regulator is detected, and a detection circuit does not need to be designed for the input voltage of the low dropout linear regulator and the output voltage of the low dropout linear regulator, so that the power consumption and the cost are further reduced.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a voltage difference detection circuit and a low-voltage difference linear voltage regulator.
Background
The linear regulator integrated circuit reduces the voltage from a higher level to a lower level without the need for an inductor. A low dropout linear regulator (LDO) is a special type of linear regulator, the difference between the input voltage and the output voltage of which is typically below 400 mV. The low dropout linear regulator has a relatively simple circuit design, is a micro-power consumption linear regulator, generally has extremely low self-noise and a high power supply rejection ratio, and is widely applied to the technical field of power supply management.
However, the input voltage or the load may change to cause the output voltage to change, which affects the stability of the output voltage. At present, the voltage monitoring design technology for the low dropout linear regulator is mature, and the monitoring voltage is mainly sampled and compared with the reference voltage through a comparator, so that the level of an alarm signal is turned over. This is usually realized by additional device modules such as a sampling circuit and a comparator, and a corresponding monitoring circuit needs to be designed for each voltage, which undoubtedly increases the power consumption of the circuit for a low dropout linear regulator with low power consumption.
Disclosure of Invention
In view of the above-mentioned shortcomings of the conventional technologies, the present invention provides a design solution for a differential pressure detection circuit, which is used to solve the above-mentioned technical problems.
In order to achieve the above and other related objects, the present invention provides a voltage difference detection circuit for detecting a difference between an input voltage and an output voltage of a low dropout regulator, including a first detection branch, a second detection branch, and a third detection branch, where the first detection branch, the second detection branch, and the third detection branch are respectively connected between the input voltage of the low dropout regulator and ground, the second detection branch is electrically connected to the third detection branch, the second detection branch is electrically connected to an output terminal of an error amplifier in the low dropout regulator, the third detection branch outputs a detection signal, and the second detection branch adjusts and controls the detection signal according to the difference between the input voltage of the low dropout regulator and the output voltage of the low dropout regulator.
Optionally, first detection branch road is including the first resistance, triode, second resistance, first MOS pipe and the second MOS pipe that concatenate in proper order, the one end of first resistance connects the input voltage of low dropout linear regulator, the other end of first resistance connects simultaneously the base and the collecting electrode of triode, the projecting pole of triode connects the one end of second resistance, another termination of second resistance the drain electrode of first MOS pipe, the grid of first MOS pipe connects the reference voltage of low dropout linear regulator, the source electrode of first MOS pipe connects the drain electrode of second MOS pipe, the grid of second MOS pipe connects offset voltage, the source electrode ground connection of second MOS pipe.
Optionally, the second detection branch includes a third MOS transistor and a fourth MOS transistor connected in series in sequence, a source of the third MOS transistor is connected to the base of the triode, a gate of the third MOS transistor is connected to the output end of the error amplifier in the low dropout linear regulator, a drain of the third MOS transistor is connected to a drain of the fourth MOS transistor, a gate of the fourth MOS transistor is connected to the bias voltage, and a source of the fourth MOS transistor is grounded.
Optionally, the third detection branch includes a fifth MOS transistor and a sixth MOS transistor connected in series in sequence, the source of the fifth MOS transistor is connected to the input voltage of the low dropout linear regulator, the drain of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the gate of the sixth MOS transistor is connected to the bias voltage, and the source of the sixth MOS transistor is grounded.
Optionally, the third detection branch further includes a first inverter and a second inverter connected in series in sequence, an input end of the first inverter is connected to the drain of the fifth MOS transistor, an output end of the first inverter is connected to an input end of the second inverter, and an output end of the second inverter outputs the detection signal.
Optionally, the voltage difference detection circuit further includes a third resistor and a seventh MOS transistor, one end of the third resistor is connected to the drain of the third MOS transistor, the other end of the third resistor is connected to the gate of the seventh MOS transistor, the drain of the seventh MOS transistor is connected to the gate of the fifth MOS transistor, and the source of the seventh MOS transistor is grounded.
Optionally, the differential pressure detection circuit further includes a first capacitor and a second capacitor, one end of the first capacitor is connected to the gate of the seventh MOS transistor, the other end of the first capacitor is grounded, one end of the second capacitor is connected to the gate of the fifth MOS transistor, and the other end of the second capacitor is grounded.
Optionally, the voltage difference detection circuit further comprises a bias sub-circuit, which provides the bias voltage.
Optionally, the triode is an NPN triode, the first MOS transistor, the second MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are NMOS transistors, and the third MOS transistor and the fifth MOS transistor are PMOS transistors.
In addition, to achieve the above and other related objects, the present invention provides a low dropout regulator including the dropout detection circuit described in any one of the above.
As described above, the differential pressure detection circuit of the present invention has the following advantageous effects:
the second detection branch and the third detection branch are added on the basis of the existing error amplifier in the low dropout linear regulator, the second detection branch is electrically connected with the output end of the error amplifier in the low dropout linear regulator, the second detection branch is electrically connected with the third detection branch, the second detection branch and the third detection branch are respectively connected between the input voltage of the low dropout linear regulator and the ground, the second detection branch adjusts and controls the detection signal output by the third detection branch according to the difference value of the input voltage of the low dropout linear regulator and the output voltage of the low dropout linear regulator, the difference value change of the input voltage of the low dropout linear regulator and the output voltage of the low dropout linear regulator can be judged according to the level change of the detection signal, the circuit structure of the whole voltage difference detection circuit is simple, and no additional sampling circuit and comparison circuit are needed, the power consumption and the cost are reduced; meanwhile, the circuit detects the difference value between the input voltage of the low dropout linear regulator and the output voltage of the low dropout linear regulator, and a detection circuit does not need to be designed for the input voltage of the low dropout linear regulator and the output voltage of the low dropout linear regulator respectively, so that the power consumption and the cost are further reduced.
Drawings
Fig. 1 is a schematic circuit diagram of a voltage difference detection circuit according to an embodiment of the present invention.
Fig. 2 is a simulation diagram of the output voltage Vout of the low dropout regulator including the voltage difference detection circuit shown in fig. 1 according to the difference between the input voltage VDD and the output voltage Vout.
Fig. 3 is a simulation diagram showing the variation of the detection signal ERR output by the voltage difference detection circuit in fig. 2 with the difference between the input voltage VDD and the output voltage Vout.
Description of the reference numerals
R1-first resistor, R2-second resistor, R3-third resistor, M1-first MOS tube, M2-second MOS tube, M3-third MOS tube, M4-fourth MOS tube, M5-fifth MOS tube, M6-sixth MOS tube, M7-seventh MOS tube, INV 1-first inverter, INV 2-second inverter, C1-first capacitor, C2-second capacitor, EA-error amplifier in low dropout linear regulator, BIAS-BIAS sub-circuit, GND-ground, V-voltage regulatorFB-feedback voltage in low dropout linear regulator, VREF-reference voltage in low dropout linear regulator, VDD-input voltage in low dropout linear regulator, ERR-detect signal, I1-first current, I2-second current, I3-third current.
Detailed Description
As described in the background art, the current voltage detection scheme for the input voltage and the output voltage of the low dropout linear regulator has a complex circuit design structure, requires an additional sampling circuit and a comparison circuit, and has high power consumption and high cost; meanwhile, the detection circuits need to be designed respectively for the input voltage and the output voltage, so that power consumption and cost are further increased.
Based on this, the invention provides a voltage difference detection circuit for the input voltage and the output voltage of the low dropout regulator, which adds a detection branch circuit on the basis of the existing error amplifier in the low dropout regulator, and carries out the critical point detection on the input voltage of the low dropout regulator and the output of the error amplifier in the low dropout regulator, and the output of the error amplifier is related to the output voltage of the low dropout regulator (when the reference voltage is constant), thereby indirectly realizing the critical point detection of the difference value between the input voltage of the low dropout regulator and the output voltage of the low dropout regulator.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy or attainment of the same purpose, are intended to fall within the scope of the present disclosure.
As shown in fig. 1, the present invention provides a voltage difference detection circuit for detecting a difference between an input voltage VDD and an output voltage Vout of a low dropout regulator, including a first detection branch, a second detection branch, and a third detection branch, where the first detection branch, the second detection branch, and the third detection branch are respectively connected between the input voltage VDD and a ground GND of the low dropout regulator, the second detection branch is electrically connected to the third detection branch, the second detection branch is electrically connected to an output terminal of an error amplifier EA of the low dropout regulator, the third detection branch outputs a detection signal ERR, and the second detection branch adjusts and controls the detection signal ERR according to the difference between the input voltage VDD of the low dropout regulator and the output voltage Vout of the low dropout regulator.
In detail, as shown in fig. 1, the first detection branch includes a first resistor R1, a triode Q1, a second resistor R2, a first MOS transistor M1 and a second MOS transistor M2 connected in series in sequence, one end of the first resistor R1 is connected to the input voltage VDD of the low dropout linear regulator, the other end of the first resistor R1 is connected to the base and collector of the triode Q1, the emitter of the triode Q1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the first MOS transistor M1, the gate of the first MOS transistor M1 is connected to the reference voltage V of the low dropout linear regulatorREFThe source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the gate of the second MOS transistor M2 is connected to the bias voltage, and the source of the second MOS transistor M2 is grounded GND.
In detail, as shown in fig. 1, the second detection branch includes a third MOS transistor M3 and a fourth MOS transistor M4 connected in series in sequence, a source of the third MOS transistor M3 is connected to a base of the triode Q1, a gate of the third MOS transistor M3 is connected to an output terminal of the error amplifier EA in the low dropout linear regulator, a drain of the third MOS transistor M3 is connected to a drain of the fourth MOS transistor M4, a gate of the fourth MOS transistor M4 is connected to a bias voltage, and a source of the fourth MOS transistor M4 is grounded GND.
In detail, as shown in fig. 1, the third detection branch includes a fifth MOS transistor M5 and a sixth MOS transistor M6 connected in series in sequence, a source of the fifth MOS transistor M5 is connected to the input voltage VDD of the low dropout linear regulator, a drain of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6, a gate of the sixth MOS transistor M6 is connected to the bias voltage, and a source of the sixth MOS transistor M6 is grounded GND.
In detail, as shown in fig. 1, the third detection branch further includes a first inverter INV1 and a second inverter INV2 connected in series in sequence, an input terminal of the first inverter INV1 is connected to a drain of the fifth MOS transistor M5, an output terminal of the first inverter INV1 is connected to an input terminal of the second inverter INV2, and an output terminal of the second inverter INV2 outputs the detection signal ERR.
In detail, as shown in fig. 1, the differential pressure detection circuit further includes a third resistor R3 and a seventh MOS transistor M7, one end of the third resistor R3 is connected to the drain of the third MOS transistor M3, the other end of the third resistor R3 is connected to the gate of the seventh MOS transistor M7, the drain of the seventh MOS transistor M7 is connected to the gate of the fifth MOS transistor M5, and the source of the seventh MOS transistor M7 is grounded to GND.
Optionally, as shown in fig. 1, the differential pressure detection circuit further includes a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected to the gate of the seventh MOS transistor M7, the other end of the first capacitor C1 is connected to the GND, one end of the second capacitor C2 is connected to the gate of the fifth MOS transistor M5, and the other end of the second capacitor C2 is connected to the GND.
Optionally, as shown in fig. 1, the differential voltage detection circuit further includes a BIAS sub-circuit BIAS, which provides BIAS voltages to the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6, and determines magnitudes of the first current I1 flowing through the first detection branch, the second current I2 flowing through the second detection branch, and the third current I3 flowing through the third detection branch. The detailed structure of the BIAS sub-circuit BIAS can refer to the prior art, and is not described herein again.
In detail, as shown in fig. 1, the transistor Q1 is an NPN transistor, the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6 and the seventh MOS transistor M7 are NMOS transistors, and the third MOS transistor M3 and the fifth MOS transistor M5 are PMOS transistors.
It is understood that the types of the transistor Q1, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 may be appropriately changed, that is, the transistor Q1 may be a PNP transistor, the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, and the seventh MOS transistor M7 may also be PMOS transistors, and the third MOS transistor M3 and the fifth MOS transistor M5 may also be NMOS transistors. When the type of the tube is changed, the circuit structure needs to be adjusted accordingly, and the detailed description is omitted here.
In detail, for the low dropout linear regulator, there are two cases that the difference between the input voltage VDD and the output voltage Vout is reduced:
(1) when the input voltage VDD at one end of the adjusting tube is reduced, the output voltage Vout at the other end of the adjusting tube is reduced, and the feedback voltage V connected to the error amplifier EA is reducedFBWith decreasing output voltage VoutThe voltage drop at two ends of the adjusting tube is reduced, so that the output voltage Vout is increased in a phase-changing manner, and finally the output voltage Vout is unchanged; that is to say, when the input voltage VDD decreases, the output voltage Vout is reduced and then restored, and finally the difference between the input voltage VDD and the output voltage Vout decreases accordingly, the output voltage of the error amplifier EA decreases with the decrease of the input voltage VDD, and meanwhile, through the amplification of the error amplifier EA, the reduction range of the output voltage of the error amplifier EA is greater than the reduction range of the input voltage VDD, so that the difference between the input voltage VDD and the output voltage of the error amplifier EA increases with the decrease of the input voltage VDD.
(2) When the output voltage Vout is increased due to abnormal load on the output voltage Vout side, the feedback voltage V of the error amplifier EA is connectedFBThe output voltage Vout is increased along with the increase of the output voltage Vout, so that the output voltage of the error amplifier EA is increased, the current flowing through the adjusting tube is increased, the voltage drop at two ends of the adjusting tube is increased, the output voltage Vout is reduced in a phase-changing manner, and finally the output voltage Vout is unchanged; that is, when the input voltage VDD is not changed and the output voltage Vout is increased, the output voltage Vout is corrected by the feedback loop quickly, and at this time, the difference between the input voltage VDD and the output voltage Vout is reduced instantaneously and then restored quickly without detection.
Therefore, as shown in fig. 1, the entire voltage difference detection circuit mainly detects that the difference between the input voltage VDD and the output voltage Vout is reduced due to the reduction of the input voltage VDD in the low-dropout linear regulator, and the corresponding operation principle is as follows:
1) when the input voltage VDD decreases and the difference between the input voltage VDD and the output voltage of the error amplifier EA is smaller than I1 × R1+ | Vtp |, the first MOS transistor M1 is turned off, neither the second detection branch nor the third detection branch is turned on, and the detection signal ERR output by the third detection branch is at a low level (zero), at this time, the decreased value of the input voltage VDD is acceptable, the low dropout linear regulator operates normally, only the first detection branch is turned on, and the current consumed by the whole dropout detection circuit is the first current I1, where Vtp is the threshold voltage of the first MOS transistor M1 (i.e., the gate-source voltage when the first MOS transistor M1 is turned on);
2) when the input voltage VDD is continuously decreased and the difference between the input voltage VDD and the output voltage of the error amplifier EA is greater than or equal to I1 × R1+ | Vtp |, the first MOS transistor M1 is turned on, the second detection branch and the third detection branch are simultaneously turned on, the detection signal ERR output by the third detection branch is high level, which warns the outside to prompt that the input voltage VDD is lower than the limit value, at this time, the decrease value of the input voltage VDD exceeds a certain range, the low dropout linear regulator operates abnormally, the first detection branch, the second detection branch and the third detection branch are all turned on, and consumed currents include a first current I1 flowing through the first detection branch, a second current I2 flowing through the second detection branch and a third current I3 flowing through the third detection branch.
In more detail, as shown in fig. 1, the minimum value of the input voltage VDD is also determined by the first detection branch: VDD (u)MIN≥(R1+R2)*I1+VBE+VREFVtn, where VDDMINIs the minimum value of the input voltage VDD, VBEThe BE junction voltage of the transistor Q1, Vtn is the threshold voltage of the first MOS transistor M1.
In addition, the invention also provides a low dropout regulator which comprises the voltage difference detection circuit, and the voltage difference detection circuit can detect and warn the difference value of the input voltage VDD and the output voltage Vout in real time.
In detail, to verify the technical effect of the voltage difference detection circuit of the present invention, in an embodiment of the present invention, the output voltage Vout is designed to be 3.3V, and the reference voltage V is designed to beREFAbout 1.2V, the first current I1 is 4 μ A, the second current I2 is 500nA, the third current I3 is 250nA, the first resistor R1 is 77K Ω, the second resistor R2 is 35K Ω, the minimum voltage difference between the input voltage VDD and the output voltage Vout is 130mV, and the detection threshold of the voltage difference between the input voltage VDD and the output voltage Vout is about 170mV, as shown in the simulations of FIGS. 2-3.
In more detail, as shown in fig. 2, when the difference between the input voltage VDD and the output voltage Vout is greater than or equal to 130mV, the output voltage Vout can be stably maintained at 3.3V, that is: when the input voltage VDD is equal to or greater than 3.43V, the output voltage Vout is 3.3V.
In more detail, as shown in fig. 3, when the output voltage Vout is 3.3V and the difference between the input voltage VDD and the output voltage Vout is greater than 173mV, the detection signal ERR is at a low level; when the difference between the input voltage VDD and the output voltage Vout is less than 170mV, the detection signal ERR is at a high level. That is, when the difference between the input voltage VDD and the output voltage Vout is reduced to 170 to 173mV, the detection signal ERR is inverted and changes from low level to high level.
In summary, the voltage difference detection circuit and the low dropout regulator provided by the present invention utilize the inherent error amplifier and the reference voltage in the structure of the low dropout regulator, and combine with the detection branch formed by the additionally added few components, and the difference change between the input voltage of the low dropout regulator and the output voltage of the low dropout regulator can be judged according to the level change of the detection signal output by the detection branch, so as to realize the abnormal monitoring of the input voltage of the low dropout regulator and the output voltage of the low dropout regulator, and the voltage difference detection circuit abandons the sampling circuit and the comparison circuit required in the prior art, has a simple circuit structure, and reduces the power consumption and the cost; meanwhile, the differential pressure detection circuit detects the difference value between the input voltage of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator, and a detection circuit does not need to be designed for the input voltage of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator respectively, so that the power consumption and the cost are further reduced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. The utility model provides a pressure difference detection circuitry detects input voltage and output voltage's difference in the low-dropout linear regulator, its characterized in that, including first detection branch road, second detection branch road and third detection branch road, first detection branch road second detection branch road reaches the third detection branch road connects respectively between the input voltage of low-dropout linear regulator and ground, the second detection branch road with third detection branch road electricity is connected, the second detection branch road with error amplifier's in the low-dropout linear regulator output electricity is connected, the third detects the branch road and exports detected signal, the second detection branch road according to the input voltage of low-dropout linear regulator with the difference adjustment control of the output voltage of low-dropout linear regulator detection signal.
2. The differential pressure detection circuit according to claim 1, wherein the first detection branch comprises a first resistor, a triode, a second resistor, a first MOS transistor and a second MOS transistor connected in series in sequence, one end of the first resistor is connected to the input voltage of the low-voltage-difference linear regulator, the other end of the first resistor is connected to the base and the collector of the triode simultaneously, the emitter of the triode is connected to one end of the second resistor, the other end of the second resistor is connected to the drain of the first MOS transistor, the gate of the first MOS transistor is connected to the reference voltage of the low-voltage-difference linear regulator, the source of the first MOS transistor is connected to the drain of the second MOS transistor, the gate of the second MOS transistor is connected to the bias voltage, and the source of the second MOS transistor is grounded.
3. The voltage difference detection circuit according to claim 2, wherein the second detection branch comprises a third MOS transistor and a fourth MOS transistor connected in series in sequence, a source of the third MOS transistor is connected to a base of the triode, a gate of the third MOS transistor is connected to an output terminal of an error amplifier in the low voltage difference linear regulator, a drain of the third MOS transistor is connected to a drain of the fourth MOS transistor, a gate of the fourth MOS transistor is connected to the bias voltage, and a source of the fourth MOS transistor is grounded.
4. The voltage difference detection circuit according to claim 3, wherein the third detection branch comprises a fifth MOS transistor and a sixth MOS transistor connected in series in sequence, a source of the fifth MOS transistor is connected to the input voltage of the low voltage difference linear regulator, a drain of the fifth MOS transistor is connected to a drain of the sixth MOS transistor, a gate of the sixth MOS transistor is connected to the bias voltage, and a source of the sixth MOS transistor is grounded.
5. The differential pressure detection circuit according to claim 4, wherein the third detection branch further comprises a first inverter and a second inverter connected in series in sequence, an input end of the first inverter is connected to the drain of the fifth MOS transistor, an output end of the first inverter is connected to an input end of the second inverter, and an output end of the second inverter outputs the detection signal.
6. The voltage difference detection circuit according to claim 5, further comprising a third resistor and a seventh MOS transistor, wherein one end of the third resistor is connected to a drain of the third MOS transistor, the other end of the third resistor is connected to a gate of the seventh MOS transistor, a drain of the seventh MOS transistor is connected to a gate of the fifth MOS transistor, and a source of the seventh MOS transistor is grounded.
7. The voltage difference detection circuit according to claim 6, further comprising a first capacitor and a second capacitor, wherein one end of the first capacitor is connected to the gate of the seventh MOS transistor, the other end of the first capacitor is grounded, one end of the second capacitor is connected to the gate of the fifth MOS transistor, and the other end of the second capacitor is grounded.
8. The differential pressure detection circuit of claim 7, further comprising a bias subcircuit that provides the bias voltage.
9. The differential pressure detection circuit according to claim 8, wherein the triode is an NPN triode, the first MOS transistor, the second MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are NMOS transistors, and the third MOS transistor and the fifth MOS transistor are PMOS transistors.
10. A low dropout regulator comprising the voltage difference detection circuit according to any one of claims 1 to 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113325226A (en) * | 2021-05-27 | 2021-08-31 | 上海华岭集成电路技术股份有限公司 | Method for testing voltage drop of low-voltage linear voltage stabilizer |
| CN116500369A (en) * | 2023-06-28 | 2023-07-28 | 深圳安森德半导体有限公司 | Differential voltage detection method for DCDC voltage stabilizer |
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| CN113325226A (en) * | 2021-05-27 | 2021-08-31 | 上海华岭集成电路技术股份有限公司 | Method for testing voltage drop of low-voltage linear voltage stabilizer |
| CN113325226B (en) * | 2021-05-27 | 2024-04-19 | 上海华岭集成电路技术股份有限公司 | Method for testing voltage drop of low-voltage linear voltage stabilizer |
| CN116500369A (en) * | 2023-06-28 | 2023-07-28 | 深圳安森德半导体有限公司 | Differential voltage detection method for DCDC voltage stabilizer |
| CN116500369B (en) * | 2023-06-28 | 2023-09-15 | 深圳安森德半导体有限公司 | DCDC voltage stabilizer voltage detection method |
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