CN113325226B - Method for testing voltage drop of low-voltage linear voltage stabilizer - Google Patents
Method for testing voltage drop of low-voltage linear voltage stabilizer Download PDFInfo
- Publication number
- CN113325226B CN113325226B CN202110587357.4A CN202110587357A CN113325226B CN 113325226 B CN113325226 B CN 113325226B CN 202110587357 A CN202110587357 A CN 202110587357A CN 113325226 B CN113325226 B CN 113325226B
- Authority
- CN
- China
- Prior art keywords
- voltage
- low
- linear
- stabilizer
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 59
- 239000003381 stabilizer Substances 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000010998 test method Methods 0.000 claims description 4
- 238000007405 data analysis Methods 0.000 abstract description 5
- 238000013461 design Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
The invention discloses a method for testing the voltage drop of a low-voltage linear voltage stabilizer, which comprises the following steps: inputting the first input voltage to the low-voltage linear voltage stabilizer, and measuring the first actual output voltage of the low-voltage linear voltage stabilizer; calculating to obtain a second input voltage of the low-voltage linear voltage stabilizer; inputting a second input voltage to the low-voltage linear voltage stabilizer, and measuring a second actual output voltage of the low-voltage linear voltage stabilizer; calculating to obtain a theoretical output voltage; calculating a third input voltage of the low-voltage linear voltage stabilizer; inputting the third input voltage to the low-voltage linear voltage stabilizer, and measuring the third actual output voltage of the low-voltage linear voltage stabilizer; and calculating the difference value between the third input voltage and the third actual output voltage to obtain the actual voltage drop voltage value of the low-voltage linear voltage stabilizer. The invention solves the problems of long test time and complex test data analysis in the prior art by simplifying the test steps, and greatly improves the test convenience and the test efficiency.
Description
Technical Field
The invention relates to the field of electronic design, in particular to a method for testing the voltage drop of a low-voltage linear voltage stabilizer.
Background
In electronic design, different dc voltages are often required to supply different devices, and the most widely used dc voltage output is achieved by a low voltage linear regulator (LDO). The drop-out voltage is one of the most critical parameters for the proper operation of an LDO, which refers to the difference between the input and output voltages that allows an integrated circuit to regulate the output load voltage.
A power supply board card of semiconductor Automatic Test Equipment (ATE) or any signal generator is adopted to generate a ramp wave, the ramp wave is supplied to an input pin of an LDO chip, then a Pin Precision Measurement Unit (PPMU) is adopted to load a specified current load on an output pin of the LDO chip, and a digitizer is adopted to test waveforms of the output pin. These input and output resources are required to work in parallel at the time of testing. Waveforms acquired by the input arbitrary signal generator and the output digitizer must be synchronized. After the test is completed, a post data analysis must be performed to find the point in time when the output voltage (Vout) decreases by 100mV from normal. After this point in time, the corresponding drop voltage value can be calculated. The disadvantage of this conventional test method is that it requires the use of arbitrary signal generators and digitizer channels, increasing the complexity of test development; after the test, the final result can be obtained by data analysis; the test time is longer.
Disclosure of Invention
The invention aims to provide a testing method for the voltage drop of a low-voltage linear voltage stabilizer, which aims to solve the problems of complex process and long testing time of the traditional testing of the voltage drop value of the low-voltage linear voltage stabilizer.
In order to solve the above problems, the present invention provides a method for testing a drop-out voltage of a low-voltage linear voltage regulator, comprising:
inputting a first input voltage to the low-voltage linear voltage stabilizer, and measuring a first actual output voltage of the low-voltage linear voltage stabilizer under a specified load current;
Calculating the difference value between the first actual output voltage and a second set value to obtain a second input voltage of the low-voltage linear voltage stabilizer;
Inputting the second input voltage to the low-voltage linear voltage stabilizer, and measuring a second actual output voltage of the low-voltage linear voltage stabilizer at the specified load current;
calculating to obtain a theoretical output voltage by using the first actual output voltage;
calculating a third input voltage of the low-voltage linear voltage stabilizer by using the second input voltage, the second actual output voltage and the theoretical output voltage;
Inputting the third input voltage to the low-voltage linear voltage stabilizer, and measuring the third actual output voltage of the low-voltage linear voltage stabilizer under the specified load current;
And calculating the difference value between the third input voltage and the third actual output voltage to obtain the actual voltage drop voltage value of the low-voltage linear voltage stabilizer.
Preferably, in the method for testing a drop voltage of a low-voltage linear voltage regulator, the first input voltage is set to a value higher than an output voltage of the low-voltage linear voltage regulator specified in a specification by a first set value.
Preferably, in the method for testing the drop-out voltage of the low-voltage linear voltage regulator, the first set value is 1V.
Preferably, in the method for testing the drop-out voltage of the low-voltage linear voltage regulator, the specified load current is a load current specified in a specification.
Preferably, in the method for testing the drop voltage of the low-voltage linear voltage regulator, the second set value is a drop voltage value specified in the specification.
In the above method for testing the drop voltage of the low-voltage linear voltage regulator, the method for calculating a theoretical output voltage by using the first actual output voltage includes:
And calculating the difference value between the first actual output voltage and a third set value to obtain the theoretical output voltage.
Preferably, in the method for testing the drop-out voltage of the low-voltage linear voltage regulator, the third set value is 0.1V.
Preferably, in the method for testing the drop voltage of the low-voltage linear voltage regulator, the third input voltage is calculated by adopting the following formula:
Vin1-Vout1＝Vin2-Vout；
Wherein V in1 represents the second input voltage; v out1 represents the second actual output voltage; v in2 denotes the third input voltage; v out represents the theoretical output voltage.
Preferably, in the method for testing the drop-out voltage of the low-voltage linear voltage regulator, after obtaining the third actual output voltage, the method further includes:
the inverse k (n-2) of the slope is calculated using the following formula:
Vin(n-1)-Vin(n-2)＝k(n-2)(Vout(n-1)-Vout(n-2))
Wherein V in(n-2) represents the (n-1) -th input voltage, V out(n-2) represents the (n-1) -th actual output voltage, V in(n-1) represents the n-th input voltage, V out(n-1) represents the n-th actual output voltage, and k (n-2) represents the inverse of the slope of the n-th line;
The (n+1) th input voltage of the low-voltage linear voltage regulator is calculated by adopting the following formula:
Vin(n)-Vin(n-2)＝k(n-2)(Vout-Vout(n-2))
Wherein V in(n) represents the (n+1) -th input voltage, and V out represents the theoretical output voltage;
Calculating to obtain V in(n), namely the (n+1) th input voltage;
inputting the (n+1) th input voltage to the low-voltage linear voltage stabilizer, and measuring the (n+1) th actual output voltage of the low-voltage linear voltage stabilizer under the specified load current;
calculating the difference value between the (n+1) th input voltage and the (n+1) th actual output voltage to update the actual voltage drop voltage value of the low-voltage linear voltage stabilizer;
wherein n is a natural number not less than 3.
Preferably, in the method for testing the drop-out voltage of the low-voltage linear voltage regulator, n is equal to 3.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
By simplifying the testing steps and calculating by utilizing the linear relation between the input voltage and the output voltage, the expected testing result is obtained, the problems of long testing time and complex analysis of testing data when the ATE is adopted to test the voltage drop of the LDO chip are solved, and the testing convenience and the testing efficiency are greatly improved.
Drawings
Those skilled in the art will appreciate that the following figures merely illustrate some embodiments of the invention and that other embodiments of the same nature can be obtained by those skilled in the art from these figures without undue effort.
FIG. 1 is a flow chart of obtaining an actual drop voltage according to an embodiment of the invention;
FIG. 2 is a graph showing the relationship between input voltage and output voltage according to the first embodiment of the present invention;
FIG. 3 is a flow chart of updating the actual drop voltage based on the first embodiment of the second embodiment of the present invention;
fig. 4 is a graph showing the relationship between input voltage and output voltage in the second embodiment of the present invention.
Detailed Description
The method for testing the drop-out voltage of the low-voltage linear voltage stabilizer provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various proportions.
[ Example 1]
As shown in fig. 1, the embodiment provides a method for testing the drop-out voltage of a low-voltage linear voltage regulator, which includes the following steps:
S11, inputting a first input voltage to the low-voltage linear voltage stabilizer, and measuring a first actual output voltage of the low-voltage linear voltage stabilizer under a specified load current;
s12, calculating the difference value between the first actual output voltage and a second set value to obtain a second input voltage of the low-voltage linear voltage stabilizer;
S13, inputting the second input voltage to the low-voltage linear voltage stabilizer, and measuring a second actual output voltage of the low-voltage linear voltage stabilizer under the specified load current;
s14, calculating to obtain a theoretical output voltage by using the first actual output voltage;
s15, calculating a third input voltage of the low-voltage linear voltage stabilizer by using the second input voltage, the second actual output voltage and the theoretical output voltage;
s16, inputting the third input voltage to the low-voltage linear voltage stabilizer, and measuring the third actual output voltage of the low-voltage linear voltage stabilizer under the specified load current;
S17, calculating the difference value between the third input voltage and the third actual output voltage to obtain the actual voltage drop value of the low-voltage linear voltage stabilizer.
The above steps are described in further detail below.
In step S11, the first input voltage is set to a value higher than the output voltage of the low-voltage linear regulator specified in the specification by a first set value. According to the conventional test specification, the first set value may be 1V, but it should be noted that the specific setting of the first set value does not limit the present application, for example, in other embodiments, the first set value may be set to 1.1V, 1.2V, or the like according to actual needs.
In a specific application scenario, according to the test specification, the output voltage of the low-voltage linear voltage regulator is 3.3V, so that the first input voltage can be set to 4.3V when the low-voltage linear voltage regulator is tested.
In addition, in step S11, the specified load current may be a load current specified in specifications. According to the test specification, when the output voltage of the low-voltage linear voltage regulator is 3.3V, the load current specified by the specification can be 300mA.
In step S12, the second set value is a drop voltage value specified in the specification.
For example, when the specification specifies a load current of 300mA, the specification specifies a drop voltage value of 130mV.
And when the first input voltage of 4.3V is input to the low-voltage linear voltage stabilizer, the first actual output voltage of the low-voltage linear voltage stabilizer is measured to be 3.303V under the condition that the load current is 300 mA.
And calculating the difference between the first actual output voltage 3.303V and the second set value, wherein the value of the obtained second input voltage is 3.173V.
In step S13, the second input voltage 3.173V is input to the low dropout linear regulator, and the second actual output voltage of the low dropout linear regulator is measured to be 3.048V under the condition that the load current is 300 mA.
In step S14, the method for calculating a theoretical output voltage by using the first actual output voltage may specifically include: and calculating the difference value between the first actual output voltage and a third set value to obtain the theoretical output voltage. The third set point may be set to 0.1V in this embodiment, but it should be noted that the specific setting of the third set point does not limit the present application, for example, in other embodiments, the third set point may be set to 0.2V, 0.3V, etc. according to actual needs, based on the fact that the voltage drop is generally considered to be achieved when the output voltage drops below the nominal value of 100 mV.
Since the first actual output voltage is 3.303V, the theoretical output voltage is 3.203V when the third set value is 0.1V.
In step S15, as shown in fig. 2, the third input voltage may be calculated based on the fact that the low voltage linear voltage regulator has a linear relationship between the actual output voltage and the difference value of the input voltage when the input voltage is changed, and specifically, the third input voltage may be calculated by using the following formula:
Vin1-Vout1＝Vin2-Vout；
Wherein V in1 represents the second input voltage; v out1 represents the second actual output voltage; v in2 denotes the third input voltage; v out represents the theoretical output voltage.
V in1＝3.173V,Vout1＝3.048V,Vout2 = 3.203V at this time; so V in2 = 3.328V, i.e. the third input voltage is 3.328V, can be calculated.
In step S16, the third input voltage of 3.328V is input to the low voltage linear voltage regulator, and the third actual output voltage of the low voltage linear voltage regulator is measured to be 3.196V when the load current is 300 mA.
In step S17, the difference between the third input voltage and the third actual output voltage is calculated, and at this time, the third input voltage is 3.328V, and the third actual output voltage is 3.196V, so as to obtain the actual voltage drop value of the low voltage linear voltage regulator is 132mV.
From the above description, the invention can obtain the expected test result by simplifying the test steps and calculating the linear relation between the input voltage and the output voltage and three times of tests, thereby solving the problems of long test time and complex test data analysis when the ATE is adopted to test the LDO chip voltage drop and greatly improving the test convenience and the test efficiency.
[ Example two ]
On the basis of the first embodiment, in order to obtain the voltage drop voltage of the low-voltage linear voltage regulator with higher precision, as shown in fig. 3, the method for testing the voltage drop voltage of the low-voltage linear voltage regulator according to the embodiment further includes the following steps:
S21, calculating the reciprocal k (n-2) of the slope by adopting the following formula:
Vin(n-1)-Vin(n-2)＝k(n-2)(Vout(n-1)-Vout(n-2))
Wherein V in(n-2) represents the (n-1) -th input voltage, V out(n-2) represents the (n-1) -th actual output voltage, V in(n-1) represents the n-th input voltage, V out(n-1) represents the n-th actual output voltage, and k (n-2) represents the inverse of the slope of the n-th line;
s22, calculating the (n+1) th input voltage of the low-voltage linear voltage stabilizer by adopting the following formula:
Vin(n)-Vin(n-2)＝k(n-2)(Vout-Vout(n-2))
Wherein V in(n) represents the (n+1) -th input voltage;
Calculating to obtain V in(n), namely (n+1) th input voltage;
S23, inputting the (n+1) th input voltage into the low-voltage linear voltage stabilizer, and measuring the (n+1) th actual output voltage of the low-voltage linear voltage stabilizer under the load current;
S24, calculating the difference value between the (n+1) th input voltage and the (n+1) th actual output voltage to update the actual voltage drop voltage value of the low-voltage linear voltage stabilizer. Wherein n is a natural number not less than 3.
The above steps are described in further detail below.
In step S21, the reciprocal k (n-2) of the slope obtained by V in(n-1)-Vin(n-2)＝k(n-2)(Vout(n-1)-Vout(n-2)) is the reciprocal of the slope of the straight line determined by the point (V in(n-1),Vout(n-1) and the point (V in(n-2),Vout(n-2)) in the graph of the input voltage and the output voltage, for example, when n is 3, as shown in fig. 4, the reciprocal k 1 of the slope is the reciprocal of the slope of the straight line determined by the point (V in2,Vout2) and the point (V in1,Vout1) in the graph.
In step S22, V in(n)-Vin(n-2)＝k(n-2)(Vout-Vout(n-2)) the theoretical output voltage V out is substituted into the linear equation obtained in step S21, and then the (n+1) -th input voltage is obtained, for example, as shown in fig. 4, when n is 3, the process of calculating the 4-th input voltage corresponds to the process of substituting the ordinate V out (theoretical output voltage) into the linear equation obtained in step S21, and obtaining the corresponding abscissa V in3.
In step S23, in order to improve the accuracy of the result, the load current should be consistent with the previous load current.
In step S24, the difference between the (n+1) th input voltage and the (n+1) th actual output voltage is calculated, for example, as shown in fig. 4, when n is 3, the actual voltage drop value is the difference between V in3 and V out3, and since the accuracy of the calculation result is higher than that of the previous calculation result, the actual voltage drop value needs to be updated to the calculation result.
In summary, according to the test method for the voltage drop of the low-voltage linear voltage regulator provided by the invention, the test steps are simplified, the linear relation between the input voltage and the output voltage is utilized to calculate, the expected test result is obtained, the problems of long test time and complex test data analysis when the voltage drop of the LDO chip is tested by adopting ATE are solved, and the test convenience and the test efficiency are greatly improved.
In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, so that the same similar parts of each embodiment are referred to each other.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. The method for testing the drop-out voltage of the low-voltage linear voltage stabilizer is characterized by comprising the following steps of:
Inputting a first input voltage to the low-voltage linear voltage stabilizer, and measuring a first actual output voltage of the low-voltage linear voltage stabilizer under a specified load current; the first input voltage is set to be a value higher than the output voltage of the low-voltage linear voltage stabilizer specified by the specification by a first set value;
Calculating the difference value between the first actual output voltage and a second set value to obtain a second input voltage of the low-voltage linear voltage stabilizer; the second set value is a voltage drop voltage value specified by the specification;
Inputting the second input voltage to the low-voltage linear voltage stabilizer, and measuring a second actual output voltage of the low-voltage linear voltage stabilizer at the specified load current;
calculating to obtain a theoretical output voltage by using the first actual output voltage; the theoretical output voltage is equal to the difference value between the first actual output voltage and a third set value;
Calculating a third input voltage of the low-voltage linear voltage stabilizer by using the second input voltage, the second actual output voltage and the theoretical output voltage; the third input voltage is calculated using the following formula: v in1-Vout1＝Vin2-Vout; wherein V in1 represents the second input voltage; v out1 represents the second actual output voltage; v in2 denotes the third input voltage; v out represents the theoretical output voltage;
Inputting the third input voltage to the low-voltage linear voltage stabilizer, and measuring the third actual output voltage of the low-voltage linear voltage stabilizer under the specified load current;
And calculating the difference value between the third input voltage and the third actual output voltage to obtain the actual voltage drop voltage value of the low-voltage linear voltage stabilizer.
2. The method of claim 1, wherein the first set point is 1V.
3. The method for testing the drop-out voltage of a low voltage linear voltage regulator according to claim 1, wherein the specified load current is a canonical load current.
4. The method of testing the drop-out voltage of a low voltage linear regulator of claim 1, wherein the third set point is 0.1V.
5. The method for testing the drop-out voltage of a low voltage linear regulator according to claim 1, wherein after obtaining the third actual output voltage, the method further comprises:
The following formula is used to calculate k (n-2):
Vin(n-1)-Vin(n-2)＝k(n-2)(Vout(n-1)-Vout(n-2))
Wherein V in(n-2) represents the (n-1) -th input voltage, V out(n-2) represents the (n-1) -th actual output voltage, V in(n-1) represents the n-th input voltage, V out(n-1) represents the n-th actual output voltage, and k (n-2) represents the inverse of the slope of the n-th line;
The (n+1) th input voltage of the low-voltage linear voltage regulator is calculated by adopting the following formula:
Vin(n)-Vin(n-2)＝k(n-2)(Vout-Vout(n-2))
Wherein V in(n) represents the (n+1) -th input voltage, and V out represents the theoretical output voltage;
Calculating to obtain V in(n), namely the (n+1) th input voltage;
inputting the (n+1) th input voltage to the low-voltage linear voltage stabilizer, and measuring the (n+1) th actual output voltage of the low-voltage linear voltage stabilizer under the specified load current;
calculating the difference value between the (n+1) th input voltage and the (n+1) th actual output voltage to update the actual voltage drop voltage value of the low-voltage linear voltage stabilizer;
wherein n is a natural number not less than 3.
6. The method of testing the drop-out voltage of a low voltage linear voltage regulator of claim 5, wherein n is equal to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110587357.4A CN113325226B (en) | 2021-05-27 | 2021-05-27 | Method for testing voltage drop of low-voltage linear voltage stabilizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110587357.4A CN113325226B (en) | 2021-05-27 | 2021-05-27 | Method for testing voltage drop of low-voltage linear voltage stabilizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113325226A CN113325226A (en) | 2021-08-31 |
| CN113325226B true CN113325226B (en) | 2024-04-19 |
Family
ID=77421886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110587357.4A Active CN113325226B (en) | 2021-05-27 | 2021-05-27 | Method for testing voltage drop of low-voltage linear voltage stabilizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113325226B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006234655A (en) * | 2005-02-25 | 2006-09-07 | Fuji Electric Device Technology Co Ltd | Linear regulator output voltage measuring device and method |
| CN202676817U (en) * | 2012-05-24 | 2013-01-16 | 深圳创维数字技术股份有限公司 | Low dropout regulator testing device |
| CN111679710A (en) * | 2020-07-08 | 2020-09-18 | 中国电子科技集团公司第二十四研究所 | Voltage difference detection circuit and low voltage difference linear voltage stabilizer |
| CN112649719A (en) * | 2020-11-30 | 2021-04-13 | 成都海光集成电路设计有限公司 | Method, device and equipment for testing linear voltage stabilizer in chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2648012A1 (en) * | 2012-04-06 | 2013-10-09 | Dialog Semiconductor GmbH | On-chip test technique for low drop-out regulators, comprising finite state machine |
-
2021
- 2021-05-27 CN CN202110587357.4A patent/CN113325226B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006234655A (en) * | 2005-02-25 | 2006-09-07 | Fuji Electric Device Technology Co Ltd | Linear regulator output voltage measuring device and method |
| CN202676817U (en) * | 2012-05-24 | 2013-01-16 | 深圳创维数字技术股份有限公司 | Low dropout regulator testing device |
| CN111679710A (en) * | 2020-07-08 | 2020-09-18 | 中国电子科技集团公司第二十四研究所 | Voltage difference detection circuit and low voltage difference linear voltage stabilizer |
| CN112649719A (en) * | 2020-11-30 | 2021-04-13 | 成都海光集成电路设计有限公司 | Method, device and equipment for testing linear voltage stabilizer in chip |
Non-Patent Citations (2)
| Title |
|---|
| LDO芯片CP通用测试方法研究;唐彩彬 等;电子与封装;20171120(第11期);17-20 * |
| 低压差线性调整器通用测试平台的构建;李明明 等;自动化应用;20200325(第03期);100-102 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113325226A (en) | 2021-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0811850B1 (en) | High resolution supply current test system | |
| US6879174B2 (en) | Testing method and testing device for semiconductor integrated circuits | |
| US10436874B2 (en) | Self-calibration of source-measure unit via capacitor | |
| CN100370433C (en) | CPU power estimating method | |
| CN112649719B (en) | Testing method, device and equipment for linear voltage stabilizer in chip | |
| DE102005055836B4 (en) | Performance test plate | |
| CN113325226B (en) | Method for testing voltage drop of low-voltage linear voltage stabilizer | |
| CN103576080A (en) | Chip scanning voltage testing method | |
| CN104880609A (en) | Method for measuring parasitic capacitance of circuit through ATE | |
| US11662372B2 (en) | Measuring input capacitance with automatic test equipment (ATE) | |
| CN220120936U (en) | Chip test circuit and test equipment | |
| US11067623B2 (en) | Test system and method of operating the same | |
| CN113176517A (en) | Micro-current compensation method and system for precise control | |
| CN221149221U (en) | Bipolar power supply output range adjusting circuit suitable for ATE | |
| Aksteiner et al. | Compendium of Current Proton-Induced Radiation Effect Results on Power Regulators | |
| Koniar et al. | Automated Testing of Electronic Devices: Virtual Instrumentation-Based Platform | |
| CN220064275U (en) | Transconductance parameter test circuit and test system | |
| CN109270420B (en) | Method for testing wafer | |
| CN100430738C (en) | Method and circuit arrangement for the self-testing of a reference voltage in electronic components | |
| CN108254672B (en) | Improved pseudo-four-wire test method and test structure thereof | |
| CN112447258B (en) | Method and system for measuring intrinsic breakdown time of flash memory device | |
| Upreti et al. | Post Silicon Characterization of Digital to Analog Converter using Arduino Uno | |
| CN111506986A (en) | Reliability evaluation method for small sample power supply system | |
| Zhang et al. | Research On Embedded Integrated Circuit Test System | |
| Dimitrijević et al. | Virtual instrumentation software applied to integrated circuit testing procedure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |