CN209497443U - A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit - Google Patents
A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit Download PDFInfo
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- CN209497443U CN209497443U CN201822197220.4U CN201822197220U CN209497443U CN 209497443 U CN209497443 U CN 209497443U CN 201822197220 U CN201822197220 U CN 201822197220U CN 209497443 U CN209497443 U CN 209497443U
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Abstract
The utility model provides a kind of low-power consumption positive or negative high voltage and turns low pressure multi-center selection Head switches circuit, it is characterized by: each channel in multichannel includes identical electric resistance partial pressure module, gate control voltage generation module, the first main switch module, the second main switch module and sub- LDO module, the circuit can select required channel by its voltage low pressure for being positive of conversion for back-end circuit processing in multiple positive or negative high voltage channels, can complete switch off the negative pressure in non-selected channel and high pressure and only bring a small amount of additional power consumption.
Description
Technical field
The utility model relates to field of power supplies, turn the choosing of low pressure multichannel in particular to a kind of low-power consumption positive or negative high voltage
Select Head switches circuit.
Background technique
As country steps up production domesticization militay space flight chip demand and requirement, apply to the modulus of military industry field
For converter chip as one of core circuit, the production domesticization of core technology is imperative, since chips many in military industry field are
Positive negative high-voltage input, it is necessary to which converting the low pressure being positive could be handled for rear end analog-digital converter, however, in the positive and negative height of multichannel
When voltage input, China does not grasp the switching technique effectively closed to single channel unlatching, remaining channel yet, this makes in reality
When the multipath A/D converter of existing poll positive or negative high voltage input, using the knot of the corresponding analog-digital converter in a channel
Structure, the power consumption and area of chip are all very big.
Utility model content
In order to solve the above-mentioned technical problem, the utility model proposes following technical schemes:
A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit, each channel Jun Bao in multichannel
Containing identical electric resistance partial pressure module, gate control voltage generation module, the first main switch module, the second main switch module and sub- LDO mould
Block；
In the switching circuit in each channel, the end VIN of electric resistance partial pressure module, gate control voltage generation module the end VIN with
The input voltage VIN n connection of N channel, the end GND of electric resistance partial pressure module, the end GND of the first main switch module, the second master open
Close the end GND of module, the end GND of sub- LDO module, gate control voltage generation module the end GND connect with ground voltage GND, resistance divide
The end VREF_sub of die block, the OUT terminal of the second main switch module, the end VREF_sub of sub- LDO module and gate control voltage generate
The end VREF_sub of module is connected, and the end VIN_L of electric resistance partial pressure module is connect with the end IN of the first main switch module；First is main
The end SEL of switch module, the end SEL of the second main switch module, the end SEL of sub- LDO module and channel selecting signal SELn connect
It connects；The end VREF of first main switch module, the end VREF of the second main switch module, the end VREF of sub- LDO module and reference voltage
VREF connection, output voltage terminal VOUT connection after the OUT terminal of the first main switch module and conversion, the VG_H of the first main switch module
End, the end VG_H of the second main switch module are connect with the end VG_H of gate control voltage generation module, the VG_L of the first main switch module
End, the end VG_L of the second main switch module are connect with the end VG_L of gate control voltage generation module；The vdd terminal of sub- LDO module, grid-control
The vdd terminal of voltage generating module is connect with supply voltage VDD, the end LDO_O of sub- LDO module and the end IN of the second main switch module
Connection, the end VB1 of sub- LDO module are connect with the first bias voltage VB1, the end VB2 of sub- LDO module and the first bias voltage VB2
Connection, the end VB3 of sub- LDO module is connect with the first bias voltage VB3.
Further scheme,
Electric resistance partial pressure module includes resistance R1, resistance R2 and resistance R3；One end of resistance R1 and positive or negative high voltage input signal
VIN connection, the other end of resistance R1, one end of resistance R2, resistance R3 one end with after conversion low pressure input VIN_L be connected
It connects, the other end of resistance R2 is connect with GND, output VREF_ of the other end and reference voltage of resistance R3 after sub- LDO buffering
Sub connection.
Further scheme,
Gate control voltage generation module includes resistance R4, resistance R5, resistance R6, resistance R7, resistance R8 and resistance R9；Resistance R4
One end connect with positive or negative high voltage input signal VIN, the other end of resistance R4, one end of resistance R5, resistance R6 one end with
The voltage VG_L connection of main switch shutdown is controlled, the other end of resistance R5 is connect with GND, the other end and reference voltage of resistance R6
Output VREF_sub connection after sub- LDO buffering；One end of resistance R7 is connect with positive or negative high voltage input signal VIN, resistance
The other end of R7, one end of resistance R8, the voltage VG_H that one end of resistance R9 is opened with control main switch are connect, resistance R8
The other end connect with GND, the other end of resistance R9 is connect with supply voltage VDD.
Further scheme,
Main switch module includes phase inverter INV1 and phase inverter INV2, four p-type metal-oxide-semiconductors be respectively MP1, MP2, MP3 and
MP4, four N-type metal-oxide-semiconductors are respectively MN1, MN2, MN3 and MN4；The wherein power end of phase inverter INV1, the source electrode of MP1 and control
The VG_H connection that sampling switch processed is opened, the ground terminal of phase inverter INV1, the ground terminal of phase inverter INV2, the source electrode of MN4 are electric with ground
GND connection is pressed, the input terminal of phase inverter INV1, the input terminal of phase inverter INV2 are connect with channel selecting signal SEL, phase inverter
The grid of the output end of INV1, the grid of MP1 and MP2 connects；The power end of phase inverter INV2 and externally input reference voltage
VREF connection, the grid connection of the output end of phase inverter INV2, the grid of MN1 and MN2, the drain electrode of MP1 connect with the source electrode of MP2
It connects, the substrate terminal of MP1 and the substrate terminal of MP2 connect, and the drain electrode of drain electrode MN1 of MP2, the grid of MN3 are connected with the grid of MN4
It connects, the drain electrode of the source electrode and MN2 of MN1 connects, and the substrate terminal of MN1 and the substrate terminal of MN2 connect, the drain electrode of MN3 and main switch mould
The drain electrode of the IN connection of block input terminal, the source electrode and MN4 of MN3 connects, and the substrate terminal of MN3 and the substrate terminal of MN4 connect, the source of MN4
Pole is connect with main switch module output end OUT, and the source of MN2, the source electrode of MP3 are connect with the VG_L of control sampling switch shutdown,
The drain electrode of MP3 is connect with the source electrode of MP4, and the substrate terminal of MP3 and the substrate terminal of MP4 connect.
Further scheme,
Sub- LDO module includes a phase inverter INV3, and five p-type metal-oxide-semiconductors are respectively MP5, MP6, MP7, MP8 and MP9, and seven
A N-type metal-oxide-semiconductor is respectively MN5, MN6, MN7, MN8, MN9, MN10 and MN11, a capacitor C1 and a resistance R10；Reverse phase
The power end of device INV3, the source electrode of MP5, the source electrode of MP6, MP9 source electrode connect with power end VDD, the ground terminal of phase inverter INV3,
The source electrode of MN10, the source electrode of MN11 are connect with ground voltage GND, the input terminal of phase inverter INV3, the grid of MN9 and channel selecting
Signal SEL connection, the output end of phase inverter INV3 and the grid of MN11 connect；The drain electrode of the grid of MP5, the grid of MP6, MP8
It is connected with the drain electrode of MN6, the drain electrode of MP5 is connect with the source electrode of MP7, and the drain electrode of MP6 is connect with the source electrode of MP8, the grid of MP7
Pole, MP8 grid connect with the first bias voltage VB1, the drain electrode of MP7, the drain electrode of MN5, MP9 grid and capacitor C1 one end
Connection, the drain electrode of the other end, MN11 of capacitor C1 are connect with LDO output end LDO_O, the grid of MN5, the grid of MN6 and second
The drain electrode of bias voltage VB2 connection, the source electrode of MN5 and MN7 connect, and the drain electrode of the source electrode and MN8 of MN6 connects, the grid of MN7 with
Externally input reference voltage VREF connection, the grid of MN8, one end of resistance R10 and reference voltage are after sub- LDO buffering
Output VREF_sub connection, the other end of resistance R10 connect with ground voltage GND；The source electrode of MN7, the source electrode of MN8 and MN9
The drain electrode of drain electrode connection, the source electrode and MN10 of MN9 connects, and the grid of MN10 is connect with third bias voltage VB3.
Beneficial effect by adopting the above technical scheme is:
(1) the utility model solves the select permeability to positive or negative high voltage input multichannel, and switching circuit can be effectively resistance to
Do not increased extra power consumption without electrical leakage problems by high pressure, negative pressure, while the power consumption of rear end analog-digital converter can be greatlyd save
And area.
(2) gate control signal that key switch is generated by the very high electric resistance partial pressure of resistance value solves high pressure, negative pressure signal
It is switched on and off problem, only increases a small amount of power consumption, while making all metal-oxide-semiconductors of the module using conventional pressure pipe, is saved
Chip manufacturing cost；
(3) reasonable voltage clamping is utilized, caused incomplete shutdown when switch OFF overtension is avoided；
(4) metal-oxide-semiconductor differential concatenation is used, solves the problems, such as substrate leakage, the grid voltage of sampling pipe uses and input voltage phase
The grid voltage of pass biases, and by generating fixed overdrive voltage, improves sampling linearity；
(5) increasing that sub- LDO circuit guarantees will not be by the shadow of input voltage in the end the VREF voltage of core resistor voltage divider circuit
It rings, improves the integrality of sampled signal；
(6) circuit can select required channel that its voltage is converted to the low pressure being positive in multiple positive or negative high voltage channels
For back-end circuit processing, the negative pressure in non-selected channel can be complete switched off and high pressure and only bring a small amount of additional power consumption.
Detailed description of the invention
It, below will be to use required in embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
Attached drawing be briefly described, it should be understood that the following drawings illustrates only some embodiments of the utility model, therefore should not be by
Regard the restriction to range as, for those of ordinary skill in the art, without creative efforts, may be used also
To obtain other relevant attached drawings according to these attached drawings.
It is total that Fig. 1 is that a kind of low-power consumption positive or negative high voltage of the utility model embodiment turns low pressure multi-center selection Head switches circuit
Circuit system block diagram；
Fig. 2 is electric resistance partial pressure module circuit diagram；
Fig. 3 is gate control voltage generation module circuit diagram；
Fig. 4 is main switch module circuit diagram；
Fig. 5 is sub- LDO module circuit diagram；
Fig. 6 (a) and Fig. 6 (b) is 2 main switch modules and sub- LDO module working state figure in practical situations, wherein
Fig. 6 (a) is that the course of work is opened in channel；Fig. 6 (b) is that the course of work is closed in channel.
Specific embodiment
Fig. 1 show multichannel low-power consumption positive or negative high voltage and turns low pressure multi-center selection Head switches circuit, in multichannel
Each channel includes identical electric resistance partial pressure module, gate control voltage generation module, the first main switch module, the second main switch mould
Block and sub- LDO module；In the switching circuit in each channel, the end VIN of electric resistance partial pressure module, gate control voltage generation module
The end VIN is connect with the input voltage VIN n of N channel, the end GND of electric resistance partial pressure module, the first main switch module the end GND,
The end GND of second main switch module, the end GND of sub- LDO module, the end GND of gate control voltage generation module and ground voltage GND connect
It connects, the end VREF_sub of electric resistance partial pressure module, the OUT terminal of the second main switch module, the end VREF_sub of sub- LDO module and grid
The end VREF_sub of control voltage generating module is connected, the end VIN_L of electric resistance partial pressure module and the end IN of the first main switch module
Connection；The end SEL of first main switch module, the end SEL of the second main switch module, the end SEL of sub- LDO module and channel selecting
Signal SELn connection；The end VREF of first main switch module, the end VREF of the second main switch module, sub- LDO module the end VREF
It is connect with reference voltage VREF, output voltage terminal VOUT connection after the OUT terminal of the first main switch module and conversion, the first main switch
The end VG_H, the end VG_H of the second main switch module of module are connect with the end VG_H of gate control voltage generation module, the first main switch
The end VG_L, the end VG_L of the second main switch module of module are connect with the end VG_L of gate control voltage generation module；Sub- LDO module
Vdd terminal, gate control voltage generation module vdd terminal connect with supply voltage VDD, the end LDO_O of sub- LDO module and the second main switch
The end IN of module connects, and the end VB1 of sub- LDO module is connect with the first bias voltage VB1, the end VB2 and first of sub- LDO module
Bias voltage VB2 connection, the end VB3 of sub- LDO module are connect with the first bias voltage VB3.In the switching circuit in n channel,
Input voltage has n, when channel selecting signal SELn is high level, gates the channel, rest channels are turned off, traditional multi-pass
Road positive or negative high voltage turns low pressure ADC, due to can not effectively turn off not gated channel, using n Channel front end divider resistance
Output separate connect with n ADC, considerably increase the power consumption and area of way circuit, the output end VOUT connection in each channel
Together, rear end only needs an ADC.
As shown in Fig. 2, providing electric resistance partial pressure module circuit diagram, electric resistance partial pressure module includes resistance R1, resistance R2 and resistance
R3；One end of resistance R1 is connect with positive or negative high voltage input signal VIN, the other end of resistance R1, one end of resistance R2, resistance R3
One end is connected with low pressure input VIN_L after conversion, and the other end of resistance R2 is connect with GND, the other end and base of resistance R3
Output VREF_sub connection of the quasi- voltage after sub- LDO buffering.3 resistance are connected according to mode shown in Fig. 2, it is available
The output voltage in a linear relationship with input voltage.According to circuit structure, when the passage is open, available following equation:
Available output voltage are as follows:
When channel is closed, the end VREF_sub shutdown, R3 resistance value is equivalent to infinity, available output voltage are as follows:
Electric resistance partial pressure module is that positive negative high-voltage is converted to the main modular of low-voltage, adjusts the resistance value of 3 resistance, i.e.,
The output voltage of fixedly scaling coefficient, fixed DC deviation can be obtained；Simultaneously it is also seen that the linearity of resistance directly affects
It to the linearity of output voltage, therefore chooses the lower resistance of voltage coefficient and the linearity of branch pressure voltage can be improved, some
Rear end requires in faster application sampling rate, and front end divider resistance must be smaller to guarantee certain driving capability.
Gate control voltage generation module circuit diagram is as shown in figure 3, gate control voltage generation module includes resistance R4, resistance R5, electricity
Hinder R6, resistance R7, resistance R8 and resistance R9；One end of resistance R4 is connect with positive or negative high voltage input signal VIN, and resistance R4's is another
One end, one end of resistance R5, the voltage VG_L that one end of resistance R6 is turned off with control main switch are connect, the other end of resistance R5
It is connect with GND, output VREF_sub connection of the other end and reference voltage of resistance R6 after sub- LDO buffering；Resistance R7's
One end is connect with positive or negative high voltage input signal VIN, the other end of resistance R7, one end of resistance R8, resistance R9 one end with control
The voltage VG_H connection that main switch processed is opened, the other end of resistance R8 are connect with GND, the other end and supply voltage of resistance R9
VDD connection.
6 resistance are connected according to mode shown in Fig. 3, it is identical as analyzing above, it is available linearly to be closed with input voltage
The output voltage of system.According to circuit structure, when the passage is open, available following equation:
Available output voltage are as follows:
It should ensure that the coefficient of VIN is equal with the coefficient of VIN in VIN_L expression formula in VG_H expression formula in practice.
When channel is closed, the end VREF_sub shutdown, resistance R6 resistance value is equivalent to infinity, available VG_L output electricity
Buckling are as follows:
The module mainly generates the grid voltage of control sampling switch, to save power consumption, adjusts the resistance value of 6 resistance, i.e.,
The output voltage of fixedly scaling coefficient, fixed DC deviation can be obtained；Since this module branch pressure voltage is for switching
Voltage not will have a direct impact on sampled voltage, therefore the module resistance is of less demanding to resistance accuracy；And its driving is switch
Grid, required driving capability do not need very strong, the optional biggish resistance reduction power consumption of its resistance value.When need circuit work higher
When speed, the module resistance value can be adjusted according to the actual situation.
Main switch module circuit is as shown in figure 4, main switch module includes phase inverter INV1 and phase inverter INV2, four p-types
Metal-oxide-semiconductor is respectively MP1, MP2, MP3 and MP4, and four N-type metal-oxide-semiconductors are respectively MN1, MN2, MN3 and MN4；Wherein phase inverter
The power end of INV1, the source electrode of MP1 are connect with the VG_H that control sampling switch is opened, the ground terminal of phase inverter INV1, phase inverter
The ground terminal of INV2, the source electrode of MN4 are connect with ground voltage GND, the input terminal of the input terminal of phase inverter INV1, phase inverter INV2
It is connect with channel selecting signal SEL, the grid connection of the output end of phase inverter INV1, the grid of MP1 and MP2；Phase inverter
The power end of INV2 is connect with externally input reference voltage VREF, the output end of phase inverter INV2, the grid of MN1 and MN2
Grid connection, the drain electrode of MP1 are connect with the source electrode of MP2, and the substrate terminal of MP1 and the substrate terminal of MP2 connect, the drain electrode MN1 of MP2
Drain electrode, MN3 grid be connected with the grid of MN4, the drain electrode of the source electrode of MN1 and MN2 connect, the substrate terminal of MN1 with
The substrate terminal of MN2 connects, and the drain electrode of MN3 is connect with main switch module input terminal IN, and the drain electrode of the source electrode and MN4 of MN3 connects,
The substrate terminal of MN3 and the substrate terminal of MN4 connect, and the source electrode of MN4 is connect with main switch module output end OUT, the source of MN2, MP3
Source electrode with control sampling switch shutdown VG_L connect, the drain electrode of MP3 is connect with the source electrode of MP4, the substrate terminal and MP4 of MP3
Substrate terminal connection.
The main switch module mainly completes being switched on and off for sampling switch, and guarantees all metal-oxide-semiconductors without pressure resistance
Problem, MP3 and MP4 are depletion type NMOS tube, and the lower Low threshold pipe of threshold voltage, all metal-oxide-semiconductors of the module also can be selected
It is all made of the mode of differential concatenation connection, can solve negative pressure bring substrate leakage problem in this way, because substrate is to the series connection
Pair any terminal can be considered the diode for having a shutdown, substrate can not flow in or out electric current.Third p-type metal-oxide-semiconductor
MP3, the 4th p-type metal-oxide-semiconductor MP4 are depletion type or Low threshold metal-oxide-semiconductor, it acts as clamping down on the end VG_L voltage not exceeding 0V, because
For when VG_L voltage changes with electric resistance partial pressure completely, if VG_L is higher than 0V, VG_L voltage can neither effectively turn off sampling switch,
The first N-type metal-oxide-semiconductor MN1, the second N-type MOS pipe MN2 transmission can not be passed through completely.It is weak to use Low threshold metal-oxide-semiconductor, the end VG_L electricity
Pressure cannot clamp down on 0V or also be subjected to lower than 0V but as long as sampling switch is not turned on.When VG_L is timing, clamper can band
Carry out certain power consumption.When the passage is open, sampling switch is controlled by VG_H, the fixed high DC level of voltage ratio VIN_L.
When channel is closed, sampling switch is controlled by VG_L, since VG_L is identical as VIN_L voltage, even if remaining under negative pressure state
Effectively shutdown sampling switch.The power supply of second phase inverter INV2 terminates VREF, avoids the first N-type metal-oxide-semiconductor MN1, the second N-type
There is pressure-resistant problem in metal-oxide-semiconductor MN2.
As shown in figure 5, sub- LDO module includes a phase inverter INV3, five p-type metal-oxide-semiconductors are respectively sub- LDO modular circuit
MP5, MP6, MP7, MP8 and MP9, seven N-type metal-oxide-semiconductors are respectively MN5, MN6, MN7, MN8, MN9, MN10 and MN11, an electricity
Hold C1 and resistance R10；The power end of phase inverter INV3, the source electrode of MP5, the source electrode of MP6, MP9 source electrode and power end
VDD connection, the ground terminal of phase inverter INV3, the source electrode of MN10, MN11 source electrode connect with ground voltage GND, phase inverter INV3's is defeated
Enter end, the grid of MN9 is connect with channel selecting signal SEL, the grid connection of the output end and MN11 of phase inverter INV3；MP5
The drain electrode of grid, MP8 of grid, MP6 be connected with the drain electrode of MN6, the drain electrode of MP5 is connect with the source electrode of MP7, the leakage of MP6
The connection of the source electrode of pole and MP8, the grid of MP7, the grid of MP8 connect with the first bias voltage VB1, the drain electrode of MP7, the leakage of MN5
Pole, MP9 grid connect with one end of capacitor C1, the drain electrode of the other end, MN11 of capacitor C1 and LDO output end LDO_O connect
It connects, the grid of MN5, the grid of MN6 are connect with the second bias voltage VB2, and the drain electrode of the source electrode and MN7 of MN5 connects, the source of MN6
The drain electrode of pole and MN8 connects, and the grid of MN7 is connect with externally input reference voltage VREF, and the one of the grid of MN8, resistance R10
The output VREF_sub connection of end and reference voltage after sub- LDO buffering, the other end of resistance R10 are connect with ground voltage GND；
The drain electrode of the source electrode of MN7, the source electrode of MN8 and MN9 connects, and the drain electrode of the source electrode and MN10 of MN9 connects, the grid of MN10 and the
Three bias voltage VB3 connections.
The module mainly completes the circuit of sub- LDO, in n-channel circuit, due to there is n electric resistance partial pressure module, if LDO
The current path of closing passage is not turned off, LDO can be made to consume great electric current, using the design of sub- LDO, switch OFF
The output end of LDO power tube, the end VREF of electric resistance partial pressure not will receive the influence for switching upper pressure drop, and not need big switch
It manages, in the channel of shutdown, LDO is also switched off, and does not increase extra power consumption；In the channel of unlatching, sub- LDO only increases a small amount of power consumption, is
Guarantee the stabilization of sub- LDO, increase first capacitor C1 as compensating electric capacity, about 1pF, feedback resistance R1 can design it is larger with
Reduce the quiescent dissipation of LDO.
Fig. 6 (a) and Fig. 6 (b) is two main switch modules and sub- LDO module working state figure in practical situations, wherein
Fig. 6 (a) is that the course of work is opened in channel；Fig. 6 (b) is that the course of work is closed in channel.
Working condition explanation is by taking -10V~10V voltage input switchs to 0~2.5V as an example, supply voltage 5V, ground voltage 0V,
Reference voltage 2.5V, and choose suitable resistance.
Channel each mains voltage expression formula when opening are as follows:
0~2.5V of variation range
VG_L=0
2.5~5V of variation range
At this point, VG_H level is transferred to the grid of N-type MOS pipe MN3, N-type metal-oxide-semiconductor MN4 by p-type metal-oxide-semiconductor MP1, MP2, open
It closes and opens.
Channel each mains voltage expression formula when turning off are as follows:
Variation range -2.5~2.5V
Variation range is -2.5~0V
2.5~5V of variation range
At this point, VG_L level is transferred to the grid of N-type MOS pipe MN3, MN4, switch OFF by N-type metal-oxide-semiconductor MN1, MN2.
Although hereinbefore having been made with reference to some embodiments the utility model is described, this reality is not being departed from
In the case where with novel range, various improvement can be carried out to it and can be with equivalent without replacement technical point therein, especially
It is, as long as technical contradiction is not present, the various features in the various embodiments of the utility model institute careless mistake can be by any
Mode is used in combination with, and not carrying out the description of exhaustive row to the case where these combinations in the present invention is only to be in province
Slightly length and the considerations of economizing on resources.Therefore, the utility model is not limited to specific embodiment disclosed herein, and including
Fall into claim.
Claims (5)
1. a kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit, it is characterised in that: every in multichannel
A channel includes identical electric resistance partial pressure module, gate control voltage generation module, the first main switch module, the second main switch module
With sub- LDO module；
In the switching circuit in each channel, the end VIN of the electric resistance partial pressure module, the gate control voltage generation module VIN
End is connect with the input voltage VIN n of N channel, the end GND of the electric resistance partial pressure module, the first main switch module the end GND,
The end GND of second main switch module, the end GND of sub- LDO module, the end GND of gate control voltage generation module and ground voltage GND connect
Connect, the end VREF_sub of the electric resistance partial pressure module, the OUT terminal of the second main switch module, sub- LDO module the end VREF_sub with
The end VREF_sub of the gate control voltage generation module is connected, the end VIN_L of the electric resistance partial pressure module and the first main switch
The end IN of module connects；The end SEL of first main switch module, the end SEL of the second main switch module, sub- LDO module SEL
End is connect with channel selecting signal SELn；The end VREF, the end VREF of the second main switch module, son of first main switch module
The end VREF of LDO module is connect with reference voltage VREF, output voltage terminal after the OUT terminal of first main switch module and conversion
VOUT connection, the end VG_H of first main switch module, the end VG_H of the second main switch module and the gate control voltage generate
The end VG_H of module connects, the end VG_L of first main switch module, the end VG_L of the second main switch module and the grid-control
The end VG_L of voltage generating module connects；The vdd terminal of the sub- LDO module, the vdd terminal of gate control voltage generation module and power supply electricity
VDD connection is pressed, the end LDO_O of the sub- LDO module is connect with the end IN of the second main switch module, the VB1 of the sub- LDO module
End is connect with the first bias voltage VB1, and the end VB2 of the sub- LDO module is connect with the first bias voltage VB2, the sub- LDO mould
The end VB3 of block is connect with the first bias voltage VB3.
2. a kind of low-power consumption positive or negative high voltage according to claim 1 turns low pressure multi-center selection Head switches circuit, special
Sign is: the electric resistance partial pressure module includes resistance R1, resistance R2 and resistance R3；
One end of the resistance R1 is connect with positive or negative high voltage input signal VIN, and the one of the other end of the resistance R1, resistance R2
End, resistance R3 one end with after conversion low pressure input VIN_L be connected, the other end of the resistance R2 is connect with GND, described
Output VREF_sub connection of the other end and reference voltage of resistance R3 after sub- LDO buffering.
3. a kind of low-power consumption positive or negative high voltage according to claim 1 turns low pressure multi-center selection Head switches circuit, special
Sign is: the gate control voltage generation module includes resistance R4, resistance R5, resistance R6, resistance R7, resistance R8 and resistance R9；
One end of the resistance R4 is connect with positive or negative high voltage input signal VIN, and the one of the other end of the resistance R4, resistance R5
End, the voltage VG_L that one end of resistance R6 is turned off with control main switch are connect, and the other end of resistance R5 is connect with GND, resistance
Output VREF_sub connection of the other end and reference voltage of R6 after sub- LDO buffering；One end of the resistance R7 with it is positive and negative
The VIN connection of high input voltage signal, the other end of the resistance R7, one end of resistance R8, resistance R9 one end with control master open
The voltage VG_H connection opened is closed, the other end of resistance R8 is connect with GND, and the other end of resistance R9 is connect with supply voltage VDD.
4. a kind of low-power consumption positive or negative high voltage according to claim 1 turns low pressure multi-center selection Head switches circuit, special
Sign is: the main switch module includes phase inverter INV1 and phase inverter INV2, and four p-type metal-oxide-semiconductors are respectively MP1, MP2, MP3
And MP4, four N-type metal-oxide-semiconductors are respectively MN1, MN2, MN3 and MN4；
Wherein the source electrode of the power end of the phase inverter INV1, MP1 are connect with the VG_H that sampling switch is opened is controlled, the reverse phase
The ground terminal of device INV1, the ground terminal of phase inverter INV2, MN4 source electrode connect with ground voltage GND, the input of the phase inverter INV1
End, phase inverter INV2 input terminal connect with channel selecting signal SEL, the grid of the output end of the phase inverter INV1, MP1
It is connect with the grid of MP2；The power end of the phase inverter INV2 is connect with externally input reference voltage VREF, the phase inverter
The grid of the output end of INV2, the grid of MN1 and MN2 connects, and the drain electrode of the MP1 is connect with the source electrode of MP2, the substrate of MP1
End is connect with the substrate terminal of MP2, and the drain electrode of drain electrode MN1 of the MP2, the grid of MN3 are connected with the grid of MN4, described
The drain electrode of the source electrode and MN2 of MN1 connects, and the substrate terminal of the MN1 and the substrate terminal of MN2 connect, and drain electrode and the master of the MN3 opens
Module input IN connection is closed, the drain electrode of the source electrode and MN4 of the MN3 connects, the substrate terminal of the MN3 and the substrate terminal of MN4
Connection, the source electrode of the MN4 are connect with main switch module output end OUT, and the source of the MN2, the source electrode of MP3 and control sample
The drain electrode of the VG_L connection of switch OFF, MP3 is connect with the source electrode of MP4, and the substrate terminal of the MP3 and the substrate terminal of MP4 connect.
5. a kind of low-power consumption positive or negative high voltage according to claim 1 turns low pressure multi-center selection Head switches circuit, special
Sign is: the sub- LDO module include a phase inverter INV3, five p-type metal-oxide-semiconductors be respectively MP5, MP6, MP7, MP8 and
MP9, seven N-type metal-oxide-semiconductors are respectively MN5, MN6, MN7, MN8, MN9, MN10 and MN11, a capacitor C1 and a resistance R10；
The power end of the phase inverter INV3, the source electrode of MP5, the source electrode of MP6, MP9 source electrode connect with power end VDD, it is described
The ground terminal of phase inverter INV3, the source electrode of MN10, MN11 source electrode connect with ground voltage GND, the input terminal of the phase inverter INV3,
The grid of MN9 is connect with channel selecting signal SEL, and the output end of the phase inverter INV3 and the grid of MN11 connect；The MP5
The drain electrode of grid, MP8 of grid, MP6 be connected with the drain electrode of MN6, the drain electrode of the MP5 is connect with the source electrode of MP7, described
The drain electrode of MP6 is connect with the source electrode of MP8, and the grid of the MP7, the grid of MP8 are connect with the first bias voltage VB1, the MP7
Drain electrode, the drain electrode of MN5, the grid of MP9 connect with one end of capacitor C1, the drain electrode of the other end, MN11 of capacitor C1 and LDO are defeated
Outlet LDO_O connection, the grid of the MN5, the grid of MN6 are connect with the second bias voltage VB2, the source electrode and MN7 of the MN5
Drain electrode connection, the drain electrode of the source electrode of the MN6 and MN8 connects, the grid of the MN7 and externally input reference voltage VREF
Connection, the output VREF_sub connection of the grid of the MN8, one end of resistance R10 and reference voltage after sub- LDO buffering,
The other end of the resistance R10 is connect with ground voltage GND；The drain electrode of the source electrode of the MN7, the source electrode of MN8 and MN9 connects, institute
The drain electrode for stating the source electrode and MN10 of MN9 connects, and the grid of the MN10 is connect with third bias voltage VB3.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822197220.4U CN209497443U (en) | 2018-12-25 | 2018-12-25 | A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit |
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|---|---|---|---|
| CN201822197220.4U CN209497443U (en) | 2018-12-25 | 2018-12-25 | A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit |
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| CN209497443U true CN209497443U (en) | 2019-10-15 |
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| CN201822197220.4U Withdrawn - After Issue CN209497443U (en) | 2018-12-25 | 2018-12-25 | A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109525231A (en) * | 2018-12-25 | 2019-03-26 | 西安航天民芯科技有限公司 | A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit |
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2018
- 2018-12-25 CN CN201822197220.4U patent/CN209497443U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109525231A (en) * | 2018-12-25 | 2019-03-26 | 西安航天民芯科技有限公司 | A kind of low-power consumption positive or negative high voltage turns low pressure multi-center selection Head switches circuit |
| CN109525231B (en) * | 2018-12-25 | 2023-12-19 | 西安航天民芯科技有限公司 | Low-power-consumption positive-negative high-voltage-to-low-voltage multichannel selection front-end switch circuit |
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