CN208424191U - High pressure applied to DC-DC converter enables circuit - Google Patents
High pressure applied to DC-DC converter enables circuit Download PDFInfo
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- CN208424191U CN208424191U CN201820786778.3U CN201820786778U CN208424191U CN 208424191 U CN208424191 U CN 208424191U CN 201820786778 U CN201820786778 U CN 201820786778U CN 208424191 U CN208424191 U CN 208424191U
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Abstract
A kind of enabled circuit of the high pressure applied to DC-DC converter, comprising: internal electric source generates unit, and internal electric source, which generates unit, has the first high voltage power supply input terminal, the first low-tension supply output end and the second low-tension supply output end；Voltage detection unit, voltage detection unit have the first detection input, the second detection input and the first detection output；First detection input connects enabled pin, and the second detection input connects the first low-tension supply output end；Comparison judgment unit, comparison judgment unit have first compare input terminal, second compare input terminal and first and compare output end；First, which compares input terminal, connects the first detection output；Second, which compares input terminal, connects the second low-tension supply output end, and first compares output end connection analog module.The high pressure, which enables circuit, makes corresponding chip that can either be directly connected to high voltage power supply use, and need not use special process, reduces process costs.
Description
Technical field
The utility model relates to circuit fields more particularly to a kind of high pressure applied to DC-DC converter to enable circuit.
Background technique
With the fast development of semiconductor technology and microelectric technique, DC-DC converter with its high efficiency, wide load with
And the characteristics of capability of fast response, it is widely used in the fields such as consumer electronics, communication equipment, industrial application and aerospace.
According to the difference of application environment, the power supply range of chip is also more and more wider, and representative value is from initial 3.3V, 5V
And 12V, extend 18V or even 24V till now.
Chip is controlled for the ease of electronic system, DC-DC converter usually external enabled pin, for controlling core
The work and shutdown of piece, therefore chip interior need to design enabled circuit.
In commonly used, enabled pin (EN pin) connection power supply represents chip operation, represents to connection chip shutdown.With
In application supply voltage gradually rise, the voltage carrying capacity of enabled pin is required also to increase.
Fig. 1 is a kind of system architecture diagram of existing voltage-dropping type high pressure DC-DC converter.It wherein, is typical in dotted line frame
10 internal structure of chip.Rectangle outside dotted line frame indicates load circuit 20.
It will be noted from fig. 1 that chip 10 has generally included enabled pin EN, input power pin VIN, bias pin
BS, switch pin SW, feedback pin FB and grounding pin GND.
Enabled module 11 inside enabled pin EN connection chip 10, and enabled module 11 is separately connected voltage reference module
Vref and internal voltage regulator Vreg5.The internal voltage regulator Vreg5 of chip 10 is connected to input power pin VIN and chip 10
Other circuit structures, other most of circuit structures for simplification, chip are covered using shade.
Bias pin BS, switch pin SW and feedback pin FB are separately connected the corresponding connecting pin of load circuit 20.Chip
10 internal circuit and load circuit 20 is additionally coupled to the ground terminal G in chip simultaneously.Power switch tube inside chip 10 is (not
Show), it can be composed in parallel by multiple MOSFET, realize lesser conducting resistance.
Wherein, it enables pin EN connection and enables module 11, be (internal steady for controlling 10 internal voltage regulator Vreg5 of chip
Depressor Vreg5 generally produces 5V voltage, provides power supply for each circuit structure in chip 10), and then control entire chip 10
Work and shutdown.
High voltage of the input power pin VIN sometimes for connection 12V-24V.And common semiconductor CDMOS
(Complementary and Double Diffusion MOS, complementary type MOS and dual diffused MOS integrated abbreviation) technique
For thin grid oxygen technique, the MOSFET drain-source voltage provided can bear 24V, but gate source voltage is only capable of bearing 5V.
It is limited to meet gate source voltage no more than 5V, is commonly designed bias pin BS and switch pin SW for driving and height
Low transition.
In short, there are two types of connection types for the enabled pin of high pressure DC-DC converter currently on the market:
1, in view of the limitation of thin grid oxygen CDMOS gate source voltage, many chips, which have to limit enabled pin voltage, to be surpassed
Cross 5V --- but this connection type makes chip that can not be directly connected to high voltage power supply use.
2, it uses thick grid oxygen technique instead, improves the gate source voltage voltage endurance capability of device, enabled pin can be directly connected to high pressure
Power supply uses --- but the technique of this mode is special, and the cost is relatively high.
Utility model content
The utility model solves the problems, such as to be to provide a kind of enabled circuit of the high pressure applied to DC-DC converter, so that phase
The chip answered can either be directly connected to high voltage power supply use, and need not use special process, reduce process costs.
To solve the above problems, the utility model provides a kind of enabled circuit of the high pressure applied to DC-DC converter, packet
Include: internal electric source generates unit, and the internal electric source, which generates unit, has the first high voltage power supply input terminal, the first low-tension supply defeated
Outlet and the second low-tension supply output end；Voltage detection unit, the voltage detection unit have the first detection input, second
Detection input and the first detection output；First detection input connects enabled pin, second detection input
Connect the first low-tension supply output end；Comparison judgment unit, the comparison judgment unit have first to compare input terminal, the
Two, which compare input terminal and first, compares output end；Described first, which compares input terminal, connects first detection output；Described
Two, which compare input terminal, connects the second low-tension supply output end, and described first compares output end connection analog module.
Optionally, the voltage detection unit includes detection resistance, detection NMOS tube and detection capacitor；The detection resistance
One end connect first detection input, the other end of the detection resistance connects the drain electrode of the detection NMOS tube, institute
The grid for stating detection NMOS tube connects second detection input, the source electrode connection of the detection NMOS tube first detection
Output end；Described detection capacitor one end is connected between the source electrode and first detection output of the detection NMOS tube, separately
One end ground connection.
Optionally, the drain-source voltage tolerance range of the detection NMOS tube is 0V~24V.
Optionally, it includes first resistor that the internal electric source, which generates unit, the first NMOS tube to the tenth NMOS tube, and first
PMOS tube is to the 8th PMOS tube；One end of the first resistor connects the first high voltage power supply input terminal, and the other end connects institute
State the drain electrode of the first NMOS tube, the grid of first NMOS tube, the grid of second NMOS tube and the third NMOS tube
Grid；The source electrode of first PMOS tube, the source electrode of second PMOS tube, the source electrode of the third PMOS tube and described
The drain electrode of four NMOS tubes connects the first high voltage power supply input terminal；The source electrode of first NMOS tube connects the 6th NMOS
The drain electrode of pipe, the grid of the 6th NMOS tube, the grid of the 7th NMOS tube, the 8th NMOS tube grid, described
The grid of the grid of 9th NMOS tube and the tenth NMOS tube；The source electrode of second NMOS tube connects the 7th NMOS tube
Drain electrode；The drain electrode of second NMOS tube connects the drain electrode of the 4th PMOS tube, the grid of the 4th PMOS tube and institute
State the grid of the 5th PMOS tube；The source electrode of the third NMOS tube connects the drain electrode of the 8th NMOS tube；3rd NMOS
The drain electrode of pipe connects drain electrode, the grid of second PMOS tube and the grid of the third PMOS tube of second PMOS tube；
The drain electrode of the third PMOS tube connects the source electrode of the 5th PMOS tube；The source electrode connection the described 9th of 4th NMOS tube
The drain electrode of NMOS tube；The grid of first PMOS tube connects drain electrode and the source electrode of the 4th PMOS tube of itself；Described
The drain electrode of five PMOS tube connects the grid of the 4th NMOS tube and the source electrode of the 6th PMOS tube；6th PMOS tube
Grid connects drain electrode and the source electrode of the 7th PMOS tube of itself；The grid of 7th PMOS tube connect itself drain electrode with
The source electrode of 8th PMOS tube；The grid of 8th PMOS tube connects drain electrode and the grid of the 5th PMOS tube of itself
And drain electrode；The source electrode of 5th NMOS tube, the source electrode of the 6th NMOS tube, the source electrode of the 7th NMOS tube, described
The source electrode of the source electrode of eight NMOS tubes, the source electrode of the 9th NMOS tube and the tenth NMOS tube is grounded.
Optionally, the drain-source voltage tolerance range of the 4th PMOS tube and the 5th PMOS tube is 0V~24V；It is described
The drain-source voltage tolerance range of second NMOS tube, the third NMOS tube and the 4th NMOS tube is 0V~24V.
Optionally, it includes first resistor that the internal electric source, which generates unit, the first NMOS tube to the 8th NMOS tube, and first
PMOS tube is to third PMOS tube；One end of the first resistor connects the first high voltage power supply input terminal, and the other end connects institute
State the grid of the drain electrode of the first NMOS tube, the grid of first NMOS tube and second NMOS tube；First PMOS tube
Source electrode, second PMOS tube source electrode connect the first high voltage power supply input terminal with the drain electrode of the 4th NMOS tube；
The source electrode of first NMOS tube connects the drain electrode of the 5th NMOS tube, the grid of the 5th NMOS tube, the described 6th
The grid of the grid of NMOS tube, the grid of the 7th NMOS tube and the 8th NMOS tube；The source electrode of second NMOS tube
Connect the drain electrode of the 6th NMOS tube；The drain electrode of second NMOS tube connects the drain electrode and described the of second PMOS tube
The grid of two PMOS tube；The source electrode of 4th NMOS tube connects the drain electrode of the 7th NMOS tube；First PMOS tube
Drain electrode connects the source electrode of the third PMOS tube；The grid and the 5th PMOS of the drain electrode connection of the third PMOS tube itself
The source electrode of pipe；The grid of 5th PMOS tube connects drain electrode and the drain and gate of the third NMOS tube of itself；It is described
The source electrode of third NMOS tube, the source electrode of the 5th NMOS tube, the source electrode of the 6th NMOS tube, the 7th NMOS tube source
The source electrode of pole and the 8th NMOS tube ground connection.
Optionally, the drain-source voltage tolerance range of first PMOS tube and second PMOS tube is 0V~24V；It is described
The drain-source voltage tolerance range of second NMOS tube and the 4th NMOS tube is 0V~24V.
Optionally, the comparison judgment unit includes first comparing PMOS tube, second comparing PMOS tube, first compare NMOS
Pipe, second compare NMOS tube, third compares NMOS tube, Schmidt trigger and phase inverter；Described first compares the source of PMOS tube
The source electrode that PMOS tube is compared with second in pole connects the second low-tension supply output end；Described first compare PMOS tube grid,
The drain electrode that described second grid for comparing PMOS tube compares PMOS tube with described second connects bias current end；Described first compares
PMOS tube drain electrode connection described first compare the drain electrode of NMOS tube, described second compare NMOS tube drain electrode and the Schmidt
The input terminal of trigger；The grid that described first grid for comparing NMOS tube compares NMOS tube with described second connects described first
Detection output；Described first compares the source electrode of NMOS tube and the third compares the source electrode ground connection of NMOS tube；Second ratio
The drain electrode that the third compares NMOS tube is connected compared with the source electrode of NMOS tube；The grid that the third compares NMOS tube is connected to described
Between the output of Schmidt trigger and the input of the phase inverter.
Optionally, it further includes level conversion unit that the high pressure, which enables circuit, and the level conversion unit is connected to described
Between comparison judgment unit and the analog module.
Optionally, the high pressure enables the gate source voltage tolerance range of whole metal-oxide-semiconductors in circuit in 5V or less.
In the one aspect of technical solutions of the utility model, unit, voltage detection unit are generated by internal electric source
With the respective function and even cooperation of comparison judgment unit, the enabled circuit (institute for being suitable for common thin grid oxygen CDMOS technique is formd
There is device gate source voltage to be less than 5V), technique strong applicability had not only realized chip ena-bung function, but also solved enabled pin
Can not external high voltage power supply the problem of, meanwhile, related circuit structure is simple, and process costs are low.
Further, the voltage of enabled pin is detected by detecting NMOS tube drain electrode in voltage detection unit, and
It designs builtin voltage and carries out gate driving, while judgement is compared by hysteresis comparator, make chip performance is more stable can
It leans on.
Detailed description of the invention
Fig. 1 is existing chip and load circuit connection schematic diagram；
Fig. 2 is that the high pressure provided by the embodiment of the utility model applied to DC-DC converter enables circuit diagram；
Fig. 3 is a kind of internal electric source generation element circuit figure；
Fig. 4 is that another internal electric source generates element circuit figure；
Fig. 5 is a kind of comparison judgment unit circuit diagram.
Specific embodiment
The existing high pressure applied to DC-DC converter, which enables circuit, makes chip that can not be directly connected to high voltage power supply use, or
Person's technique is special cause it is at high cost.
For this purpose, the utility model provides a kind of enabled circuit of the new high pressure applied to DC-DC converter, it is above-mentioned to solve
Existing deficiency.
More clearly to indicate, the utility model is described in detail with reference to the accompanying drawing.
The utility model embodiment provides a kind of enabled circuit of the high pressure applied to DC-DC converter, incorporated by reference to reference Fig. 2
To Fig. 5.
As shown in Fig. 2, it includes that internal electric source generates unit 110, voltage that the high pressure for being applied to DC-DC converter, which enables circuit,
Detection unit 120 and comparison judgment unit 130.
Internal electric source generates unit 110, and internal electric source generates unit 110, and there is the first high voltage power supply input terminal (not mark
Note), the first low-tension supply output end (not marking) and the second low-tension supply output end (not marking).That is, the present embodiment
In, the first high voltage power supply input terminal that internal electric source generates unit 110 accesses high voltage power supply Vin, is converted into the first low pressure
Power supply V1With the second low-tension supply V2, the first low-tension supply V1It (is please referred to for detecting transistor inside voltage detection unit 120
Subsequent content) driving, the second low-tension supply V2Power supply for comparison judgment unit 130.
Voltage detection unit 120, voltage detection unit 120 have the first detection input (not marking), the second detection defeated
Enter end (not marking) and the first detection output (not marking).First detection input connects enabled pin En, and described the
Two detection inputs connect the first low-tension supply output end.First detection output connects comparison judgment unit 130
First compare input terminal (please referring to subsequent content).
The setting of voltage detection unit 120, enabling to the high voltage that enabled pin En can be directly external, (this is practical new
High voltage or high pressure in type refer to size in the voltage of 12V~24V, because the voltage of 12V~24V is for usual CDMOS work
It is high voltage or high pressure for the metal-oxide-semiconductor of skill production), and corresponding high voltage is converted to low-voltage (this specification within 5V
In low-voltage or low pressure, refer to size in 5V or less voltage), enable pin En voltage change can be in voltage detection unit
120 first detection output embodies, and in the present embodiment, the first detection output output is voltage
V0。
Comparison judgment unit 130, comparison judgment unit 130 have first to compare input terminal (not marking), second more defeated
Enter end (not marking) and first and compares output end (not marking).As previously mentioned, described first compares input terminal connection described first
(i.e. described first compares input terminal is connected into voltage V to detection output0, in combination with referring to figs. 2 and 5).Described second is more defeated
Enter end and connect the second low-tension supply output end, described first compares output end connection analog module (not shown).
Comparison judgment unit 130 acts on analog device.As previously mentioned, described the first of comparison judgment unit 130 compares
First detection output of input terminal connection voltage detection unit 120.The power supply of comparison judgment unit 130 is by internal electric source
Generate the second low-tension supply V that unit 110 generates2It provides, comparison judgment unit 130 is described for realizing multilevel iudge function
It is enabled digital signal that first, which compares output end, which exports,.The digital signal that comparison judgment unit 130 exports can be to internal electricity
Road carries out making can control.The high potential of comparison judgment unit 130 can be the second low-tension supply V2(the second low-tension supply V2Usually
For 5V), and the low potential of comparison judgment unit 130 can be 0V (zero volt).
Voltage detection unit 120 includes detection resistance R0, detection NMOS tube MN0 and detection capacitor C0.Detection resistance R0One
The first detection input of end connection, detection resistance R0Other end connecting detection NMOS tube MN0 drain electrode, detect NMOS tube MN0
Grid connect the second detection input, detection NMOS tube MN0 source electrode connect the first detection output.Detect capacitor C0One end
It is connected between the source electrode and the first detection output of detection NMOS tube MN0, detects capacitor C0Other end ground connection.Detect NMOS tube
The output voltage signal of MN0 source electrode is passing through detection capacitor C0After filtering, voltage detecting is completed, and can will be completed after detecting
Voltage V0It is input to comparison judgment unit 130.
In the present embodiment, the drain-source voltage tolerance range of control detection NMOS tube MN0 is 0V~24V.That is, detection
The drain-source voltage of NMOS tube MN0 can achieve 24V.
As previously mentioned, first detection input of comparison judgment unit 130 connects the source of the detection NMOS tube MN0
The voltage of pole, detection NMOS tube MN0 source electrode output is (corresponding interior with reference to subsequent figure 5 to NMOS tube corresponding in comparison judgment unit 130
Hold) threshold voltage be compared judgement, realize that enabled digital signal exports.Meanwhile according to 5 corresponding contents of subsequent figure it is found that
The comparison judgment unit 130 of the present embodiment can have lag function, and noise is avoided to cause output jitter.
It further includes level conversion unit 140 that the high pressure applied to DC-DC converter of the present embodiment, which enables circuit, and level turns
Unit 140 is changed to be connected between comparison judgment unit 130 and analog module (not shown).
Due to that may have multi-group power in chip, it can use level conversion unit 140 and level carried out to the signal
Conversion, high level, which is switched to the laggard enforcement of required power supply, can control.That is, the setting of level conversion unit 140, is realized
The voltage conversion of enabled digital signal, can be by voltage V2It is switched to internal electric source, is provided for each analog module enabled
Signal.Such as in Fig. 2, before carrying out voltage conversion without level conversion unit 140, comparison judgment unit 130 can be generated
One first output Out1, and after passing through level conversion unit 140, level conversion unit 140 can generate one second
Export Out2.
Referring to FIG. 3, it includes first resistor R that internal electric source, which generates unit 110,1, the first NMOS tube MN1 to the tenth NMOS tube
MN10, the first PMOS tube MP1 to the 8th PMOS tube MP8.
First resistor R1One end connect the first high voltage power supply input terminal, the other end connect the first NMOS tube MN1 drain electrode,
The grid of the grid of first NMOS tube MN1, the grid of the second NMOS tube MN2 and third NMOS tube MN3.
The source electrode of first PMOS tube MP1, the source electrode of the second PMOS tube MP2, third PMOS tube MP3 source electrode and the 4th NMOS
The drain electrode of pipe MN4 connects the first high voltage power supply input terminal.
The source electrode of first NMOS tube MN1 connects the drain electrode of the 6th NMOS tube MN6, the grid of the 6th NMOS tube MN6, the 7th
The grid of NMOS tube MN7, the grid of the 8th NMOS tube MN8, the grid of the 9th NMOS tube MN9 and the grid of the tenth NMOS tube MN10
Pole.
The source electrode of second NMOS tube MN2 connects the drain electrode of the 7th NMOS tube MN7.The drain electrode connection the of second NMOS tube MN2
Drain electrode, the grid of the 4th PMOS tube MP4 and the grid of the 5th PMOS tube MP5 of four PMOS tube MP4.
The source electrode of third NMOS tube MN3 connects the drain electrode of the 8th NMOS tube MN8.The drain electrode connection the of third NMOS tube MN3
The drain electrode of two PMOS tube MP2, the grid of the second PMOS tube MP2 and third PMOS tube MP3 grid.The leakage of third PMOS tube MP3
Pole connects the source electrode of the 5th PMOS tube MP5.
The source electrode of 4th NMOS tube MN4 connects the drain electrode of the 9th NMOS tube MN9.
The grid of first PMOS tube MP1 connects drain electrode and the source electrode of the 4th PMOS tube MP4 of itself.
The grid of the 4th NMOS tube MN4 of drain electrode connection of 5th PMOS tube MP5 and the source electrode of the 6th PMOS tube MP6.
The grid of 6th PMOS tube MP6 connects drain electrode and the source electrode of the 7th PMOS tube MP7 of itself.
The grid of 7th PMOS tube MP7 connects drain electrode and the source electrode of the 8th PMOS tube MP8 of itself.
The grid of 8th PMOS tube MP8 connects grid and drain electrode of the drain electrode of itself with the 5th PMOS tube MP5.
The source electrode of 5th NMOS tube MN5 is grounded (not marking).
The source electrode of 6th NMOS tube MN6, the source electrode of the 7th NMOS tube MN7, the 8th NMOS tube MN8 source electrode, the 9th NMOS
The source electrode of the source electrode of pipe MN9 and the tenth NMOS tube MN10 are grounded G1。
In the present embodiment, the drain-source voltage tolerance range of the 4th PMOS tube MP4 and the 5th PMOS tube MP5 are 0V~24V, the
The drain-source voltage tolerance range of two NMOS tube MN2, third NMOS tube MN3 and the 4th NMOS tube MN4 are 0V~24V, and the 4th
The gate source voltage tolerance range of PMOS tube MP4 and the 5th PMOS tube MP5 are also in 5V hereinafter, the second NMOS tube MN2, third NMOS tube
The gate source voltage tolerance range of MN3 and the 4th NMOS tube MN4 are also in 5V or less.In addition to this, the gate source voltage of other metal-oxide-semiconductors and
Drain-source voltage tolerance range is in 5V or less.As it can be seen that the gate source voltage tolerance range of whole PMOS tube is in 5V or less in Fig. 3.
That is, in Fig. 3, it is only necessary to which five metal-oxide-semiconductors are able to bear large range of drain-source voltage.
The circuit operation principle that internal electric source shown in Fig. 3 generates unit 110 is as follows:
First resistor R1, the first NMOS tube MN1 and the 6th NMOS tube MN6 formed it is (corresponding from the first high voltage power supply input terminal
Voltage is Vin) arrive ground G1Access, formed electric current I0, electric current I0Calculation formula it is as follows:
First NMOS tube MN1, the second NMOS tube MN2 and third NMOS tube MN3 constitute current mirror (electric current I0Current mirror).
6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9 and the tenth NMOS tube
MN10 constitutes current mirror.
Second NMOS tube MN2, third NMOS tube MN3, the 7th NMOS tube MN7 and the 8th NMOS tube MN8 constitute cascade
Current mirror guarantees mirror image precision, reduces influence of the ground noise to electric current.
Second PMOS tube MP2 and third PMOS tube MP3 constitute current mirror, be the 6th PMOS tube MP6, the 7th PMOS tube MP7,
8th PMOS tube MP8 and the 5th NMOS tube MN5 provides bias current.
First PMOS tube MP1 and the 4th PMOS tube MP4 provides bias voltage, third PMOS tube MP3 for the 5th PMOS tube MP5
Common-source common-gate current mirror is constituted with the 5th PMOS tube MP5, guarantees mirror image precision, reduces influence of the Vin noise to electric current.
Flow through the electric current I of third PMOS tube MP31With the electric current I for flowing through the 9th NMOS tube MN92It can respectively indicate are as follows:
Wherein, (W/L) is the breadth length ratio of each transistor channel, and pre-sub is the mark of respective transistor.
The 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8 and the 5th of diode connection type composition
NMOS tube MN5 generates the grid voltage V of the 4th NMOS tube MN4 jointly1(i.e. aforementioned first low-tension supply V1, start from there referred to as
Voltage V1), voltage V1Calculation formula is as follows:
Drain current formula of the MOSFET work at saturation region is utilized in formula (4) (to have substituted into metal-oxide-semiconductor be saturated
Current-voltage correlation formula under area's electric current), wherein μpFor the migration rate in hole, μnFor the migration rate of electronics, CoFor unit
Area gate oxide capacitance.
It should be noted that taking (W/L) in above-mentioned formula (4)MP6=(W/L)MP7=(W/L)MP8, that is to say, that at this time:
9th NMOS tube MN9 provides bias current for the 4th NMOS tube MN4, and the tenth NMOS tube MN10 is comparison judgment unit
130 circuits provide bias current Iblas.
Due to the source voltage V of MN42(i.e. aforementioned second low-tension supply V2, start abbreviation voltage V from there2) it is to compare to sentence
Disconnected unit 130 provides power supply, and therefore, taking the electric current of comparison judgment unit 130 is ICOMP, voltage V1After subtracting gate source voltage, obtain
The source voltage V of 4th NMOS tube MN42, calculation formula is as follows:
In conjunction with formula (1) to (5) as it can be seen that by adjusting first resistor R1Size, adjustable entire module (compares and sentences
Disconnected unit 130) electric current and voltage V1With voltage V2Size (first resistor R1Influence electric current I0, and then influence electric current I1And electricity
Flow I2, final to influence voltage V1With voltage V2).Especially in the case where the breadth length ratio of each metal-oxide-semiconductor has been decided, first
Resistance R1As voltage V1With voltage V2Major influence factors.
Due to consideration that low power dissipation design, the cut-off current of chip should be as small as possible, first resistor R1Value it is general
It can be at several megohms.
In other embodiments, by adjusting the size of the 5th NMOS tube MN5, the 6th PMOS tube MP6 and the 4th NMOS tube MN4
Also adjustable voltage V1With voltage V2Size.
It has been mentioned hereinbefore that voltage V2For to circuit module power supply (the i.e. multilevel iudge list in Fig. 2 in subsequent figure 5
Member is 130).Since the gate source voltage of general MOS device is all no more than 5V, voltage V1With voltage V2Be normally controlled in 5V
Within.Voltage V1By electric current I1The metal-oxide-semiconductor for flowing through diode connection is realized, in embodiment illustrated in fig. 3, is used 3 diodes and is connected
The NMOS (that the PMOS tube (the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8) connect is connected with 1 diode
Five NMOS tube MN5) it realizes.
Certainly, due to the difference of technological parameter, the metal-oxide-semiconductor number and size of diode connection can be carried out flexibly adjusting
It is whole.Voltage V2Equal to voltage V1The gate source voltage of the 4th NMOS tube MN4 is subtracted, therefore the size of the 4th NMOS tube MN4 can also be right
Voltage V2It is finely adjusted.
It should be noted that in other cases, if insensitive to noise characteristic in practical application, being produced in internal electric source
In raw unit 110, cascode structure can not also be used, and omits the corresponding cascode structure in Fig. 3.At this point, usually
It needs to use other transistor (such as second PMOS tube MP2 and the second PMOS tube MP2 in Fig. 3) for " gate source voltage instead
Tolerance range is 5V or less and drain-source voltage tolerance range is 0V~24V " metal-oxide-semiconductor.For this purpose, in the present embodiment, also offer Fig. 4
Shown in another internal electric source generate unit 110 circuit structure.
It includes first resistor R that another kind internal electric source shown in Fig. 4, which generates unit 110,1, the first NMOS tube MN1 to the 8th
NMOS tube MN8, the first PMOS tube MP1 are to third PMOS tube MP3.First resistor R1One end connect the first high voltage power supply input
End, the other end connect drain electrode, the grid of the first NMOS tube MN1 and the grid of the second NMOS tube MN2 of the first NMOS tube MN1.The
It is defeated that the drain electrode of the source electrode of one PMOS tube MP1, the source electrode of the second PMOS tube MP2 and the 4th NMOS tube MN4 connects the first high voltage power supply
Enter end.The source electrode of first NMOS tube MN1 connects grid, the 6th NMOS of the drain electrode of the 5th NMOS tube MN5, the 5th NMOS tube MN5
The grid of the grid of pipe MN6, the grid of the 7th NMOS tube MN7 and the 8th NMOS tube MN8.The source electrode of second NMOS tube MN2 connects
The drain electrode of 6th NMOS tube MN6.The drain electrode of the second PMOS tube MP2 of drain electrode connection of second NMOS tube MN2 and the second PMOS tube MP2
Grid.The source electrode of 4th NMOS tube MN4 connects the drain electrode of the 7th NMOS tube MN7.The drain electrode of first PMOS tube MP1 connects third
The source electrode of PMOS tube MP3.The grid of the drain electrode connection of third PMOS tube MP3 itself and the source electrode of the 5th PMOS tube MP5.5th
The grid of PMOS tube MP5 connects drain and gate of the drain electrode with third NMOS tube MN3 of itself.The source electrode of third NMOS tube MN3
It is grounded (not marking), the source electrode of the 5th NMOS tube MN5, the source electrode of the 6th NMOS tube MN6, the source electrode of the 7th NMOS tube MN7 and the
The source electrode of eight NMOS tube MN8 is grounded G1.The drain-source voltage tolerance range of first PMOS tube MP1 and the second PMOS tube MP2 be 0V~
24V.The drain-source voltage tolerance range of second NMOS tube MN2 and the 4th NMOS tube MN4 is 0V~24V.
Internal electric source provided by Fig. 4, which generates unit 110, can equally divide Vin for V1And V2, concrete analysis process can be with
With reference to the derivation process with the formula (1) before analogy to formula (5).As it can be seen that realizing that internal electric source generates the circuit of unit 110
Can be to be a variety of, the utility model is not construed as limiting this.
Referring to FIG. 5, comparison judgment unit 130 includes first comparing PMOS tube mp1, second comparing PMOS tube mp2, first
Compare NMOS tube mn1, second compare NMOS tube mn2, third compares NMOS tube mn3, Schmidt trigger Smit and phase inverter are (non-
Door, does not mark), the output of the phase inverter is the first output Out1.
First, which compares the source electrode of PMOS tube mp1 and second, compares source electrode connection the second low-tension supply output of PMOS tube mp2
End.
First compares the grid of PMOS tube mp1, second compares the grid of PMOS tube mp2 and second and compare PMOS tube mp2's
Drain electrode connection bias current end (for connecting bias current Iblas).
The first drain electrode connection first for comparing PMOS tube mp1 compares the drain electrode of NMOS tube mn1, second compares NMOS tube mn2
Drain electrode and Schmidt trigger Smit input terminal.
First, which compares the grid of NMOS tube mn1 and second, compares grid the first detection output of connection of NMOS tube mn2.
First compares the source electrode of NMOS tube mn1 and third compares the source electrode ground connection of NMOS tube mn3.
The second source electrode connection third for comparing NMOS tube mn2 compares the drain electrode of NMOS tube mn3.
The grid that third compares NMOS tube mn3 is connected to the output of Schmidt trigger Smit and the input of the phase inverter
Between.
The gate source voltage of all metal-oxide-semiconductors and drain-source voltage tolerance range shown in Fig. 5 all can be 5V or less.
Second compare the grid of PMOS tube mp2 and second compare PMOS tube mp2 drain electrode be connected to bias current IBIAS.
The working principle of 130 circuit of comparison judgment unit is as follows:
The variation of enabled pin En voltage can be embodied in the output of voltage detection unit 120；
When the external enabled voltage of enabled pin En is lower, first compares NMOS tube mn1 cut-off, Schmidt trigger
The input terminal of Smit is drawn high by the electric current that first compares PMOS tube mp1, and third compares NMOS tube mn3 cut-off, the first output at this time
Out1 exports high level, closes the analog module in chip, chip shutdown；
When the external enabled voltage of enabled pin En increases, first, which compares NMOS tube mn1 grid voltage, is risen with it, and surpasses
After crossing the threshold voltage of NMOS, first compares NMOS tube mn1 conducting, and the input terminal of Schmidt trigger Smit is pulled low, Out1
Become the analog module in low level opening chip, chip is enabled, at this point, third compares NMOS tube mn3 conducting, second compares
NMOS tube mn2 accesses circuit and starts to work, and first compares NMOS tube mn1 NMOS tube mn2 parallel connection compared with second, and adjustment is enabled to draw
Foot En relevant voltage corresponding enabled thresholding when declining.
As it can be seen that second compares NMOS tube mn2 presence of NMOS tube mn3 compared with third and introduce lag function, avoid
The mistake overturning that enabled voltage dithering may cause.The ruler for comparing NMOS tube mn1 NMOS tube mn2 compared with second by adjusting first
The size of very little adjustable amount of hysteresis.Meanwhile it is slow to also function to introducing with hysteresis by Schmidt trigger Smit itself
It is stagnant, prevent the effect accidentally overturn.
According to the above it is found that in the present embodiment, high pressure enables the gate source voltage tolerance range of whole metal-oxide-semiconductors in circuit
It can be in 5V or less.
The high pressure of DC-DC converter provided in this embodiment enables circuit, generates unit 110, voltage by internal electric source
The respective function of 130 three of detection unit 120 and comparison judgment unit and even cooperation form and are suitable for common thin grid oxygen
It is enabled both to have realized chip for the enabled circuit (all device gate source voltages are less than 5V) of CDMOS technique, technique strong applicability
Function, but solve the problems, such as enabled pin En can not external high voltage power supply, meanwhile, related circuit structure is simple, process costs
It is low.
Further, the voltage of enabled pin En is carried out by detecting NMOS tube MN0 drain electrode in voltage detection unit 120
Detection, and design builtin voltage and carry out gate driving, while judgement is compared by hysteresis comparator, make chip performance more
It is reliable and stable.
Although the utility model discloses as above, the utility model is not limited to this.Anyone skilled in the art,
It does not depart from the spirit and scope of the utility model, can make various changes or modifications, therefore the protection scope of the utility model
It should be defined by the scope defined by the claims..
Claims (10)
1. a kind of high pressure applied to DC-DC converter enables circuit characterized by comprising
Internal electric source generates unit, and the internal electric source, which generates unit, has the first high voltage power supply input terminal, the first low-tension supply
Output end and the second low-tension supply output end；
Voltage detection unit, the voltage detection unit have the first detection input, the second detection input and the first detection
Output end；First detection input connects enabled pin, and second detection input connects first low-tension supply
Output end；
Comparison judgment unit, the comparison judgment unit have first compare input terminal, second compare input terminal and first and compare
Output end；Described first, which compares input terminal, connects first detection output；Described second compares input terminal connection described the
Two low-tension supply output ends, described first compares output end connection analog module.
2. high pressure as described in claim 1 enables circuit, which is characterized in that the voltage detection unit include detection resistance,
Detect NMOS tube and detection capacitor；One end of the detection resistance connects first detection input, the detection resistance
The other end connects the drain electrode of the detection NMOS tube, and the grid of the detection NMOS tube connects second detection input, institute
The source electrode for stating detection NMOS tube connects first detection output；Described detection capacitor one end is connected to the detection NMOS tube
Source electrode and first detection output between, the other end ground connection.
3. high pressure as claimed in claim 2 enables circuit, which is characterized in that the drain-source voltage of the detection NMOS tube bears model
It encloses for 0V~24V.
4. high pressure as described in claim 1 enables circuit, which is characterized in that it includes the first electricity that the internal electric source, which generates unit,
Resistance, the first NMOS tube to the tenth NMOS tube, the first PMOS tube to the 8th PMOS tube；
One end of the first resistor connects the first high voltage power supply input terminal, and the other end connects the leakage of first NMOS tube
Pole, the grid of first NMOS tube, the grid of second NMOS tube and the third NMOS tube grid；
The source electrode of first PMOS tube, the source electrode of second PMOS tube, the third PMOS tube source electrode and the described 4th
The drain electrode of NMOS tube connects the first high voltage power supply input terminal；
The source electrode of first NMOS tube connects the drain electrode of the 6th NMOS tube, the grid of the 6th NMOS tube, described
The grid of seven NMOS tubes, the grid of the 8th NMOS tube, the grid of the 9th NMOS tube and the grid of the tenth NMOS tube
Pole；
The source electrode of second NMOS tube connects the drain electrode of the 7th NMOS tube；Described in the drain electrode connection of second NMOS tube
The drain electrode of 4th PMOS tube, the grid of the 4th PMOS tube and the 5th PMOS tube grid；
The source electrode of the third NMOS tube connects the drain electrode of the 8th NMOS tube；Described in the drain electrode connection of the third NMOS tube
The drain electrode of second PMOS tube, the grid of second PMOS tube and the third PMOS tube grid；The third PMOS tube
Drain electrode connects the source electrode of the 5th PMOS tube；
The source electrode of 4th NMOS tube connects the drain electrode of the 9th NMOS tube；
The grid of first PMOS tube connects drain electrode and the source electrode of the 4th PMOS tube of itself；
The drain electrode of 5th PMOS tube connects the grid of the 4th NMOS tube and the source electrode of the 6th PMOS tube；
The grid of 6th PMOS tube connects drain electrode and the source electrode of the 7th PMOS tube of itself；
The grid of 7th PMOS tube connects drain electrode and the source electrode of the 8th PMOS tube of itself；
The grid of 8th PMOS tube connects grid and drain electrode of the drain electrode of itself with the 5th PMOS tube；
The source electrode of 5th NMOS tube, the source electrode of the 6th NMOS tube, the source electrode of the 7th NMOS tube, the described 8th
The source electrode of the source electrode of NMOS tube, the source electrode of the 9th NMOS tube and the tenth NMOS tube is grounded.
5. high pressure as claimed in claim 4 enables circuit, which is characterized in that the 4th PMOS tube and the 5th PMOS tube
Drain-source voltage tolerance range be 0V~24V；The leakage of second NMOS tube, the third NMOS tube and the 4th NMOS tube
Source voltage tolerance range is 0V~24V.
6. high pressure as described in claim 1 enables circuit, which is characterized in that it includes the first electricity that the internal electric source, which generates unit,
Resistance, the first NMOS tube to the 8th NMOS tube, the first PMOS tube to third PMOS tube；
One end of the first resistor connects the first high voltage power supply input terminal, and the other end connects the leakage of first NMOS tube
Pole, the grid of first NMOS tube and second NMOS tube grid；
The source electrode of first PMOS tube, second PMOS tube source electrode described is connected with the drain electrode of the 4th NMOS tube
One high voltage power supply input terminal；
The source electrode of first NMOS tube connects the drain electrode of the 5th NMOS tube, the grid of the 5th NMOS tube, described
The grid of the grid of six NMOS tubes, the grid of the 7th NMOS tube and the 8th NMOS tube；
The source electrode of second NMOS tube connects the drain electrode of the 6th NMOS tube；Described in the drain electrode connection of second NMOS tube
The drain electrode of second PMOS tube and the grid of second PMOS tube；
The source electrode of 4th NMOS tube connects the drain electrode of the 7th NMOS tube；
The drain electrode of first PMOS tube connects the source electrode of the third PMOS tube；
The grid of the drain electrode connection of the third PMOS tube itself and the source electrode of the 5th PMOS tube；
The grid of 5th PMOS tube connects drain electrode and the drain and gate of the third NMOS tube of itself；
The source electrode of the third NMOS tube, the source electrode of the 5th NMOS tube, the source electrode of the 6th NMOS tube, the described 7th
The source electrode of NMOS tube and the source electrode of the 8th NMOS tube ground connection.
7. high pressure as claimed in claim 6 enables circuit, which is characterized in that first PMOS tube and second PMOS tube
Drain-source voltage tolerance range be 0V~24V；The drain-source voltage tolerance range of second NMOS tube and the 4th NMOS tube
For 0V~24V.
8. high pressure as described in claim 1 enables circuit, which is characterized in that the comparison judgment unit compares including first
PMOS tube, second compare PMOS tube, first compare NMOS tube, second compare NMOS tube, third compares NMOS tube, schmidt trigger
Device and phase inverter；
Described first, which compares the source electrode of PMOS tube and second, compares source electrode connection the second low-tension supply output end of PMOS tube；
Described first compares the grid of PMOS tube, described second compares the grid of PMOS tube and leakage that described second compares PMOS tube
Pole connects bias current end；
The described first drain electrode connection described first for comparing PMOS tube compares the drain electrode of NMOS tube, described second compares NMOS tube
The input terminal of drain electrode and the Schmidt trigger；
The grid that described first grid for comparing NMOS tube compares NMOS tube with described second connects first detection output；
Described first compares the source electrode of NMOS tube and the third compares the source electrode ground connection of NMOS tube；
Described second source electrode for comparing NMOS tube connects the drain electrode that the third compares NMOS tube；
The grid that the third compares NMOS tube be connected to the Schmidt trigger output and the phase inverter input it
Between.
9. high pressure as described in claim 1 enables circuit, which is characterized in that further include level conversion unit, the level turns
Unit is changed to be connected between the comparison judgment unit and the analog module.
10. high pressure as claimed in any one of claims 1 to 9 enables circuit, which is characterized in that the high pressure enables in circuit
The gate source voltage tolerance range of whole metal-oxide-semiconductors is in 5V or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820786778.3U CN208424191U (en) | 2018-05-24 | 2018-05-24 | High pressure applied to DC-DC converter enables circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820786778.3U CN208424191U (en) | 2018-05-24 | 2018-05-24 | High pressure applied to DC-DC converter enables circuit |
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| Publication Number | Publication Date |
|---|---|
| CN208424191U true CN208424191U (en) | 2019-01-22 |
Family
ID=65112529
Family Applications (1)
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|---|---|---|---|
| CN201820786778.3U Active CN208424191U (en) | 2018-05-24 | 2018-05-24 | High pressure applied to DC-DC converter enables circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108599544A (en) * | 2018-05-24 | 2018-09-28 | 厦门元顺微电子技术有限公司 | High pressure applied to DC-DC converter enables circuit |
-
2018
- 2018-05-24 CN CN201820786778.3U patent/CN208424191U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108599544A (en) * | 2018-05-24 | 2018-09-28 | 厦门元顺微电子技术有限公司 | High pressure applied to DC-DC converter enables circuit |
| CN108599544B (en) * | 2018-05-24 | 2024-05-14 | 厦门元顺微电子技术有限公司 | High-voltage enabling circuit applied to DC-DC converter |
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