CN109756139B - Maximum angle control circuit for inversion trigger pulse of parallel IGBT high-frequency power supply - Google Patents
Maximum angle control circuit for inversion trigger pulse of parallel IGBT high-frequency power supply Download PDFInfo
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- CN109756139B CN109756139B CN201711059103.5A CN201711059103A CN109756139B CN 109756139 B CN109756139 B CN 109756139B CN 201711059103 A CN201711059103 A CN 201711059103A CN 109756139 B CN109756139 B CN 109756139B
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Abstract
The invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which comprises: the circuit comprises a rectifying circuit, a current spreading circuit, a voltage zero crossing detection circuit, a tenth operational amplifier, a comparator, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a second capacitor, a third capacitor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor. The method has the advantages that periodic trigger pulse control is adopted, namely the trigger pulse of each IGBT is controlled, when the zero crossing point of the inverter voltage is detected, the trigger pulse of one bridge arm IGBT is sent out, the width of the trigger pulse is controlled according to the set power, and when the trigger pulse exceeds a certain angle of the resonance period of the inverter voltage, the trigger pulse stop signal is forcedly output.
Description
Technical Field
The invention relates to a control circuit, in particular to a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit.
Background
The parallel inverter circuit is a basic inverter circuit and has good load adaptability and reliability, so that the parallel inverter circuit is widely applied to production. In the foundry and steel industry, high frequency power supplies are required to be applied during induction heating and melting of some metal materials, and due to the reliability of parallel inversion, parallel inversion IGBT high frequency power supplies are generally selected. The IGBT high-frequency power supply generally works from a few KHz to tens of KHz according to application occasions. In induction heating, particularly in melting, the load variation of the IGBT high frequency power supply is particularly large, so that the reliability requirement for control is becoming higher.
For parallel inversion IGBT high-frequency power supplies, the inversion works in a resonance state, namely the inversion voltage and the inversion current work in an in-phase state. And controlling the conduction of IGBTs of bridge arms at two sides according to the zero crossing point of the inversion voltage, and adjusting the width of the trigger pulse according to the set power. The use of such control has no disastrous consequences in cases where the load variation is not large or constant. However, during smelting, the load is greatly changed, under the condition of abrupt load change, the resonant period of the next inversion voltage cannot be predicted, if the width of any inversion IGBT trigger pulse cannot be controlled, the dead time of the IGBT is smaller than the minimum dead time limit, the inversion side IGBT is short-circuited, and the IGBT is damaged.
Disclosure of Invention
The maximum angle control circuit of the inversion trigger pulse of the parallel IGBT high-frequency power supply adopts periodic trigger pulse control, namely, the trigger pulse of each IGBT is controlled, when the zero crossing point of the inversion voltage is detected, the trigger pulse of one bridge arm IGBT is sent out, the width of the trigger pulse is controlled according to the set power, and when the trigger pulse exceeds a certain angle of the resonance period of the inversion voltage, a trigger pulse stop signal is forcedly output; solves the problems of the prior art to overcome the defects of the prior art.
The invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which comprises: the circuit comprises a rectifying circuit, a current spreading circuit, a voltage zero crossing detection circuit, a tenth operational amplifier U10, a comparator U11, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a second capacitor C2, a third capacitor C3, a second field effect transistor Q2, a third field effect transistor Q3 and a fourth field effect transistor Q4; the rectifying circuit is connected with the input end INV-VOL and inputs inversion voltage; the output end is connected with the current spreading circuit; the voltage zero crossing detection circuit is connected with the input end INV-VOL and inputs inversion voltage; one end of the thirteenth resistor R13 is connected with the output end of the current-spreading circuit, and the other end of the thirteenth resistor R is connected with the drain electrode of the second field effect transistor Q2; one end of a sixteenth resistor R16 is connected with the source electrode of the second field effect transistor Q2, and the other end of the sixteenth resistor R is connected with the non-inverting input end of the tenth operational amplifier U10; one end of the second capacitor C2 is connected with the source electrode of the second field effect transistor Q2, and the other end of the second capacitor C is grounded; one end of the fourteenth resistor R14 is connected with the grid electrode of the second field effect transistor Q2, and the other end of the fourteenth resistor R is connected with the first positive power supply end; the grid electrode of the third field effect transistor Q3 is connected with the output end of the voltage zero crossing point detection circuit; the drain electrode of the third field effect transistor Q3 is connected with the grid electrode of the second field effect transistor Q2; the source electrode of the third field effect transistor Q3 is grounded; the grid electrode of the fourth field effect transistor Q4 is connected with the output end of the voltage zero crossing point detection circuit; the source electrode of the fourth field effect transistor Q4 is grounded; one end of the fifteenth resistor R15 is connected with the source electrode of the second field effect tube Q2, and the other end of the fifteenth resistor R is connected with the drain electrode of the fourth field effect tube Q4; one end of a seventeenth resistor R17 is connected with the inverting input end of the tenth operational amplifier U10, and the other end of the seventeenth resistor R is connected with the output end of the tenth operational amplifier U10; one end of the eighteenth resistor R18 is connected with the output end of the tenth operational amplifier U10, and the other end of the eighteenth resistor R is connected with the non-inverting input end of the comparator U11; one end of the twentieth resistor R20 is connected with the non-inverting input end of the comparator U11, and the other end is grounded; one end of a nineteenth resistor R19 is connected with the inverting input end of the comparator U11, and the other end of the nineteenth resistor R is connected with the output end of the rectifying circuit; one end of a twenty-first resistor R21 is connected with the output end of the comparator U11, and the other end of the twenty-first resistor R is connected with a second positive power supply end; one end of the third capacitor C3 is connected with the output end of the comparator U11, and the other end of the third capacitor C is grounded.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the rectification circuit comprises a first operational amplifier U1, a third operational amplifier U3, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a sixth resistor R6 and an eighth resistor R8; one end of the first resistor R1 is connected with the input end INV-VOL, and the other end of the first resistor R1 is connected with the inverting input end of the first operational amplifier U1; the non-inverting input end of the first operational amplifier U1 is grounded; one end of the second resistor R2 is connected with the input end INV-VOL, and the other end of the second resistor R2 is connected with the inverting input end of the third operational amplifier U3; one end of a sixth resistor R6 is connected with the inverting input end of the third operational amplifier U3, and the other end of the sixth resistor R6 is connected with the anode of the second diode D2; the cathode of the second diode D2 is connected with the output end of the first operational amplifier U1; the positive electrode of the first diode D1 is connected with the output end of the first operational amplifier U1, and the negative electrode of the first diode D1 is connected with the inverting input end of the first operational amplifier U1; one end of the third resistor R3 is connected with the inverting input end of the first operational amplifier U1, and the other end of the third resistor R3 is connected with the anode of the second diode D2; one end of the eighth resistor R8 is connected with the inverting input end of the third operational amplifier U3, and the other end of the eighth resistor R8 is connected with the output end of the third operational amplifier U3; the output end of the third operational amplifier U3 is the output end of the rectifying circuit, and the non-inverting input end of the third operational amplifier U3 is grounded.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the current-expanding circuit comprises a fifth operational amplifier U5, a triode Q1, a tenth resistor R10, an eleventh resistor R11, a fourth diode D4, a fifth diode D5 and a sixth diode D6; one end of a tenth resistor R10 is connected with the non-inverting input end of a fifth operational amplifier U5, and the other end of the tenth resistor R is connected with the output end of the rectifying circuit; one end of the eleventh resistor R11 is connected with the inverting input end of the fifth operational amplifier U5, and the other end of the eleventh resistor R11 is connected with the anode of the fourth diode D4; the cathode of the fourth diode D4 is connected with the first negative power supply end; the positive electrode of the fifth diode D5 is connected with the positive electrode of the sixth diode D6, and the negative electrode of the fifth diode D5 is connected with the inverting input end of the fifth operational amplifier U5; the base electrode of the triode Q1 is connected with the output end of the fifth operational amplifier U5, the emitter electrode is connected with the positive electrode of the sixth diode D6, and the collector electrode is connected with the first positive power supply end; the cathode of the sixth diode D6 is the output terminal of the current spreading circuit.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the voltage zero crossing detection circuit comprises a second operational amplifier U2, a third diode D3, a fourth inverter U4, a sixth inverter U6, a seventh NAND gate U7, an eighth NAND gate U8, a ninth NAND gate U9, a first capacitor C1, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, a ninth resistor R9 and a twelfth resistor R12; one end of the fifth resistor R5 is connected with the input end INV-VOL, and the other end of the fifth resistor R5 is connected with the non-inverting input end of the second operational amplifier U2; one end of the fourth resistor R4 is connected with the inverting input end of the second operational amplifier U2, and the other end of the fourth resistor R is grounded; one end of the seventh resistor R7 is connected with the inverting input end of the second operational amplifier U2, and the other end of the seventh resistor R7 is connected with the output end of the second operational amplifier U2; the positive electrode of the third diode D3 is connected with the output end of the second operational amplifier U2, and the negative electrode of the third diode D is connected with the input end of the fourth inverter U4; one end of the ninth resistor R9 is connected with the cathode of the third diode D3, and the other end of the ninth resistor R is grounded; one end of the twelfth resistor R12 is connected with the input end of the fourth inverter U4, and the other end of the twelfth resistor R is connected with the input end of the sixth inverter U6; one end of the first capacitor C1 is connected with the input end of the sixth inverter U6, and the other end of the first capacitor C is grounded; two input ends of the seventh NAND gate U7 are respectively connected with the cathode of the third diode D3 and the output end of the sixth inverter U6; two input ends of the eighth NAND gate U8 are respectively connected with the output end of the fourth inverter U4 and the input end of the sixth inverter U6; two input ends of the ninth NAND gate U9 are respectively connected with the output end of the seventh NAND gate U7 and the output end of the eighth NAND gate U8; the output end of the ninth NAND gate U9 is the output end of the voltage zero crossing point detection circuit.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the fourth inverter U4 and/or the sixth inverter U6 is MC14106.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the seventh nand gate U7 and/or the eighth nand gate U8 and/or the ninth nand gate U9 are CD4093.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the second positive power supply terminal is +5V.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the first positive supply terminal and the first negative supply terminal are at the same voltage.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the absolute value of the voltage of the first positive power supply terminal and the first negative power supply terminal is 5V or 10V or 15V.
Further, the invention provides a parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit, which can also have the following characteristics: the output of the comparator U11 is connected to the output FORCE-STOP.
Drawings
Fig. 1 is a circuit diagram of a parallel IGBT high frequency power supply inversion trigger pulse maximum angle control.
Detailed Description
The invention is further described below with reference to the drawings and specific embodiments.
Fig. 1 is a circuit diagram of a parallel IGBT high frequency power supply inversion trigger pulse maximum angle control.
As shown in fig. 1, in this embodiment, the parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit includes: the circuit comprises a rectifying circuit, a current spreading circuit, a voltage zero crossing detection circuit, a tenth operational amplifier U10, a comparator U11, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a second capacitor C2, a third capacitor C3, a second field effect transistor Q2, a third field effect transistor Q3 and a fourth field effect transistor Q4.
The rectifying circuit is connected with the input end INV-VOL and inputs inversion voltage; the output end is connected with the current spreading circuit. The rectifying circuit includes: the first operational amplifier U1, the third operational amplifier U3, the first diode D1, the second diode D2, the first resistor R1, the second resistor R2, the third resistor R3, the sixth resistor R6 and the eighth resistor R8.
One end of the first resistor R1 is connected with the input end INV-VOL, and the other end of the first resistor R1 is connected with the inverting input end of the first operational amplifier U1; the non-inverting input terminal of the first operational amplifier U1 is grounded. One end of the second resistor R2 is connected with the input end INV-VOL, and the other end is connected with the inverting input end of the third operational amplifier U3. One end of a sixth resistor R6 is connected with the inverting input end of the third operational amplifier U3, and the other end of the sixth resistor R6 is connected with the anode of the second diode D2; the cathode of the second diode D2 is connected to the output terminal of the first operational amplifier U1. The positive pole of the first diode D1 is connected with the output end of the first operational amplifier U1, and the negative pole is connected with the inverting input end of the first operational amplifier U1. One end of the third resistor R3 is connected to the inverting input terminal of the first operational amplifier U1, and the other end is connected to the anode of the second diode D2. One end of the eighth resistor R8 is connected to the inverting input terminal of the third operational amplifier U3, and the other end is connected to the output terminal of the third operational amplifier U3. The output end of the third operational amplifier U3 is the output end of the rectifying circuit, and the non-inverting input end of the third operational amplifier U3 is grounded.
The current spreading circuit includes: a fifth operational amplifier U5, a transistor Q1, a tenth resistor R10, an eleventh resistor R11, a fourth diode D4, a fifth diode D5, and a sixth diode D6.
One end of the tenth resistor R10 is connected with the non-inverting input end of the fifth operational amplifier U5, and the other end of the tenth resistor R is connected with the output end of the rectifying circuit, namely the output end of the third operational amplifier U3. One end of the eleventh resistor R11 is connected with the inverting input end of the fifth operational amplifier U5, and the other end of the eleventh resistor R11 is connected with the anode of the fourth diode D4; the negative electrode of the fourth diode D4 is connected with the first negative power supply end-15V. The positive electrode of the fifth diode D5 is connected to the positive electrode of the sixth diode D6, and the negative electrode is connected to the inverting input terminal of the fifth operational amplifier U5. The base electrode of the triode Q1 is connected with the output end of the fifth operational amplifier U5, the emitter electrode is connected with the positive electrode of the sixth diode D6, and the collector electrode is connected with the first positive power supply end +15V. The cathode of the sixth diode D6 is the output terminal of the current spreading circuit.
The voltage zero crossing detection circuit includes: the second operational amplifier U2, the third diode D3, the fourth inverter U4, the sixth inverter U6, the seventh nand gate U7, the eighth nand gate U8, the ninth nand gate U9, the first capacitor C1, the fourth resistor R4, the fifth resistor R5, the seventh resistor R7, the ninth resistor R9, and the twelfth resistor R12. The fourth and gate U4 and the sixth and gate U6 are MC14106. The seventh nand gate U7, eighth nand gate U8, and ninth nand gate U9 are CD4093.
One end of the fifth resistor R5 is connected with the input end INV-VOL, and the other end of the fifth resistor R5 is connected with the non-inverting input end of the second operational amplifier U2. One end of the fourth resistor R4 is connected with the inverting input end of the second operational amplifier U2, and the other end of the fourth resistor R is grounded. One end of the seventh resistor R7 is connected with the inverting input end of the second operational amplifier U2, and the other end is connected with the output end of the second operational amplifier U2. The positive pole of the third diode D3 is connected to the output terminal of the second operational amplifier U2, and the negative pole is connected to the input terminal of the fourth inverter U4. One end of the ninth resistor R9 is connected to the negative electrode of the third diode D3, and the other end is grounded. One end of the twelfth resistor R12 is connected to the input terminal of the fourth inverter U4, and the other end is connected to the input terminal of the sixth inverter U6. One end of the first capacitor C1 is connected to the input end of the sixth inverter U6, and the other end is grounded. Two input ends of the seventh NAND gate U7 are respectively connected with the cathode of the third diode D3 and the output end of the sixth inverter U6. Two input ends of the eighth NAND gate U8 are respectively connected with the output end of the fourth inverter U4 and the input end of the sixth inverter U6. Two input ends of the ninth NAND gate U9 are respectively connected with the output end of the seventh NAND gate U7 and the output end of the eighth NAND gate U8; the output end of the ninth NAND gate U9 is the output end of the voltage zero crossing point detection circuit.
One end of the thirteenth resistor R13 is connected with the output end of the current-expanding circuit, namely connected with the cathode of the sixth diode D6; the other end is connected with the drain electrode of the second field effect tube Q2. One end of the sixteenth resistor R16 is connected to the source of the second field effect transistor Q2, and the other end is connected to the non-inverting input terminal of the tenth operational amplifier U10. One end of the second capacitor C2 is connected with the source electrode of the second field effect transistor Q2, and the other end of the second capacitor C is grounded. One end of the fourteenth resistor R14 is connected with the grid electrode of the second field effect transistor Q2, and the other end of the fourteenth resistor R is connected with the first positive power supply end +15V.
The grid electrode of the third field effect transistor Q3 is connected with the output end of the voltage zero crossing point detection circuit, namely the output end of the ninth NAND gate U9; the drain electrode of the third field effect transistor Q3 is connected with the grid electrode of the second field effect transistor Q2; the source of the third field effect transistor Q3 is grounded. The grid electrode of the fourth field effect transistor Q4 is connected with the output end of the voltage zero crossing point detection circuit; the source of the fourth fet Q4 is grounded. One end of the fifteenth resistor R15 is connected with the source electrode of the second field effect transistor Q2, and the other end is connected with the drain electrode of the fourth field effect transistor Q4. One end of the seventeenth resistor R17 is connected to the inverting input terminal of the tenth operational amplifier U10, and the other end is connected to the output terminal of the tenth operational amplifier U10. One end of the eighteenth resistor R18 is connected to the output terminal of the tenth operational amplifier U10, and the other end is connected to the non-inverting input terminal of the comparator U11. One end of the twentieth resistor R20 is connected to the non-inverting input terminal of the comparator U11, and the other end is grounded. One end of the nineteenth resistor R19 is connected to the inverting input terminal of the comparator U11, and the other end is connected to the output terminal of the rectifying circuit. One end of the twenty-first resistor R21 is connected with the output end of the comparator U11, and the other end of the twenty-first resistor R is connected with the second positive power supply end +5V. One end of the third capacitor C3 is connected with the output end of the comparator U11, and the other end of the third capacitor C is grounded. The output of the comparator U11 is connected to the output FORCE-STOP.
The working principle of the parallel IGBT high-frequency power supply inversion trigger pulse maximum angle control circuit is as follows:
the input end INV-VOL is an inversion voltage, and the signal is a sine wave. The direct-current voltage waveform is obtained through precise rectification of the first operational amplifier U1, the first operational amplifier U3, the first resistor R1, the second resistor R2, the third resistor R3, the sixth resistor R6 and the eighth resistor R8, and the first diode D1 and the second diode D2.
The inverted voltage of the input end INV-VOL is input to the operational amplifier U2 through the fifth resistor R5, is output and input to the output end of the operational amplifier U2 through the fourth resistor R4 and the seventh resistor R7, the amplification factor of the output and input is 1+R7/R4, if the amplification factor is large enough, the inverted voltage of the sine wave is amplified into a square wave, and the square wave is changed into a square wave with the high level of +15V and the low level of 0V at the cathode of the third diode D3 through the third diode D3 and the ninth resistor R9. The rising edge and the falling edge of the square wave are changed into positive pulse signals through the fourth inverter U4, the sixth inverter U6, the seventh NAND gate U7 and the eighth NAND gate U8, and the pulse width is determined by the first capacitor C1 and the twelfth resistor R12. Through the operational amplifier U2, the fourth resistor R4, the fifth resistor R5, the seventh resistor R7, the third diode D3 and the ninth resistor R9, the zero crossing point of the sine wave of the inversion voltage is more reliable than the zero crossing point obtained through a comparator, and the anti-interference performance is better.
When the zero crossing point of the inversion voltage is obtained, when the ninth NAND gate U9 outputs a high-level pulse, the pulse width is determined by the first capacitor C1 and the twelfth resistor R12, the third field effect transistor Q3 is turned on, the second field effect transistor Q2 is turned off, the thirteenth resistor R13 cannot charge the second capacitor C2, the fourth field effect transistor Q4 is turned on, the second capacitor C2 is discharged through the fifteenth resistor R15, and the voltage of the second capacitor C2 is 0 after the discharge is finished, so that preparation is made for the period of operation.
After the short-time high pulse of the zero crossing point is finished, the ninth NAND gate U9 outputs 0, the third field effect transistor Q3 is closed, the second field effect transistor Q2 is conducted, the thirteenth resistor R13 can charge the second capacitor C2, the fourth field effect transistor Q4 is closed, and the fifteenth resistor R15 cannot discharge the second capacitor C2. At this time, through the fifth operational amplifier U5, the tenth resistor R10, the eleventh resistor R11, the fourth diode D4, the fifth diode D5, the sixth diode D6, and the current spreading of the transistor Q1, the thirteenth resistor R13 charges the second capacitor C2, and the voltage of the second capacitor C2 will follow the precisely rectified inversion voltage outputted from the third operational amplifier U3 until the inversion voltage reaches the peak value, at this time, the second capacitor C2 will maintain the peak value of the inversion voltage. The tenth operational amplifier U10 outputs the voltage of the second capacitor C2 after the sixteenth resistor R16 and the seventeenth resistor R17. When the sine wave rises, the output voltage of the ten operational amplifier U10 follows the inverted voltage after the precision rectification. When the sine wave reaches a peak value, the ten operational amplifier U10 outputs a peak voltage of the precisely rectified inverter voltage. The sine wave is reduced in voltage through an eighteenth resistor R18 and a twentieth resistor R20, and is input to a positive phase input end of the comparator U11, and the precisely rectified inversion voltage VINV is input to a negative phase input end of the comparator U11 through a nineteenth resistor R19. When the positive-side input terminal of the comparator U11 is greater than the negative-side input terminal, the comparator U11 outputs a high level, that is, when the inverter voltage is operated to a certain angle greater than 90 degrees up to 180 degrees, the comparator U11 outputs a high level. The control circuit may use this signal, when above this angle the trigger pulse has not stopped, forcing the end of the drive pulse of the IGBT. The angle at which the forced trigger pulse ends is determined by 180-arcsin (R18/(R18+R20)).
When the next zero crossing point of the inversion voltage comes, the voltage of the second capacitor C2 is released through the second field effect tube Q2, the third field effect tube Q3 and the fourth field effect tube Q4, and the preparation is made for the next period comparison. The third capacitor C3 is configured to avoid noise generated in the circuit during the discharging of the voltage of the second capacitor C2 by the zero crossing short pulse outputted from the ninth nand gate U9.
Claims (10)
1. The utility model provides a parallelly connected IGBT high frequency power contravariant trigger pulse maximum angle control circuit which characterized in that: the circuit comprises a rectifying circuit, a current spreading circuit, a voltage zero crossing detection circuit, a tenth operational amplifier (U10), a comparator (U11), a thirteenth resistor (R13), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), an eighteenth resistor (R18), a nineteenth resistor (R19), a twentieth resistor (R20), a twenty first resistor (R21), a second capacitor (C2), a third capacitor (C3), a second field effect transistor (Q2), a third field effect transistor (Q3) and a fourth field effect transistor (Q4);
the rectifying circuit is connected with the input end INV-VOL and inputs the inversion voltage; the output end is connected with the current spreading circuit;
the voltage zero crossing detection circuit is connected with the input end INV-VOL and inputs inversion voltage;
one end of the thirteenth resistor (R13) is connected with the output end of the current-spreading circuit, and the other end of the thirteenth resistor is connected with the drain electrode of the second field effect transistor (Q2);
one end of a sixteenth resistor (R16) is connected with the source electrode of the second field effect transistor (Q2), and the other end of the sixteenth resistor is connected with the non-inverting input end of a tenth operational amplifier (U10);
one end of the second capacitor (C2) is connected with the source electrode of the second field effect transistor (Q2), and the other end of the second capacitor is grounded;
one end of a fourteenth resistor (R14) is connected with the grid electrode of the second field effect transistor (Q2), and the other end of the fourteenth resistor is connected with the first positive power supply end;
the grid electrode of the third field effect transistor (Q3) is connected with the output end of the voltage zero crossing point detection circuit; the drain electrode of the third field effect tube (Q3) is connected with the grid electrode of the second field effect tube (Q2); the source electrode of the third field effect transistor (Q3) is grounded;
the grid electrode of the fourth field effect transistor (Q4) is connected with the output end of the voltage zero crossing point detection circuit; the source electrode of the fourth field effect transistor (Q4) is grounded;
one end of the fifteenth resistor (R15) is connected with the source electrode of the second field effect transistor (Q2), and the other end of the fifteenth resistor is connected with the drain electrode of the fourth field effect transistor (Q4);
one end of a seventeenth resistor (R17) is connected with the inverting input end of the tenth operational amplifier (U10), and the other end of the seventeenth resistor is connected with the output end of the tenth operational amplifier (U10);
one end of the eighteenth resistor (R18) is connected with the output end of the tenth operational amplifier (U10), and the other end of the eighteenth resistor is connected with the non-inverting input end of the comparator (U11);
one end of the twentieth resistor (R20) is connected with the non-inverting input end of the comparator (U11), and the other end is grounded;
one end of a nineteenth resistor (R19) is connected with the inverting input end of the comparator (U11), and the other end of the nineteenth resistor is connected with the output end of the rectifying circuit;
one end of a twenty-first resistor (R21) is connected with the output end of the comparator (U11), and the other end of the twenty-first resistor is connected with a second positive power supply end;
one end of the third capacitor (C3) is connected with the output end of the comparator (U11), and the other end of the third capacitor is grounded.
2. The parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit of claim 1, wherein:
the rectifying circuit comprises a first operational amplifier (U1), a third operational amplifier (U3), a first diode (D1), a second diode (D2), a first resistor (R1), a second resistor (R2), a third resistor (R3), a sixth resistor (R6) and an eighth resistor (R8);
one end of the first resistor (R1) is connected with the input end INV-VOL, and the other end of the first resistor is connected with the inverting input end of the first operational amplifier (U1); the non-inverting input end of the first operational amplifier (U1) is grounded;
one end of the second resistor (R2) is connected with the input end INV-VOL, and the other end of the second resistor is connected with the inverting input end of the third operational amplifier (U3);
one end of a sixth resistor (R6) is connected with the inverting input end of the third operational amplifier (U3), and the other end of the sixth resistor is connected with the anode of the second diode (D2); the negative electrode of the second diode (D2) is connected with the output end of the first operational amplifier (U1);
the positive electrode of the first diode (D1) is connected with the output end of the first operational amplifier (U1), and the negative electrode of the first diode is connected with the inverting input end of the first operational amplifier (U1);
one end of the third resistor (R3) is connected with the inverting input end of the first operational amplifier (U1), and the other end of the third resistor is connected with the anode of the second diode (D2);
one end of the eighth resistor (R8) is connected with the inverting input end of the third operational amplifier (U3), and the other end of the eighth resistor is connected with the output end of the third operational amplifier (U3);
the output end of the third operational amplifier (U3) is the output end of the rectifying circuit, and the non-inverting input end of the third operational amplifier (U3) is grounded.
3. The parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit of claim 1, wherein:
the current expansion circuit comprises a fifth operational amplifier (U5), a triode (Q1), a tenth resistor (R10), an eleventh resistor (R11), a fourth diode (D4), a fifth diode (D5) and a sixth diode (D6);
one end of a tenth resistor (R10) is connected with the non-inverting input end of a fifth operational amplifier (U5), and the other end of the tenth resistor is connected with the output end of the rectifying circuit;
one end of the eleventh resistor (R11) is connected with the inverting input end of the fifth operational amplifier (U5), and the other end of the eleventh resistor is connected with the anode of the fourth diode (D4); the negative electrode of the fourth diode (D4) is connected with the first negative power supply end;
the positive electrode of the fifth diode (D5) is connected with the positive electrode of the sixth diode (D6), and the negative electrode of the fifth diode (D5) is connected with the inverting input end of the fifth operational amplifier (U5);
the base electrode of the triode (Q1) is connected with the output end of the fifth operational amplifier (U5), the emitter electrode is connected with the positive electrode of the sixth diode (D6), and the collector electrode is connected with the first positive power supply end;
the negative electrode of the sixth diode (D6) is the output end of the current spreading circuit.
4. The parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit of claim 1, wherein:
the voltage zero crossing detection circuit comprises a second operational amplifier (U2), a third diode (D3), a fourth inverter (U4), a sixth inverter (U6), a seventh NAND gate (U7), an eighth NAND gate (U8), a ninth NAND gate (U9), a first capacitor (C1), a fourth resistor (R4), a fifth resistor (R5), a seventh resistor (R7), a ninth resistor (R9) and a twelfth resistor (R12);
one end of a fifth resistor (R5) is connected with the input end INV-VOL, and the other end of the fifth resistor is connected with the non-inverting input end of the second operational amplifier (U2);
one end of the fourth resistor (R4) is connected with the inverting input end of the second operational amplifier (U2), and the other end of the fourth resistor is grounded;
one end of the seventh resistor (R7) is connected with the inverting input end of the second operational amplifier (U2), and the other end of the seventh resistor is connected with the output end of the second operational amplifier (U2);
the positive electrode of the third diode (D3) is connected with the output end of the second operational amplifier (U2), and the negative electrode of the third diode is connected with the input end of the fourth inverter (U4);
one end of the ninth resistor (R9) is connected with the cathode of the third diode (D3), and the other end of the ninth resistor is grounded;
one end of the twelfth resistor (R12) is connected with the input end of the fourth inverter (U4), and the other end of the twelfth resistor is connected with the input end of the sixth inverter (U6);
one end of the first capacitor (C1) is connected with the input end of the sixth inverter (U6), and the other end of the first capacitor is grounded;
two input ends of the seventh NAND gate (U7) are respectively connected with the cathode of the third diode (D3) and the output end of the sixth inverter (U6);
two input ends of the eighth NAND gate (U8) are respectively connected with the output end of the fourth inverter (U4) and the input end of the sixth inverter (U6);
two input ends of the ninth NAND gate (U9) are respectively connected with the output end of the seventh NAND gate (U7) and the output end of the eighth NAND gate (U8); the output end of the ninth NAND gate (U9) is the output end of the voltage zero crossing point detection circuit.
5. The parallel IGBT high frequency power inverter trigger pulse maximum angle control circuit of claim 4 wherein: the fourth inverter (U4) and/or the sixth inverter (U6) is MC14106.
6. The parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit of claim 1, wherein: the seventh nand gate (U7) and/or the eighth nand gate (U8) and/or the ninth nand gate (U9) are CD4093.
7. The parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit of claim 1, wherein: the second positive power supply terminal is +5V.
8. The parallel IGBT high frequency power inverter trigger pulse maximum angle control circuit of claim 3, wherein: the first positive supply terminal and the first negative supply terminal are at the same voltage.
9. The parallel IGBT high frequency power inverter trigger pulse maximum angle control circuit of claim 8, wherein: the absolute value of the voltage of the first positive power supply terminal and the first negative power supply terminal is 5V or 10V or 15V.
10. The parallel IGBT high frequency power supply inversion trigger pulse maximum angle control circuit of claim 1, wherein: the output of the comparator (U11) is connected to the output FORCE-STOP.
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| CN201711059103.5A CN109756139B (en) | 2017-11-01 | 2017-11-01 | Maximum angle control circuit for inversion trigger pulse of parallel IGBT high-frequency power supply |
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| US4866592A (en) * | 1988-03-30 | 1989-09-12 | Fuji Electric Co., Ltd. | Control system for an inverter apparatus |
| JPH1198861A (en) * | 1997-09-17 | 1999-04-09 | Sansha Electric Mfg Co Ltd | Inverter and dc power unit using the same |
| CN203398981U (en) * | 2013-08-07 | 2014-01-15 | 上海新研工业设备有限公司 | Inversion drive modulation circuit of parallel resonant intermediate frequency power supply |
| WO2016019642A1 (en) * | 2014-08-07 | 2016-02-11 | 中兴通讯股份有限公司 | Device for preventing current from flowing backward |
| CN205070801U (en) * | 2015-11-06 | 2016-03-02 | 成都通用整流电器研究所 | Parallelly connected soft switching mode rectification power supply of looks IGBT contravariant that moves of multimode |
| CN207410246U (en) * | 2017-11-01 | 2018-05-25 | 上海新研工业设备股份有限公司 | High frequency electric source inversion trigger pulse maximum angle control circuit in parallel |
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2017
- 2017-11-01 CN CN201711059103.5A patent/CN109756139B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4866592A (en) * | 1988-03-30 | 1989-09-12 | Fuji Electric Co., Ltd. | Control system for an inverter apparatus |
| JPH1198861A (en) * | 1997-09-17 | 1999-04-09 | Sansha Electric Mfg Co Ltd | Inverter and dc power unit using the same |
| CN203398981U (en) * | 2013-08-07 | 2014-01-15 | 上海新研工业设备有限公司 | Inversion drive modulation circuit of parallel resonant intermediate frequency power supply |
| WO2016019642A1 (en) * | 2014-08-07 | 2016-02-11 | 中兴通讯股份有限公司 | Device for preventing current from flowing backward |
| CN205070801U (en) * | 2015-11-06 | 2016-03-02 | 成都通用整流电器研究所 | Parallelly connected soft switching mode rectification power supply of looks IGBT contravariant that moves of multimode |
| CN207410246U (en) * | 2017-11-01 | 2018-05-25 | 上海新研工业设备股份有限公司 | High frequency electric source inversion trigger pulse maximum angle control circuit in parallel |
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