CN203722474U - Quasi-Z-source DC-DC boost converter circuit - Google Patents

Abstract

The utility model provides a quasi-Z source DC-DC step-up converter circuit, which includes a voltage source, a quasi-Z source impedance network composed of a first inductance, a second inductance, a first capacitor, a second capacitor and a diode, and a MOS tube, third inductor, output capacitor and load. In the quasi-Z source DC-DC boost converter circuit described in the utility model, a voltage source, a quasi-Z source impedance network and a MOS tube are sequentially connected in series to form a boost circuit; the third inductance, an output capacitor and a load form an output circuit. The structure of the whole circuit is simple, there is only one MOS transistor, the input and output share the same ground, it has a high output voltage gain, and the voltage stress of the quasi-Z source impedance network capacitor is low, the circuit does not have the problem of startup shock, the moment the MOS transistor is turned on, the output capacitor will not Causes an instantaneous current impact on the MOS tube.

Description

A Quasi-Z Source DC-DC Boost Converter Circuit

technical field

The utility model relates to the technical field of power electronic circuits, in particular to a quasi-Z source DC-DC boost converter circuit.

Background technique

In fuel cell power generation and photovoltaic power generation, due to the low DC voltage provided by a single solar cell or a single fuel cell, it cannot meet the electricity demand of existing electrical equipment, nor can it meet the demand for grid-connected voltage. Batteries are connected in series to achieve the required voltage. On the one hand, this method greatly reduces the reliability of the entire system, and on the other hand, it needs to solve the problem of series voltage equalization. For this reason, a high-gain DC-DC converter capable of converting low voltage to high voltage is required. The quasi-Z source DC-DC converter proposed in recent years is a high-gain DC-DC converter, but the input and output of the circuit do not share the same ground, which is not conducive to the design of the control circuit, and has a high quasi-Z source impedance Network capacitor voltage stress, there is also a relatively large start-up surge current and voltage when the circuit starts, which limits the actual application of the circuit.

Utility model content

The purpose of the utility model is to overcome the above-mentioned deficiencies in the prior art and provide a quasi-Z source DC-DC boost converter circuit.

A quasi-Z source DC-DC step-up converter circuit includes a voltage source, a quasi-Z source impedance network, a MOS tube, a third inductor, an output capacitor and a load. The quasi-Z source impedance network is composed of a first inductance, a second inductance, a first capacitor, a second capacitor and a diode; the voltage source, a quasi-Z source impedance network and a MOS tube are sequentially connected in series to form a boost circuit; the third inductance , output capacitor and load form the output circuit.

Further, the specific connection mode of the quasi-Z source DC-DC boost converter circuit is as follows: the anode of the voltage source is respectively connected to one end of the first inductor and the cathode of the first capacitor; the anode of the diode is respectively connected to the first The other end of an inductor is connected to the negative pole of the second capacitor; the cathode of the diode is respectively connected to the positive pole of the first capacitor and one end of the second inductor; the drain of the MOS transistor is respectively connected to the positive pole of the second capacitor, the second The other end of the inductance is connected to one end of the third inductance; the other end of the third inductance is respectively connected to the positive pole of the output capacitor and one end of the load; the negative pole of the voltage source is respectively connected to the negative pole of the output capacitor, the other end of the load and The source connection of the MOS tube.

Compared with the prior art, the utility model circuit has the following advantages and technical effects: the voltage gain is higher, the input and output share the same ground, the capacitance voltage stress of the quasi-Z source impedance network is low, and the starting surge current and voltage are well suppressed The role, and the moment the MOS tube is turned on, the output capacitor will not cause an instantaneous current impact on the MOS tube. The circuit of the utility model is suitable for occasions where the input voltage varies widely, such as fuel cell power generation, photovoltaic power generation and other new energy power generation technical fields.

Description of drawings

FIG. 1 is a quasi-Z source DC-DC boost converter circuit in a specific embodiment of the present invention.

Figure 2a and Figure 2b are the equivalent circuit diagrams of a quasi-Z source DC-DC boost converter circuit shown in Figure 1 from the perspective of voltage relationship when the MOS transistor S is turned on and off, and the solid line in the figure indicates The part where current flows in the converter, and the dotted line indicates the part where no current flows in the converter.

Fig. 3 a is the comparison diagram of the gain curve of the utility model circuit and the gain curve of the basic boost circuit, the solid line represents the gain curve of the utility model circuit among the figure, and the dotted line represents the gain curve of the basic boost circuit;

Fig. 3b is a comparison diagram between the gain curve of the utility model circuit in Fig. 3a and the gain curve of the basic boost circuit when the duty ratio d is less than 0.4.

Fig. 4 is the working waveform diagram of the circuit of the utility model.

Detailed ways

The specific implementation of the utility model will be further described below in conjunction with the accompanying drawings.

Referring to Fig. 1 , a quasi-Z source DC-DC boost converter circuit described in the present invention includes a voltage source V _i composed of a first inductance L ₁ , a second inductance L ₂ , a first capacitor C ₁ , The quasi-Z source impedance network composed of the second capacitor C ₂ and the diode D (as shown in the dotted line box in Figure 1), the MOS transistor S, the third inductor L ₃ , the output capacitor C _o and the load R _L . The quasi-Z source DC-DC boost converter circuit described in the utility model, the voltage source V _i , the quasi-Z source impedance network and the MOS tube S are sequentially connected in series to form a boost circuit; the third inductance L ₃ , The output capacitor C _o and the load R _L constitute the output circuit. When the MOS transistor S is turned on, the voltage source V _i is connected in series with the first capacitor _C1 to charge and store energy for the second inductor _L2 ; the voltage source V _i is connected in series with the second capacitor _C2 to charge and store energy for the first inductor _L1 ; At the same time, the voltage source V _i together with the first capacitor C ₁ , the second capacitor C ₂ , and the third inductor L ₃ supply power to the output capacitor C _o and the load R _L ; when the MOS transistor S is turned off, the voltage source V _i Together with the first inductor L ₁ and the second inductor L ₂ , the third inductor L ₃ , the output capacitor C _o and the load R _L are powered. The whole circuit structure is simple, there is only one MOS tube, the input and output share the same ground, and it has a high output voltage gain. The capacitor will not cause an instantaneous current impact on the MOS tube.

The specific connection of the utility model circuit is as follows: the positive pole of the voltage source V _i is connected with one end of the first inductor _L1 and the negative pole of the first capacitor _C1 respectively; the anode of the diode D is connected with the first inductor _L1 respectively. The other end is connected to the negative pole of the second capacitor _C2 ; the cathode of the diode D is respectively connected to the positive pole of the first capacitor _C1 and one end of the second inductor _L2 ; the drain of the MOS transistor S is respectively connected to the second capacitor The positive pole of C ₂ , the other end of the second inductance L ₂ and one end of the third inductance L ₃ are connected; the other end of the third inductance L ₃ is respectively connected to the positive pole of the output capacitor C _o and one end of the load _RL ; The negative pole of the voltage source V _i is respectively connected to the negative pole of the output capacitor C _o , the other end of the load _RL and the source of the MOS transistor S.

Fig. 2a, Fig. 2b have provided the working process diagram of the circuit of the utility model. Figure 2a and Figure 2b are the equivalent circuit diagrams obtained from the perspective of voltage relationship when the MOS transistor S is turned on and turned off, respectively.

The working process of the present utility model is as follows:

Stage 1, as shown in Figure 2a: MOS transistor S is turned on, and diode D is in an off state at this time. The circuit forms three loops, namely: the voltage source V _i and the second capacitor C ₂ together charge and store the energy of the first inductor L ₁ to form a loop; the voltage source V _i and the first capacitor C ₁ together charge the second inductor L 1 L ₂ charges and stores energy to form a loop; the voltage source V _i together with the first capacitor C ₁ , the second capacitor C ₂ and the third inductor L ₃ supplies power to the output capacitor C _o and the load R _L to form a loop.

Stage 2, as shown in Figure 2b: the MOS transistor S is turned off, and the diode D is turned on at this time, and the circuit forms three loops, namely: the voltage source V _i together with the first inductance L ₁ and the second inductance L ₂ to the third The inductor L ₃ , the output capacitor C _o and the load R _L supply power to form a loop; the first inductor L ₁ is connected in parallel with the first capacitor C ₁ to form a loop; the second inductor L ₂ is connected in parallel to the second capacitor C ₂ to form a loop.

In summary, let the duty cycle of the MOS transistor S be d, and the switching period be T _s . Due to the symmetry of the quasi-Z source impedance network, that is, the inductance of the first inductor L ₁ and the second inductor L ₂ are equal, the capacitance values of the first capacitor C ₁ and the second capacitor C ₂ are equal. Therefore, v _L1 =v _L2 =v _L , V _C1 =V _C2 =V _C . v _L1 , v _L2 , V _C1 and V _C2 are the voltages of the first inductor L ₁ , the second inductor L ₂ , the first capacitor C ₁ and the second capacitor C ₂ respectively, so set v _L and V _C respectively Z source impedance network inductor voltage and capacitor voltage, v _L3 is the voltage of the third inductor L ₃ , V _S is the voltage between the drain and source of the MOS transistor S. In a switching period T _s , let the output voltage be V _o . When the converter enters the steady-state operation, the following voltage relationship derivation process is obtained.

During the conduction period of the MOS transistor S, it corresponds to the working situation described in stage 1, so the following formula is given:

v _L1 ＝v _L ＝V _i +V _C2 ＝V _i +V _C (1)

v _L2 ＝v _L ＝V _i +V _C1 ＝V _i +V _C (2)

v _L3 ＝-V _o (3)

The conduction time of the MOS transistor S is dT _s .

When the MOS transistor S is turned off, it corresponds to the working situation described in stage 2, so the following formula is given:

v _L1 ＝v _L ＝-V _C1 ＝-V _C (4)

v _L2 ＝v _L ＝-V _C2 ＝-V _C (5)

V _S ＝V _i +v _L +V _C ＝V _i +2V _C (6)

v _L3 ＝V _S -V _o ＝V _i +2V _C -V _o (7)

The turn-off time of the MOS transistor S is (1-d) T _s .

From the above analysis, according to the symmetry of the quasi-Z source impedance network and the principle of inductive volt-second conservation, the simultaneous equations (1), (2), (4) and (5) can be obtained:

(V _i +V _C )dT _s +(-V _C )(1-d)T _s ＝0 (6)

Therefore, the relationship between the capacitance voltage V _C of the quasi-Z source impedance network and the voltage source V _i can be obtained as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

From equations (3) and (7), and applying the principle of inductance volt-second conservation to the third inductance L ₃ , it can be obtained:

(-V _o )dT _s +(V _i +2V _C -V _o )(1-d)T _s ＝0 (8)

From the formula (7), the gain expression of the utility model circuit can be obtained as:

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

As shown in Fig. 3 a, it is the comparison figure of the gain curve of the utility model circuit and the gain curve of the basic boost circuit; Fig. 3 b is the gain curve of the utility model circuit gain curve and the basic boost circuit in Fig. 3 a at duty ratio d The comparison diagram within 0.4, the solid line in the figure represents the gain curve of the circuit of the utility model, and the dotted line represents the gain curve of the basic boost circuit. As can be seen from the figure, the utility model circuit can achieve a large gain G when the duty ratio d does not exceed 0.5, and the utility model circuit will not exceed 0.5 when the MOS tube duty ratio is reached. Therefore, in comparison , the gain of the utility model circuit is very high.

From formula (7) and formula (9), the relationship between the capacitance voltage V _C of the quasi-Z source impedance network of the utility model circuit, the voltage source V _i and the output voltage V _o can be obtained as follows:

V _C =V _o -V _i (10)

It can be seen from formula (10) that the maximum value of the capacitive voltage V _C of the quasi-Z source impedance network of the utility model circuit does not exceed the difference between the output voltage V _o and the voltage source V _i , thus making the utility model circuit quasi-Z source The capacitive voltage stress of the impedance network becomes lower. As shown in Fig. 4, it is the main waveform diagram when the circuit of the present invention works, in which V _g is the drive of the MOS tube, and i _L1 , i _L2 and i _L3 are respectively the first inductance L ₁ , the second inductance L 2 and the first inductance L ₂ The current of the three inductors _L3 .

In addition, due to the characteristics of the topology structure of the utility model circuit itself, when it is started, the first inductance L ₁ and the second inductance L ₂ in the quasi-Z source impedance network have an inhibitory effect on the start-up inrush current, which is beneficial to the softness of the converter. Start-up reduces the impact damage to the device; similarly, due to the existence of the third inductance _L3 , when the MOS tube is turned on, the output capacitor will not cause an instantaneous current impact on the MOS tube.

To sum up, the circuit of the utility model not only has a higher voltage gain, the input and output share the same ground, but also the quasi-Z source impedance network capacitor voltage stress is low, there is no start-up shock circuit, and the moment the MOS tube is turned on, the output capacitor will not affect the The MOS tube causes an instantaneous current shock.

The above-mentioned embodiment is a preferred implementation mode of the present utility model, but the implementation mode of the present utility model is not limited by the described embodiment, and any other changes, modifications, modifications, Substitution, combination, and simplification should all be equivalent replacement methods, and are all included in the protection scope of the present utility model.

Claims (2)

1. an accurate Z source DC-DC voltage boosting converter circuit, is characterized in that comprising voltage source (V _i), accurate Z source impedance network, metal-oxide-semiconductor (S), the 3rd inductance (L ₃), output capacitance (C _o) and load (R _l); Described accurate Z source impedance network is by the first inductance (L ₁), the second inductance (L ₂), the first electric capacity (C ₁), the second electric capacity (C ₂) and diode (D) formation; Described voltage source (V _i), accurate Z source impedance network and metal-oxide-semiconductor (S) be followed in series to form booster circuit; Described the 3rd inductance (L ₃), output capacitance (C _o) and load (R _l) formation output circuit.

2. the accurate Z of one according to claim 1 source DC-DC voltage boosting converter circuit, is characterized in that described voltage source (V _i) positive pole respectively with the first inductance (L ₁) one end and the first electric capacity (C ₁) negative pole connect; The anode of described diode (D) respectively with the first inductance (L ₁) the other end and the second electric capacity (C ₂) negative pole connect; The negative electrode of described diode (D) respectively with the first electric capacity (C ₁) positive pole and the second inductance (L ₂) one end connect; The drain electrode of described metal-oxide-semiconductor (S) respectively with the second electric capacity (C ₂) positive pole, the second inductance (L ₂) the other end and the 3rd inductance (L ₃) one end connect; Described the 3rd inductance (L ₃) the other end respectively with output capacitance (C _o) positive pole and load (R _l) one end connect; Described voltage source (V _i) negative pole respectively with output capacitance (C _o) negative pole, load (R _l) the other end be connected with the source electrode of metal-oxide-semiconductor (S).