CN115632541B - Self-adaptive no-signal time control circuit - Google Patents

Self-adaptive no-signal time control circuit Download PDF

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CN115632541B
CN115632541B CN202211652601.1A CN202211652601A CN115632541B CN 115632541 B CN115632541 B CN 115632541B CN 202211652601 A CN202211652601 A CN 202211652601A CN 115632541 B CN115632541 B CN 115632541B
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current source
module
controllable current
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CN115632541A (en
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Suzhou Baker Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The application relates to a self-adaptive no-signal time control circuit, in particular to the technical field of circuit power supply. The circuit comprises a driving signal detection module, a no-signal time adjustment module, a driving module and a power loop; a first output end of the driving signal detection module is connected to a clock end of a first D trigger of the no-signal time adjustment module; the output end of the first D trigger is connected to the first control end of the third controllable current source; a second control end of the third controllable current source is connected to the first voltage; two output ends of the third controllable current source are respectively connected with two ends of the first capacitor; two ends of the first capacitor are respectively connected to the control end of the fifth controllable current source; two output ends of the fifth controllable current source are respectively connected with two ends of the third capacitor; the first end of the third capacitor is connected to the non-inverting input end of the third comparator; and the inverting input end of the third comparator is connected with a second voltage. The circuit can make the no-signal time stable at the optimum working point of the design.

Description

Self-adaptive no-signal time control circuit
Technical Field
The application relates to the technical field of circuit power supply, in particular to a self-adaptive no-signal time control circuit.
Background
When an integrated circuit control chip controls a half-bridge type power loop or a full-bridge type power loop, it is usually necessary to set a no-signal time (so-called dead time).
However, in the prior art, the integrated circuit control chip usually adopts a control mode of fixed no-signal time, but because the switching speeds of the switching tubes in different power circuits are different, in order to ensure the universality of the integrated circuit control chip, a longer no-signal time is usually set, so that the integrated circuit control chip can be suitable for the switching tubes in different power circuits.
In this case, for most power loops, the no-signal time is too long, which may reduce the efficiency of the power loop, and a large reverse recovery current may be introduced, which may reduce the efficiency and reliability of the circuit.
Disclosure of Invention
The application provides a self-adaptive no-signal time control circuit, which can enable the no-signal time to be self-adaptively adjusted according to the switching speed of a switching tube, and finally enable the no-signal time to be stabilized at the designed optimal working point.
The circuit comprises a driving signal detection module, a no-signal time adjustment module, a driving module and a power loop;
the driving module is used for generating control signals of a first power switch tube M1 and a second power switch tube M2 in a power loop; the input end of the driving signal detection module receives control signals of the first power switch tube M1 and the second power switch tube M2 respectively;
a first output end of the driving signal detection module is connected to a clock end of a first D flip-flop A6 of the no-signal time adjustment module; a second output end of the driving signal detection module is connected to a clock end of a second D flip-flop A7 of the no-signal time adjustment module;
the output end of the first D flip-flop A6 is connected to the first control end of a third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of a fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to a first voltage;
two output ends of the third controllable current source G3 are respectively connected with two ends of the first capacitor C1; two output ends of the fourth controllable current source G4 are connected to two ends of the second capacitor C2, respectively; two ends of the first capacitor C1 are respectively connected to two control ends of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to two control ends of a sixth controllable current source G6;
two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to a first discharging loop; two output ends of the sixth controllable current source G6 are connected to two ends of the fourth capacitor C4, respectively; two ends of the fourth capacitor C4 are respectively connected to a second discharging loop;
a first end of the third capacitor C3 is connected to a non-inverting input end of a third comparator A8; a first end of the fourth capacitor C4 is connected to a non-inverting input end of a fourth comparator A9; the inverting input ends of the third comparator A8 and the fourth comparator A9 are connected with a second voltage;
the output end of the third comparator A8 transmits a first delay signal to the driving module through a NOT gate; the output end of the fourth comparator A9 transmits a second delay signal to the driving module through the NOT gate.
In a possible implementation manner, a first signal output end of the driving module is connected with a control end of the first power switch tube M1; and a second signal output end of the driving module is connected with a control end of the second power switch tube M2.
In a possible implementation manner, the input end of the driving signal detection module includes a first input end of the driving signal detection module and a second input end of the driving signal detection module;
the first signal output end of the driving module is also connected to the first input end of the driving signal detection module; and the second signal output end of the driving module is also connected to the second input end of the driving signal detection module.
In one possible implementation manner, the first signal output terminal of the driving module outputs a difference between a first periodic signal and the first delayed signal; a second signal output end of the driving module outputs a difference between a second periodic signal and the second delayed signal; the first periodic signal is an inverted signal of the second periodic signal;
in a possible implementation manner, if the first input end and the second input end of the driving signal detection module are both at a low level, when the first periodic signal is at a high level, the first output end of the driving signal detection module outputs a high level; and when the second periodic signal is at a high level, the second output end of the driving signal detection module outputs the high level.
In a possible implementation manner, the driving module is further configured to generate a first reset signal and a second reset signal; the first reset signal, the second reset signal, the first periodic signal, and the second periodic signal have the same period;
the driving module transmits the first reset signal to a first D flip-flop A6 to control the reset of the first D flip-flop A6;
the driving module transmits the second reset signal to a second D flip-flop A7 to control the reset of the second D flip-flop A7;
the driving module transmits the first reset signal to a first discharging loop so as to control the discharging of the third capacitor C3;
the driving module transmits the second reset signal to a second discharge loop to control the discharge of the fourth capacitor C4.
In one possible implementation, a falling edge of the first reset signal coincides with a rising edge of the first periodic signal; a falling edge of the second reset signal coincides with a rising edge of the second periodic signal.
In a possible implementation manner, the first control terminal of the third controllable current source G3 is a positive control terminal; the second control end of the third controllable current source G3 is a negative control end;
the first control end of the fourth controllable current source G4 is a positive control end; the second control terminal of the fourth controllable current source G4 is a negative control terminal.
In a possible implementation manner, when the voltage of the first input terminal of the driving signal detection module is less than the third voltage, the first input terminal of the driving signal detection module is at a low level;
and when the voltage of the second input end of the driving signal detection module is less than the fourth voltage, the second input end of the driving signal detection module is at a low level.
In a possible implementation manner, the driving signal detection module includes a first operational amplifier A1, a second operational amplifier A2, a first not gate A3, a first switch module, a second switch module, a first current source G7, a first and gate A4, and a second and gate A5;
a non-inverting input end of the first operational amplifier A1 is connected to a third voltage, and an inverting input end of the first operational amplifier A1 is a first input end of the driving signal detection module;
a non-inverting input end of the second operational amplifier A2 is connected to a fourth voltage, and an inverting input end of the second operational amplifier A2 is a second input end of the driving signal detection module;
the output end of the first operational amplifier A1 is connected to the control end of the first switch module; the output end of the second operational amplifier A2 is connected to the control end of the second switch module;
the first current source G7 is connected to an input terminal of the first not gate A3; the input end of the first NOT gate A3 is grounded through the first switch module and the second switch module in sequence; the output end of the first not gate A3 is respectively connected to the second input end of the first and gate A4 and the first input end of the second and gate A5; a first periodic signal is input to a first input end of the first AND gate A4; a second periodic signal is input to a second input end of the second and gate A5;
the output end of the first and gate A4 is a first output end of the driving signal detection module, and the output end of the second and gate A5 is a second output end of the driving signal detection module.
In a possible implementation manner, the first switch module is a first controllable current source G1, and the second switch module is a second controllable current source G2;
the output end of the first operational amplifier A1 is connected to the positive control end of a first controllable current source G1; the output end of the second operational amplifier A2 is connected to the positive control end of a second controllable current source G2; the negative control end of the first controllable current source G1 and the negative control end of the second controllable current source G2 are grounded, respectively.
In a possible implementation manner, the no-signal time adjustment module further includes a first current limiting module;
the fifth controllable current source G5 is connected to the first node of the first current limiting module; the second node of the first current limiting module is connected to the first end of a third capacitor C3;
and the third node of the first current limiting module is grounded.
In one possible implementation manner, in the first current limiting module, a first node of the first current limiting module is connected to a fourth node of the first current limiting module through a second resistor R2;
the fourth node of the first current limiting module is connected to the positive control end of a tenth controllable current source G14 through a seventh controllable current source G11; the positive control end of the tenth controllable current source G14 is connected to the third node of the first current limiting module through a first resistor R1;
the fourth node of the first current limiting module is connected to the negative control end of a seventh controllable current source G11 through a second current source G16; the negative control end of the seventh controllable current source G11 is connected to the third node of the first current limiting module through an eleventh controllable current source G15;
the fourth node of the first current limiting module is further connected to the positive control end of an eighth controllable current source G12 through a ninth controllable current source G13 in sequence;
the positive control end of the eighth controllable current source G12 is connected to the third node of the first current limiting module through a third resistor R3 and a tenth controllable current source G14, respectively;
the positive control end of the eighth controllable current source G12 is further connected to the positive control end of the eleventh controllable current source G15;
positive control ends of the seventh controllable current source G11 and the ninth controllable current source G13 are respectively connected to the fourth node of the first current limiting module;
the negative control end of the ninth controllable current source G13 is connected to the first node of the first current limiting module;
negative control ends of the eighth controllable current source G12, the tenth controllable current source G14 and the eleventh controllable current source G15 are respectively connected to the third node of the first current limiting module;
the second node of the first current limiting module is connected to the third node of the first current limiting module through an eighth controllable current source G12.
In a possible implementation manner, the no-signal time adjusting module further includes a second current limiting module;
the sixth controllable current source G6 is connected to the first node of the second current limiting module; the second node of the second current limiting module is connected to the first end of a fourth capacitor C4;
and a third node of the second current limiting module is grounded.
In a possible implementation manner, in the second current limiting module, a first node of the second current limiting module is connected to a fourth node of the second current limiting module through a fifth resistor R5;
the fourth node of the second current limiting module is connected to the positive control end of a fifteenth controllable current source G24 through a twelfth controllable current source G21; the positive control end of the fifteenth controllable current source G24 is connected to the third node of the second current limiting module through a fourth resistor R4;
the fourth node of the second current limiting module is connected to the negative control end of a twelfth controllable current source G21 through a third current source G26; the negative control end of the twelfth controllable current source G21 is connected to the third node of the second current limiting module through a sixteenth controllable current source G25;
the fourth node of the second current limiting module is further connected to the positive control end of a thirteenth controllable current source G22 through a fourteenth controllable current source G23 in sequence;
the positive control end of the thirteenth controllable current source G22 is connected to the third node of the second current limiting module through a sixth resistor R6 and a fifteenth controllable current source G24, respectively;
the positive control end of the thirteenth controllable current source G22 is further connected to the positive control end of the sixteenth controllable current source G25;
positive control ends of the twelfth controllable current source G21 and the fourteenth controllable current source G23 are respectively connected to a fourth node of the second current limiting module;
a negative control end of the fourteenth controllable current source G23 is connected to the first node of the second current limiting module;
negative control ends of the thirteenth controllable current source G22, the fifteenth controllable current source G24 and the sixteenth controllable current source G25 are respectively connected to the third node of the second current limiting module;
the second node of the second current limiting module is connected to the third node of the second current limiting module via a thirteenth controllable current source G22.
The technical scheme provided by the application can comprise the following beneficial effects:
in the self-adaptive no-signal time control circuit, a driving module is used for generating control signals of a first power switch tube M1 and a second power switch tube M2 in a power loop; the input end of the driving signal detection module receives control signals of a first power switch tube M1 and a second power switch tube M2 respectively; a first output end of the driving signal detection module is connected to a clock end of a first D trigger A6 of the no-signal time adjustment module; the second output end of the driving signal detection module is connected to the clock end of a second D trigger A7 of the no-signal time adjustment module; the output end of the first D flip-flop A6 is connected to the first control end of the third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of the fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to the first voltage; two ends of the first capacitor C1 are respectively connected to two control ends of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to two control ends of a sixth controllable current source G6; two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to the first discharging loop; two output ends of the sixth controllable current source G6 are connected to two ends of the fourth capacitor C4, respectively; two ends of the fourth capacitor C4 are respectively connected to the second discharging loop; a first end of the third capacitor C3 is connected to the non-inverting input end of the third comparator A8; a first end of the fourth capacitor C4 is connected to the non-inverting input end of the fourth comparator A9; the inverting input end of the third comparator A8 and the inverting input end of the fourth comparator A9 are connected with a second voltage; the output end of the third comparator A8 transmits a first delay signal to the driving module through the NOT gate; the output terminal of the fourth comparator A9 transmits the second delayed signal to the driving module through the not gate. Through the structure, the no-signal time is determined by the coincidence moment when the voltage of the output signal of the first signal output end is equal to the third voltage and the voltage of the output signal of the second signal output end is equal to the fourth voltage, so that the no-signal time can be adaptively adjusted according to the switching speed of the switching tube when different processes, applications and environments change to cause different switching speeds of the switching tube (for example, when the switching tube with different switching speeds is used by a power loop or when the switching tube is in different working stages), finally, the no-signal time is stabilized at the designed optimal working point, and the efficiency and the reliability of the power loop are both considered.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings used in the detailed description or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram illustrating a structure of an adaptive no-signal time control circuit according to an exemplary embodiment.
Fig. 2 shows a signal waveform diagram of an adaptive no-signal time control circuit according to an embodiment of the present application.
Fig. 3 shows a schematic structural diagram of an adaptive signal-free time control circuit according to an embodiment of the present application.
Fig. 4 shows a schematic structural diagram of an adaptive signal-free time control circuit according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram illustrating an adaptive no-signal time control circuit according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram illustrating a first current limiting module according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram illustrating a second current limiting module according to an embodiment of the present disclosure.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic diagram illustrating a structure of an adaptive no-signal time control circuit according to an exemplary embodiment. The self-adaptive no-signal time control circuit can enable the no-signal time to be self-adaptively adjusted according to the switching speed of the switching tube, and finally enables the no-signal time to be stable at the designed optimal working point. As shown in fig. 1, the circuit includes a driving signal detection module, a no-signal time adjustment module, a driving module and a power loop;
the driving module is used for generating control signals of a first power switch tube M1 and a second power switch tube M2 in a power loop; the input end of the driving signal detection module receives control signals of a first power switch tube M1 and a second power switch tube M2 respectively;
a first output end of the driving signal detection module is connected to a clock end of a first D flip-flop A6 of the no-signal time adjustment module; the second output end of the driving signal detection module is connected to the clock end of a second D trigger A7 of the no-signal time adjustment module;
the output terminal of the first D flip-flop A6 is connected to the first control terminal of the third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of the fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to a first voltage;
two output ends of the third controllable current source G3 are connected to two ends of the first capacitor C1, respectively; two output ends of the fourth controllable current source G4 are connected to two ends of the second capacitor C2, respectively; two ends of the first capacitor C1 are respectively connected to two control ends of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to two control ends of a sixth controllable current source G6;
two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to the first discharging loop; two output ends of the sixth controllable current source G6 are connected to two ends of the fourth capacitor C4, respectively; two ends of the fourth capacitor C4 are respectively connected to a second discharging loop;
the first end of the third capacitor C3 is connected to the non-inverting input terminal of the third comparator A8; a first end of the fourth capacitor C4 is connected to the non-inverting input terminal of the fourth comparator A9; the inverting input terminal of the third comparator A8 and the inverting input terminal of the fourth comparator A9 are connected to a second voltage;
the output terminal of the third comparator A8 transmits the first DELAY signal DELAY1 to the driving module through the not gate; the output terminal of the fourth comparator A9 transmits the second DELAY signal DELAY2 to the driving module through the not gate.
In a possible implementation manner, the first signal output terminal TG of the driving module is connected to the control terminal of the first power switch M1; the second signal output end BG of the driving module is connected with the control end of the second power switch tube M2.
In one possible implementation manner, the input end of the driving signal detection module includes a first input end of the driving signal detection module and a second input end of the driving signal detection module;
the first signal output end of the driving module is also connected to the first input end of the driving signal detection module; the second signal output end of the driving module is also connected to the second input end of the driving signal detection module.
In one possible implementation manner, the driving signal output by the first signal output terminal TG of the driving module is a difference between the first periodic signal SWON and the first delayed signal DELAY1; the driving signal output by the second signal output terminal BG of the driving module is the difference between the second periodic signal SWONB and the second DELAY signal DELAY 2; the first periodic signal SWON is an inverted signal of the second periodic signal SWONB.
In a possible implementation manner, if the voltage VGR of the first input terminal and the voltage VGF of the second input terminal of the driving signal detection module are both at a low level, when the first period signal SWON is at a high level, the first output terminal of the driving signal detection module outputs a high level; when the second periodic signal SWONB is at a high level, the second output terminal of the driving signal detection module outputs a high level.
In a possible implementation, the driving module is further configured to generate a first RESET signal RESET1 and a second RESET signal RESET2; the periods of the first RESET signal RESET1, the second RESET signal RESET2, the first periodic signal SWON and the second periodic signal SWONB are the same;
the driving module transmits the first RESET signal RESET1 to a first D flip-flop A6 to control the RESET of the first D flip-flop A6;
the driving module transmits the second RESET signal RESET2 to a second D flip-flop A7 to control the RESET of the second D flip-flop A7;
the driving module transmits the first RESET signal RESET1 to a first discharging loop to control the discharging of the third capacitor C3;
the driving module transmits the second RESET signal RESET2 to a second discharging circuit to control the discharging of the fourth capacitor C4.
In one possible implementation, the falling edge of the first RESET signal RESET1 coincides with the rising edge of the first periodic signal SWON; the falling edge of the second RESET signal RESET2 coincides with the rising edge of the second periodic signal SWONB.
In a possible implementation manner, the first control terminal of the third controllable current source G3 is a positive control terminal; the second control end of the third controllable current source G3 is a negative control end;
the first control terminal of the fourth controllable current source G4 is a positive control terminal; the second control terminal of the fourth controllable current source G4 is a negative control terminal.
Optionally, the first current end of the third controllable current source G3 is connected to the positive control end of the fifth controllable current source G5; a second current end of the third controllable current source G3 is connected to a negative control end of the fifth controllable current source G5; a first current end of the fifth controllable current source G5 is connected to a first end of the third capacitor C3; a second current end of the fifth controllable current source G5 is connected to a second end of the third capacitor C3;
the first current end of the fourth controllable current source G4 is connected to the positive control end of the sixth controllable current source G6; the second current end of the fourth controllable current source G4 is connected to the negative control end of the sixth controllable current source G6; a first current end of the sixth controllable current source G6 is connected to a first end of the fourth capacitor C4; a second current terminal of the sixth controllable current source G6 is connected to a second terminal of the fourth capacitor C4.
Optionally, the second end of the third capacitor C3 is grounded; the second terminal of the fourth capacitor C4 is grounded.
In a possible implementation manner, when the voltage VGR of the first input terminal of the driving signal detection module is less than the third voltage VTR, the voltage VGR of the first input terminal of the driving signal detection module is at a low level;
when the voltage VGF of the second input terminal of the driving signal detection module is less than the fourth voltage VTF, the voltage VGF of the second input terminal of the driving signal detection module is at a low level.
Fig. 2 shows a signal waveform diagram of an adaptive no-signal time control circuit according to an embodiment of the present application. With reference to fig. 2, the principle of the adaptive no-signal time control circuit shown in fig. 1 is as follows:
when the circuit is just powered on, the driving module outputs a first period signal SWON and a first RESET signal RESET1 to the driving signal detection module and the no-signal time adjustment module. Therefore, at this time, the voltage across the third capacitor C3 is discharged to 0 by the first discharging circuit, and meanwhile, since the voltage on the first capacitor C1 is also 0 at this time, the output current of the fifth controllable current source G5 is 0, the voltage at the non-inverting input terminal of the third comparator A8 is at a low level, and the first DELAY signal DELAY1 output by the third comparator A8 is at a high level.
Since the first periodic signal SWON is an original driving signal for turning ON the first power switch tube M1 and the second periodic signal SWONB is an original driving signal for turning ON the second power switch tube M2, the actual driving signal TG _ ON of the first power switch tube M1 is SWON-DELAY 1, and the actual driving signal BG _ ON of the second power switch tube M2 is SWONB-DELAY 2. Since the first DELAY signal DELAY1 and the second DELAY signal DELAY2 are no-signal time signals when the switching tube is turned on, the falling edge of the actual driving signal is the same as the falling edge of the original driving signal.
Therefore, when the circuit is just powered on, the output signal of the first signal output terminal TG is at a low level (i.e. the voltage of the output signal of the first signal output terminal TG is less than the third voltage VTR), and the output signal of the second signal output terminal BG is in a falling edge state (as shown in fig. 2). When the voltage of the output signal of the second signal output terminal BG decreases to be less than the fourth voltage VTF, the output signal TD1 of the first output terminal changes from low level to high level, and the output signal TD2 of the second output terminal remains at low level.
As can be seen from fig. 2, before the first period signal SWON changes to a high level, the first RESET signal RESET1 first outputs a high level pulse for resetting the first D flip-flop A6 and controlling the first discharging circuit to discharge the third capacitor C3. At this time, since the output signal TD1 of the first output terminal changes from the low level to the high level, the output signal TD1X of the first D flip-flop A6 is at the high level 4V, the third controllable current source G3 is turned on, a charging current is generated to charge the first capacitor C1, and the voltage across the first capacitor C1 increases, so that the fifth controllable current source G5 outputs the charging current to charge the third capacitor C3.
Therefore, the terminal voltage of the third capacitor C3 continuously increases, and when the terminal voltage of the third capacitor C3 increases to 1V, the first DELAY signal DELAY1 decreases from a high level to a low level. At this time, the actual driving signal TG _ ON of the first power switch M1 changes from low level to high level, the voltage of the output signal of the first signal output terminal TG starts to gradually rise, and when the voltage of the output signal of the first signal output terminal TG rises to be greater than the third voltage VTR, the output signal TD1 of the first output terminal is changed from high level to low level. And due to the characteristics of the D flip-flop, before the next time the first RESET signal RESET1 changes from the low level to the high level, the output signal TD1X of the first D flip-flop A6 is always at the high level 4V, at this time, the third controllable current source G3 is always in the on state, and the first capacitor C1 is always charged, so that the control voltage is always present at the control end of the fifth controllable current source G5, so the fifth controllable current source G5 is always in the on state, and the third capacitor C3 is always in the charged state, until the first discharging circuit receives the first RESET signal RESET1 at the high level, the first discharging circuit discharges the voltage of the third capacitor C3 to 0.
After the second period of the first RESET signal RESET1 changes from low level to high level, the output signal TD1X of the first D flip-flop A6 is RESET to low level, the current output by the third controllable current source G3 is reversed, the first capacitor C1 is discharged, and the first capacitor C1 is discharged for a short time (the discharging time is much shorter than the charging time because the output signal TD1 of the first output terminal is also quickly changed from low level to high level after the first RESET signal RESET1 changes from low level to high level), the current output by the third controllable current source G3 is reversed again to the charging current of the first capacitor C1, and the terminal voltage of the first capacitor C1 continues to rise.
At this time, since the initial terminal voltage of the first capacitor C1 in the second period is greater than the initial terminal voltage of the first capacitor C1 in the first period, the current generated by the fifth controllable current source G5 in the second period is greater than the current generated by the fifth controllable current source G5 in the first period, so that the time for charging the third capacitor C3 from 0V to 1V in the second period is less than the time for charging the third capacitor C3 from 0V to 1V in the first period, that is, the no-signal time generated in the second period is less than the no-signal time generated in the first period, and therefore, the high level duration of the output signal TD1 of the first output terminal generated in the second period is also less than the high level duration of the output signal TD1 of the first output terminal generated in the first period.
Then, every time a period passes, the no-signal time is reduced until the time when the voltage of the output signal of the first signal output terminal TG is equal to the third voltage VTR and the voltage of the output signal of the second signal output terminal BG is equal to the fourth voltage VTF coincides within the S-th period after a plurality of periods pass (note that the no-signal time signal in this period is DELAY 1-0), and at this time, the voltage of the output signal of the first signal output terminal TG is not present and is less than the coincidence time period of the third voltage VTR and the voltage of the output signal of the second signal output terminal BG and is less than the fourth voltage VTF. Therefore, the output signal TD1 of the first output terminal is 0, and in this period, after the first RESET signal RESET1 changes from low level to high level, the output signal TD1X of the first D flip-flop A6 is always low level, and the first capacitor C1 is always in a discharging state.
In the (S + 1) th period, because the voltage across the first capacitor C1 is reduced, the time that the first DELAY signal DELAY1 is at a high level is prolonged, the output signal TD1 of the first output end is generated, and the first capacitor C1 starts to charge; meanwhile, as can be seen from fig. 2, the discharge time of the first capacitor C1 in the S-th period is the time from when the first RESET signal RESET1 is at a high level to when the output signal TD1 of the first output terminal in the S + 1-th period is at a high level, and the charge time of the first capacitor C1 in the S + 1-th period is only the time from when the output signal TD1 of the first output terminal in the S + 1-th period is at a high level to when the first RESET signal RESET1 is at a high level in the S + 2-th period, so that the charge time of the first capacitor C1 in the S + 1-th period is short, that is, the terminal voltages at two ends of the first capacitor C1 after charging in the S +1 th cycle cannot make the time when the voltage of the output signal of the first signal output terminal TG is equal to the third voltage VTR coincide with the time when the voltage of the output signal of the second signal output terminal BG is equal to the fourth voltage VTF, that is, in the S +2 th cycle, the time when the first DELAY signal DELAY1 is at a high level is longer than DELAY1-0, the output signal TD1 of the first output terminal is still generated, the first capacitor C1 starts to be charged, and after the S +2 th cycle is ended, the voltage of the first capacitor C1 is higher, so that the time when the first DELAY signal DELAY1 is at a high level in the S +3 th cycle is shorter than DELAY1-0, the output signal TD1 of the first output terminal is 0, and the first capacitor C1 is discharged; after m periods of adjustment, the time when the voltage of the output signal of the first signal output terminal TG is equal to the third voltage VTR and the time when the voltage of the output signal of the second signal output terminal BG is equal to the fourth voltage VTF coincide, so that the final circuit no-signal time is stabilized at the time when DELAY1-0 is high level from the large signal analysis.
For the first period when the circuit is just powered on, because the voltages on the second capacitor C2 and the fourth capacitor C4 are both 0, the voltage at the non-inverting input terminal of the fourth comparator A9 is at a low level, and the second DELAY signal DELAY2 output by the fourth comparator A9 is always at a high level (the waveform of the second DELAY signal DELAY2 is shown in fig. 2).
It should be noted that the first discharge circuit and the second discharge circuit may be discharge circuits commonly used in the art, such as discharge circuits composed of a switch tube and a resistor.
In summary, in the adaptive no-signal time control circuit, the driving module is configured to generate control signals of the first power switch M1 and the second power switch M2 in the power loop; the input end of the driving signal detection module receives control signals of the first power switch tube and the second power switch tube respectively; a first output end of the driving signal detection module is connected to a clock end of a first D trigger A6 of the no-signal time adjustment module; a second output end of the driving signal detection module is connected to a clock end of a second D trigger A7 of the no-signal time adjustment module; the output end of the first D flip-flop A6 is connected to the first control end of the third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of the fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to the first voltage; two ends of the first capacitor C1 are respectively connected to the control end of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to the control end of the sixth controllable current source G6; two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to the first discharging loop; two output ends of the sixth controllable current source G6 are connected to two ends of the fourth capacitor C4, respectively; two ends of the fourth capacitor C4 are respectively connected to the second discharging loop; a first end of the third capacitor C3 is connected to the non-inverting input end of the third comparator A8; a first end of the fourth capacitor C4 is connected to the non-inverting input end of the fourth comparator A9; the inverting input end of the third comparator A8 and the inverting input end of the fourth comparator A9 are connected with a second voltage; the output end of the third comparator A8 transmits a first delay signal to the driving module through the NOT gate; the output terminal of the fourth comparator A9 transmits the second delayed signal to the driving module through the not gate. Through the structure, the no-signal time is determined by the coincidence moment that the voltage of the output signal of the first signal output end is equal to the third voltage and the voltage of the output signal of the second signal output end is equal to the fourth voltage, so that the no-signal time is adaptively adjusted according to the switching speed of the switching tube when the switching speed of the switching tube is different due to different processes, applications and environment changes (for example, when the switching tube with different switching speeds is used in a power loop or when the switching speed of the switching tube is different in different working stages due to the fact that the power loop is in different working stages), and finally the no-signal time is stabilized at the designed optimal working point, and the efficiency and the reliability of the power loop are both considered.
On the basis of fig. 1, the driving signal detecting module may also be a structure as shown in fig. 3. Fig. 3 shows a schematic structural diagram of an adaptive signal-free time control circuit according to an embodiment of the present application.
As shown in fig. 3, in a possible implementation manner, the driving signal detection module includes a first operational amplifier A1, a second operational amplifier A2, a first not gate A3, a first switch module, a second switch module, a first current source G7, a first and gate A4, and a second and gate A5;
the non-inverting input end of the first operational amplifier A1 is connected with a third voltage, and the inverting input end of the first operational amplifier A1 is the first input end of the driving signal detection module;
the non-inverting input end of the second operational amplifier A2 is connected to a fourth voltage, and the inverting input end of the second operational amplifier A2 is the second input end of the driving signal detection module;
the output end of the first operational amplifier A1 is connected to the control end of the first switch module; the output end of the second operational amplifier A2 is connected to the control end of the second switch module;
the first current source G7 is connected to the input terminal of the first not gate A3; the input end of the first NOT gate A3 is grounded through the first switch module and the second switch module in sequence; the output end of the first not gate A3 is respectively connected to the second input end of the first and gate A4 and the first input end of the second and gate A5; a first input end of the first and gate A4 inputs a first periodic signal; a second periodic signal is input to a second input end of the second and gate A5;
the output end of the first and gate A4 is a first output end of the driving signal detection module, and the output end of the second and gate A5 is a second output end of the driving signal detection module.
The working principle of the driving signal detection module of the adaptive signal-free time control circuit shown in fig. 3 is as follows:
when the circuit is just powered on, the output signal of the first signal output terminal TG is at a low level (i.e. the voltage of the output signal of the first signal output terminal TG is less than the third voltage VTR), and the output signal of the second signal output terminal BG is in a falling edge stage (as shown in fig. 2). When the voltage of the output signal of the second signal output terminal BG is decreased to be less than the fourth voltage VTF, the first operational amplifier A1 and the second operational amplifier A2 both output a high level, and at this time, the first switch module and the second switch module generate a current to pull down the input terminal of the first not gate A3, so that at this time, the input terminals of the first and gate A4 and the second and gate A5 connected to the output terminal of the first not gate A3 are both at a high level, and at this time, the first periodic signal SWON is at a high level, and the second periodic signal SWONB is at a low level, so the output signal TD1 of the first output terminal is changed from a low level to a high level, and the output signal TD2 of the second output terminal is still at a low level.
Further, on the basis of fig. 3, the first switch module and the second switch module may also be configured as shown in fig. 4. Fig. 4 shows a schematic structural diagram of an adaptive signal-free time control circuit according to an embodiment of the present application.
As shown in fig. 4, in a possible implementation manner, the first switch module is a first controllable current source G1, and the second switch module is a second controllable current source G2;
the output end of the first operational amplifier A1 is connected to the positive control end of a first controllable current source G1; the output end of the second operational amplifier A2 is connected to the positive control end of a second controllable current source G2; the negative control terminal of the first controllable current source G1 and the negative control terminal of the second controllable current source G2 are grounded, respectively.
The working principle of the driving signal detection module of the adaptive signal-free time control circuit shown in fig. 4 is as follows:
when the circuit is just powered on, the output signal of the first signal output terminal TG is at a low level (i.e. the voltage of the output signal of the first signal output terminal TG is less than the third voltage VTR), and the output signal of the second signal output terminal BG is in a falling edge stage (as shown in fig. 2). When the voltage of the output signal of the second signal output terminal BG decreases to be less than the fourth voltage VTF, the first operational amplifier A1 and the second operational amplifier A2 both output a high level, at this time, the first controllable current source G1 and the second controllable current source G2 generate currents to pull down the input terminal of the not gate A3, so at this time, the input terminals of the first and gate A4 and the second and gate A5 connected to the output terminal of the first not gate A3 are both at a high level, and at this time, the first periodic signal SWON is at a high level, the second periodic signal SWONB is at a low level, therefore, the output signal TD1 of the first output terminal changes from a low level to a high level, and the output signal TD2 of the second output terminal remains at a low level.
Optionally, the first switch module and the second switch module may be implemented by a switch tube, in addition to the controllable current source shown in fig. 4.
At this time, it should be noted that the third voltage VTR and the fourth voltage VTF have a value range of 0V or more and less than the turn-on voltage VTH of the switching tube (usually, the turn-on voltage VTH is 0.7V). Meanwhile, as can be seen from the above description, the timing when the voltage of the output signal of the first signal output terminal TG is equal to the third voltage VTR occurs earlier than the timing when the voltage of the output signal of the second signal output terminal BG is equal to the fourth voltage VTF during the circuit adjustment process. Therefore, in order to prevent the shoot-through as much as possible, the values of the third voltage VTR and the fourth voltage VTF may be both designed to be 0V.
In summary, in the adaptive no-signal time control circuit, the driving module is configured to generate control signals of the first power switch M1 and the second power switch M2 in the power loop; the input end of the driving signal detection module receives control signals of the first power switch tube and the second power switch tube respectively; a first output end of the driving signal detection module is connected to a clock end of a first D trigger A6 of the no-signal time adjustment module; a second output end of the driving signal detection module is connected to a clock end of a second D trigger A7 of the no-signal time adjustment module; the output end of the first D flip-flop A6 is connected to the first control end of the third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of the fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to the first voltage; two ends of the first capacitor C1 are respectively connected to the control end of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to the control end of a sixth controllable current source G6; two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to the first discharging loop; two output ends of a sixth controllable current source G6 are respectively connected with two ends of a fourth capacitor C4; two ends of the fourth capacitor C4 are respectively connected to the second discharging loop; a first end of the third capacitor C3 is connected to the non-inverting input end of the third comparator A8; a first end of the fourth capacitor C4 is connected to the non-inverting input end of the fourth comparator A9; the inverting input end of the third comparator A8 and the inverting input end of the fourth comparator A9 are connected with a second voltage; the output end of the third comparator A8 transmits a first delay signal to the driving module through the NOT gate; the output terminal of the fourth comparator A9 transmits the second delayed signal to the driving module through the not gate. Through the structure, the no-signal time is determined by the coincidence moment that the voltage of the output signal of the first signal output end is equal to the third voltage and the voltage of the output signal of the second signal output end is equal to the fourth voltage, so that the no-signal time is adaptively adjusted according to the switching speed of the switching tube when the switching speed of the switching tube is different due to different processes, applications and environment changes (for example, when the switching tube with different switching speeds is used in a power loop or when the switching speed of the switching tube is different in different working stages due to the fact that the power loop is in different working stages), and finally the no-signal time is stabilized at the designed optimal working point, and the efficiency and the reliability of the power loop are both considered.
Further, in order to ensure that no through-current occurs in the circuit, a first current limiting module and a second current limiting module may be disposed in the no-signal time adjusting module in the adaptive no-signal time control circuit as shown in any one of fig. 1, fig. 3, and fig. 4. Fig. 5 is a schematic structural diagram of an adaptive no-signal time control circuit according to an embodiment of the present application, and as shown in fig. 5, a circuit formed by adding a first current limiting module and a second current limiting module to fig. 4 is provided. Fig. 6 shows a schematic structural diagram of a first current limiting module according to an embodiment of the present application, and fig. 7 shows a schematic structural diagram of a second current limiting module according to an embodiment of the present application.
As shown in fig. 6, in a possible implementation, the fifth controllable current source G5 is connected to the first node of the first current limiting module; the second node of the first current limiting module is connected to the first end of a third capacitor C3;
the third node of the first current limiting module is grounded.
As shown in fig. 6, in one possible implementation manner, in the first current limiting module, a first node of the first current limiting module is connected to a fourth node of the first current limiting module through a second resistor R2; in the first current limiting module, a fourth node of the first current limiting module is connected to a power supply VDD.
The fourth node of the first current limiting module is connected to the positive control end of a tenth controllable current source G14 through a seventh controllable current source G11; the positive control end of the tenth controllable current source G14 is connected to the third node of the first current limiting module through the first resistor R1;
the fourth node of the first current limiting module is connected to the negative control end of a seventh controllable current source G11 through a second current source G16; the negative control terminal of the seventh controllable current source G11 is connected to the third node of the first current limiting module through an eleventh controllable current source G15;
the fourth node of the first current limiting module is further connected to the positive control end of an eighth controllable current source G12 through a ninth controllable current source G13 in sequence;
the positive control terminal of the eighth controllable current source G12 is connected to the third node of the first current limiting module through a third resistor R3 and a tenth controllable current source G14, respectively;
the positive control terminal of the eighth controllable current source G12 is further connected to the positive control terminal of the eleventh controllable current source G15;
positive control ends of the seventh controllable current source G11 and the ninth controllable current source G13 are respectively connected to the fourth node of the first current limiting module;
the negative control end of the ninth controllable current source G13 is connected to the first node of the first current limiting module;
the negative control terminals of the eighth controllable current source G12, the tenth controllable current source G14 and the eleventh controllable current source G15 are respectively connected to the third node of the first current limiting module;
the second node of the first current limiting module is connected to the third node of the first current limiting module via an eighth controllable current source G12.
As shown in fig. 7, in a possible implementation, the sixth controllable current source G6 is connected to the first node of the second current limiting module; the second node of the second current limiting module is connected to the first end of a fourth capacitor C4;
the third node of the second current limiting module is grounded.
As shown in fig. 7, in one possible implementation manner, in the second current limiting module, the first node of the second current limiting module is connected to the fourth node of the second current limiting module through a fifth resistor R5; in the second current limiting module, a fourth node of the second current limiting module is connected to the power supply VDD.
A fourth node of the second current limiting module is connected to a positive control terminal of a fifteenth controllable current source G24 through a twelfth controllable current source G21; the positive control end of the fifteenth controllable current source G24 is connected to the third node of the second current limiting module through the fourth resistor R4;
the fourth node of the second current limiting module is connected to the negative control end of a twelfth controllable current source G21 through a third current source G26; the negative control terminal of the twelfth controllable current source G21 is connected to the third node of the second current limiting module through a sixteenth controllable current source G25;
the fourth node of the second current limiting module is further connected to the positive control end of a thirteenth controllable current source G22 through a fourteenth controllable current source G23 in sequence;
the positive control terminal of the thirteenth controllable current source G22 is connected to the third node of the second current limiting module through a sixth resistor R6 and a fifteenth controllable current source G24, respectively;
the positive control terminal of the thirteenth controllable current source G22 is further connected to the positive control terminal of the sixteenth controllable current source G25;
positive control ends of the twelfth controllable current source G21 and the fourteenth controllable current source G23 are respectively connected to the fourth node of the second current limiting module;
the negative control terminal of the fourteenth controllable current source G23 is connected to the first node of the second current limiting module;
the negative control terminals of the thirteenth controllable current source G22, the fifteenth controllable current source G24 and the sixteenth controllable current source G25 are connected to the third node of the second current limiting module, respectively;
the second node of the second current limiting module is connected to the third node of the second current limiting module via a thirteenth controllable current source G22.
The working principle of the adaptive no-signal time control circuit shown in fig. 5 is as follows:
assume that the current scaling factor of the eleventh controllable current source G15 is N (N)>1) The current proportionality coefficients of the controllable current sources G11-G14 are all 1, and when the controllable current sources G12-G15 work, the positive and negative poles of the control ends have no charge flowing in or flowing out. At this time, since the second resistor R2 is connected in series with the fifth controllable current source G5, I 1 =I R2 =I G13 ，I R3 =N*I G15 =I OUT Wherein, I 1 For the current generated by the fifth controllable current source G5, I R2 Is the current flowing through the second resistor R2, I G13 Is the current flowing through the ninth controllable current source G13, I R3 Is the current flowing through the third resistor R3, I G15 Is the current through the eleventh controllable current source G15.
When the first limit is reachedOutput current I of current module OUT Is less than or equal to I max ，I max =N*I 2 At this time, the voltage difference between the positive and negative electrodes of the control terminal of the seventh controllable current source G11 is smaller than the turn-on voltage thereof, so the seventh controllable current source G11 is in the off state, and since the ninth controllable current source G13 and the third resistor R3 are connected in series, I is G13 =I R3 . Also, as can be seen from the above analysis, I 1 =I R2 =I G13 ，I R3 =N*I G15 =I OUT Therefore, at this time, I 1 =I R2 =I G13 =I R3 =N*I G15 =I OUT ，I G15 =(1/N)*I OUT Therefore, when the fifth controllable current source G5 generates the current I 1 Is less than or equal to I max The output current I of the first current limiting module OUT Equal to the current I generated by the fifth controllable current source G5 1 And at this time, I G15 ≤I 2 . Wherein, I max Is the maximum limiting flow value, I 2 Is the current flowing through G16.
When the current I generated by the fifth controllable current source G5 1 Is greater than I max ，I max =N*I 2 The output current I of the first current limiting module OUT Is also greater than I max At this time I OUT >N*I 2 While (1/N). Times.I OUT >I 2 Therefore, I G15 >I 2 At this time, the voltage V of the node X1 connected to the negative control terminal of the seventh controllable current source G11 X1 Is pulled down to increase the voltage difference between the positive and negative poles of the control terminal of the seventh controllable current source G11, and the voltage difference reaches the turn-on voltage of the seventh controllable current source G11, the seventh controllable current source G11 is turned on, the current flows from the fourth node of the first current limiting module to the first resistor R1 through the seventh controllable current source G11, and at this time, the current I flows through the first resistor R1 R1 The tenth controllable current source G14 generates the on-current I G14 (ii) a Since the current input terminal of the tenth controllable current source G14 is connected to the node X0, the on-state current I generated in the tenth controllable current source G14 G14 Part of the pull-up current at node X0 is pumped away, so that current I flowing into third resistor R3 R3 The size is reduced; and due to I R3 =N*I G15 =I OUT Therefore, the output current I of the first current limiting module OUT And the current I in the eleventh controllable current source G15 G15 Are all following I R3 Until the output current I of the first current limiting module is reduced OUT Down to I max =N*I 2 。
Then, due to the output current I of the first current limiting module OUT Down to maximum current limit value I max =N*I 2 Therefore, I G15 Is also reduced to 2 Equal, at this time, if the current I generated by the fifth controllable current source G5 1 If the current is still larger, the seventh controllable current source G11 is still in a conducting or semi-conducting state, the current still flows from the fourth node of the first current limiting module to the first resistor R1 through the seventh controllable current source G11, and the conducting current I generated in the tenth controllable current source G14 G14 Part of the pull-up current at node X0 is still drawn away, thereby ensuring the output current I of the current limiting module OUT Is stabilized at the maximum limit flow value I max =N*I 2 。
Finally, when the current I generated by the fifth controllable current source G5 1 Also reduced to less than or equal to I max =N*I 2 When no current flows in the seventh controllable current source G11, the voltage V of the node X1 X1 Is pulled up to the state of normal operation, thereby reducing the voltage difference between the positive and negative poles of the control terminal of the seventh controllable current source G11, making the voltage difference between the positive and negative poles of the control terminal less than the turn-on voltage thereof, the seventh controllable current source G11 is completely turned off, no current flows in the first resistor R1 at this time, therefore, the tenth controllable current source G14 is also turned off, no current flows, making I 1 =I R2 =I G13 =I R3 =I OUT At this time, the output current I of the current limiting module OUT Equal to the current I generated by the fifth controllable current source G5 1 . Through the first current limiting module, the charging current for charging the third capacitor C3 can be limited, and the current limiting value can be set according to the minimum no-signal time, so that the situation that the charging current generated by the fifth controllable current source G5 is too large, or the no-signal time is extremely short due to disorder of a control loop circuit, and the circuit is damaged due to direct connectionNamely, the minimum no-signal time is set through the first current limiting module, so that the circuit safety is improved.
Preferably, the minimum no-signal time is 10ns.
The principle of the second current limiting module shown in fig. 7 is similar to that of the first current limiting module shown in fig. 6, and thus, the description thereof is omitted.
In summary, in the adaptive no-signal time control circuit, the driving module is configured to generate control signals of the first power switch M1 and the second power switch M2 in the power loop; the input end of the driving signal detection module receives control signals of a first power switch tube and a second power switch tube respectively; a first output end of the driving signal detection module is connected to a clock end of a first D trigger A6 of the no-signal time adjustment module; a second output end of the driving signal detection module is connected to a clock end of a second D trigger A7 of the no-signal time adjustment module; the output end of the first D flip-flop A6 is connected to the first control end of the third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of the fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to the first voltage; two ends of the first capacitor C1 are respectively connected to the control end of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to the control end of a sixth controllable current source G6; two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to the first discharging loop; two output ends of the sixth controllable current source G6 are connected to two ends of the fourth capacitor C4, respectively; two ends of the fourth capacitor C4 are respectively connected to the second discharging loop; a first end of the third capacitor C3 is connected to the non-inverting input end of the third comparator A8; a first end of the fourth capacitor C4 is connected to the non-inverting input end of the fourth comparator A9; the inverting input end of the third comparator A8 and the inverting input end of the fourth comparator A9 are connected with a second voltage; the output end of the third comparator A8 transmits a first delay signal to the driving module through the NOT gate; the output terminal of the fourth comparator A9 transmits the second delayed signal to the driving module through the not gate. Through the structure, the no-signal time is determined by the coincidence moment that the voltage of the output signal of the first signal output end is equal to the third voltage and the voltage of the output signal of the second signal output end is equal to the fourth voltage, so that the no-signal time is adaptively adjusted according to the switching speed of the switching tube when the switching speed of the switching tube is different due to different processes, applications and environment changes (for example, when the switching tube with different switching speeds is used in a power loop or when the switching speed of the switching tube is different in different working stages due to the fact that the power loop is in different working stages), and finally the no-signal time is stabilized at the designed optimal working point, and the efficiency and the reliability of the power loop are both considered.
And through the first current-limiting module, the charging current for charging the third capacitor can be limited, so that the situation that the circuit is damaged due to direct connection caused by overlarge charging current generated by the fifth controllable current source or due to disorder of a control loop circuit, namely, the minimum no-signal time is set through the current-limiting module, is prevented, and the safety of the circuit is improved. The beneficial effect of the second current limiting module is the same as that of the first current limiting module, and is not repeated here.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (15)

1. A self-adaptive no-signal time control circuit is characterized by comprising a driving signal detection module, a no-signal time adjustment module, a driving module and a power loop;
the driving module is used for generating control signals of a first power switch tube M1 and a second power switch tube M2 in a power loop; the input end of the driving signal detection module receives control signals of the first power switch tube M1 and the second power switch tube M2 respectively;
a first output end of the driving signal detection module is connected to a clock end of a first D flip-flop A6 of the no-signal time adjustment module; a second output end of the driving signal detection module is connected to a clock end of a second D trigger A7 of the no-signal time adjustment module;
the output end of the first D flip-flop A6 is connected to the first control end of a third controllable current source G3; the output end of the second D flip-flop A7 is connected to the first control end of a fourth controllable current source G4; a second control end of the third controllable current source G3 and a second control end of the fourth controllable current source G4 are respectively connected to a first voltage;
two output ends of the third controllable current source G3 are respectively connected with two ends of the first capacitor C1; two output ends of the fourth controllable current source G4 are connected to two ends of the second capacitor C2, respectively; two ends of the first capacitor C1 are respectively connected to two control ends of a fifth controllable current source G5; two ends of the second capacitor C2 are respectively connected to two control ends of a sixth controllable current source G6;
two output ends of the fifth controllable current source G5 are connected to two ends of the third capacitor C3, respectively; two ends of the third capacitor C3 are respectively connected to a first discharging loop; two output ends of the sixth controllable current source G6 are connected to two ends of the fourth capacitor C4, respectively; two ends of the fourth capacitor C4 are respectively connected to a second discharging loop;
a first end of the third capacitor C3 is connected to the non-inverting input end of the third comparator A8; a first end of the fourth capacitor C4 is connected to a non-inverting input end of a fourth comparator A9; the inverting input ends of the third comparator A8 and the fourth comparator A9 are connected with a second voltage;
the output end of the third comparator A8 transmits a first delay signal to the driving module through a NOT gate; the output end of the fourth comparator A9 transmits a second delay signal to the driving module through the not gate.
2. The circuit according to claim 1, wherein the first signal output terminal of the driving module is connected to the control terminal of the first power switch M1; and a second signal output end of the driving module is connected with a control end of the second power switch tube M2.
3. The circuit of claim 2, wherein the input terminals of the driving signal detection module comprise a first input terminal of the driving signal detection module and a second input terminal of the driving signal detection module;
the first signal output end of the driving module is also connected to the first input end of the driving signal detection module; and the second signal output end of the driving module is also connected to the second input end of the driving signal detection module.
4. The circuit of claim 3, wherein the first signal output of the driving module outputs a difference between a first periodic signal and the first delayed signal; a second signal output end of the driving module outputs a difference between a second periodic signal and the second delayed signal; the first periodic signal is an inverted signal of the second periodic signal;
the first periodic signal is an original driving signal for turning on the first power switch tube M1, and the second periodic signal is an original driving signal for turning on the second power switch tube M2.
5. The circuit of claim 4, wherein if the first input terminal and the second input terminal of the driving signal detecting module are both low level, the first output terminal of the driving signal detecting module outputs high level when the first periodic signal is high level; and when the second periodic signal is at a high level, the second output end of the driving signal detection module outputs the high level.
6. The circuit of claim 4, wherein the driving module is further configured to generate a first reset signal and a second reset signal; the first reset signal, the second reset signal, the first periodic signal, and the second periodic signal have the same period;
the driving module transmits the first reset signal to a first D flip-flop A6 to control the reset of the first D flip-flop A6;
the driving module transmits the second reset signal to a second D flip-flop A7 to control the reset of the second D flip-flop A7;
the driving module transmits the first reset signal to a first discharging loop so as to control the discharging of the third capacitor C3;
the driving module transmits the second reset signal to a second discharge loop to control the discharge of the fourth capacitor C4.
7. The circuit of claim 6, wherein a falling edge of the first reset signal coincides with a rising edge of the first periodic signal; a falling edge of the second reset signal coincides with a rising edge of the second periodic signal.
8. The circuit of claim 1, wherein the first control terminal of the third controllable current source G3 is a positive control terminal; the second control end of the third controllable current source G3 is a negative control end;
the first control end of the fourth controllable current source G4 is a positive control end; the second control terminal of the fourth controllable current source G4 is a negative control terminal.
9. The circuit of claim 5, wherein when the voltage at the first input terminal of the driving signal detecting module is less than the third voltage, the first input terminal of the driving signal detecting module is at a low level;
and when the voltage of the second input end of the driving signal detection module is less than the fourth voltage, the second input end of the driving signal detection module is at a low level.
10. The circuit of claim 9, wherein the driving signal detection module comprises a first operational amplifier A1, a second operational amplifier A2, a first not gate A3, a first switch module, a second switch module, a first current source G7, a first and gate A4, and a second and gate A5;
a non-inverting input end of the first operational amplifier A1 is connected to a third voltage, and an inverting input end of the first operational amplifier A1 is a first input end of the driving signal detection module;
a non-inverting input end of the second operational amplifier A2 is connected to a fourth voltage, and an inverting input end of the second operational amplifier A2 is a second input end of the driving signal detection module;
the output end of the first operational amplifier A1 is connected to the control end of the first switch module; the output end of the second operational amplifier A2 is connected to the control end of the second switch module;
the first current source G7 is connected to an input terminal of the first not gate A3; the input end of the first NOT gate A3 is grounded through the first switch module and the second switch module in sequence; the output end of the first not gate A3 is respectively connected to the second input end of the first and gate A4 and the first input end of the second and gate A5; a first periodic signal is input to a first input end of the first AND gate A4; a second periodic signal is input to a second input end of the second and gate A5;
the output end of the first and gate A4 is a first output end of the driving signal detection module, and the output end of the second and gate A5 is a second output end of the driving signal detection module.
11. The circuit of claim 10, wherein the first switch module is a first controllable current source G1, and the second switch module is a second controllable current source G2;
the output end of the first operational amplifier A1 is connected to the positive control end of a first controllable current source G1; the output end of the second operational amplifier A2 is connected to the positive control end of a second controllable current source G2; the negative control terminal of the first controllable current source G1 and the negative control terminal of the second controllable current source G2 are grounded, respectively.
12. The circuit of any one of claims 1 to 11, wherein the no-signal time adjustment module further comprises a first current limiting module;
the output terminal of the fifth controllable current source G5 comprises a first current terminal of the fifth controllable current source G5 and a second current terminal of the fifth controllable current source G5;
a first current end of the fifth controllable current source G5 is connected to the first node of the first current limiting module; the second node of the first current limiting module is connected to the first end of a third capacitor C3; a second current end of the fifth controllable current source G5 is connected to a second end of the third capacitor C3;
and the third node of the first current limiting module is grounded.
13. The circuit of claim 12, wherein in the first current limiting module, the first node of the first current limiting module is connected to the fourth node of the first current limiting module through a second resistor R2;
the fourth node of the first current limiting module is connected to the positive control end of a tenth controllable current source G14 through a seventh controllable current source G11; the positive control end of the tenth controllable current source G14 is connected to the third node of the first current limiting module through a first resistor R1;
the fourth node of the first current limiting module is connected to the negative control end of a seventh controllable current source G11 through a second current source G16; the negative control end of the seventh controllable current source G11 is connected to the third node of the first current limiting module through an eleventh controllable current source G15;
the fourth node of the first current limiting module is further connected to the positive control end of an eighth controllable current source G12 through a ninth controllable current source G13 in sequence;
the positive control end of the eighth controllable current source G12 is connected to the third node of the first current limiting module through a third resistor R3 and a tenth controllable current source G14, respectively;
the positive control end of the eighth controllable current source G12 is further connected to the positive control end of the eleventh controllable current source G15;
positive control ends of the seventh controllable current source G11 and the ninth controllable current source G13 are respectively connected to the fourth node of the first current limiting module;
the negative control end of the ninth controllable current source G13 is connected to the first node of the first current limiting module;
negative control ends of the eighth controllable current source G12, the tenth controllable current source G14 and the eleventh controllable current source G15 are respectively connected to the third node of the first current limiting module;
the second node of the first current limiting module is connected to the third node of the first current limiting module through an eighth controllable current source G12.
14. The circuit of any one of claims 1 to 11, wherein the no-signal time adjustment module further comprises a second current limiting module;
the output terminal of the sixth controllable current source G6 comprises a first current terminal of the sixth controllable current source G6 and a second current terminal of the sixth controllable current source G6;
a first current end of the sixth controllable current source G6 is connected to the first node of the second current limiting module; the second node of the second current limiting module is connected to the first end of a fourth capacitor C4; a second current end of the sixth controllable current source G6 is connected to a second end of the fourth capacitor C4;
and a third node of the second current limiting module is grounded.
15. The circuit of claim 14, wherein in the second current limiting module, the first node of the second current limiting module is connected to the fourth node of the second current limiting module through a fifth resistor R5;
the fourth node of the second current limiting module is connected to the positive control end of a fifteenth controllable current source G24 through a twelfth controllable current source G21; the positive control end of the fifteenth controllable current source G24 is connected to the third node of the second current limiting module through a fourth resistor R4;
the fourth node of the second current limiting module is connected to the negative control end of a twelfth controllable current source G21 through a third current source G26; the negative control end of the twelfth controllable current source G21 is connected to the third node of the second current limiting module through a sixteenth controllable current source G25;
the fourth node of the second current limiting module is further connected to the positive control end of a thirteenth controllable current source G22 through a fourteenth controllable current source G23 in sequence;
a positive control end of the thirteenth controllable current source G22 is connected to the third node of the second current limiting module through a sixth resistor R6 and a fifteenth controllable current source G24, respectively;
the positive control end of the thirteenth controllable current source G22 is further connected to the positive control end of the sixteenth controllable current source G25;
positive control ends of the twelfth controllable current source G21 and the fourteenth controllable current source G23 are respectively connected to a fourth node of the second current limiting module;
a negative control end of the fourteenth controllable current source G23 is connected to the first node of the second current limiting module;
negative control ends of the thirteenth controllable current source G22, the fifteenth controllable current source G24 and the sixteenth controllable current source G25 are respectively connected to the third node of the second current limiting module;
the second node of the second current limiting module is connected to the third node of the second current limiting module via a thirteenth controllable current source G22.
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