CN117318479B - Ultralow-power-consumption step-down DC-DC converter applicable to FLTR - Google Patents

Ultralow-power-consumption step-down DC-DC converter applicable to FLTR Download PDF

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CN117318479B
CN117318479B CN202311052623.9A CN202311052623A CN117318479B CN 117318479 B CN117318479 B CN 117318479B CN 202311052623 A CN202311052623 A CN 202311052623A CN 117318479 B CN117318479 B CN 117318479B
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signal
gate
power tube
output
voltage
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CN117318479A (en
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余凯
胡群山
李思臻
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Guangdong University of Technology
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Guangdong University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides an ultra-low power buck DC-DC converter suitable for FLTR, comprising: first Comparator (COMP) 0 ) A second Comparator (COMP) 1 ) Third Comparator (COMP) 2 ) Fourth Comparator (COMP) 3 ) The device comprises a Sleep Control module, an EN_FLTR module, a first power tube grid driving signal generating circuit (ph 1Pulse Gen.), a second power tube grid driving signal generating circuit (ph 2 Pulse Gen.), a first driving stage (driver_H), a second driving stage (driver_L), a first power tube (NM 0), a second power tube (NM 1), a third power tube (PM 0), a fourth power tube (PM 1) and a zero crossing detection circuit (ZCD). The invention can further realize low power consumption level under DVFS and FLTR performance, and most of the control of the whole loop is digitized, the circuit can exit from the sleep mode to power on operation faster, and the temperature stability of the pulse widths of the signals ph1 and ph2 can be improved by controlling the pulse widths of the delay chain delay adjusting signals ph1 and ph2 with smaller temperature change.

Description

Ultralow-power-consumption step-down DC-DC converter applicable to FLTR
Technical Field
The invention relates to the technical field of electronics, in particular to an ultralow-power-consumption buck DC-DC converter suitable for FLTR.
Background
For Ultra-Low-Power (ULP) wearable devices, in order to meet the requirement of long endurance of the devices, the Power consumption and the efficiency of the Power management chip are required to be higher. The traditional ultra-low power consumption step-down DC-DC converter adopts two structures, and realizes low static power consumption and high conversion efficiency. One is an event driven asynchronous control scheme. The input/output voltage is regulated by a Constant-Time (CT) comparator based amplifier. The comparator generates an enabling signal to enable the pulse generating block to start, and generates phi 1 and phi 2 to charge and discharge the inductor, wherein phi 2 is triggered by the negative edge of phi 1, and when the enabling signal is turned off, the pulse generating block is turned off, and the power tube does not conduct switching operation. Another adopts a baseIn the synchronous Pulse Frequency Modulation (PFM) scheme, the clock frequency is adjusted according to the input/output power. When the output power is higher, the clock frequency is increased to more frequently compare V REF And V OUT And performing a power transfer operation. When the output power is low, the clock frequency is reduced to save dynamic power loss. Thus, the PFM may adjust the frequency to balance power loss and speed.
To achieve a fast load transient response (Fast Load Transient Response, FLTR), the asynchronous control scheme requires increasing the bias current of the comparator to achieve higher speeds; while the synchronization scheme must always be operated at a high frequency to increase bandwidth and response speed, this would be disadvantageous for reduction of power consumption. Because of these inherent drawbacks, conventional ultra-low power buck DC-DC converters are not suitable for ULP FLTR applications.
Disclosure of Invention
The invention aims to provide an ultra-low power consumption buck DC-DC converter suitable for FLTR, which can ensure that the low power consumption level is further realized under the performance of DVFS and FLTR.
Ultra-low power buck DC-DC converter suitable for FLTR, as in fig. 1, includes: a Sleep Control module, an en_fltr module, a first power tube gate driving signal generating circuit (ph 1 Pulse gen.), a second power tube gate driving signal generating circuit (ph 2 Pulse gen.), a first driving stage (driver_h), a second driving stage (driver_l), a first power tube (NM 0), a second power tube (NM 1), a third power tube (PM 0), and a fourth power tube (PM 1);
the zero-setting end of the seventh flip-flop (DFF 7) in the Sleep Control module and the third Comparator (COMP) 2 ) Is connected to the trigger terminal and the second comparator (COMP 1 ) The output end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) and the second power tube grid driving signal generating circuit (ph 2 Pulse Gen.) are connected; the input end of the Sleep Control module is connected with the EN_FLTR module;
the input end of the EN_FLTR module is connected with the first terminalFour Comparators (COMP) 3 ) Sixth OR gate (OR) 6 ) Output signal VX of (c), third Comparator (COMP) 2 ) The output end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) is connected with the Sleep Control module;
the input end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) is connected with the Sleep Control module and the EN_FLTR module, and the output end is connected with a first driving stage (driver_H) and ph2 Pulse Gen;
the input end of the second power tube grid driving signal generating circuit (ph 2 Pulse Gen.) is connected with the zero-crossing detection circuit (ZCD), ph1 Pulse Gen.) and the Sleep Control module, and the output end is connected with the input end of the second driving stage (driver_L), the INV6, the sixth OR gate (OR) 6 ) Is connected with the input end of the power supply;
the input end of the first driving stage (driver_H) is connected with a first power tube grid driving signal generating circuit (ph 1 Pulse Gen.); the output end is connected with a third power tube (PM 0) and a fourth power tube (PM 1);
the input end of the second driving stage (driver_L) is connected with a second power tube grid driving signal generating circuit (ph 2 Pulse Gen.), and the output end of the second driving stage (driver_L) is connected with a first power tube (NM 0) and a second power tube (NM 1);
in both cases of stable load current operation and load current jump reduction: is controlled and regulated by the Sleep Control module circuit when the converter output voltage (OUT) is detected to be higher than the first voltage (V H ) Generating a signal En1, turning off a first power tube (NM 0), a second power tube (NM 1), a third power tube (PM 0) and a fourth power tube (PM 1), entering a sleep state, and outputting a signal (C) from a load capacitor (C OUT ) Discharging is performed when the converter output voltage (OUT) decreases to a second voltage (V) REF ) Triggering to generate an En0 signal, setting the signal En1 to zero, exiting from a dormant state, and performing a new round of charging and discharging;
when the load current rises in a jump, the converter output voltage (OUT ) There is a drop, if it drops to a third voltage (V L ) In the following, the en_fltr module circuit is triggered and regulated, en_vx is set to a high level, the turn-on signal VX, and the gate driving signals ph1 of the third power transistor (PM 0) and the fourth power transistor (PM 1) are triggered by the falling edges of the gate driving signals ph2 of the first power transistor (NM 0) and the second power transistor (NM 1) of the previous charge-discharge cycle after the delay Td.
Preferably, the Sleep Control module includes: a seventh flip-flop (DFF 7), a third AND gate (AND 3), a fourth AND gate (AND 4);
the D end of the seventh trigger (DFF 7) is connected with the input voltage VIN, the Q end outputs En1, the trigger end is connected with En_VH, and the zero setting end is connected with En0;
the input end of the fourth AND gate (AND 4) is connected with EN_VX_N AND En0, AND the output is m 0';
the input end of the third AND gate (AND 3) is connected with m0 'AND m 0', AND the output is m0_1;
when the converter output voltage (OUT) is higher than the first voltage (V H ) When the second comparator (COMP 1 ) The output signal En_VH changes from low to high, the output Q end signal En1 triggering the seventh trigger (DFF 7) changes from low to high, the third power tube (PM 0), the fourth power tube (PM 1), the first power tube (NM 0) and the second power tube (NM 1) are turned off, and OUT consists of a load capacitor (C OUT ) Supplying power and entering a dormant state;
when the output voltage (OUT) of the converter is lower than the second voltage (V REF ），COMP 2 The output signal En0 changes from low to high, the signal En0 is connected to the zero setting end of the DFF7 and sets En1 to zero, the sleep state is exited, the falling edge of En1 is then triggered to generate a low-to-high step signal m 0', the signal m0_1 generates a low-to-high step to trigger a new inductive charging and discharging process, and when OUT is higher than VREF, en0 is changed to 0, and m0_1 is set to zero;
the converter output voltage (OUT) is always higher than the third voltage (V L ），COMP 3 The output signal en_vl of the en_fltr block is kept at low level, en_vx_n is high level, and the fifth and gate #, the output signal en_vx of the en_fltr block is kept at low levelAND 5) includes en_vx, VX, an output signal m0_2, where m0_2= "0", AND an m0 signal is determined by an output signal m0_1 of the Sleep Control block circuit.
Preferably, the en_fltr module includes: a fifth AND gate (AND 5);
the input end of the fifth AND gate (AND 5) is connected with VX AND EN_VX, AND outputs m0_2;
when the load current rises in a jump by the signals En0, en_vl to enable the signal en_vx, the converter output voltage (OUT) drops, if it drops to a third voltage (V L ) Hereinafter, the fourth comparator (COMP 3 ) The output signal En_VL of the mask Sleep Control module is changed from low to high, EN_VX= "1", EN_VX_N= "0", and the output signal m0_1 of the mask Sleep Control module is determined by the output m0_2 of the EN_FLTR module;
the input of the fifth AND gate (AND 5) comprises EN_VX, VX, an output signal m0_2, a step trigger signal VX generated by the falling edge of ph2 is transmitted to m0_2, AND a new charge-discharge process is triggered until the output voltage (OUT) of the converter is raised to a second voltage (V REF ) En0 is set to zero, the falling edge EN_VX of En0 sets the signal to zero, at which time m0_2= "0", and the m0 signal is determined by m0_1.
Preferably, the first power tube gate driving signal generating circuit (ph 1 Pulse gen.) includes: a first flip-flop (DFF 1), a second flip-flop (DFF 2), a third flip-flop (DFF 3), a first OR gate (OR 1 ) A second OR gate (OR) 2 ) A first buffer (Buff 1), a second buffer (Buff 2), a first AND gate (AND 1), a first inverter (INV 1), a second inverter (INV 2), a first transmission gate (1), a second transmission gate (2), a third transmission gate (TG 3), a fourth transmission gate (TG 4), a Delay part (Delay), a first Delay chain (T0-tN), a second Delay chain (T0-TN), a first Switch (SW) 00 ~SW 0N ) A second Switch (SW) 10 ~SW 1N ）；
The ph1 Pulse Gen. The module inputs the signals m0, trim <2:0>, en1, outputs the signal ph1;
triggering the first trigger by the trigger signal m0DFF 1), the signal ph1 of the output Q port goes from low to high, the second flip-flop (DFF 2) is formed by the first OR gate (OR) 1 ) The output signals Y1 of the first and second transmission gates (TG 1, TG2, TG 3) and TG4 are triggered and generate high and low alternating voltages Q and Q_N, Q and Q_N for gating the first transmission gate (TG 1), the second transmission gate (TG 2), the third transmission gate (TG 3) and the fourth transmission gate (TG 4), if Q=1, the second transmission gate (TG 2) is conducted with the fourth transmission gate (TG 4), the first transmission gate (TG 1) and the third transmission gate (TG 3) are closed, the ph1 signal is transmitted through a delay chain t 0-tN, and after Tx1 delay, the first OR gate (OR 1 ) The output signal Y1 of the flip-flop DFF3 is changed from low to high, the Q port signal Q1 of the flip-flop DFF3 is changed from low to high, AND a pulse signal Q2 is generated through a circuit formed by the first buffer (Buff 1), the second inverter (INV 2) AND the first AND gate (AND 1), AND the width of the pulse signal is the delay time of the first buffer (Buff 1);
at a converter output voltage (OUT) lower than a first voltage (V) H ) Under the condition that En1 keeps low level, a signal Q2 is transmitted into a set end of a first trigger (DFF 1), a signal ph1 is set to be zero, and the high level duration of the signal ph1 is determined by the duration Tx1 of a delay chain;
gamma is the proportionality coefficient of the product,input gate capacitance for delay chain basic unit Ti (i=0, 1 … N), ti (i=0, 1 … N), +.>The loads representing Ti (i=0, 1 … N), ti (i=0, 1 … N) are just intrinsic capacitances +.>Delay of time, wherein->Regarding the diffusion capacitance and the gate-drain coverage capacitance, i=0 to n, n is an even number.
Preferably, the second power tube gate driving signal generating circuit (ph 2 Pulse gen.) includes: a fourth flip-flop (DFF 4), a fifth flip-flop (DFF 5), a sixth flip-flop (DFF 6), a third OR gate (OR) 3 ) Fourth OR gate (OR) 4 ) A third buffer (Buff 3), a fourth buffer (Buff 4), a second AND gate (AND 2), a third inverter (INV 3), a fourth inverter (INV 4), a fifth transfer gate (5), a sixth transfer gate (6), a seventh transfer gate (TG 7), an eighth transfer gate (TG 8), a Delay section (Delay), a third Delay chain (N0-nM), a fourth Delay chain (N0-NM), a third Switch (SW) 30 ~SW 3M ) Fourth Switch (SW) 40 ~SW 4M ) Zero crossing detection circuit (ZCD);
the ph2 Pulse gen. The module input signals include ph1, en1, T1, output signal ph2;
the signal ph2 is triggered by the falling edge of ph1 from low to high, and the fifth flip-flop (DFF 5) is triggered by a third OR gate (OR 3 ) The output signal Y2 of (a) triggers and generates high-low alternating voltages Q ' and Q ' N, Q ' and Q ' N for gating the fifth transmission gate (TG 5), the sixth transmission gate (TG 6), the seventh transmission gate (TG 7) and the eighth transmission gate (TG 8), if Q ' =1, the sixth transmission gate (TG 6) is conducted with the eighth transmission gate (TG 8), the fifth transmission gate (TG 5) and the seventh transmission gate (TG 7) are closed, the ph2 signal is transmitted through delay chains N0-nM, and the third OR gate (OR) is delayed by Tx2 3 ) The output signal Y2 of the second AND gate (AND 2) is changed from low to high, the Q port signal Q '1 triggering the sixth flip-flop (DFF 6) is changed from low to high, AND a pulse signal Q' 2 is generated by a circuit formed by the third buffer (Buff 3), the fourth inverter (INV 4) AND the second AND gate (AND 2), AND the pulse signal has a width of the third buffer (Buff 3)Is a delay time of (2);
at a converter output voltage (OUT) lower than a first voltage (V) H ) Under the condition that En1 keeps low level, a signal Q ' 2 is transmitted to a set end of a fourth trigger (DFF 4), under the condition that no inversion of the inductor current is detected, T1 keeps low level, Q ' 2 sets a signal ph2 to zero, the duration of the high level of the signal ph2 is determined by the duration Tx2 of a delay chain, and if the inversion of the inductor current is detected before a pulse signal Q ' 2 is not generated, the signal T1 is changed from low to high, and the signal ph2 is set to zero.
Preferably, the zero crossing detection circuit (ZCD) comprises: first Comparator (COMP) 0 ) And Digital-control circuitry;
the first comparator (COMP 0 ) The positive end of the voltage is grounded, and the negative end of the voltage is grounded, so as to output a signal T0; the input signals of the Digital-control comprise T0, ph1 and ph2, and the output signal T1 is output.
Preferably, the first power tube (NM 0) and the second power tube (NM 1) are connected in series;
the third power tube (PM 0) and the fourth power tube (PM 1) are connected in series;
the drain end of the third power tube (PM 0) is connected with the drain end of the second power tube (NM 1).
Preferably, the method further comprises: an inductance (L);
the inductor (L) is connected with the node (SW) at one end and the output capacitor (C) at the other end OUT ）。
Preferably, the method further comprises: first Comparator (COMP) 0 ) A second Comparator (COMP) 1 ) Third Comparator (COMP) 2 ）；
The first comparator (COMP 0 ) The output end of the Digital-control module is connected with the Digital-control module, the positive end of the Digital-control module is connected with the SW point voltage, and the negative end of the Digital-control module is grounded;
the second comparator (COMP 1 ) The output end of the converter is connected with the Sleep Control module, the positive end is connected with the output voltage (OUT) of the converter, and the negative end is connected with the first voltage (V H ）；
The third comparator (COMP 2 ) And the Sleep ControlThe module, the EN_FLTR module is connected with the second voltage (V REF ) The negative terminal is connected with the output voltage (OUT) of the converter;
the fourth comparator (COMP 3 ) Is connected to the EN_FLTR module, and has a positive terminal connected to a third voltage (V L ) The negative terminal is connected to the converter output voltage (OUT).
The start of the next charging period ph1 signal is delayed by a minimum time delay Td from the negative edge of the ph2 of the previous period, and the pulse widths of ph1 and ph2 are both realized through digitization, so that the delay Td is not limited by the slow response speed of the low-power comparator, and when the load current jumps, the Td is not required to be reduced by adding an extra bias current to realize higher charging and discharging speed, the Td can be further reduced to accelerate the charging and discharging frequency without sacrificing the static current, the method is suitable for low-power scenes, and the trade-off between the speeds of the low-power and low-speed comparators is weakened.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a circuit structure of the present invention;
fig. 2 is a schematic diagram of the generation control logic (en_vx= "0", m0_2= "0") of the trigger flag signal m0 according to the present invention;
fig. 3 is a schematic diagram of generation control logic (en_vx= "0", m0_2= "0") of ph1, ph2 according to the present invention;
fig. 4 is a schematic diagram of generation control logic (en_vx= "1", m0_1= "0") of ph1, ph2 according to the present invention;
FIG. 5 is a waveform diagram of key signals of the ultra-low power buck DC-DC converter of the present invention;
FIG. 6 is a key signal connection diagram of a Sleep Control module and an EN_FLTR module of the present invention;
FIG. 7 is a diagram showing a digitized implementation of the power transistor gate drive signal of the present invention;
FIG. 8 is a graph comparing the adjustment times of the present scheme and the calibration scheme for the same power consumption and OUT variation range of the present invention;
FIG. 9 is a graph showing the comparison of the ph1 pulse width time with temperature according to the present invention;
FIG. 10 is a graph of the resume operation time (within 5 ns) for exiting sleep state in accordance with the present invention;
FIG. 11 is a graph of load current transient response time of the present invention;
fig. 12 is a graph showing the trend of the converter operating efficiency at different load currents according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Because the bandwidth of the synchronous feedback control loop of the traditional switching inductance type buck converter is limited, the low-static-power converter cannot realize rapid Load transient response, and in order to simultaneously support rapid DVFS (Dynamic Voltage and Frequency Scaling) and FLTR (Fast Load-Transient Response), the synchronous scheme must always operate at high frequency so as to improve the bandwidth and response speed and sacrifice power consumption; conventional asynchronous control schemes require increasing the bias current of the comparator to achieve higher speeds; the invention is therefore used to address the further implementation of low power consumption levels by conventional modules while guaranteeing DVFS and FLTR performance.
Ultra-low power buck DC-DC converter suitable for FLTR, as in fig. 1, includes: a Sleep Control module, an en_fltr module, a first power tube gate driving signal generating circuit (ph 1 Pulse gen.), a second power tube gate driving signal generating circuit (ph 2 Pulse gen.), a first driving stage (driver_h), a second driving stage (driver_l), a first power tube (NM 0), a second power tube (NM 1), a third power tube (PM 0), and a fourth power tube (PM 1);
the zero-setting end of the seventh flip-flop (DFF 7) in the Sleep Control module and the third Comparator (COMP) 2 ) Is connected to the trigger terminal and the second comparator (COMP 1 ) The output end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) and the second power tube grid driving signal generating circuit (ph 2 Pulse Gen.) are connected; the input end of the Sleep Control module is connected with the EN_FLTR module;
the input of the EN_FLTR module is connected to a fourth comparator (COMP 3 ) Sixth OR gate (OR) 6 ) Output signal VX of (c), third Comparator (COMP) 2 ) The output end is connected with a first power tube grid drive signal generating circuit (ph 1 Pulse Gen.) and The Sleep Control module is connected;
the input end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) is connected with the Sleep Control module and the EN_FLTR module, and the output end is connected with the first driving stage (driver_H) and ph2 Pulse Gen;
the input end of the second power tube grid driving signal generating circuit (ph 2 Pulse Gen.) is connected with the zero-crossing detection circuit (ZCD), ph1 Pulse Gen.) and the Sleep Control module, and the output end is connected with the input end of the second driving stage (driver_L) and the INV6, and the sixth OR gate (OR) 6 ) Is connected with the input end of the power supply;
the input end of the first driving stage (driver_H) is connected with a first power tube grid driving signal generating circuit (ph 1 Pulse Gen.); the output end is connected with a third power tube (PM 0) and a fourth power tube (PM 1);
the input end of the second driving stage (driver_L) is connected with a second power tube grid driving signal generating circuit (ph 2 Pulse Gen.), and the output end is connected with the first power tube (NM 0) and the second power tube (NM 1);
in both cases of stable load current operation and load current jump reduction: is controlled and regulated by a Sleep Control module circuit when the converter output voltage (OUT) is detected to be higher than the first voltage (V H ) Generating a signal En1, turning off a first power tube (NM 0), a second power tube (NM 1), a third power tube (PM 0) and a fourth power tube (PM 1), entering a sleep state, and outputting a signal (C) from a load capacitor (C OUT ) Discharging is performed when the converter output voltage (OUT) decreases to a second voltage (V) REF ) Triggering to generate an En0 signal, setting the signal En1 to zero, exiting from a dormant state, and performing a new round of charging and discharging;
when the load current rises in a jump, the output voltage (OUT) of the converter drops, if the output voltage drops to a third voltage (V L ) The EN_FLTR module circuit is triggered and regulated, EN_VX is set to high level, the signal VX is turned on, and the gate drive signals ph1 of the third power tube (PM 0) and the fourth power tube (PM 1) are controlled by the first power of the previous charge-discharge periodThe falling edges of the gate driving signals ph2 of the tube (NM 0) and the second power tube (NM 1) are triggered to be generated after the delay Td. Wherein the third voltage (V L ）<Second voltage (V) REF ）<First voltage (V) H ）。
The invention mainly consists of a Comparator (COMP) 0 、COMP 1 、COMP 2 、COMP 3 ) The power transistor comprises an EN_FLTR module, a Sleep Control module, a power transistor grid electrode driving signal generating circuit (ph 1/ph2 Pulse Gen.), a zero crossing detection circuit (ZCD), a driving stage (driver_H/driver_L) and a power stage (NM 0, NM1, PM0 and PM 1). Wherein COMP 3 Is connected with the positive terminal voltage VL and the negative terminal voltage OUT of the converter, and when OUT is detected to be lower than VL, COMP is performed 3 The output signal En VL goes from low to high. COMP 2 Is connected with reference voltage V at the positive end REF A negative terminal connected to OUT, when OUT is detected to be lower than V REF When COMP 2 The output signal En0 goes from low to high. COMP 1 Is connected with the voltage VH at the positive terminal and the voltage OUT at the negative terminal, and COMP is performed when OUT is detected to be higher than VH 1 The output signal en_vh changes from low to high (VH, V REF The VL voltage is externally supplied, and VH>V REF >VL）。
The input signals of the en_fltr module include EN0, en_vl and VX, and the output signals include en_vx, m0_2. The input signals of the Sleep Control module comprise En_VH, en0 and EN_VX_N, and the output signals comprise En1 and m0_1. Fifth OR gate (OR) 5 ) Signals m0_1 and m0_2 are input, and signal m0 is output.
ph1 Pulse Gen. Module input connects signal m0, trim<2:0>En1, and outputs a signal ph1. The ph2 Pulse gen. The module input signals include ph1, en1, T1, output signal ph2. The inverter INV6 has an input connected to the signal ph2, an output signal ph2_n, a Delay block (Delay) input connected to the signal ph2_n, and a Delay Td to generate an output signal v_d, a sixth OR gate (OR) 6 ) Inputs ph2 and v_d, and outputs the connection signal VX.
Zero-crossing detection circuit (ZCD) is mainly composed of comparator COMP 0 Digital-control circuit, COMP 0 The positive terminal of the (a) is connected with the SW node voltage, the negative terminal is grounded, and a signal T0 is output. Input of Digital-controlThe signals include T0, ph1, ph2, and the signal T1 is output.
For the driving stage, the input of the driving module driver_H is connected with ph1_N, the output of the driving module driver_H is connected with ph1_D, the input of the driving module driver_L is connected with ph2_B, and the output of the driving module driver_L is connected with ph2_D. The inverter INV7 has an input connected to ph1, an output connected to ph1_n, and a buffer Buff5 input connected to ph2 and an output connected to ph2_b. The signal ph1_d is connected to the gates of the power transistors PM0 and PM1, and the signal ph2_d is connected to the gates of the power transistors NM0 and NM 1.
For the power stage, the upper power transistors PM0 and PM1 are connected in series, and the lower power transistors NM0 and NM1 are connected in series. The source terminal of PM1 is connected with the input voltage VIN, and the drain terminal of PM1 is connected with the source terminal of PM 0. PM0 drain terminal is connected with drain terminal of NM1, and node is SW. The source terminal of NM1 is connected with the drain terminal of NM0, and the source terminal of NM0 is grounded. The inductor L is connected with the node SW at the left end, the output voltage OUT at the right end and the output capacitor C OUT The upper polar plate is connected with the right end of the inductor, and the lower polar plate is grounded. Capacitor C IN The upper polar plate of the capacitor is connected with the PM1 source end, and the lower polar plate is grounded.
(1) If the output voltage OUT drops below the voltage VL, COMP 3 When en_vx= "1", en_vx_n= "0", m0_1= "0", mask Sleep Control module outputs signal m0_1, trigger flag signal m0 is determined by m0_2, and system is controlled by en_fltr module.
(2) If the output voltage OUT is always maintained above the voltage VL, COMP 3 If en_vx= "0", en_vx_n= "1", m0_2= "0", mask en_fltr module output signal m0_2, trigger flag signal m0 is determined by m0_1, and system is controlled by Sleep Control module.
(3) The trigger mark signal m0 is used for controlling whether to start the charging and discharging process of the inductor, when m0 has a step jump from low to high, the charging and discharging process of the inductor is triggered, otherwise, the charging and discharging of the inductor is not performed.
In both cases of stable load current operation and load current jump reduction:
at this time, OUT is kept above the voltage VL, en_vx= "0", m0_2= "0", m0 is determined by m0_1, en_fltr module is inactive, and the system is controlled and regulated by the Sleep Control module circuit.
When it is detected that the converter output voltage OUT is higher than the voltage VH (VH>V REF >VL), en_vh changes from low to high, so that En1 changes from low to high, the upper and lower power tubes are cut off, and meanwhile, a Sleep state (Sleep Time) is entered, most circuits are cut off, and static power consumption is saved. During this period, the output is formed by the load capacitor C OUT Discharging is performed when the output OUT decreases to V REF The voltage, triggering the En0 signal, zeroing the En1 signal, exiting the sleep state, while the falling edge of En1 will generate the low-to-high trigger signal m0_1 (or m 0), see FIG. 2 (a), where there will be a brief delay T between the falling edge of En1 and the generated m0 D Under the condition of ensuring a certain low power consumption level, the delay is set to be the shortest time required by the system to exit from sleep and resume normal operation. If the output voltage OUT does not exceed the voltage VH, en1 is always kept low, the system does not go into sleep, and the trigger signal m0_1 (or m 0) is directly synchronized with the signal En0, see FIG. 2 (b).
Since the en_fltr module does not contribute to the generation of ph1, ph2, the generation of signals ph1, ph2 is controlled by the Sleep Control module, see fig. 3.
In the event of a jump rise in load current:
when the load current jumps up, the output voltage OUT will drop to a certain extent, if the output voltage OUT drops below VL, the signal En_VL is changed from low to high, the EN_FLTR module is enabled, EN_VX= "1", m0_1= "0", m0 is determined by m0_2, the Sleep Control module does not work, and the system is controlled and regulated by the EN_FLTR module circuit.
After the charge-discharge cycle is finished, the falling edge of ph2 generates a step signal VX from low to high after a certain delay Td, and the upward step of the signal VX triggers the signal m0_2 (or m 0) to jump from low to high again, so as to start to enter the charge-discharge process of a new round. Thus, the next cycle of signal ph1 will be generated by the falling edge control of the present cycle of signal ph2, and the system enters the cycle triggered state, see fig. 4. When the output voltage OUT rises back to V REF After the voltage is higher, en0 is changed from high to low, and en_vx is set to zero by the falling edge of En0 (en_vx= "0")The en_fltr module circuit no longer functions, exits the loop trigger state, again enables the Sleep Control module, and the trigger flag signal m0 is again determined by m0_1 and no longer controlled by the previous period ph 2.
The pulse width of ph1 and ph2 in the scheme is realized through digitalization, so that the delay time Td is not limited by the slow response speed of the low-power consumption comparator, the size of Td can be further reduced, the charge and discharge frequency is accelerated, and the static current is not sacrificed. In the overall loop control, the key signal waveforms are shown in fig. 5.
Preferably, as shown in fig. 6, the sleep Control module includes: a seventh flip-flop (DFF 7), a third AND gate (AND 3), a fourth AND gate (AND 4);
the D end of the seventh trigger (DFF 7) is connected with the input voltage VIN, the Q end outputs En1, the trigger end is connected with En_VH, and the zero setting end is connected with En0;
the input end of the fourth AND gate (AND 4) is connected with EN_VX_N AND En0, AND the output is m 0';
the input end of the third AND gate (AND 3) is connected with m0 'AND m 0', AND the output is m0_1;
when the converter output voltage (OUT) is higher than the first voltage (V H ) When the second comparator (COMP 1 ) The output signal En_VH changes from low to high, the output Q end signal En1 triggering the seventh trigger (DFF 7) changes from low to high, the third power tube (PM 0), the fourth power tube (PM 1), the first power tube (NM 0) and the second power tube (NM 1) are turned off, and OUT consists of a load capacitor (C OUT ) Supplying power and entering a dormant state;
when the output voltage (OUT) of the converter is lower than the second voltage (V REF ），COMP 2 The output signal En0 changes from low to high, the signal En0 is connected to the zero setting end of the DFF7 and sets En1 to zero, the sleep state is exited, the falling edge of En1 is then triggered to generate a low-to-high step signal m 0', the signal m0_1 generates a low-to-high step to trigger a new inductive charging and discharging process, and when OUT is higher than VREF, en0 is changed to 0, and m0_1 is set to zero;
the converter output voltage (OUT) is always higher than the third voltage (V L ），COMP 3 The output signal En_VL signal of (2) is lowThe output signal en_vx of the en_fltr block remains low, en_vx_n is high, the input of the fifth AND gate (AND 5) includes en_vx, VX, the output signal m0_2, where m0_2= "0", AND the m0 signal is determined by the output signal m0_1 of the Sleep Control block circuit.
The input signals of the en_fltr module include EN0, en_vl and VX, and the output signals include en_vx, m0_2. Wherein the inputs of AND5 include EN_VX, VX, AND the output is signal m0_2.
The input signals of the Sleep Control module comprise En_VH, en0 and EN_VX_N, and the output signals comprise En1 and m0_1. The circuit module mainly comprises a DFF7, an AND3 AND an AND4, wherein a clock trigger of the DFF7 is connected with En_VH, a zero setting end is connected with En0, a D end is connected with VIN, AND a Q end outputs En1. The inputs to AND4 include EN_VX_ N, en0, with an output of m0 ". The inputs of AND3 are signal m0' AND signal m0″ AND output signal m0_1.
When the system is controlled by the Sleep Control module, en_vx= "0", en_vx_n= "1", m0_2= "0", m0″ is determined by EN0 through AND gate AND4, AND m0 is determined by m0_1.
When the output voltage OUT exceeds the voltage VH and the signal En_VH triggers the DFF7 from low to high, the Q-terminal signal En1 is changed from low to high, and enters a sleep state, once the OUT voltage is lower than V REF ，COMP 2 The output signal En0 goes from low to high, the signal En0 is connected to the zero-setting terminal of the DFF7, and the signal En1 is set to zero. Because of the transmission delay of the flip-flop, the signal En1 is still at the high level at the time of the low-to-high signal En0, and the system does not exit the sleep state yet, and m 0' is still kept at the high level state. However, the low-to-high step transition at the time En0 causes a low-to-high step transition of the signal m0″ and thus causes a low-to-high step transition of the signal m0_1 (or m 0), but the trigger flag signal m0 generated at this time is not active and does not enter a new charge-discharge process because the system is not yet in the sleep state at this time. When En1 is successfully zeroed, the system exits from the sleep state, the falling edge of En1 triggers m 0' to generate a short undershoot, and the undershoot time is T D So that the signal m0 'generates a low-to-high step, m0_1 (or m 0) is determined by m0' because m0″ is already high at this time, and thus m 0_1 (or m 0) again generates a step jump from low to high, and the system starts to enter a new round of charge and discharge process.
If the output voltage OUT does not exceed the voltage VH, the signal en_vh is always low, and DFF7 is not triggered, the En1 is always maintained in a low state, the system does not enter a sleep state, the m0' is always maintained in a high state, m0_1 (or m 0) is determined by m0″, and since m0″ is determined by En0, in this case, the signal m0_1 (or m 0) is directly synchronized with the signal En0, see fig. 7 (b).
Preferably, the en_fltr module includes: a fifth AND gate (AND 5);
the input end of the fifth AND gate (AND 5) is connected with VX AND EN_VX, AND outputs m0_2;
when the load current rises in a jump by the signals En0, en_vl to enable the signal en_vx, the converter output voltage (OUT) drops, if it drops to a third voltage (V L ) Hereinafter, the fourth comparator (COMP 3 ) The output signal En_VL of the mask Sleep Control module is changed from low to high, EN_VX= "1", EN_VX_N= "0", and the output signal m0_1 of the mask Sleep Control module is determined by the output m0_2 of the EN_FLTR module;
the input of the fifth AND gate (AND 5) comprises EN_VX, VX, an output signal m0_2, a step trigger signal VX generated by the falling edge of ph2 is transmitted to m0_2, AND a new charge-discharge process is triggered until the output voltage (OUT) of the converter is raised to a second voltage (V REF ) En0 is set to zero, the falling edge EN_VX of En0 sets the signal to zero, at which time m0_2= "0", and the m0 signal is determined by m0_1.
When the signal en_vl goes from low to high, the en_fltr block is enabled AND the signal en_vx= "1", at this time, the signal VX is gated through AND gate AND5, m0_2 is controlled by VX, at which time the step trigger signal VX generated by the falling edge of ph2 with a certain delay Td will be transmitted to m0_2. Until OUT is raised to V REF The En0 is set to zero, the En0 falling edge sets the en_vx signal to zero (en_vx= "0"), at which time m0_2= "0", and the m0 signal is again determined by m0_1.
When the signal en_vl is always maintained in the low state, the en_fltr module is not enabled, the signal en_vx= "0", m0_2= "0", the mask m0_2, and the en_fltr module are not active.
Preferably, the first power tube gate driving signal generating circuit (ph 1 Pulse gen.) includes: a first flip-flop (DFF 1), a second flip-flop (DFF 2), a third flip-flop (DFF 3), a first OR gate (OR 1 ) A second OR gate (OR) 2 ) A first buffer (Buff 1), a second buffer (Buff 2), a first AND gate (AND 1), a first inverter (INV 1), a second inverter (INV 2), a first transmission gate (1), a second transmission gate (2), a third transmission gate (TG 3), a fourth transmission gate (TG 4), a Delay part (Delay), a first Delay chain (T0-tN), a second Delay chain (T0-TN), a first Switch (SW) 00 ~SW 0N ) A second Switch (SW) 10 ~SW 1N ）；
The ph1 Pulse Gen. The module inputs the signals m0, trim <2:0>, en1, outputs the signal ph1;
the trigger signal m0 triggers the first trigger (DFF 1), the signal ph1 of the output Q port goes from low to high, the second trigger (DFF 2) is formed by the first OR gate (OR 1 ) The output signal Y1 of (a) triggers and generates high and low alternating voltages Q and Q_N, Q and Q_N are used for gating a first transmission gate (TG 1), a second transmission gate (TG 2), a third transmission gate (TG 3) and a fourth transmission gate (TG 4), if Q=1, the second transmission gate (TG 2) is conducted with the fourth transmission gate (TG 4), the first transmission gate (TG 1) and the third transmission gate (TG 3) are closed, the ph1 signal is transmitted through a delay chain t 0-tN, and the first OR gate (OR) is delayed by Tx1 1 ) The output signal Y1 of the flip-flop DFF3 is changed from low to high, the Q port signal Q1 of the flip-flop DFF3 is changed from low to high, AND a pulse signal Q2 is generated through a circuit formed by a first buffer (Buff 1), a second inverter (INV 2) AND a first AND gate (AND 1), AND the width of the pulse signal is the delay time of the first buffer (Buff 1);
at a converter output voltage (OUT) lower than a first voltage (V) H ) Under the condition that En1 keeps low level, a signal Q2 is transmitted into a set end of a first trigger (DFF 1), a signal ph1 is set to be zero, and the high level duration of the signal ph1 is determined by the duration Tx1 of a delay chain;
Gamma is the proportionality coefficient of the product,input gate capacitance for delay chain basic unit Ti (i=0, 1 … N), ti (i=0, 1 … N), +.>The loads representing Ti (i=0, 1 … N), ti (i=0, 1 … N) are just intrinsic capacitances +.>Delay of time, wherein->Regarding the diffusion capacitance and the gate-drain coverage capacitance, i=0 to n, n is an even number.
Gamma is a scaling factor, which is process-dependent only,input gate capacitance for inverter, +.>The load representing the inverter is simply its intrinsic capacitance (+.>) Delay of time, wherein->In relation to the diffusion capacitance and the gate drain cover (miller) capacitance. Due to the intrinsic delay of the inverter->Independent of the size of the AND gate, only depends on the process and the inverter layout, therefore +.>The temperature characteristics are relatively good.
Preferably, the second power tube gate driving signal generating circuit (ph 2 Pulse gen.) includes: a fourth flip-flop (DFF 4), a fifth flip-flop (DFF 5), a sixth flip-flop (DFF 6), a third OR gate (OR) 3 ) Fourth OR gate (OR) 4 ) A third buffer (Buff 3), a fourth buffer (Buff 4), a second AND gate (AND 2), a third inverter (INV 3), a fourth inverter (INV 4), a fifth transfer gate (5), a sixth transfer gate (6), a seventh transfer gate (TG 7), an eighth transfer gate (TG 8), a Delay section (Delay), a third Delay chain (N0-nM), a fourth Delay chain (N0-NM), a third Switch (SW) 30 ~SW 3M ) Fourth Switch (SW) 40 ~SW 4M ) Zero crossing detection circuit (ZCD);
the ph2 Pulse gen. The module input signals include ph1, en1, T1, output signal ph2;
the signal ph2 is triggered by the falling edge of ph1 from low to high, and the fifth flip-flop (DFF 5) is triggered by a third OR gate (OR 3 ) The output signal Y2 of (a) triggers and generates high-low alternating voltages Q ' and Q ' N, Q ' and Q ' N for gating the fifth transmission gate (TG 5), the sixth transmission gate (TG 6), the seventh transmission gate (TG 7) and the eighth transmission gate (TG 8), if Q ' =1, the sixth transmission gate (TG 6) is conducted with the eighth transmission gate (TG 8), the fifth transmission gate (TG 5) and the seventh transmission gate (TG 7) are closed, the ph2 signal is transmitted through a delay chain N0-nM, and the third OR gate (OR) is performed after the delay of Tx2 3 ) The output signal Y2 of the (3) is changed from low to high, the Q port signal Q '1 triggering the sixth flip-flop (DFF 6) is changed from low to high, AND a pulse signal Q' 2 is generated through a circuit formed by the third buffer (Buff 3), the fourth inverter (INV 4) AND the second AND gate (AND 2), AND the width of the pulse signal is the delay time of the third buffer (Buff 3);
at a converter output voltage (OUT) lower than a first voltage (V) H ) In the case where En1 remains low, the signal Q' 2 goes into the fourth flip-flop (DFF 4) ) When the inductor current is detected not to be reversed, the T1 keeps low level, the Q '2 sets the signal ph2 to zero, the high level duration of the ph2 is determined by the duration Tx2 of the delay chain, and if the inductor current is detected to be reversed before the pulse signal Q' 2 is generated, the signal T1 is changed from low to high, and the ph2 signal is set to zero.
If it is detected that the inductor current has been reversed before the pulse signal Q' 2 has not been generated, the signal T1 will go from low to high, thereby zeroing the ph2 signal in advance.
It can be seen from this: since the intrinsic delay t_p0 of the inverter is independent of the size of the gate, and depends only on the process and the inverter layout, the temperature characteristics of t_x1, t_x2 are relatively good. The pulse width of the signals ph1 and ph2 is determined by the T_x1 and T_x2, and the pulse width of the gate driving signals can be adjusted by selecting the access number of i and j. (i.ltoreq.N, j.ltoreq.M.) the digital control implementation replaces the amplifier-based continuous time comparator without taking into account the tradeoff between low power, low comparator speed.
On the gating of the transmission gates TG 1-TG 4, the change of the gating signal Q is mainly triggered and regulated by Y1, but is not controlled by m 0. If DFF2 is triggered and regulated by m0, when the output voltage suddenly rises above VH, the signal En1 is changed from low to high, at this time ph1 will be set to zero in advance, at the time TG2, TG4 is turned on, TG1, TG3 is turned off, at this time Y1 has not yet changed to high to trigger DFF3, if before this time m0 triggers DFF1 again, ph1 will be set to zero by the Y1 signal which should act in the last charge-discharge process, at this time TG2, TG4 is turned off, TG1, TG3 is turned on, and the signal Y1 generated by the delay chain T0 to TN will act in the next charge-discharge loop, therefore, the time sequence will be wrong. In order to ensure the accuracy of the control time sequence, the trigger of the DFF2 is triggered and controlled by Y1, and the DFF2 is triggered to replace the transmission path only when Y1 is changed from low to high, so that the accuracy of the control is ensured.
Preferably, the zero crossing detection circuit (ZCD) comprises: first Comparator (COMP) 0 ) And Digital-control circuitry;
first Comparator (COMP) 0 ) The positive end of the voltage is grounded, and the negative end of the voltage is grounded, so as to output a signal T0; the input signals of Digital-control include T0, ph1, ph2, and output signal T1.
Preferably, the first power tube (NM 0) and the second power tube (NM 1) are connected in series;
the third power tube (PM 0) and the fourth power tube (PM 1) are connected in series;
the drain end of the third power tube (PM 0) is connected with the drain end of the second power tube (NM 1).
Preferably, the method further comprises: an inductance (L);
the inductor (L) is connected to the node (SW) and to the output capacitor (C) OUT ）。
Preferably, the method further comprises: first Comparator (COMP) 0 ) A second Comparator (COMP) 1 ) Third Comparator (COMP) 2 ）；
First Comparator (COMP) 0 ) The output end of the power supply is connected with a Digital-control module, the positive end of the power supply is connected with the SW point voltage, and the negative end of the power supply is connected with the ground;
second Comparator (COMP) 1 ) The output end of the voltage regulator is connected with a Sleep Control module, the positive end is connected with the output voltage (OUT) of the converter, and the negative end is connected with the first voltage (V H ）；
The third comparator (COMP 2 ) The output end of the (E) is connected with the Sleep Control module and the EN_FLTR module, and the positive end is connected with a second voltage (V REF ) The negative terminal is connected with the output voltage (OUT) of the converter;
fourth Comparator (COMP) 3 ) The output terminal of (a) is connected with the EN_FLTR module, the positive terminal is connected with a third voltage (V L ) The negative terminal is connected to the converter output voltage (OUT).
According to the invention, the charge and discharge of the inductor are triggered through digital logic enabling, the continuous time comparator is replaced, and faster response adjustment is realized under a low-power consumption scene.
The generation of the power tube grid driving signals ph1 and ph2 does not use a low-speed comparator, when load transient jump occurs, the upper frequency limit which can be reached by the signals is improved, and meanwhile, excessive bias current is not required to be lifted, so that the recovery time is shortened on the premise of not sacrificing the power consumption.
The start of the next charging period ph1 signal lags behind the negative edge of the ph2 of the previous period by a minimum time delay Td, and the pulse widths of ph1 and ph2 in the scheme are realized through digitization, so that the delay Td is not limited by the slow response speed of the low-power comparator, and when the load current jumps, the Td is not required to be reduced by adding an extra bias current to realize higher charging and discharging speed.
Through simulation tests, as shown in fig. 8, under the same power consumption, the low level time of VX signal can be further reduced to accelerate the charge and discharge frequency of the inductor, so that the time can be shorter under the same variation amplitude of OUT voltage (set delta OUT 160 mV), and the scheme is proved to have a certain improvement effect.
As shown in fig. 9, the pulse widths of ph1 and ph2 are controlled by using a capacitor charging and discharging method, and the pulse widths are unstable because the current varies greatly with temperature, and the pulse widths of ph1 and ph2 in the scheme are controlled by a digital circuit, and the temperature coefficient (TC 1) of the pulse widths varying with temperature is relatively small (TC 1< TC 2) under the same temperature variation (-40 ℃ -125 ℃), so that the pulse widths are more stable.
In the simulation result of fig. 10, if OUT is higher than the set threshold voltage VH, the signal en1= "1", the system enters into sleep mode, and turns off most of the circuits, when OUT is reduced to VREF, the signal en1= "0", at this time, the sleep state is exited, the whole system is powered up normally, at the same time, a pulse m0 is generated by the falling edge trigger of the signal en1, a new round of charging and discharging of the inductor is entered, and the time from exiting sleep to generating the pulse signal m0 can reach within 5ns (i.e., TD).
Under the condition of vin=2v and out=1v, after the gate driving signals ph1/ph2 of the upper/lower power tubes are specifically adjusted, the load current jumps from 500ua to 10ma, and the transient jump is simulated, as shown in fig. 11.
As shown in fig. 12, the system efficiency was simulated, and the peak efficiency was about 85%. In the dormant state, the total quiescent current is about 263nA, the power supply voltage VIN of the whole loop is 2V, the quiescent power consumption is about 526nW, and the low-power consumption scene is met.
The start of the next charging period ph1 signal is delayed by a minimum time delay Td from the negative edge of the ph2 of the previous period, and the pulse widths of ph1 and ph2 are both realized through digitization, so that the delay Td is not limited by the slow response speed of the low-power comparator, and when the load current jumps, the Td is not required to be reduced by adding an extra bias current to realize higher charging and discharging speed, the Td can be further reduced to accelerate the charging and discharging frequency without sacrificing the static current, the method is suitable for low-power scenes, and the trade-off between the speeds of the low-power and low-speed comparators is weakened.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. Ultra-low power consumption step-down DC-DC converter suitable for FLTR, characterized by comprising: a Sleep Control module, an en_fltr module, a first power tube gate driving signal generating circuit (ph 1 Pulse gen.), a second power tube gate driving signal generating circuit (ph 2 Pulse gen.), a first driving stage (driver_h), a second driving stage (driver_l), a first power tube (NM 0), a second power tube (NM 1), a third power tube (PM 0), and a fourth power tube (PM 1);
seventh trigger in the Sleep Control moduleZero-set end of (DFF 7) and third Comparator (COMP) 2 ) Is connected to the trigger terminal and the second comparator (COMP 1 ) The output end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) and the second power tube grid driving signal generating circuit (ph 2 Pulse Gen.) are connected; the input end of the Sleep Control module is connected with the EN_FLTR module;
the input of the EN_FLTR module is connected to a fourth comparator (COMP 3 ) Sixth OR gate (OR) 6 ) Output signal VX of (c), third Comparator (COMP) 2 ) The output end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) is connected with the Sleep Control module;
The input end of the first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) is connected with the Sleep Control module and the EN_FLTR module, and the output end is connected with a first driving stage (driver_H) and ph2 Pulse Gen;
the input end of the second power tube grid driving signal generating circuit (ph 2 Pulse Gen.) is connected with the zero-crossing detection circuit (ZCD), ph1 Pulse Gen.) and the Sleep Control module, and the output end is connected with the input end of the second driving stage (driver_L), the INV6, the sixth OR gate (OR) 6 ) Is connected with the input end of the power supply;
the input end of the first driving stage (driver_H) is connected with a first power tube grid driving signal generating circuit (ph 1 Pulse Gen.); the output end is connected with a third power tube (PM 0) and a fourth power tube (PM 1);
the input end of the second driving stage (driver_L) is connected with a second power tube grid driving signal generating circuit (ph 2 Pulse Gen.), and the output end of the second driving stage (driver_L) is connected with a first power tube (NM 0) and a second power tube (NM 1);
in both cases of stable load current operation and load current jump reduction: is controlled and regulated by the Sleep Control module circuit when the converter output voltage (OUT) is detected to be higher than the first voltage (V H ) Generating a signal En1, turning off a first power tube (NM 0), a second power tube (NM 1),A third power tube (PM 0) and a fourth power tube (PM 1) enter a dormant state, and during the period, the output is outputted by a load capacitor (C OUT ) Discharging is performed when the converter output voltage (OUT) decreases to a second voltage (V) REF ) Triggering to generate an En0 signal, setting the signal En1 to zero, exiting from a dormant state, and performing a new round of charging and discharging;
when the load current rises in a jump, the output voltage (OUT) of the converter drops, if the output voltage drops to a third voltage (V L ) The en_fltr module circuit is triggered and regulated, en_vx is set to a high level, the turn-on signal VX, and the gate driving signals ph1 of the third power tube (PM 0) and the fourth power tube (PM 1) are triggered and generated after the falling edges of the gate driving signals ph2 of the first power tube (NM 0) and the second power tube (NM 1) of the previous charge-discharge period pass through the delay Td;
the Sleep Control module includes: a seventh flip-flop (DFF 7), a third AND gate (AND 3), a fourth AND gate (AND 4);
the D end of the seventh trigger (DFF 7) is connected with the input voltage VIN, the Q end outputs En1, the trigger end is connected with En_VH, and the zero setting end is connected with En0;
The input end of the fourth AND gate (AND 4) is connected with EN_VX_N AND En0, AND the output is m 0';
the input end of the third AND gate (AND 3) is connected with m0 'AND m 0', AND the output is m0_1;
when the converter output voltage (OUT) is higher than the first voltage (V H ) When the second comparator (COMP 1 ) The output signal En_VH changes from low to high, the output Q end signal En1 triggering the seventh trigger (DFF 7) changes from low to high, the third power tube (PM 0), the fourth power tube (PM 1), the first power tube (NM 0) and the second power tube (NM 1) are turned off, and OUT consists of a load capacitor (C OUT ) Supplying power and entering a dormant state;
when the output voltage (OUT) of the converter is lower than the second voltage (V REF ) Third Comparator (COMP) 2 ) The output signal En0 changes from low to high, the signal En0 is connected to the zero setting end of the DFF7 and sets En1 to zero, the sleep state is exited, and the falling edge of En1 is then triggered to generate a signal from low to lowA high step signal m0', signal m0_1 will generate a step from low to high to trigger a new inductive charge-discharge process when OUT is higher than V REF Then En0 becomes "0", and m0_1 is set to zero;
the converter output voltage (OUT) is always higher than the third voltage (V L ) Fourth Comparator (COMP) 3 ) The output signal en_vl of the en_fltr block is at low level, the output signal en_vx of the en_fltr block is at low level, en_vx_n is at high level, the input of the fifth AND gate (AND 5) comprises en_vx, VX, the output signal m0_2, at this time m0_2= "0", AND the m0 signal is determined by the output signal m0_1 of the Sleep Control block circuit;
The en_fltr module includes: a fifth AND gate (AND 5);
the input end of the fifth AND gate (AND 5) is connected with VX AND EN_VX, AND outputs m0_2;
when the load current rises in a jump by the signals En0, en_vl to enable the signal en_vx, the converter output voltage (OUT) drops, if it drops to a third voltage (V L ) Hereinafter, the fourth comparator (COMP 3 ) The output signal En_VL of the mask Sleep Control module is changed from low to high, EN_VX= "1", EN_VX_N= "0", and the output signal m0_1 of the mask Sleep Control module is determined by the output m0_2 of the EN_FLTR module;
the input of the fifth AND gate (AND 5) comprises EN_VX, VX, an output signal m0_2, a step trigger signal VX generated by the falling edge of ph2 is transmitted to m0_2, AND a new charge-discharge process is triggered until the output voltage (OUT) of the converter is raised to a second voltage (V REF ) En0 is set to zero, the falling edge of En0 sets the EN_VX signal to zero, at which time m0_2= "0", and the m0 signal is determined by m0_1;
the first power tube gate driving signal generating circuit (ph 1 Pulse gen.) includes: a first flip-flop (DFF 1), a second flip-flop (DFF 2), a third flip-flop (DFF 3), a first OR gate (OR 1 ) A second OR gate (OR) 2 ) A first buffer (Buff 1), a second buffer (Buff 2), a first AND gate (AND 1), a first inverter (INV 1), a second inverter (INV 2), a first transmission gate (TG 1), a second transmission gate (TG 2)A third transmission gate (TG 3), a fourth transmission gate (TG 4), a Delay section (Delay), a first Delay chain (T0 to tN), a second Delay chain (T0 to TN), a first Switch (SW) 00 ~SW 0N ) A second Switch (SW) 10 ~SW 1N ）；
The first power tube grid driving signal generating circuit (ph 1 Pulse Gen.) inputs signals m0, trim <2:0>, en1 and outputs a signal ph1;
the trigger signal m0 triggers a first trigger (DFF 1) which outputs the signal ph1 of the Q port from low to high, and the second trigger (DFF 2) is formed by the first OR gate (OR 1 ) The output signals Y1 of the first and second transmission gates (TG 1, TG2, TG 3) and TG4 are triggered and generate high and low alternating voltages Q and Q_N, Q and Q_N for gating the first transmission gate (TG 1), the second transmission gate (TG 2), the third transmission gate (TG 3) and the fourth transmission gate (TG 4), if Q=1, the second transmission gate (TG 2) is conducted with the fourth transmission gate (TG 4), the first transmission gate (TG 1) and the third transmission gate (TG 3) are closed, the ph1 signal is transmitted through a delay chain t 0-tN, and after Tx1 delay, the first OR gate (OR 1 ) The output signal Y1 of the flip-flop DFF3 is changed from low to high, the Q port signal Q1 of the flip-flop DFF3 is changed from low to high, AND a pulse signal Q2 is generated through a circuit formed by the first buffer (Buff 1), the second inverter (INV 2) AND the first AND gate (AND 1), AND the width of the pulse signal is the delay time of the first buffer (Buff 1);
at a converter output voltage (OUT) lower than a first voltage (V) H ) Under the condition that En1 keeps low level, a signal Q2 is transmitted into a set end of a first trigger (DFF 1), a signal ph1 is set to be zero, and the high level duration of the signal ph1 is determined by the duration Tx1 of a delay chain;
gamma is the proportionality coefficient of the product,input gate capacitance for delay chain basic unit Ti (i=0, 1 … N), ti (i=0, 1 … N), +.>The loads representing Ti (i=0, 1 … N), ti (i=0, 1 … N) are just intrinsic capacitances +.>Delay of time, wherein->Regarding the diffusion capacitance and the gate-drain coverage capacitance, i=0 to n, n being an even number;
the second power tube gate driving signal generating circuit (ph 2 Pulse gen.) includes: a fourth flip-flop (DFF 4), a fifth flip-flop (DFF 5), a sixth flip-flop (DFF 6), a third OR gate (OR) 3 ) Fourth OR gate (OR) 4 ) A third buffer (Buff 3), a fourth buffer (Buff 4), a second AND gate (AND 2), a third inverter (INV 3), a fourth inverter (INV 4), a fifth transfer gate (5), a sixth transfer gate (6), a seventh transfer gate (TG 7), an eighth transfer gate (TG 8), a Delay section (Delay), a third Delay chain (N0-nM), a fourth Delay chain (N0-NM), a third Switch (SW) 30 ~SW 3M ) Fourth Switch (SW) 40 ~SW 4M ) Zero crossing detection circuit (ZCD);
the second power tube grid driving signal generating circuit (ph 2 Pulse gen.) input signals comprise ph1, en1 and T1, and output signals ph2;
the signal ph2 is triggered by the falling edge of ph1 from low to high, and the fifth flip-flop (DFF 5) is triggered by a third OR gate (OR 3 ) The output signal Y2 of (2) triggers and generates high-low alternating voltages Q 'and Q' N, Q 'and Q' N for gating the fifth transmission gate (TG 5), the sixth transmission gate (TG 6), the seventh transmission gate (TG 7) and the fifth transmission gateAn eight transmission gate (TG 8), if Q' =1, the sixth transmission gate (TG 6) is turned on with the eighth transmission gate (TG 8), the fifth transmission gate (TG 5) and the seventh transmission gate (TG 7) are turned off, the ph2 signal is transmitted through the delay chain n 0-nM, and the third OR gate (OR after the delay of Tx2 3 ) The output signal Y2 of the second AND gate (AND 2) is changed from low to high, the Q port signal Q '1 triggering the sixth trigger (DFF 6) is changed from low to high, AND a pulse signal Q' 2 is generated through a circuit formed by the third buffer (Buff 3), the fourth inverter (INV 4) AND the second AND gate (AND 2), AND the width of the pulse signal is the delay time of the third buffer (Buff 3);
at a converter output voltage (OUT) lower than a first voltage (V) H ) Under the condition that En1 keeps low level, a signal Q ' 2 is transmitted to a set end of a fourth trigger (DFF 4), under the condition that no inversion of the inductor current is detected, T1 keeps low level, Q ' 2 sets a signal ph2 to zero, the duration of the high level of the signal ph2 is determined by the duration Tx2 of a delay chain, and if the inversion of the inductor current is detected before a pulse signal Q ' 2 is not generated, the signal T1 is changed from low to high, and the signal ph2 is set to zero.
2. Ultra low power buck DC-DC converter suitable for FLTR according to claim 1, wherein the zero crossing detection circuit (ZCD) includes: first Comparator (COMP) 0 ) And Digital-control circuitry;
the first comparator (COMP 0 ) The positive end of the voltage is grounded, and the negative end of the voltage is grounded, so as to output a signal T0; the input signals of the Digital-control circuit comprise T0, ph1 and ph2, and the output signal T1 is output.
3. The ultra-low power buck DC-DC converter suitable for FLTR according to claim 1, characterized in that said first power tube (NM 0) and second power tube (NM 1) are connected in series;
the third power tube (PM 0) and the fourth power tube (PM 1) are connected in series;
the drain end of the third power tube (PM 0) is connected with the drain end of the second power tube (NM 1).
4. The ultra-low power buck DC-DC converter for use with FLTR according to claim 1, further comprising: an inductance (L);
the inductor (L) is connected with the node (SW) at one end and the output capacitor (C) at the other end OUT ）。
5. The ultra-low power buck DC-DC converter for use with FLTR according to claim 1, further comprising: first Comparator (COMP) 0 ) A second Comparator (COMP) 1 ) Third Comparator (COMP) 2 ）；
The first comparator (COMP 0 ) The output end of the power supply is connected with a Digital-control circuit, the positive end of the power supply is connected with the SW point voltage, and the negative end of the power supply is connected with the ground;
the second comparator (COMP 1 ) The output end of the converter is connected with the Sleep Control module, the positive end is connected with the output voltage (OUT) of the converter, and the negative end is connected with the first voltage (V H ）；
The third comparator (COMP 2 ) The output end of the (E) is connected with the Sleep Control module and the EN_FLTR module, and the positive end is connected with a second voltage (V REF ) The negative terminal is connected with the output voltage (OUT) of the converter;
the fourth comparator (COMP 3 ) Is connected to the EN_FLTR module, and has a positive terminal connected to a third voltage (V L ) The negative terminal is connected to the converter output voltage (OUT).
CN202311052623.9A 2023-08-18 2023-08-18 Ultralow-power-consumption step-down DC-DC converter applicable to FLTR Active CN117318479B (en)

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CN111740569A (en) * 2020-07-06 2020-10-02 重庆邮电大学 Floating gate width switching circuit applied to high-efficiency DC-DC converter

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KR100487654B1 (en) * 2002-10-22 2005-05-03 삼성전자주식회사 Low power flip-flop circuit

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CN111740569A (en) * 2020-07-06 2020-10-02 重庆邮电大学 Floating gate width switching circuit applied to high-efficiency DC-DC converter

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