CN111082658A - DCDC converter based on PCB plane inductance - Google Patents

DCDC converter based on PCB plane inductance Download PDF

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Publication number
CN111082658A
CN111082658A CN201911320354.3A CN201911320354A CN111082658A CN 111082658 A CN111082658 A CN 111082658A CN 201911320354 A CN201911320354 A CN 201911320354A CN 111082658 A CN111082658 A CN 111082658A
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China
Prior art keywords
output
current sampling
driving circuit
resistor
input terminal
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CN201911320354.3A
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Chinese (zh)
Inventor
张亮
唐晓
黄洪伟
叶凡
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Zhuhai Yingji Semiconductor Co ltd
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Zhuhai Yingji Semiconductor Co ltd
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Priority to CN201911320354.3A priority Critical patent/CN111082658A/en
Publication of CN111082658A publication Critical patent/CN111082658A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention belongs to the technical field of DCDC converters, and particularly relates to a DCDC converter based on PCB planar inductance, which comprises: one end of the PCB planar inductor is connected with the input voltage; the input end of the current sampling circuit is connected with the other end of the PCB planar inductor; the input end of the driving circuit is connected with the output end of the current sampling circuit; the output end of the driving circuit is connected with the first power tube, and the input end of the current sampling circuit is connected with the first power tube. The invention can correctly sample and limit the peak value of the inductance, normally work under high frequency and avoid the EMI interference problem.

Description

DCDC converter based on PCB plane inductance
Technical Field
The invention belongs to the technical field of DCDC converters, and particularly relates to a DCDC converter based on a PCB (printed circuit board) planar inductor.
Background
The power inductor is a very critical component in the DCDC converter, and plays a role in storing and releasing energy. With the increasing competition in the DCDC market, reducing costs becomes a significant challenge for designers. The traditional DCDC generally selects a wound inductor and a laminated inductor, the inductance value is larger but the price is higher, and the cost of the PCB coreless planar inductor is low, so that the DCDC is very suitable for manufacturing low-cost DCDC.
However, the PCB planar inductor also has a great disadvantage compared to the wound inductor and the stacked inductor: the inductance value is relatively small, when the number of turns is 10mil, the line width is 8mil, and the line spacing is 10mil, the inductance value reaches about 500nH, considering area and cost actually, the inductance value can only be about 100-200 nH generally. The low inductance value can cause the rising and the falling of the inductive current to be very rapid, the inductive current sampling circuit must be capable of carrying out high-speed sampling, otherwise, the inductive current sampling value cannot be correctly obtained, the peak value of the inductive current cannot be correctly limited, and a chip can be burnt by instant large current heating; because the peak value of the inductive current must be limited, in order to maintain the load capacity unchanged, the DCDC must adopt a high-frequency clock; in order to obtain a wide input-output voltage range, the high level time of the minimum duty cycle pulse and the low level time of the maximum duty cycle pulse must be sufficiently small under a high frequency clock. The driving circuit normally works in a small pulse time, which inevitably causes the voltage of the LX to change rapidly, thereby affecting the EMI performance of the DCDC.
In summary, the DCDC cost can be greatly reduced by using the PCB planar inductor, but since the inductance value is generally small, a series of problems such as inductor current sampling, high-frequency driving, EMI interference, etc. may be caused.
In order to solve the problems, the invention provides a DCDC converter based on PCB planar inductance.
Disclosure of Invention
An object of the present invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
It is still another object of the present invention to provide a DCDC converter based on PCB planar inductance, which can sample the inductor current at a high speed, thereby avoiding the inductor current peak value from being too high.
To achieve these objects and other advantages in accordance with the purpose of the invention, the present invention provides a DCDC converter based on a PCB plane inductance, comprising:
one end of the PCB planar inductor is connected with the input voltage;
the input end of the current sampling circuit is connected with the other end of the PCB planar inductor;
the input end of the driving circuit is connected with the output end of the current sampling circuit;
the output end of the driving circuit is connected with the first power tube, and the input end of the current sampling circuit is connected with the first power tube.
The invention can sample the inductive current at high speed, thereby ensuring that the peak value of the inductive current cannot rush too high; under the high-frequency working state, the driving circuit is combined, the rising time and the falling time of the power tube are reduced, and meanwhile, the enough conversion time of the LX voltage is ensured, so that the EMI interference of the converter is not deteriorated.
Preferably, the current sampling circuit further comprises a comparator, an input negative terminal of the comparator is connected with the output terminal of the current sampling circuit, an input positive terminal of the comparator is connected with the output voltage, and an output terminal of the comparator is connected with the driving circuit.
Preferably, the voltage regulator further comprises an error amplifier, a resistor R0, a resistor R1, a resistor R2 and a capacitor C0, wherein one end of the resistor R1 is connected to one end of an output voltage, the other end of the resistor R1 is connected to the negative input terminal of the error amplifier and one end of the resistor R2, the other end of the resistor R2 is connected to ground, the positive input terminal of the error amplifier is a reference voltage, and the output terminal of the error amplifier is connected to the positive input terminal of the comparator; the two ends of the resistor R0 and the capacitor C0 are respectively connected with two ends of the output voltage, preferably, the circuit further comprises a compensation circuit, the compensation circuit is connected with the input positive end of the comparator, the compensation circuit comprises a capacitor C0, a capacitor C1 and a resistor Rcl, one end of the capacitor C0 and the capacitor C1 which are connected in parallel is connected with the ground, and one path of the capacitor C1 which is connected in parallel is connected in series with the resistor Rcl and then is connected with the input positive end of the comparator.
Preferably, the current sampling circuit is a double-loop structure, the double-loop structure includes a fast loop and a slow loop, an input end of the fast loop is connected with a drain of the first power tube, an input end of the slow loop is connected with a drain of the current sampling tube, and output ends of the fast loop and the slow loop output current signals;
the grid electrode of the first power tube is connected with the grid electrode of the current sampling tube, and the source electrode of the first power tube is connected with the source electrode of the current sampling tube and the ground.
Preferably, the current sampling circuit further includes a first inverter, a plurality of N-type MOS transistors and a plurality of P-type MOS transistors, the plurality of N-type MOS transistors are defined as MN1, MN2, MN3, MN4, MN5, MN6, MN7, and the plurality of P-type MOS transistors are defined as MP1, MP2, MP3, MP4, MP5, MP6, MP 7;
the MN7 is respectively connected to the first power tube, the MN1, the MN2 and the MN5, the MN6, the MN3, the MN4 and the MP7 are all connected to the current sampling tube, and the current sampling tube is connected to the MN5 and the MN6 after being connected to the inverter; the MN 1-MN 4 are connected together, the MN1 is connected with the MP4, the MP4 is connected with the MP5, and the MP5 is connected with the MP6 and the MN 4; the MN2 is connected with the MP2 and the MP6, the MN3 is connected with the MP3, the MP6, the MP7 and the MP8, the MN4 is connected with the MP6 and the MP5, and the MP1, the MP2 and the MP3 are connected.
Preferably, the loops connected by MN1, MN4, MP4, MP5 and MP6 form fast loops, and the loops connected by MN2, MN3 and MP7 form slow loops.
Preferably, the driving circuit includes a second phase inverter, a pull-up driving circuit and a pull-down driving circuit, an input end of the second phase inverter is connected to an input end of the pull-down driving circuit, an output end of the second phase inverter is connected to an input end of the pull-up driving circuit, and output ends of the pull-up driving circuit and the pull-down driving circuit are connected to the first power tube.
Preferably, the pull-up driving circuit includes a first delayer, an or gate, and two P-type MOS transistors, which are defined as MP9 and MP10, an output terminal of the first inverter is connected to an input terminal of the first delayer and an input terminal of the or gate, respectively, an output terminal of the first delayer is connected to an input terminal of the or gate, an output terminal of the or gate is connected to the MP9, and the MP9 is connected to the MP 10; the pull-down driving circuit comprises a second delayer, an AND gate and two N-type MOS (metal oxide semiconductor) transistors, wherein the two N-type MOS transistors are defined as MN8 and MN9, the input end of the first phase inverter is connected with the input end of the second delayer, the output end of the first phase inverter is connected with the input end of the AND gate, the output end of the second delayer is connected with the input end of the AND gate, the output end of the AND gate is connected with MN8, and MN8 is connected with MN 9;
the drains of the MP9, the MP10, the MN8 and the MN9 are connected with the first power tube.
Preferably, the power supply further comprises a diode D, wherein the anode of the diode D is connected to the drain of the first power tube, and the cathode of the diode D is connected to the output voltage.
The invention at least comprises the following beneficial effects:
1. according to the DCDC converter based on the PCB planar inductor, the inductor current sampling circuit is of a double-ring structure, so that the inductor current can be accurately sampled at a high speed, and the peak value of the inductor current cannot be too high.
2. The DCDC converter based on the PCB planar inductance provided by the invention accelerates the driving in a subsection manner under the high-frequency working state, and ensures that the LX voltage has enough conversion time, thereby ensuring that the EMI interference of the converter is not deteriorated.
3. According to the DCDC converter based on the PCB planar inductance, the adopted drive circuit can greatly reduce the rise time and the fall time under the condition of not influencing the EMI characteristic.
4. The DCDC converter based on the PCB planar inductance can greatly reduce the DCDC cost and enlarge the popularization and application range.
Drawings
Fig. 1 is a schematic circuit diagram of a PCB planar inductance based DCDC converter according to the present invention;
FIG. 2 is a schematic diagram of a current sampling circuit according to the present invention;
FIG. 3 is a schematic diagram of the drive circuit of the present invention;
FIG. 4 is a schematic diagram of the logic processing circuit of the present invention;
FIG. 5 is a waveform diagram of the drive on and off times and LX of the present invention;
FIG. 6 is a waveform diagram of conventional drive on and off times and LX;
wherein, Vin: input voltage, Vo: output voltage, Ci: input capacitance, L: PCB planar inductance, LX: drain electrode of the first power tube, BG: a first power tube, D: flywheel diode, Co: output capacitance, Ro: load resistance, EA: error amplifier, VREF: reference voltage, Vea: output signal of error amplifier, Vfb: divided signal of output voltage, CMP 2: comparator, OCP: an overcurrent signal generated after sampling, Vsense: current sampling signal, PWMON: duty ratio control signal, BG _ ON: precursor control signal of the first power tube, BG _ DRV: drive signal, BG _ SEN: current sampling tube, LXS: drain of current sampling tube, DLY 1: first delayer, DLY2 second delayer, INV 1: first inverter, INV 2: second inverter, OR 1: or gate, ND1 and gate.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
In the present specification, when an element is referred to as being "connected to" or coupled to "or" disposed in "another element, it may be" directly connected to "or coupled to" or "directly disposed in" the other element. Or be connected or coupled to or disposed in another element with other elements interposed therebetween, unless it is volumetrically "directly coupled or connected to" or "directly disposed in" the other element. Further, it will be understood that when an element is referred to as being "on," "over," "under" or "under" another element, it can be "in direct" contact with the other element or in contact with the other element interposed therebetween, unless it is referred to as being in direct contact with the other element.
The present invention provides a DCDC converter based on PCB planar inductance, as shown in fig. 1, comprising:
one end of the PCB planar inductor is connected with the input voltage Vin;
the input end of the current sampling circuit is connected with the other end of the PCB planar inductor through the LX;
the input end of the driving circuit is connected with the output end of the current sampling circuit;
the output end of the driving circuit is connected with the grid electrode of the first power tube, the input end of the current sampling circuit is connected with the drain electrode LX of the first power tube, and the source electrode of the first power tube is connected with the ground.
The invention can sample the inductive current at high speed, thereby ensuring that the peak value of the inductive current cannot rush too high; under the high-frequency working state, the driving circuit is combined, the rising time and the falling time of the power tube are reduced, and meanwhile, the enough conversion time of the LX voltage is ensured, so that the EMI interference of the converter is not deteriorated.
Specifically, the current sampling circuit further comprises a comparator, wherein the input negative end of the comparator is connected with the output end of the current sampling circuit, the input positive end of the comparator is connected with the output voltage, and the output end of the comparator is connected with the driving circuit; the input negative end of the comparator is connected with the output end of the current sampling circuit, the input positive end of the comparator is connected with the output voltage, namely, after the current sampling signal Vsense acquired by the current sampling circuit is compared with the output voltage, a duty ratio control signal PWMON is generated, then the duty ratio control signal PWMON is input into the driving circuit, the driving capability of the driving circuit is increased, and then a driving signal is generated to drive the first power tube to be switched on and off.
Before the duty ratio control signal PWMON is input into the drive circuit, the overcurrent signal OCP generated after the sampling of the current sampling circuit and the duty ratio control signal PWMON can be processed logically at the same time, wherein, the logic processing circuit is a logic processing circuit, as shown in fig. 4, the logic processing circuit comprises an inverter and an and gate, the input end of the phase inverter is connected with one path of the output OCP overcurrent signal of the output end of the current sampling circuit, the output end of the phase inverter is connected with one end of the input of the AND gate, the other end of the input of the AND gate is connected with the output end of the comparator, the output end of the AND gate is connected with the driving circuit, when the inductive current is overhigh, the OCP signal is high, and BG _ ON is forcibly pulled down after the OCP signal passes through the inverter and the AND gate, so that the power tube BG is turned off, and the DCDC is protected from being burnt out due to overheating.
Specifically, the device also comprises an error amplifier EA and a resistor R0A resistor R1, a resistor R2 and a capacitor C0Wherein Co is an output capacitor, Ro is a load resistor, and the load resistor is respectively connected with two ends of Vo; r1 and R2 are voltage dividing resistor strings, the input negative end of the error amplifier is connected with the divided voltage of the output voltage, the input positive end of the error amplifier is a reference voltage VREF, and the output end of the error amplifier is connected with the input positive end of the comparator; the resistor R0And said capacitor C0The two ends of the resistor R1 are respectively connected with the two ends of the output voltage, one end of the resistor R1 is connected with one end of the output voltage, the other end of the resistor R1 is respectively connected with the input negative end of the error amplifier and one end of the resistor R2, the other end of the resistor R2 is connected with the ground, the resistor R1 and the resistor R2 are voltage dividing resistor strings, and the voltage dividing value of the resistor R1 and the voltage dividing value of the resistor R2 are connected with the negative end of the EA.
Specifically, the dc-dc converter further comprises a compensation circuit, the compensation circuit is connected with the positive input terminal of the comparator, the compensation circuit comprises a capacitor C0, a capacitor C1 and a resistor Rcl, one end of the capacitor C0 and the capacitor C1 after being connected in parallel is connected with ground, one path of the capacitor C1 in parallel is connected in series with the resistor Rcl and then is connected with the positive input terminal of the comparator, and the compensation circuit is used for ensuring the stability of the DCDC loop.
As shown in fig. 1, the inductor adopts a PCB planar inductor, the circuit adopts a peak current mode control of PWM, the DCDC frequency is higher than the conventional DCDC frequency due to the low inductance value, and the current sampling circuit and the driving circuit invent a new circuit architecture. In fig. 1, Ci is an input capacitor connected to both ends of an input voltage Vin; l is a PCB planar inductor, and two ends of the L are respectively connected with Vin and a power tube drain electrode LX; BG is a power tube, the drain electrode is connected to an inductor, and the source end is connected with the ground; d is a freewheeling diode, the anode of which is connected with LX and the cathode of which is connected with the output Vo; co is an output capacitor, Ro is a load resistor, and the load resistor is respectively connected with two ends of Vo; r1 and R2 are voltage dividing resistor strings, and the voltage dividing value of the voltage dividing resistor strings is connected with the negative end of the EA; VREF is a reference voltage and is connected with the positive end of the EA; EA is an error amplifier, and the output Vea is connected with a compensation circuit consisting of Rc1, C1 and C0 and enters the positive terminal of a comparator CMP 2; the current sampling circuit samples the current when the first power tube BG is switched on (namely the inductive current when BG is switched on), the current sampling circuit is connected to the LX for current sampling, an overcurrent signal OCP generated after sampling enters the logic processing circuit, when the OCP is high, the logic processing circuit for logic processing can generate a signal to close BG (as shown in figure 4), another current sampling signal Vsense generated after current sampling is connected to the negative end of a comparator CMP2, and a duty ratio control signal PWMON generated by comparing the current sampling signal with Vea is input to the logic processing circuit; the logic processing circuit generates a precursor control signal BG _ ON of a first power tube BG _ ON, the precursor control signal BG _ ON enters a driving circuit, and a driving signal BG _ DRV is generated after the driving capability of the driving circuit is increased; BG _ DRV is connected with the grid of the first power tube BG to control the on and off of the first power tube BG.
The working principle of the DCDC converter based on the PCB planar inductance provided by the invention is as follows: when the output voltage is low, the output feedback voltage is compared with VREF, an error signal Vea is output to be high after passing through an error amplifier EA, the duty ratio of a PWMON control signal obtained after being compared with an inductive current sampling signal is increased, and then the duty ratio of a driving signal BG _ DRV signal obtained after being processed by a driving circuit is increased, so that the inductive current is increased, more energy is released to output, and the output voltage is increased to keep the stability of the output voltage; when the output voltage is higher, the output feedback voltage is compared with VREF, an output error signal Vea becomes lower after passing through an error amplifier EA, the duty ratio of a PWMON control signal obtained after comparison with an inductive current sampling signal becomes smaller, and then the duty ratio of a driving signal BG _ DRV signal obtained after processing by a driving circuit becomes smaller, so that the inductive current is reduced, less energy is released to output, the output voltage is reduced, and the stability of the output voltage is kept.
On the basis of the above embodiments, in yet another embodiment, as shown in fig. 2, the current sampling circuit has a dual-loop structure, where the dual-loop structure includes a fast loop and a slow loop, an input end of the fast loop is connected to the drain of the first power transistor, an input end of the slow loop is connected to the drain of the current sampling transistor, and output ends of the fast loop and the slow loop output current signals; the current sampling circuit adopts double-loop control, and can accurately sample in the rapid rising process of the inductive current.
The grid electrode of the first power tube is connected with the grid electrode of the current sampling tube, and the source electrode of the first power tube is connected with the source electrode of the current sampling tube and the ground. BG is a power tube, BG _ SEN is a current sampling tube, grid electrodes are all connected with a driving signal BG _ DRV, a source end of the BG is connected with the ground, a drain end of the BG is connected with LX, and a drain end of the BG _ SEN is connected with LXS.
Specifically, the current sampling circuit further comprises a first inverter, a plurality of N-type MOS transistors and a plurality of P-type MOS transistors, the plurality of N-type MOS transistors are defined as MN1, MN2, MN3, MN4, MN5, MN6 and MN7, and the plurality of P-type MOS transistors are defined as MP1, MP2, MP3, MP4, MP5, MP6 and MP 7;
the MN7 is a switch tube, a gate is connected with BG _ DRV, a drain is connected with LX, a source stage is respectively connected with the source of MN1, the source of MN2 and the drain of MN5, BG _ DRV is connected with the gates of MN5 and MN6 after passing through an inverter, source ends of MN5 and MN6 are both connected to a ground potential, drain ends of MN6, source ends of MN3 and MN4 and drain ends of MP7 are both connected to LXS; the gates of the MN 1-MN 4 are connected together, the drain terminal of the MN1 is connected with the drain terminal of the MP4, the drain source of the MN2 is connected with the point B to form a diode connection mode, the point B is connected with the drain terminals of the MP2 and the MP6, the drain terminal of the MN3 is connected with the drain terminal of the MP3, the source terminal of the MP6 and the gate terminals of the MP7 and the MP8 are connected with the point A, and the drain terminal of the MN4 is connected with the gate terminal of the MP6 and the drain terminal of the MP5 and is connected with the point C; MP1, MP2 are connected with the grid of MP3, and the drain of MP1 is connected; the drain terminal of the MP8 is connected to the resistor R2, the generated current sampling signal Vsense is connected to the positive terminal of the comparison, the reference voltage VREF is connected to the negative terminal of the comparator, and the overcurrent signal OCP is obtained after the comparison.
As shown in fig. 2, MP1, MP2, and MP3 form a current mirror to provide current for the circuit, MN2, MN3 are clamp circuits to ensure that LX is equal to LXs voltage, BG is a power tube, BG _ SEN is a sampling tube, BG _ SEN will proportionally mirror BG current when LX is equal to LXs, MN5, MN6, and MN7 are switching tubes, loops connected with MN1, MN4, and MP4 to MP6 form a fast loop, loops connected with MP7, MN2, and MN3 form a slow loop, MP8 and MP7 are current mirrors, C2 and C3 are parasitic capacitances of MP7, VREF 2 converts the sampling current into a sampling voltage Vsense, and compares with the sampling voltage to obtain a peak current over-current signal OCP.
The working principle of the current sampling circuit is as follows: when the power tube BG is turned off, that is, BG _ DRV is low, no current sampling is performed, so that BG and BG _ SEN are both turned off, MN7 is turned off, MN5 and MN6 are turned on, and at this time, the clamp circuit formed by MP3 and MP4 still works to avoid time consumption for the circuit to reestablish the loop when BG is turned on in the next period. When BG is turned on, namely BG _ DRV is high, current sampling is needed, BG and BG _ SEN are both turned on, MN7 is turned on, MN5 and MN6 are turned off, at the moment, LX and LXS are clamped at equal voltage due to the same current of MN2 and MN3, BG _ SEN mirrors the current on BG1 in proportion (at the moment, the current on BG1 is equal to the inductive current), the current is mirrored to MP8 through MP7, and finally converted into Vsense, and the Vsense is compared with VREF to generate an overcurrent OCP signal. Since the size of the MP7 is generally large (because of taking a sampling current of mA level), the parasitic capacitances C2 and C3 of MP7 are also large, so the speed of the negative feedback loop formed by MP7, MN2 and MN3 is slow, when BG is turned on, the voltage at point a needs to be reduced, the current of MN3 is large when C1 and C2 discharge, and the current of MN2 is small because the gate capacitances of MN2 and MN3 charge, so LX and LXs are not equal, when the inductive current rises quickly, the circuit cannot sample correctly. At this time, a fast feedback loop composed of MN1, MN4, and MP4 to MP6 is required to accelerate the sampling process, and the principle is as follows: when BG is switched on, the current of MN3 is larger than that of MN2 due to the existence of the register capacitor, the voltage C point of the gate terminal of MP6 is pulled low due to the fact that MN4 is the current of the mirrored MN3 and MN1 is the current of the mirrored MN2, the point A and the point B are conducted, and as a result, the current passing through MN3 is reduced and the current passing through MN2 is increased until the currents of MN2 and MN3 are equal to each other, so that the voltage is stable, LX is equal to LXS, and the circuit is correctly sampled.
On the basis of the above embodiments, as shown in fig. 3, in yet another embodiment, the driving circuit includes a second inverter, a pull-up driving circuit, and a pull-down driving circuit, an input end of the second inverter is connected to an input end of the pull-down driving circuit, an output end of the second inverter is connected to an input end of the pull-up driving circuit, and output ends of the pull-up driving circuit and the pull-down driving circuit are connected to the first power transistor.
Specifically, the pull-up driving circuit includes a first delayer, an or gate, and two P-type MOS transistors, where the two P-type MOS transistors are defined as MP9 and MP10, an output end of the first inverter is connected to an input end of the first delayer and an input end of the or gate, respectively, an output end of the first delayer is connected to an input end of the or gate, an output end of the or gate is connected to MP9, and MP9 is connected to MP 10; the pull-down driving circuit comprises a second delayer, an AND gate and two N-type MOS (metal oxide semiconductor) transistors, wherein the two N-type MOS transistors are defined as MN8 and MN9, the input end of the first phase inverter is connected with the input end of the second delayer, the output end of the first phase inverter is connected with the input end of the AND gate, the output end of the second delayer is connected with the input end of the AND gate, the output end of the AND gate is connected with MN8, and MN8 is connected with MN 9;
the drains of the MP9, the MP10, the MN8 and the MN9 are connected with the first power tube.
As shown in fig. 3, the predecessor BG _ ON is connected to the input of the inverter INV and the delay unit DLY 2; the output signal a of the inverter INV is connected to the input of the delay unit DLY1, the inputs of the OR gate OR1 and the and gate ND1, and the gates of MP2 and MN 2; the output D of DLY1 is connected to the other input of OR1, and the output E of DLY2 is connected to the other input of ND 1; the output B of the OR1 is connected to the gate of the MP1, and the output C of the ND1 is connected to the gate of the MN 1; the drain terminals of the MP1, the MP2, the MN1 and the MN2 are connected to obtain an output signal BG _ DRV, the source terminals of the MP1 and the MP2 are connected to a power supply voltage, and the source terminals of the MN1 and the MN2 are connected to a ground potential.
As shown in fig. 6, waveforms of the driving signal and LX in the conventional driving circuit are described first, where the precursor signal BG _ ON is high, the driving signal BG _ DRV starts to rise for a time t1, and the current of the power tube BG during this time period rapidly increases to the inductive current, but the LX voltage remains unchanged; in a time period t2, the power tube Miller platform is driven to enter, BG _ DRV keeps unchanged, and LX voltage gradually drops to 0; after the time period t3, the driving signal BG _ DRV continues to rise to the maximum voltage, and the LX voltage remains 0. The turn-off process is similar to the turn-on process: in the time t4, the driving signal BG _ DRV is reduced until the driving signal BG _ DRV enters the power tube Miller platform, and the LX voltage is kept to be 0 in the process; in t5, the driving is carried out on the power tube Miller platform, the BG _ DRV is kept unchanged, and the LX voltage gradually rises to the highest voltage; during the time period t6, the driving signal continuously decreases until the voltage is 0, the voltage of the LX keeps the highest and the current on the BG1 rapidly decreases to 0.
Since the DCDC minimum duty ratio time and the maximum duty ratio low level time based on the PCB plane inductance are very small, the turn-on and turn-off processes of the power tube BG must be accelerated, that is, the time of t1+ t2+ t3 and t4+ t5+ t6 are shortened, if the overall driving capability is increased, the rising and falling speed of the LX must be increased, which affects the EMI performance of the DCDC. From the above analysis, it can be known that the rising and falling speeds of LX are only related to t2 and t5 (i.e. miller plateau time), so that the time of t2 and t5 can be kept unchanged, and the time of t1, t3, t4 and t6 can be reduced.
Therefore, the working principle of the driving circuit of the invention is as follows: when the precursor BG _ ON is changed from low to high (namely when a power tube is turned ON), the voltage at the point A is changed into low, the voltage at the point C obtained by passing an AND gate is also low, so that MN1 and MN2 are turned off, MP2 is turned ON, and the voltage at the point D is still high without jumping in the delay time due to the existence of DLY1, so that the point B is also high at the moment, and MP1 is turned off; after the delay is finished, the point D jumps to be low, the point B also changes to be low, at this time, the MP1 opens the accelerated pull-up BG _ DRV, the delay time is more than or equal to t1+ t2, and the accelerated time period is t 3. When the precursor BG _ ON is changed from high to low (namely when a power tube is turned off), the voltage at the point A jumps to high, the voltage at the point B obtained by passing through an OR gate is also high, so that MP1 and MP2 are turned off, MN2 is turned ON, and because of the existence of DLY2, the voltage at the point E is still high in delay time, so that the voltage at the point C is also high, MN1 is also turned ON, BG _ DRV is pulled down in an acceleration mode, the delay time is less than or equal to t4, and the acceleration time is t 4; after the delay is finished, the voltage at the point E jumps to be low, so that the voltage at the point C also jumps to be low, the MN1 is switched off, and the time of t5 and t6 is not influenced.
As shown in fig. 3 and 5, the driving circuit provided by the present invention mainly reduces the time periods t3 and t4 with relatively long time, and as shown in the waveform diagram of the driving on and off time and LX of the present invention shown in fig. 5, it can be seen that in this example, the time periods t1, t2, t5 and t6 are not changed, so that the rise time and the fall time of LX are not changed, and the EMI characteristic of the circuit is better. the time t3 and t4 is greatly reduced to t3 'and t 4', so that the rising and falling time of BG _ DRV is greatly reduced, and the new driving can be applied to the conditions of high frequency and small duty ratio and large duty ratio. If the frequency requirement is higher, the time at t1 and t6 can be continuously reduced, which will not be repeated herein.
In addition, the invention also comprises a diode D, wherein the anode of the diode D is connected with the drain electrode of the first power tube, and the cathode of the diode D is connected with the output voltage.
Further comprising an input capacitance Ci connected across said input voltage Vin.
According to the DCDC converter based on the PCB planar inductor, the designed inductor current sampling circuit adopts a double-ring structure, and can sample the inductor current at a high speed, so that the peak value of the inductor current is prevented from being too high; under the high-frequency working state, the driving is accelerated in a segmented mode, the rising time and the falling time of a power tube are reduced, and meanwhile, the enough conversion time of the LX voltage is guaranteed, so that the EMI interference of the converter is guaranteed not to be worsened.
It is obvious that those skilled in the art can obtain various effects not directly mentioned according to the respective embodiments without trouble from various structures according to the embodiments of the present invention.
While embodiments of the invention have been disclosed above, it is not intended to be limited to the uses set forth in the specification and examples. It can be applied to all kinds of fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. It is therefore intended that the invention not be limited to the exact details and illustrations described and illustrated herein, but fall within the scope of the appended claims and equivalents thereof.

Claims (10)

1. A DCDC converter based on PCB planar inductance, comprising:
one end of the PCB planar inductor is connected with the input voltage;
the input end of the current sampling circuit is connected with the other end of the PCB planar inductor;
the input end of the driving circuit is connected with the output end of the current sampling circuit;
the output end of the driving circuit is connected with the first power tube, and the input end of the current sampling circuit is connected with the first power tube.
2. The PCB planar inductance based DCDC converter of claim 1, further comprising a comparator, wherein the negative input terminal of said comparator is connected to the output terminal of said current sampling circuit, the positive input terminal of said comparator is connected to the output voltage, and the output terminal of said comparator is connected to said driving circuit.
3. The PCB planar inductance based DCDC converter of claim 2, further comprising an error amplifier, a resistor R0, a resistor R1, a resistor R2 and a capacitor C0, wherein one end of said resistor R1 is connected to one end of an output voltage, the other end of said resistor R1 is connected to the negative input terminal of said error amplifier and one end of said resistor R2, respectively, the other end of said resistor R2 is connected to ground, the positive input terminal of said error amplifier is a reference voltage, the output terminal of said error amplifier is connected to the positive input terminal of said comparator, and the two ends of said resistor R0 and said capacitor C0 are connected to the two ends of the output voltage, respectively.
4. The PCB planar inductance based DCDC converter of claim 2, further comprising a compensation circuit, said compensation circuit being connected to the positive input terminal of said comparator, said compensation circuit comprising a capacitor C0, a capacitor C1 and a resistor Rcl, one end of said capacitor C0 being connected in parallel with said capacitor C1 being connected to ground, one end of said capacitor C1 being connected in parallel with said resistor Rcl being connected in series to the positive input terminal of said comparator.
5. The PCB planar inductance based DCDC converter of claim 1, wherein the current sampling circuit is a dual-loop structure, the dual-loop structure comprises a fast loop and a slow loop, an input terminal of the fast loop is connected to a drain of the first power transistor, an input terminal of the slow loop is connected to a drain of the current sampling transistor, and the fast loop and an output terminal of the slow loop output current signals;
the grid electrode of the first power tube is connected with the grid electrode of the current sampling tube, and the source electrode of the first power tube is connected with the source electrode of the current sampling tube and the ground.
6. The PCB planar inductance based DCDC converter of claim 5, wherein the current sampling circuit further comprises a first inverter, a plurality of N-type MOS transistors and a plurality of P-type MOS transistors, the plurality of N-type MOS transistors are defined as MN1, MN2, MN3, MN4, MN5, MN6 and MN7, the plurality of P-type MOS transistors are defined as MP1, MP2, MP3, MP4, MP5, MP6 and MP 7;
the MN7 is respectively connected to the first power tube, the MN1, the MN2 and the MN5, the MN6, the MN3, the MN4 and the MP7 are all connected to the current sampling tube, and the current sampling tube is connected to the MN5 and the MN6 after being connected to the inverter; the MN 1-MN 4 are connected together, the MN1 is connected with the MP4, the MP4 is connected with the MP5, and the MP5 is connected with the MP6 and the MN 4; the MN2 is connected with the MP2 and the MP6, the MN3 is connected with the MP3, the MP6, the MP7 and the MP8, the MN4 is connected with the MP6 and the MP5, and the MP1, the MP2 and the MP3 are connected.
7. The PCB planar inductance based DCDC converter of claim 6, wherein the loops to which MN1, MN4, MP4, MP5 and MP6 are connected form a fast loop, and the loops to which MN2, MN3 and MP7 are connected form a slow loop.
8. The PCB planar inductance based DCDC converter of claim 2, wherein the driving circuit comprises a second inverter, a pull-up driving circuit and a pull-down driving circuit, an input terminal of the second inverter is connected to an input terminal of the pull-down driving circuit, an output terminal of the second inverter is connected to an input terminal of the pull-up driving circuit, and output terminals of the pull-up driving circuit and the pull-down driving circuit are connected to the first power tube.
9. The PCB planar inductance based DCDC converter of claim 8, wherein said pull-up driving circuit comprises a first delayer, an OR gate, two P-type MOS transistors defined as MP9 and MP10, an output terminal of said first inverter is connected to an input terminal of said first delayer and an input terminal of said OR gate, respectively, an output terminal of said first delayer is connected to an input terminal of said OR gate, an output terminal of said OR gate is connected to said MP9, and said MP9 is connected to said MP 10; the pull-down driving circuit comprises a second delayer, an AND gate and two N-type MOS (metal oxide semiconductor) transistors, wherein the two N-type MOS transistors are defined as MN8 and MN9, the input end of the first phase inverter is connected with the input end of the second delayer, the output end of the first phase inverter is connected with the input end of the AND gate, the output end of the second delayer is connected with the input end of the AND gate, the output end of the AND gate is connected with MN8, and MN8 is connected with MN 9;
the drains of the MP9, the MP10, the MN8 and the MN9 are connected with the first power tube.
10. The PCB planar inductance based DCDC converter of any one of claims 1 to 9, further comprising a diode D, wherein the anode of said diode D is connected to the drain of said first power tube, and the cathode of said diode D is connected to the output voltage.
CN201911320354.3A 2019-12-19 2019-12-19 DCDC converter based on PCB plane inductance Pending CN111082658A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113037253A (en) * 2021-02-25 2021-06-25 中国电子科技集团公司第五十八研究所 Open drain output circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113037253A (en) * 2021-02-25 2021-06-25 中国电子科技集团公司第五十八研究所 Open drain output circuit

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