CN113054838A - Hybrid dual-path buck converter - Google Patents
Hybrid dual-path buck converter Download PDFInfo
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- CN113054838A CN113054838A CN202110348405.4A CN202110348405A CN113054838A CN 113054838 A CN113054838 A CN 113054838A CN 202110348405 A CN202110348405 A CN 202110348405A CN 113054838 A CN113054838 A CN 113054838A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
Abstract
The invention belongs to the field of integrated circuits and the technical field of switching power supplies, and particularly relates to a hybrid dual-path buck converter. The hybrid dual-path topological structure combines the switch capacitor voltage converter and the switch inductor voltage converter, has two parallel power supply paths, and can reduce the inductor current and the DCR loss. In addition, the flying capacitor bears part of the voltage drop, so the voltage stress of the power switch tube is also reduced. Due to the smaller voltage swing at the switching node, the switching losses and the inductor current ripple are also reduced. Compared with the traditional buck converter, the hybrid dual-path buck converter greatly improves the energy conversion efficiency.
Description
Technical Field
The invention belongs to the field of integrated circuits and the technical field of switching power supplies, and particularly relates to a hybrid dual-path buck converter.
Background
With the continuous progress and development of technology, portable electronic devices have become widely popular, and as an essential component thereof, power management chips have become increasingly indispensable. While maintaining performance, portable electronic devices are expected to have improved power density and energy conversion efficiency, which is undoubtedly a great challenge for power management chips, inductance is a difficult problem therein because a trade-off needs to be made between package size, inductance, and direct current Resistance (DC Resistance, DCR), and the problem of large inductance DCR and small saturation current in small-sized packages makes efficiency limited at large currents. The inductor is located on an output current path in the traditional buck topology structure, the current on the inductor is the output current, and the size of the inductor is in inverse proportion to the DCR of the inductor, so that the DCR loss of the small-size power inductor in the traditional buck is large, and the temperature is higher and the efficiency is worse when the heavy load is carried out. The Equivalent Series Resistance (ESR) of ceramic capacitors is much smaller than that of small-sized power inductors, so that the loss of inductance in the converter can be reduced by using a low ESR of the switched capacitor, and thus hybrid dual-path DC-DC buck converter topologies combining the switched capacitor and the switched inductor are proposed, the main idea being to achieve higher conversion efficiency than the conventional buck converter structure by reducing inductor current and DCR loss.
As shown in FIG. 1, 3 hybrid two-way buck converter (DPSD) topologies have been proposed, where the voltage conversion ratio of Type-I and Type-II are both higher than 1/2 and the voltage conversion ratio of Type-III is lower than 1/2. As the size of the CMOS is continuously reduced, the power supply voltage of the processor is also continuously reduced to 0.5V-1.2V which is far lower than the power supply voltage of the lithium battery (the power supply voltage when the lithium battery is fully charged and is close to being exhausted is respectively 4.2V and 2.7V), so that the Type-I and Type-II are not suitable for the processor with low power supply voltage; although the Type-III voltage conversion ratio is below 1/2, the converter is dedicated to high voltage and high power applications and is not suitable for portable electronic devices.
Disclosure of Invention
The invention aims to provide a hybrid two-way buck converter suitable for low-voltage and large-current, which can effectively reduce the DCR loss of an inductor, improve the energy conversion efficiency and realize a voltage conversion ratio smaller than 1/2.
The technical scheme of the invention is as follows:
a hybrid dual path buck converter includes a power stage topology and a bootstrap drive circuit module; the power stage topological structure comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a flying capacitor CFAn output capacitor COInductor L and load resistor RL；
The drain of the first NMOS transistor MN1 is connected to the input voltage, the gate is connected to the first driving signal, and the source of the first NMOS transistor MN1 is connected to the flying capacitor CFOne end of (a);
the drain of the second NMOS transistor MN2 is connected to the source of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 is connected to the second driving signal, and the source of the second NMOS transistor MN2 is connected to the output capacitor COAnd a load resistor RLOne end of (a);
the drain of the third NMOS transistor MN3 is connected to the source of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3 is connected to the third driving signal, and the source of the third NMOS transistor MN3 is connected to one end of the inductor L and the flying capacitor CFThe other end of (a);
the source electrode of the second NMOS transistor MN2, the drain electrode of the third NMOS transistor MN3 and the output capacitor COOne end of (1), load resistance RLThe connection point of one end of the first switching element is the output end of the buck converter; the other end of the inductor L and the output capacitor COAnother terminal of (1), a load resistor RLThe other ends of the two are grounded;
the bootstrap drive circuit module comprises a first switch tube MSN1, a second switch tube MSP1, a third switch tube MSP2 and a first bootstrap capacitor CBoot1A second bootstrap capacitor CBoot2A third bootstrap capacitor CBoot3And a fourth self-lifting capacitor CBDThe driving circuit comprises a first level shift circuit LS1, a second level shift circuit LS2, a third level shift circuit LS3, a first driving circuit DRV1, a second driving circuit DRV2, a third driving circuit DRV3, a diode DB, an inverter INV1 and an LDO module;
the source of the first switch tube MSN1 is connected with the input voltage and the anode of the diode DB, the grid of the first switch tube MSN1 is connected with the cathode of the diode DB and the fourth self-lifting capacitor CBDThe drain of the first switch tube MSN1 is connected to the input end of the LDO;
fourth self-lifting capacitor CBDThe other end of the inverter INV is connected with the output end of the inverter INV1, and the input end of the inverter INV1 is connected with the pulse input signal;
the grid electrode of the second switch tube MSP1 is connected with a first external control signal, and the source electrode of the second switch tube MSP1 is connected with a first bootstrap capacitor CBoot1And a drain of the second switch transistor MSP1 is connected to the second bootstrap capacitor CBoot2And a power source terminal of the second drive circuit DRV 2;
the grid electrode of the third switch tube MSP2 is connected with a second external control signal, the drain electrode of the third switch tube MSP2 is connected with the output section of the LDO and the third bootstrap capacitor CBoot3And a power source terminal of the third drive circuit DRV 3;
the input end of the first level shift circuit LS1 is connected with a pulse input signal, and the output end of the first level shift circuit LS1 is connected with the input end of the first driving circuit DRV 1; the ground signal of the first driving circuit DRV1 is connected with the drain of the first NMOS transistor MN1 and the flying capacitor CFThe ground signal terminal of the first driving circuit DRV1 and a first bootstrap capacitor CBoot1The other end of the first driving circuit DRV1, and the output end of the first driving circuit DRV1 outputs a first driving signal;
the input end of the second level shift circuit LS2 is connected with the pulse input signal, and the output end of the second level shift circuit LS2 is connected with the input end of the second driving circuit DRV 2; the ground signal terminal of the second driving circuit DRV2 is connected with the output terminal of the buck converter, and the ground signal terminal of the second driving circuit DRV2 is connected with a second bootstrap capacitor CBoot2The other end of the second driving circuit DRV2, the output end of the ground signal end of the second driving circuit DRV2 outputs a second driving signal;
the input end of the third level shift circuit LS3 is connected with the pulse input signal, and the output end of the third level shift circuit LS3 is connected with the input end of the third driving circuit DRV 3; the ground signal of the third driving circuit DRV3 is connected with the drain of the third NMOS transistor MN3And flying capacitor CFA ground signal terminal of the third driving circuit DRV3 and a third bootstrap capacitor CBoot3And the other end of the third driving circuit DRV3 is connected to the ground signal end of the LDO module, and the output end of the third driving circuit DRV3 outputs a third driving signal.
The invention has the beneficial effects that: the hybrid dual path topology combines a switched capacitor voltage converter and a switched inductor voltage converter with two parallel power supply paths that reduce inductor current and DCR losses. In addition, the flying capacitor bears part of the voltage drop, so the voltage stress of the power switch tube is also reduced. Due to the smaller voltage swing at the switching node, the switching losses and the inductor ripple are also reduced.
Drawings
FIG. 1 is a circuit diagram of 3 hybrid dual buck converter topologies;
FIG. 2 is a circuit diagram of a hybrid two-way buck converter topology according to the present invention;
FIG. 3 is a circuit diagram of an embodiment of the present invention;
FIG. 4 is a timing logic diagram of an embodiment of the present invention;
FIG. 5 is a graph of the efficiency of the present invention compared to a conventional buck at different loads and different voltage conversion ratios.
Detailed Description
The following description of specific embodiments of the present invention is made with reference to the accompanying drawings and examples:
FIG. 2 is a circuit diagram of a hybrid dual buck converter topology according to the present invention, which includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a first capacitor CFA second capacitor COInductor L and load resistor RL. The capacitor and the inductor are energy storage elements, energy is not consumed, in addition, the voltage at two ends of the capacitor cannot change suddenly, and the current at two ends of the inductor cannot change suddenly. By means of these characteristics, the energy conversion from input to output can be achieved and the first capacitance C can be determinedFPressure drop over is VCF＝VIN-VOUTAccording to the volt-second balance of the inductance, i.e. the inductance in steady state, the volt-second of the switch on-time (current rise)The number of the voltage-second is equal to the number of the voltage-second when the switch is turned off (current falling section), and the conversion ratio of the input and output voltages can be obtained as follows:
examples
The circuit structure of this example is shown in fig. 3, and includes two parts, namely a power stage topology and a bootstrap driving circuit module. The power stage topology comprises 3 power switch tubes MN1, MN2 and MN3, and a flying capacitor CFAn output capacitor COAn inductor L and a load resistor RL。
Specifically, the drain of the first NMOS transistor MN1 is connected to the input voltage VBATA gate connected to a driving signal TG1, and a source connected to a flying capacitor CFAnd the drain of the second NMOS transistor MN 2.
The gate of the second NMOS transistor MN2 is connected to the drive signal TG2, and the source is connected to the drain of the third NMOS transistor and the output capacitor COAnd a load resistor RLAnd to an output voltage.
The gate of the third NMOS transistor MN3 is connected to the driving signal BG, and the source is connected to one end of the inductor L and the flying capacitor CFAnd the other end of the same.
The other end of the inductor L is connected with the ground; output capacitor COThe other end of which is connected to ground, a load resistor RLThe other end of which is also connected to ground.
The bootstrap drive circuit module comprises 3 switching tubes MSN1, MSP1 and MSP2, and 4 bootstrap capacitors CBoot1、CBoot2、CBoot3、C BD3 level shift circuits LS1, LS2 and LS3, 3 driving circuits DRV1, DRV2, DRV3, a diode DB and an LDO module.
Specifically, the source of the fourth NMOS transistor MN4 is connected to the input voltage VBATOne end of a diode DB, the other end of which is connected to the gate of the diode DB and a bootstrap capacitor CBDAnd the drain is connected with the input end of the LDO.
The gate of the first PMOS transistor MP1 is connected to the control signal S1, and the source is connected to the first transistorBootstrap capacitor CBoot1One terminal of the first driving circuit DRV1, a power supply terminal BST1, a drain terminal connected to the source of the second PMOS transistor MP2, and a second bootstrap capacitor CBoot2And a power source terminal BST2 of the second drive circuit DRV 2.
The gate of the second PMOS transistor MP2 is connected to the control signal S2, the drain is connected to the output of LDO, and the third bootstrap capacitor CBoot3And a power source terminal BST3 of the third drive circuit DRV 3.
The input of the first level shift circuit LS1 is an NPWM signal, and the output is the input of the first driving circuit DRV 1; the ground signal of the first driving circuit DRV1 is SW1, and is connected to the first bootstrap capacitor CBoot1The other end of the first NMOS transistor MN1 is connected, and the output of the first NMOS transistor TG1 provides a gate drive signal for the first NMOS transistor MN1 in the power stage topology.
The input of the second level shift circuit LS2 is a PWM signal, and the output is the input of the second driving circuit DRV 2; the ground signal of the second driving circuit DRV2 is VOUTAnd a second bootstrap capacitor CBoot2The output of which is TG2, and provides a gate drive signal for the second NMOS transistor MN2 in the power stage topology.
The input of the third level shift circuit LS3 is NPWM signal, and the output is the input of the third driving circuit DRV 3; the ground signal of the third driving circuit DRV3 is SW2, and is connected to the third bootstrap capacitor CBoot3The other end of the first NMOS transistor is connected with a ground signal of the LDO, the output of the first NMOS transistor is BG, and a gate driving signal is provided for a third NMOS transistor MN3 in the power stage topology.
The input of the inverter INV1 is NPWM signal, and the output is bootstrap capacitor CBDAnd the other end of the same.
In this example, the hybrid two-way buck converter topology has 2 working states, where the second NMOS transistor MN2 is turned on, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned off to be state 1, at this time, the PWM signal is high, the NPWM signal is low, the inductive current rises, the inductive energy is stored, and the voltage of the first switching node SW1 is VOUTThe voltage of the second switch node SW2 is 2VOUT-VIN(ii) a The first NMOS transistor MN1 and the third NMOS transistor MN3 are in a state 2 when being turned on and the second NMOS transistor MN2 is turned off, at the moment, the PWM signal is low, the NPWM signal is high, the inductive current is reduced, and the inductance is releasedDischarging energy, the voltage of the first switch node SW1 is VINThe voltage of the second switch node SW2 is VOUT。
In this example, the ground signal FGND of the LDO module is a floating signal, connected to the second switch node SW2 of the power stage topology, and used as the ground signal of the third driving circuit DRV 3; the supply voltage input end VIN of the LDO is controlled by the switch tube MSN1 to be connected to the input voltage, and the output end OUT of the LDO is the supply signal BST3 of the third driving circuit DRV 3. Through the design of LDO, C can be ensuredBoot3The voltage at two ends is always maintained at VINSW2 at 2VOUT-VIN～VOUTSo BST3 is at 2VOUT～VIN+VOUTTo change between. The BST3 is connected to the BST2 through a switch tube MSP2, and the S2 signal controls the on and off of the BST. The BST2 is connected to the BST1 through a switch tube MSP1, and the signal of S1 controls the on and off of the BST. When the PWM is low, S2 is low, S1 is high, MSP2 is conducted, MSP1 is turned off, and then BST3 supplies power to BST 2; when the PWM is high, S2 is high, S1 is low, MSP2 is off, MSP1 is on, and BST2 powers BST 1.
FIG. 4 is a logic diagram of the present invention, wherein when the PWM is high and the hybrid converter operates in state 1, MN2 and MSP1 are turned on, MN1, MN3 and MSP2 are turned off, and SW1 is VOUTSW2 is 2VOUT-VINBST1 is VIN+VOUTBST2 is VIN+VOUTBST3 is 2VOUTTherefore TG2 is VIN+VOUTTG1 is VOUTBG 2VOUT-VINS1 is VOUTS2 is VIN+VOUT(ii) a When the PWM is low and the hybrid converter works in a state 2, MN1, MN3 and MSP2 are conducted, MN2 and MSP1 are turned off, and SW1 is VINSW2 is VOUTBST1 is 2VINBST2 is VIN+VOUTBST3 is VIN+VOUTTherefore TG2 is VOUTTG1 is 2VINBG is VIN+VOUTAnd S1 is 2VINS2 is VOUT。
The simulation analysis of the embodiment of the invention is carried out by virtuoso software, and the result is as follows.
FIG. 5 is a graph of efficiency curves of the present invention and a conventional buck at different loads and different voltage conversion ratios, wherein the simulation conditions are as follows: the input voltage is 4.2V, 3.6V and 2.7V respectively, the output voltage is 1.2V, the switching frequency is 2MHz, and the load current is 0.5A-5A. It can be seen that under the same simulation condition, the efficiency of the topology of the invention is greatly higher than that of the traditional buck converter, so that the invention can effectively realize the improvement of the energy conversion efficiency.
From the above detailed description, it can be seen that: the hybrid dual path topology combines a switched capacitor voltage converter and a switched inductor voltage converter with two parallel power supply paths that reduce inductor current and DCR losses. In addition, the flying capacitor bears part of the voltage drop, so the voltage stress of the power switch tube is also reduced. Due to the smaller voltage swing at the switching node, the switching losses and the inductor ripple are also reduced.
Claims (1)
1. A hybrid dual path buck converter includes a power stage topology and a bootstrap drive circuit module; the power stage topological structure comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a flying capacitor CFAn output capacitor COInductor L and load resistor RL；
The drain of the first NMOS transistor MN1 is connected to the input voltage, the gate is connected to the first driving signal, and the source of the first NMOS transistor MN1 is connected to the flying capacitor CFOne end of (a);
the drain of the second NMOS transistor MN2 is connected to the source of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 is connected to the second driving signal, and the source of the second NMOS transistor MN2 is connected to the output capacitor COAnd a load resistor RLOne end of (a);
the drain of the third NMOS transistor MN3 is connected to the source of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3 is connected to the third driving signal, and the source of the third NMOS transistor MN3 is connected to one end of the inductor L and the flying capacitor CFThe other end of (a);
the source electrode of the second NMOS transistor MN2, the drain electrode of the third NMOS transistor MN3 and the output capacitor COOne end of (A)Load resistance RLThe connection point of one end of the first switching element is the output end of the buck converter; the other end of the inductor L and the output capacitor COAnother terminal of (1), a load resistor RLThe other ends of the two are grounded;
the bootstrap drive circuit module comprises a first switch tube MSN1, a second switch tube MSP1, a third switch tube MSP2 and a first bootstrap capacitor CBoot1A second bootstrap capacitor CBoot2A third bootstrap capacitor CBoot3And a fourth self-lifting capacitor CBDThe driving circuit comprises a first level shift circuit LS1, a second level shift circuit LS2, a third level shift circuit LS3, a first driving circuit DRV1, a second driving circuit DRV2, a third driving circuit DRV3, a diode DB, an inverter INV1 and an LDO module;
the source of the first switch tube MSN1 is connected with the input voltage and the anode of the diode DB, the grid of the first switch tube MSN1 is connected with the cathode of the diode DB and the fourth self-lifting capacitor CBDThe drain of the first switch tube MSN1 is connected to the input end of the LDO;
fourth self-lifting capacitor CBDThe other end of the inverter INV is connected with the output end of the inverter INV1, and the input end of the inverter INV1 is connected with the pulse input signal;
the grid electrode of the second switch tube MSP1 is connected with a first external control signal, and the source electrode of the second switch tube MSP1 is connected with a first bootstrap capacitor CBoot1And a drain of the second switch transistor MSP1 is connected to the second bootstrap capacitor CBoot2And a power source terminal of the second drive circuit DRV 2;
the grid electrode of the third switch tube MSP2 is connected with a second external control signal, the drain electrode of the third switch tube MSP2 is connected with the output section of the LDO and the third bootstrap capacitor CBoot3And a power source terminal of the third drive circuit DRV 3;
the input end of the first level shift circuit LS1 is connected with a pulse input signal, and the output end of the first level shift circuit LS1 is connected with the input end of the first driving circuit DRV 1; the ground signal of the first driving circuit DRV1 is connected with the drain of the first NMOS transistor MN1 and the flying capacitor CFThe ground signal terminal of the first driving circuit DRV1 and a first bootstrap capacitor CBoot1Is connected to the other end of the first driving circuit DRV1The output end outputs a first driving signal;
the input end of the second level shift circuit LS2 is connected with the pulse input signal, and the output end of the second level shift circuit LS2 is connected with the input end of the second driving circuit DRV 2; the ground signal terminal of the second driving circuit DRV2 is connected with the output terminal of the buck converter, and the ground signal terminal of the second driving circuit DRV2 is connected with a second bootstrap capacitor CBoot2The other end of the second driving circuit DRV2, the output end of the ground signal end of the second driving circuit DRV2 outputs a second driving signal;
the input end of the third level shift circuit LS3 is connected with the pulse input signal, and the output end of the third level shift circuit LS3 is connected with the input end of the third driving circuit DRV 3; the ground signal of the third driving circuit DRV3 is connected with the drain of the third NMOS transistor MN3 and the flying capacitor CFA ground signal terminal of the third driving circuit DRV3 and a third bootstrap capacitor CBoot3And the other end of the third driving circuit DRV3 is connected to the ground signal end of the LDO module, and the output end of the third driving circuit DRV3 outputs a third driving signal.
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Cited By (7)
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| CN113746322A (en) * | 2021-09-27 | 2021-12-03 | 电子科技大学 | Mixed-mode high-efficiency boost converter |
| CN113783429A (en) * | 2021-09-27 | 2021-12-10 | 电子科技大学 | Hybrid DC-DC boost converter |
| CN113783428A (en) * | 2021-09-27 | 2021-12-10 | 电子科技大学 | Mixed-mode boost converter |
| CN113794374A (en) * | 2021-09-27 | 2021-12-14 | 电子科技大学 | Mixed-mode boost converter suitable for battery voltage supply |
| CN114172374A (en) * | 2021-12-20 | 2022-03-11 | 广东工业大学 | Cross flying capacitor hybrid boost-buck DC-DC converter based on double inductors |
| CN114785114A (en) * | 2022-05-26 | 2022-07-22 | 电子科技大学 | High-voltage transformation ratio mixed mode two-phase power converter |
| CN117439406A (en) * | 2023-10-23 | 2024-01-23 | 华南理工大学 | Three-current-path hybrid buck converter with high conversion ratio |
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| CN113746322B (en) * | 2021-09-27 | 2023-03-31 | 电子科技大学 | Mixed-mode high-efficiency boost converter |
| CN113783429A (en) * | 2021-09-27 | 2021-12-10 | 电子科技大学 | Hybrid DC-DC boost converter |
| CN113783428A (en) * | 2021-09-27 | 2021-12-10 | 电子科技大学 | Mixed-mode boost converter |
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| CN113783429B (en) * | 2021-09-27 | 2023-03-31 | 电子科技大学 | Hybrid DC-DC boost converter |
| CN113794374B (en) * | 2021-09-27 | 2023-03-31 | 电子科技大学 | Mixed-mode boost converter suitable for battery voltage supply |
| CN113746322A (en) * | 2021-09-27 | 2021-12-03 | 电子科技大学 | Mixed-mode high-efficiency boost converter |
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| CN114172374A (en) * | 2021-12-20 | 2022-03-11 | 广东工业大学 | Cross flying capacitor hybrid boost-buck DC-DC converter based on double inductors |
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| CN114785114A (en) * | 2022-05-26 | 2022-07-22 | 电子科技大学 | High-voltage transformation ratio mixed mode two-phase power converter |
| CN114785114B (en) * | 2022-05-26 | 2023-04-28 | 电子科技大学 | Mixed mode biphase power converter with high voltage transformation ratio |
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