CN113794374B - Mixed-mode boost converter suitable for battery voltage supply - Google Patents

Mixed-mode boost converter suitable for battery voltage supply Download PDF

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CN113794374B
CN113794374B CN202111138723.4A CN202111138723A CN113794374B CN 113794374 B CN113794374 B CN 113794374B CN 202111138723 A CN202111138723 A CN 202111138723A CN 113794374 B CN113794374 B CN 113794374B
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capacitor
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inverter
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CN113794374A (en
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甄少伟
赵冰清
熊海亮
谢泽亚
杨芮
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Dc-Dc Converters (AREA)

Abstract

The invention belongs to the field of integrated circuits and the technical field of switching power supplies, and particularly relates to a mixed-mode boost converter suitable for supplying voltage to a battery. The hybrid boost converter combines the switch capacitor voltage converter and the switch inductor voltage converter, reduces the voltage swing of a switch node and the average current of an inductor through the flying capacitor, thereby reducing the switching loss and the inductor DCR loss of a power switch tube, simultaneously increasing the duty ratio of a control signal, realizing the voltage conversion ratio more than 2, and being suitable for the application of portable equipment under high frequency.

Description

Mixed-mode boost converter suitable for battery voltage supply
Technical Field
The invention belongs to the field of integrated circuits and the technical field of switching power supplies, and particularly relates to a mixed-mode boost converter suitable for supplying voltage to a battery.
Background
Boost converters are used more and more widely as important components of power management modules. With the development of scientific technology and the generation of a large number of low-power-consumption and high-performance portable applications, the performance requirements for the boost converter are higher and higher, and especially the boost converter with high energy Conversion efficiency and high voltage Conversion Ratio (CR) becomes a key point of wide attention. A Conventional DC-DC Boost Converter (CBC) has a large switching stress of a power tube, and thus a large switching loss is generated during a switching operation, and thus it is difficult to achieve high energy conversion efficiency. In addition, conduction loss caused by Direct Current Resistance (DCR) is particularly significant in CBC, and particularly when the output Current is large, the DCR loss of the inductor becomes a main part of energy loss of the DC-DC converter, so that the energy conversion efficiency of the CBC is greatly reduced. This problem is particularly pronounced in portable devices with stringent requirements for power consumption, where large DCR losses also cause difficulties in heat dissipation.
On the other hand, in some applications requiring a high voltage conversion ratio, a larger control signal duty cycle is required. Generating an excessive control signal duty cycle is a significant challenge for the control signal generation circuit. Due to the limitation of the problems of time delay of a peripheral control circuit and a driving circuit and the like, the duty ratio of a large control signal is difficult to realize, so that the further improvement of the voltage conversion ratio is limited, and the application of CBC under high frequency is also limited. In order to realize the application under high-dropout voltage boosting and high frequency, a higher CR boost converter is needed to realize the requirement of reducing the duty ratio of a control signal under the condition of the same voltage conversion ratio as that of CBC, thereby reducing the complexity and the design difficulty of a control circuit and further saving the area cost and the labor cost of a chip.
Disclosure of Invention
The invention aims to provide a hybrid boost converter suitable for portable equipment and battery voltage supply, which can reduce the DCR loss of an inductor and the switching loss of a power switching tube, improve the energy conversion efficiency and realize a voltage conversion ratio more than 2.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a mixed mode boost converter suitable for battery voltage supply comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a flying capacitor C F An inductor L, a first output capacitor C O Load resistance R O Operational amplifier, PMOS switchA switch tube, a PMOS adjusting tube, a first resistor R1, a second resistor R2, a first bootstrap capacitor C Boot1 A second bootstrap capacitor C Boot2 Voltage source V REF The diode, the first driving module DRV1, the second driving module DRV2, the third driving module DRV3, the first potential translation module LS1, the second potential translation module LS2, the third potential translation module LS3, the first PMOS transistor MSP1, the second PMOS transistor MSP2, the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the first NAND gate 1, the second NAND gate 2, the first DELAY module DELAY1, the second DELAY module DELAY2, the third DELAY module DELAY3 and the fourth DELAY module DELAY4;
wherein, the source of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 and the flying capacitor C F The gate of the first NMOS transistor MN1 is connected to the first driving signal TG1 output by the first driving module DRV1, the drain of the first NMOS transistor MN1 is the output terminal of the boost converter and is connected to the output capacitor C O And a load resistance R O A first output capacitor C O And a load resistance R O The other ends of the two are grounded; the source of the second NMOS transistor MN2 is connected to the input voltage V IN The gate of the second NMOS transistor MN2 is connected to a second driving signal output by the second driving module DRV 2; the source of the third NMOS transistor MN3 is grounded, the gate is connected to the third driving signal output by the third driving module DRV3, and the drain of the third NMOS transistor MN3 is connected to the other end of the inductor L and the flying capacitor C F The other end of (a);
the inverting input terminal of the operational amplifier is connected to a voltage source V REF The non-inverting input end of the positive electrode of the operational amplifier is connected with one end of a first resistor R1 and one end of a second resistor R2, and the output of the operational amplifier is connected to the grid electrode of the PMOS adjusting tube; the source of the PMOS adjusting tube is connected with the cathode of the diode, the drain of the PMOS adjusting tube is connected with the other end of the first resistor R1 and the second bootstrap capacitor C Boot2 And a power supply terminal of the second driving module DRV 2; the other end of the second resistor R2 and a second bootstrap capacitor C Boot2 OfOne terminal and a voltage source V REF Negative poles of the two-way switch are connected with an input voltage V IN ；
The power supply terminal of the first driving module DRV1 is connected with the first bootstrap capacitor C Boot1 The ground end of the first driving module DRV1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first driving module DRV1 is connected with the output of the first potential translation module LS1, and the output of the first driving module DRV1 is connected to the grid electrode of the first NMOS transistor MN 1;
the power supply of the second driving module DRV2 is connected with the second bootstrap capacitor C Boot2 The ground terminal is connected to the input voltage V IN The input end of the second driving module DRV2 is connected to the output of the second level shifting module LS2, and the output of the second driving module DRV2 is connected to the gate of the second NMOS transistor MN 2;
the power supply terminal of the third driving module DRV3 is connected to the voltage V DR The ground terminal is grounded, wherein V DR Is the driving voltage of the switching tube when V IN When less than 5V, V DR ＝V IN (ii) a When V is IN When greater than 5V, V DR =5V; the input end of the third driving module DRV3 is connected to the output end of the second inverter INV2, and the output of the third driving module DRV3 is connected to the gate of the third NMOS transistor MN 3;
an input power supply end of the first level shift module LS1 is connected with V DR The input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the first potential translation module LS1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first potential translation module LS1 is connected with the output end of the seventh inverter INV7, and the output end of the first potential translation module LS1 is connected with the input end of the first driving module DRV 1;
the input power supply terminal of the second level shift module LS2 is connected with V DR The input ground terminal is grounded, the output power terminal is connected with the power terminal of the second driving module DRV1, and the output ground terminal of the second level shift module LS2 is connected with the input voltage V IN The input end of the second level shift module LS2 is connected to the output end of the second inverter, and the output end of the second level shift module LS2 is connected to the input end of the second driving module DRV 2;
an input power supply end of the third level shift module LS3 is connected with V DR And an input placeThe end of the third potential translation module LS3 is grounded, the output power end of the third potential translation module LS3 is connected with the source electrode of the first NMOS transistor MN1, the input end of the third potential translation module LS3 is connected with the output end of the third inverter INV3, and the output end of the third potential translation module LS3 is connected with the grid electrode of the first PMOS transistor MSP 1;
a first bootstrap capacitor C Boot1 The upper electrode plate is connected with a power supply end of the first driving module DRV1, and the lower electrode plate is connected with a source electrode of the first NMOS transistor MN 1;
second bootstrap capacitor C Boot2 The upper electrode plate is connected to the power supply terminal of the second driving module DRV1, the lower electrode plate and the input voltage V IN Connecting;
the source electrode of the PMOS switching tube is connected with the power supply end of the first driving module DRV1, the grid electrode of the PMOS switching tube is connected to the output of the third potential translation module LS3, and the drain electrode of the PMOS switching tube is connected with the power supply end of the second driving module DRV 1; the anode of the diode is connected with the source electrode of the first NMOS transistor MN1, and the cathode of the diode is connected with the source electrode of the second PMOS transistor MSP 2;
one input end of the first NAND gate NAND1 is connected with the PWM signal, the other input end of the first NAND gate NAND1 is connected with the output end of the first inverter INV1, the output end of the first NAND gate NAND1 is connected with the input end of the first DELAY module DELAY1, and the input end of the first inverter INV1 is connected with the output end of the seventh inverter INV 7; the output end of the first DELAY module DELAY1 is connected with one end of a first capacitor C1 and the input end of the second DELAY module DELAY2, and the other end of the first capacitor C1 is grounded; the output end of the second DELAY module DELAY2 is connected with one end of the second capacitor C2 and the input end of the second inverter INV2, and the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with one input end of the second NAND gate NAND2, the other input end of the second NAND gate NAND2 is connected with the output end of the fourth inverter INV4, and the input end of the fourth inverter INV4 is connected with the PWM signal; the output end of the second NAND gate NAND2 is connected with the input end of a fifth inverter INV5, the output end of the fifth inverter INV5 is connected with the input end of a third DELAY module DELAY3, the output end of the third DELAY module DELAY3 is connected with one end of a third capacitor C2 and the input end of a fourth DELAY module DELAY4, and the other end of the third capacitor C3 is grounded; the output end of the fourth DELAY module DELAY4 is connected to one end of the fourth capacitor C4 and the input end of the sixth inverter INV6, and the other end of the fourth capacitor C4 is grounded; an output of the sixth inverter INV6 is connected to an input of the seventh inverter INV 7.
The invention has the advantages that the hybrid boost converter is combined with the switch capacitor voltage converter and the switch inductance voltage converter through the flying capacitor C F The average current of the inductor and the voltage swing of a switch node are reduced, so that the loss of the inductor DCR and the switching loss of a power switch tube are reduced, the duty ratio of a control signal is increased, a high voltage conversion ratio is realized, and the high-voltage-conversion-ratio high-frequency-switching-ratio high-voltage-switching-ratio high-power-source switching device is suitable for application under high voltage conversion ratio and high frequency.
Drawings
FIG. 1 is a power stage topology for a hybrid boost converter in accordance with the present invention;
FIG. 2 is a circuit diagram of a hybrid boost converter power stage topology in accordance with the present invention;
FIG. 3 is a waveform of the operation of the power stage topology of the hybrid boost converter proposed by the present invention;
FIG. 4 is a circuit diagram of an embodiment of the present invention;
FIG. 5 is a timing logic diagram of an embodiment of the present invention;
FIG. 6 is a graph comparing efficiency curves of an embodiment of the present invention and a conventional boost converter.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the attached drawings:
for convenience of description, the hybrid boost converter of the present invention is divided into three parts, a power stage topology, a bootstrap driver circuit module, and a dead-zone generation circuit. The power stage topology comprises three power switching tubes S1, S2 and S3 and a flying capacitor C F An inductor L, an output capacitor C O And a load resistor R O As in fig. 1. The power switch tube can adopt an NMOS tube or a PMOS tube. Taking NMOS transistors as an example, the first NMOS transistor MN1 is a switch S1, the second NMOS transistor MN2 is a switch S2, and the third NMOS transistor MN3 is a switch S3, as shown in fig. 2. The source of the first NMOS transistor MN1 and the drain of the second NMOS transistor MN2And a flying capacitor C F Has a gate connected to the driving signal TG1 and a drain connected to the output capacitor C O And a load resistance R O . The source of the second NMOS transistor MN2 is connected to the input and to one end of the inductor L, and the gate is connected to the driving signal TG2. The source electrode of the third NMOS transistor MN3 is grounded, the grid electrode is connected with the driving signal BG1, and the drain electrode is connected with the other end of the inductor L and the capacitor C F And the other end of the same. Output capacitor C O And a load resistance R O The other ends of the two are all grounded.
The bootstrap driving circuit module, as shown in fig. 3, includes three driving modules DRV1, DRV2, DRV3, three Level Shift modules (Level Shift) LS1, LS2, LS3, two bootstrap capacitors C Boot1 、C Boot2 Switch PMOS pipe MSP1, PMOS adjusting pipe MSP2, diode D1, operational amplifier A1, feedback resistance R1, R2, voltage source V REF1 . The power supply terminal BST1 of the first driving module DRV1 is connected with a bootstrap capacitor C Boot1 The ground end is connected with the first switch node SW1, the input end is connected with the output of the first Level Shift module LS1, and the output is connected to the grid TG1 of the first NMOS transistor MN 1. The power supply terminal BST2 of the second driving module DRV2 is connected with the bootstrap capacitor C Boot2 Ground terminal connected to input voltage V IN The input end of the second Level Shift module LS2 is connected with the output of the second NMOS transistor MN2, and the output of the second Level Shift module LS2 is connected with the grid TG2 of the second NMOS transistor MN 2. The power supply terminal of the third driving module DRV3 is connected to the output voltage V of the LDO module DR Ground terminal is grounded, wherein V DR Is the driving voltage of the switching tube, when V IN When less than 5V, V DR ＝V IN (ii) a When V is IN When greater than 5V, V DR And =5V. The input end of the DRV3 is connected with the output signal PWM1 of the dead zone generating circuit module, and the output end of the DRV is connected to the grid BG1 of the third NMOS transistor MN3. V is connected to input power end of first Level Shift module LS1 DR The input ground end is grounded, the output power supply end is connected with the BST1, the output ground end is connected with the first switch node SW1, the input end is connected with an output signal NPWM1 of the dead zone generating circuit, and the output end is connected with the input end of the first driving module DRV 1. Input power supply end connection V of second Level Shift module LS2 DR The input ground terminal is grounded, the output power terminal is connected with BST2, and the output ground terminal is connected with an input voltage V IN The input end of the dead zone generating circuit is connected with the output signal PWM1 of the dead zone generating circuit, and the output end of the dead zone generating circuit is connected with the input end of the second driving module DRV 2. Input power supply end connection V of third Level Shift module LS3 DR The input ground end is grounded, the output power supply end is connected with the BST1, the output ground end is connected with the first switch node SW1, the input end is connected with the output signal PWM2 of the dead zone generating circuit, and the output end is connected with the first bootstrap capacitor C of the grid GP1 of the first PMOS tube MSP1 Boot1 The upper plate is connected with BST1, and the lower plate is connected with a first switch node SW1. A second bootstrap capacitor C Boot2 The upper plate is connected to BST2, the lower plate and the input voltage V IN Are connected. The source electrode of the first PMOS tube MSP1 is connected with BST1, the grid electrode GP1 is connected with the output of the third Level Shift module LS3, and the drain electrode is connected with BST2. The anode of the diode D1 is connected to the first switch node SW1, and the cathode is connected to the source of the second PMOS transistor MSP 2. The grid electrode of the second PMOS tube MSP2 is connected with the output end of the operational amplifier A1, and the drain electrode is connected with the BST2. The non-inverting input terminal of the operational amplifier A1 is connected with one end of the resistors R1 and R2, and the inverting input terminal is connected with the voltage source V REF1 The positive electrode of (1). The other end of the resistor R1 is connected to the BST2, and the other end of the resistor R2 is connected to the input voltage V IN . Voltage source V REF1 Negative pole of (2) is connected with input voltage V IN 。
The dead time generation circuit includes seven inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, two NAND gates NAND1 and NAND2, four DELAY modules DELAY1, DELAY2, DELAY3, DELAY4, and four capacitors C1, C2, C3, C4, as shown in fig. 4. The input of the first inverter INV1 is connected to the output of the seventh inverter INV7, and the output is connected to the input of the first NAND gate NAND 1. The input of the second inverter INV2 is connected to the output of the second DELAY module DELAY2, and is also connected to the capacitor C2, and the output is connected to the input of the third inverter INV3, and is used as the output signal PWM1. The input of the third inverter INV3 is connected to the output of the second inverter INV2, and the output is connected to the input of the second NAND gate NAND2, and serves as the output signal PWM2. The input end of the fourth inverter INV4 is connected to the input signal PWM _ IN, and the output end is connected to the other input end of the second NAND gate NAND 2. The input of the fifth inverter INV5 is connected to the output of the second NAND gate NAND2, and the output is connected to the input of the third DELAY module DELAY 3. An input end of the sixth inverter INV6 is connected to the output of the fourth DELAY module DELAY4 and the capacitor C4, and an output end thereof is connected to an input end of the seventh inverter INV7, and serves as the output signal NPWM2. An input end of the seventh inverter INV7 is connected to an output end of the sixth inverter INV6, and an output end is the output signal NPWM1. The input of the first DELAY module DELAY1 is connected to the output of the first NAND gate NAND1, and the output is connected to the input of the second DELAY module DELAY2 and the capacitor C1. An output of the second DELAY module DELAY2 is connected to an input terminal of the second inverter INV2 and one end of the capacitor C2. An input terminal of the third DELAY module DELAY3 is connected to an output terminal of the fifth inverter INV5, and an output terminal thereof is connected to an input terminal of the fourth DELAY module DELAY4 and the capacitor C3. The output of the fourth DELAY module DELAY4 is connected to the output end of the sixth inverter INV6 and the capacitor C4. The other ends of the capacitors C1, C2, C3 and C4 are all grounded.
FIG. 2 is a circuit diagram of a power stage topology of a hybrid boost converter according to the present invention, which includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, an inductor L, and a flying capacitor C F An output capacitor C O And a load resistor R O . The L current can not suddenly change by using the inductance of the energy storage element and the capacitance C F The characteristic that the voltage can not be suddenly changed realizes the boosting from the input to the output. From the characteristics of the capacitance, the flying capacitance C can be derived F The voltage at both ends is input voltage V IN The voltage conversion ratio of the boost converter can be obtained by voltage-second balance of the inductor
Figure BDA0003282989500000061
Where D is the control signal duty cycle. At duty cycle 0<D<At 1 time, there is CR>2。
The power stage topology provided by the invention has two working states, wherein in the state 1, the first NMOS tube MN1 is switched off, the second NMOS tube MN2 and the third NMOS tube MN3 are switched on, and the voltage of the switch node SW1 is the input voltage V IN The voltage of the switch node SW2 is 0, the current flows through the inductor L and the third NMOS tube MN3 from the input end and then is conducted to the ground, and meanwhile the current flows through the second NMOS tube MN2 and the flying capacitor C F And a third NMOS transistor MN3 to ground. Inductance in this stateL and a capacitor C F After parallel connection, the input voltage is charged at the same time, and the current of the inductor L is increased linearly at the moment. In the state 2, the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned off, the first NMOS transistor MN1 is turned on, and the voltage of the switch node SW1 is the output voltage V OUT The voltage of the switch node SW2 is the difference V between the output voltage and the input voltage OUT -V IN The current flows from the input through the inductor L and the flying capacitor C F And a first NMOS transistor MN1 to an output capacitor C O And a load resistance R O . In this state, the inductor L and the capacitor C F Discharging after series connection to output capacitor C O And a load resistance R O When power is supplied, the current of the inductor L is linearly decreased.
The flying capacitor C is known from the two working states of the power stage topology F The inductor L charges and discharges simultaneously, and the flying capacitor bears part of current in the process of discharging the load, so that the average current of the inductor is greatly reduced, the loss of the DCR is reduced, and the energy conversion efficiency is improved. In addition, the voltage swing of the switch nodes SW1 and SW2 is lower than that of CBC, so that the voltage stress of the power switch tube is correspondingly reduced, the switching loss of the power switch tube is reduced, and the energy conversion efficiency is further improved.
Fig. 3 is a waveform diagram illustrating the operation of the power stage topology of the hybrid boost converter according to the present invention. When the power stage topology operates in the state 1, the voltage of the first switch node SW1 is V IN The voltage of the second switch node SW2 is 0, and the voltage across the inductor L is V IN Inductor L current rises linearly, capacitor C F The current gradually decreases, and the output current I OUT Is 0. When the power stage topology operates in the state 2, the voltage of the first switch node SW1 is V OUT The voltage of the second switch node SW2 is V OUT -V IN The voltage across the inductor L is 2V IN -V OUT The current of the inductor L decreases linearly and the capacitance C decreases linearly F Current is equal to inductance current, and output current I OUT Equal to the inductor L current.
Fig. 4 is a circuit diagram of an embodiment of the present invention, including a power stage topology and a bootstrap driver circuit module. Wherein the power stage topology circuitThe circuit diagram is the circuit diagram shown in fig. 2, and includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, an inductor L, and a flying capacitor C F Output capacitor C O And a load resistor R O . The bootstrap drive circuit module comprises three drive modules DRV1, DRV2 and DRV3, three potential translation modules LS1, LS2 and LS3, and two bootstrap capacitors C Boot1 、C Boot2 Switch PMOS tube MSP1, PMOS adjusting tube MSP2, diode D1, operational amplifier A1, feedback resistors R1 and R1, and voltage source V REF1 . The dead time generation circuit comprises seven inverters INV1, INV2, INV3, INV4, INV5, INV6 and INV7, two NAND gates NAND1 and NAND2, four DELAY modules DELAY1, DELAY2, DELAY3 and DELAY4 and four capacitors C1, C2, C3 and C4.
Specifically, the dead zone generation circuit module delays the output signal PWM _ IN through two branches, and utilizes the first NAND gate NAND1 and the second NAND gate NAND2 to realize generation of dead zone time between the output signals PWM1 and NPWM1 and between the output signals PWM2 and NPWM2, thereby avoiding simultaneous conduction of the power switching tubes IN the power stage topology when the working states are switched.
Specifically, the bootstrap driving module has a second bootstrap capacitor C Boot2 The voltage on the second PMOS tube MSP2, an operational amplifier A1, resistors R1 and R2 and a voltage source V REF1 And the negative feedback loop is controlled, and when the first NMOS transistor MN1 is conducted, the first switch node SW1 is charged through the forward biased diode D1. Second bootstrap capacitor C Boot2 The voltage on the second NMOS transistor MN2 is used as a power supply of the second driving module DRV2 to drive the second NMOS transistor MN2, so that bootstrap driving of the second NMOS transistor MN2 is realized. A first bootstrap capacitor C Boot1 Controlled by a first PMOS transistor MSP1 and provided with a second bootstrap capacitor C Boot2 And charging, wherein the upper voltage of the first drive module is used as the power supply voltage of the first drive module DRV1 and drives the first NMOS transistor MN1, so as to realize bootstrap drive of the first NMOS transistor MN 1. The bootstrap drive circuit has two operating states that cooperate with the two operating states of the power stage topology.
When the input control signal PWM1 is high, the power stage topology and the bootstrap driving module both work in state 1. The first drive is performed at the moment because the first NMOS transistor MN1 is turned offThe module DRV1 does not work, the first PMOS tube MSP1 is conducted, so the second bootstrap capacitor C Boot2 Discharging, and taking the first PMOS tube MSP1 as a first bootstrap capacitor C Boot1 And charging and simultaneously supplying power to the second driving module DRV 2. In state 1 the voltage at the first switching node SW1 is equal to the input voltage V IN And the diode D1 is reversely biased to be cut off, so that the current on the second PMOS tube MSP2 is zero. At the same time, the input voltage V IN And supplying power to the third driving module DRV3 to drive the third NMOS transistor MN3.
When the input control signal PWM1 is at a low level, the power stage topology and the bootstrap driver module both operate in state 2. Because the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned off, the second driving module DRV2 and the third driving module DRV3 do not work at the moment, the first PMOS transistor MSP1 is turned off, and the first bootstrap capacitor C is turned on at the moment Boot1 And discharging to serve as a power supply of the first driving module DRV 1. In state 2 the voltage at the first switching node SW1 is V OUT The diode D1 is conducted in forward bias, the first switch node SW1 passes through the diode D1, the second PMOS transistor MSP2, the operational amplifier A1, the resistors R1 and R2 and the voltage source V REF1 The negative feedback loop controls the second bootstrap capacitor C Boot2 And (6) charging. Voltage source V REF1 Should be of a value of
Figure BDA0003282989500000081
A negative feedback loop connects a second bootstrap capacitor C Boot2 The voltage at both ends is stabilized at V DR As the supply voltage of the second driving module DRV2, and a first bootstrap capacitor C Boot1 The charging voltage of (1).
FIG. 5 is a sequential logic diagram of an embodiment of the present invention. When the PWM1 is at a high level, the hybrid boost converter operates in the state 1, at this time, the second NMOS transistor MN2, the third NMOS transistor MN3, and the first PMOS transistor MSP1 are turned on, and the first NMOS transistor MN1 and the diode D1 are turned off. In this state, the voltage at the first switch node SW1 is V IN The voltage of the second switch node SW2 is 0, and the voltage of BST1 is V IN +V DR BST2 voltage is V IN +V DR TG1 has a voltage of V IN TG2 at BST2 and BG1 at V DR GP1 has a voltage V IN . When the PWM1 is at a low level, the hybrid boost converter operates in the state 2, at this time, the second NMOS transistor MN2, the third NMOS transistor MN3, and the first PMOS transistor MSP1 are turned off, and the first NMOS transistor MN1, the diode D1, and the second PMOS transistor MSP2 are turned on. In this state, the voltage at the first switch node SW1 is V OUT The voltage of the second switch node SW2 is V OUT -V IN At this time, the voltage of BST1 is V OUT +V DR BST2 voltage is V IN +V DR The voltage of TG1 is BST1, and the voltage of TG2 is V IN BG1 has a voltage of 0 and GP1 has a voltage of BST1.
From the above detailed description, it can be seen that: the hybrid boost converter combines a switched capacitor converter and a switched inductor converter with a fly capacitor C F The voltage swing of the switch node and the average current of the inductor are reduced, so that the switching loss of the power switch tube and the DCR loss of the inductor are reduced, and the energy conversion efficiency is improved. The efficiency comparison between the hybrid boost converter proposed by the present invention and the conventional DC-DC boost converter is shown in fig. 6. Within the battery voltage input range, the efficiency of the hybrid boost converter is obviously improved compared with the efficiency of a CBC converter, and the efficiency is greatly improved when the hybrid boost converter is in heavy load. Meanwhile, the duty ratio of the control signal is increased by the hybrid converter, the voltage conversion ratio larger than 2 can be realized, and the hybrid converter is suitable for portable equipment and high-frequency application.

Claims (1)

1. A mixed mode boost converter suitable for battery voltage supply is characterized by comprising a first NMOS (N-channel metal oxide semiconductor) tube MN1, a second NMOS tube MN2, a third NMOS tube MN3 and a flying capacitor C F An inductor L, a first output capacitor C O And a load resistor R O An operational amplifier, a PMOS switch tube, a PMOS adjusting tube, a first resistor R1, a second resistor R2, a first bootstrap capacitor C Boot1 A second bootstrap capacitor C Boot2 Voltage source V REF A diode, a first driving module DRV1, a second driving module DRV2, a third driving module DRV3, a first level shift module LS1 a second potential translation module LS2, a third potential translation module LS3, a first PMOS transistor MSP1, a second PMOS transistor MSP2,The DELAY circuit comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NAND gate NAND1, a second NAND gate NAND2, a first DELAY module DELAY1, a second DELAY module DELAY2, a third DELAY module DELAY3 and a fourth DELAY module DELAY4;
wherein, the source of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 and the flying capacitor C F The gate of the first NMOS transistor MN1 is connected to the first driving signal TG1 output by the first driving module DRV1, the drain of the first NMOS transistor MN1 is the output terminal of the boost converter and is connected to the output capacitor C O And a load resistance R O A first output capacitor C O And a load resistance R O The other ends of the two are grounded; the source of the second NMOS transistor MN2 is connected to the input voltage V IN The gate of the second NMOS transistor MN2 is connected to a second driving signal output by the second driving module DRV 2; the source electrode of the third NMOS transistor MN3 is grounded, the gate electrode is connected to the third driving signal output by the third driving module DRV3, and the drain electrode of the third NMOS transistor MN3 is connected to the other end of the inductor L and the flying capacitor C F The other end of (a);
the inverting input terminal of the operational amplifier is connected to a voltage source V REF The non-inverting input end of the positive electrode of the operational amplifier is connected with one end of a first resistor R1 and one end of a second resistor R2, and the output of the operational amplifier is connected to the grid electrode of the PMOS adjusting tube; the source of the PMOS adjusting tube is connected with the cathode of the diode, the drain of the PMOS adjusting tube is connected with the other end of the first resistor R1 and the second bootstrap capacitor C Boot2 And a power supply terminal of the second driving module DRV 2; the other end of the second resistor R2 and a second bootstrap capacitor C Boot2 And the other end of (V) and a voltage source V REF Negative poles of the two-phase current transformer are connected with an input voltage V IN ；
The power supply terminal of the first driving module DRV1 is connected with the first bootstrap capacitor C Boot1 The ground end of the first driving module DRV1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first driving module DRV1 is connected with the output of the first potential translation module LS1, and the output of the first driving module DRV1 is connected to the grid electrode of the first NMOS transistor MN 1;
the power supply of the second driving module DRV2 is connected with the second bootstrap capacitor C Boot2 The ground terminal is connected to the input voltage V IN The input end of the second driving module DRV2 is connected to the output of the second level shifting module LS2, and the output of the second driving module DRV2 is connected to the gate of the second NMOS transistor MN 2;
the power supply terminal of the third driving module DRV3 is connected to the voltage V DR The ground terminal is grounded, wherein V DR Is the driving voltage of the switching tube, when V IN When less than 5V, V DR ＝V IN (ii) a When V is IN When greater than 5V, V DR =5V; the input end of the third driving module DRV3 is connected to the output end of the second inverter INV2, and the output of the third driving module DRV3 is connected to the gate of the third NMOS transistor MN 3;
the input power supply terminal of the first level shift module LS1 is connected to V DR The input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the first potential translation module LS1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first potential translation module LS1 is connected with the output end of the seventh inverter INV7, and the output end of the first potential translation module LS1 is connected with the input end of the first driving module DRV 1;
the input power supply terminal of the second level shift module LS2 is connected to V DR The input ground terminal is grounded, the output power terminal is connected with the power terminal of the second driving module DRV1, and the output ground terminal of the second level shift module LS2 is connected with the input voltage V IN The input end of the second level shift module LS2 is connected to the output end of the second inverter, and the output end of the second level shift module LS2 is connected to the input end of the second driving module DRV 2;
the input power supply terminal of the third level shift module LS3 is connected to V DR The input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the third potential translation module LS3 is connected with the source electrode of the first NMOS transistor MN1, the input end of the third potential translation module LS3 is connected with the output end of the third inverter INV3, and the output end of the third potential translation module LS3 is connected with the grid electrode of the first PMOS transistor MSP 1;
a first bootstrap capacitor C Boot1 The upper polar plate is connected with a first driverThe lower electrode plate of the power supply end of the module DRV1 is connected with the source electrode of the first NMOS tube MN 1;
second bootstrap capacitor C Boot2 The upper electrode plate is connected to the power supply terminal of the second driving module DRV1, the lower electrode plate and the input voltage V IN Connecting;
the source electrode of the PMOS switching tube is connected with the power supply end of the first driving module DRV1, the grid electrode of the PMOS switching tube is connected to the output of the third potential translation module LS3, and the drain electrode of the PMOS switching tube is connected with the power supply end of the second driving module DRV 1;
the anode of the diode is connected with the source electrode of a first NMOS transistor MN1, and the cathode of the diode is connected with the source electrode of a second PMOS transistor MSP 2;
one input end of the first NAND gate NAND1 is connected with the PWM signal, the other input end of the first NAND gate NAND1 is connected with the output end of the first inverter INV1, the output end of the first NAND gate NAND1 is connected with the input end of the first DELAY module DELAY1, and the input end of the first inverter INV1 is connected with the output end of the seventh inverter INV 7; the output end of the first DELAY module DELAY1 is connected with one end of a first capacitor C1 and the input end of the second DELAY module DELAY2, and the other end of the first capacitor C1 is grounded; the output end of the second DELAY module DELAY2 is connected with one end of a second capacitor C2 and the input end of the second inverter INV2, and the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with one input end of the second NAND gate NAND2, the other input end of the second NAND gate NAND2 is connected with the output end of the fourth inverter INV4, and the input end of the fourth inverter INV4 is connected with the PWM signal; the output end of the second NAND gate NAND2 is connected with the input end of a fifth inverter INV5, the output end of the fifth inverter INV5 is connected with the input end of a third DELAY module DELAY3, the output end of the third DELAY module DELAY3 is connected with one end of a third capacitor C2 and the input end of a fourth DELAY module DELAY4, and the other end of the third capacitor C3 is grounded; the output end of the fourth DELAY module DELAY4 is connected to one end of the fourth capacitor C4 and the input end of the sixth inverter INV6, and the other end of the fourth capacitor C4 is grounded; an output of the sixth inverter INV6 is connected to an input of the seventh inverter INV 7.
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