CN113794374B - Mixed-mode boost converter suitable for battery voltage supply - Google Patents

Mixed-mode boost converter suitable for battery voltage supply Download PDF

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CN113794374B
CN113794374B CN202111138723.4A CN202111138723A CN113794374B CN 113794374 B CN113794374 B CN 113794374B CN 202111138723 A CN202111138723 A CN 202111138723A CN 113794374 B CN113794374 B CN 113794374B
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CN113794374A (en
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甄少伟
赵冰清
熊海亮
谢泽亚
杨芮
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

本发明属于集成电路领域与开关电源技术领域，具体涉及一种适用于电池供压的混合模式升压变换器。本发明的混合升压变换器结合开关电容电压变换器以及开关电感电压变换器，通过飞电容降低开关节点的电压摆幅以及电感平均电流，从而减小了功率开关管的开关损耗和电感DCR损耗，并同时增大了控制信号的占空比，实现大于2的电压转换比，适用于便携式设备高频下的应用。

Figure 202111138723

The invention belongs to the field of integrated circuits and switching power supply technology, and in particular relates to a mixed-mode boost converter suitable for battery voltage supply. The hybrid boost converter of the present invention combines the switched capacitor voltage converter and the switched inductor voltage converter, and reduces the voltage swing of the switch node and the average current of the inductor through the flying capacitor, thereby reducing the switching loss of the power switch tube and the DCR loss of the inductor , and at the same time increase the duty cycle of the control signal to achieve a voltage conversion ratio greater than 2, which is suitable for applications at high frequencies in portable devices.

Figure 202111138723

Description

一种适用于电池供压的混合模式升压变换器A Mixed-Mode Boost Converter for Battery Supply

技术领域technical field

本发明属于集成电路领域与开关电源技术领域，具体涉及一种适用于电池供压的混合模式升压变换器。The invention belongs to the field of integrated circuits and switching power supply technology, and in particular relates to a mixed-mode boost converter suitable for battery voltage supply.

背景技术Background technique

升压变换器作为电源管理模块的重要组成部分，有着越来越广泛的应用。随着科学技术的发展和大量低功耗、高性能便携式应用的产生，对于升压变换器的性能要求也越来越高，尤其是高能量转换效率、高电压转换比(Conversion Rate，CR)的升压变换器成为广泛关注的重点。传统的DC-DC升压变换器(Conventional Boost Converter，CBC)的功率管开关应力较大，故而在开关动作时产生较大的开关损耗，因此难以实现高的能量转换效率。另外，由电感直流电阻(Direct Current Resistance，DCR)引起的导通损耗在CBC中尤其显著，特别是在输出电流较大的情况下，电感的DCR损耗成为DC-DC变换器能量损耗的主要部分，使得CBC的能量转换效率大幅降低。该问题在对功耗要求严格的便携式设备中尤其显著，较大的DCR损耗同时造成了散热困难的问题。As an important part of the power management module, the boost converter has been widely used. With the development of science and technology and the emergence of a large number of low-power, high-performance portable applications, the performance requirements for boost converters are getting higher and higher, especially high energy conversion efficiency and high voltage conversion ratio (Conversion Rate, CR) The boost converter has become the focus of widespread attention. The traditional DC-DC boost converter (Conventional Boost Converter, CBC) has a large switching stress of the power tube, so a large switching loss is generated during the switching operation, so it is difficult to achieve high energy conversion efficiency. In addition, the conduction loss caused by the inductor DC resistance (Direct Current Resistance, DCR) is particularly significant in CBC, especially in the case of high output current, the DCR loss of the inductor becomes the main part of the energy loss of the DC-DC converter , so that the energy conversion efficiency of CBC is greatly reduced. This problem is especially significant in portable devices that have strict requirements on power consumption, and the large DCR loss also causes difficulty in heat dissipation.

另一方面，在一些需要高的电压转换比的应用中，需要较大的控制信号占空比。但是产生过大的控制信号占空比对于控制信号产生电路来说是个巨大的挑战。由于外围控制电路、驱动电路延时等问题的限制，大的控制信号占空比难以实现，因而限制了电压转换比的进一步提高，同时也限制了CBC在高频下的应用。为了实现在高压差升压以及高频下的应用，需要更高CR的升压变换器，以实现在与CBC相同的电压转换比的情况下降低对控制信号的占空比的要求，从而降低控制电路的复杂程度和设计难度，进而节省芯片的面积成本和人力成本。On the other hand, in some applications that require a high voltage conversion ratio, a larger duty cycle of the control signal is required. However, it is a huge challenge for the control signal generation circuit to generate an excessively large control signal duty cycle. Due to the limitations of the peripheral control circuit and the delay of the drive circuit, it is difficult to achieve a large duty cycle of the control signal, which limits the further improvement of the voltage conversion ratio and also limits the application of CBC at high frequencies. In order to realize the application of high-voltage dropout boost and high frequency, a higher CR boost converter is required to achieve the same voltage conversion ratio as CBC to reduce the duty cycle requirements of the control signal, thereby reducing Control the complexity and design difficulty of the circuit, thereby saving the area cost and labor cost of the chip.

发明内容Contents of the invention

本发明的目的在于，提出一种适用于便携式设备、电池供压的混合升压变换器，该变换器能够减小电感的DCR损耗以及功率开关管的开关损耗，提高能量转换效率，并实现大于2的电压转换比。The purpose of the present invention is to propose a hybrid boost converter suitable for portable equipment and battery supply, which can reduce the DCR loss of the inductor and the switching loss of the power switch tube, improve the energy conversion efficiency, and achieve greater than 2 voltage conversion ratio.

为实现上述目的，本发明的技术方案为：To achieve the above object, the technical solution of the present invention is:

一种适用于电池供压的混合模式升压变换器，包括第一NMOS管MN1、第二NMOS管MN2为、第三NMOS管MN3、飞电容CF、电感L、第一输出电容CO、负载电阻RO、运算放大器、PMOS开关管、PMOS调整管、第一电阻R1、第二电阻R2、第一自举电容CBoot1、第二自举电容CBoot2、电压源VREF、二极管、第一驱动模块DRV1、第二驱动模块DRV2、第三驱动模块DRV3、第一电位平移模块LS1、第二电位平移模块LS2、第三电位平移模块LS3、第一PMOS管MSP1、第二PMOS管MSP2、第一反相器INV1、第二反相器INV2、第三反相器INV3、第四反相器INV4、第五反相器INV5、第六反相器INV6、第七反相器INV7、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第一与非门NAND1、第二与非门NAND2、第一延时模块DELAY1、第二延时模块DELAY2、第三延时模块DELAY3和第四延时模块DELAY4；A mixed-mode boost converter suitable for battery supply voltage, comprising a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a flying capacitor C F , an inductor L, a first output capacitor C O , load resistor R O , operational amplifier, PMOS switch tube, PMOS regulator tube, first resistor R1, second resistor R2, first bootstrap capacitor C Boot1 , second bootstrap capacitor C Boot2 , voltage source V REF , diode, second A drive module DRV1, a second drive module DRV2, a third drive module DRV3, a first potential shift module LS1, a second potential shift module LS2, a third potential shift module LS3, a first PMOS transistor MSP1, a second PMOS transistor MSP2, The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, the A capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NAND gate NAND1, a second NAND gate NAND2, a first delay module DELAY1, a second delay module DELAY2, a third delay Time module DELAY3 and the 4th delay module DELAY4;

其中，第一NMOS管MN1的源极与第二NMOS管MN2的漏极以及飞电容CF的一端相连，第一NMOS管MN1的栅极连接第一驱动模块DRV1输出的第一驱动信号TG1，第一NMOS管MN1的漏极为升压变换器输出端，并连接输出电容CO与负载电阻RO，第一输出电容CO和负载电阻RO的另一端均接地；第二NMOS管MN2的源极连接至输入电压VIN，同时与电感L的一端相连，第二NMOS管MN2的栅极接第二驱动模块DRV2输出的第二驱动信号；第三NMOS管MN3的源极接地，栅极连接第三驱动模块DRV3输出的第三驱动信号，第三NMOS管MN3的漏极连接至电感L的另一端以及飞电容CF的另一端；Wherein, the source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2 and one end of the flying capacitor CF , and the gate of the first NMOS transistor MN1 is connected to the first driving signal TG1 output by the first driving module DRV1, The drain of the first NMOS transistor MN1 is the output terminal of the boost converter, and is connected to the output capacitor C O and the load resistor R O , and the other ends of the first output capacitor C O and the load resistor R O are grounded; the drain of the second NMOS transistor MN2 The source is connected to the input voltage V IN and connected to one end of the inductor L at the same time, the gate of the second NMOS transistor MN2 is connected to the second driving signal output by the second driving module DRV2; the source of the third NMOS transistor MN3 is grounded, and the gate Connect the third driving signal output by the third driving module DRV3, the drain of the third NMOS transistor MN3 is connected to the other end of the inductor L and the other end of the flying capacitor CF ;

运算放大器的反相输入端连接至电压源VREF的正极，同相输入端与第一电阻R1、第二电阻R2的一端相连，运算放大器的输出接至PMOS调整管的栅极；PMOS调整管的源极接二极管的负极，其漏极与第一电阻R1的另一端、第二自举电容CBoot2的一端以及第二驱动模块DRV2的电源端相连；第二电阻R2的另一端、第二自举电容CBoot2的的另一端以及电压源VREF的负极均接输入电压VIN；The inverting input terminal of the operational amplifier is connected to the positive pole of the voltage source V REF , the non-inverting input terminal is connected to one end of the first resistor R1 and the second resistor R2, and the output of the operational amplifier is connected to the grid of the PMOS pass transistor; the PMOS pass transistor The source is connected to the cathode of the diode, and its drain is connected to the other end of the first resistor R1, one end of the second bootstrap capacitor C Boot2 and the power supply end of the second drive module DRV2; the other end of the second resistor R2, the second self The other end of the lifting capacitor C Boot2 and the negative pole of the voltage source V REF are both connected to the input voltage V IN ;

第一驱动模块DRV1的电源端连接第一自举电容CBoot1、地端连接第一NMOS管MN1源极，第一驱动模块DRV1的输入端与第一电位平移模块LS1的输出相连，第一驱动模块DRV1的输出接至第一NMOS管MN1的栅极；The power terminal of the first drive module DRV1 is connected to the first bootstrap capacitor C Boot1 , the ground terminal is connected to the source of the first NMOS transistor MN1, the input terminal of the first drive module DRV1 is connected to the output of the first potential shifting module LS1, and the first drive The output of the module DRV1 is connected to the gate of the first NMOS transistor MN1;

第二驱动模块DRV2的电源端接第二自举电容CBoot2、地端连接至输入电压VIN，第二驱动模块DRV2的输入端连接第二电位平移模块LS2的输出，第二驱动模块DRV2的输出接至第二NMOS管MN2的栅极；The power supply terminal of the second driving module DRV2 is connected to the second bootstrap capacitor C Boot2 , the ground terminal is connected to the input voltage V IN , the input terminal of the second driving module DRV2 is connected to the output of the second potential shifting module LS2 , and the The output is connected to the gate of the second NMOS transistor MN2;

第三驱动模块DRV3的电源端连接至电压VDR、地端接地，其中VDR为开关管的驱动电压，当VIN小于5V时，VDR＝VIN；当VIN大于5V时，VDR＝5V；第三驱动模块DRV3的输入端接第二反相器INV2的输出端，第三驱动模块DRV3的输出连接至第三NMOS管MN3的栅极；The power terminal of the third drive module DRV3 is connected to the voltage V DR , and the ground terminal is grounded, wherein V DR is the driving voltage of the switch tube. When V IN is less than 5V, V DR =V IN ; when V IN is greater than 5V, V DR =5V; the input terminal of the third driving module DRV3 is connected to the output terminal of the second inverter INV2, and the output of the third driving module DRV3 is connected to the gate of the third NMOS transistor MN3;

第一电位平移模块LS1的输入电源端连接VDR、输入地端接地、输出电源端连接第一驱动模块DRV1的电源端，第一电位平移模块LS1的输出地端连接第一NMOS管MN1源极，第一电位平移模块LS1的输入端接第七反相器INV7的输出端，第一电位平移模块LS1的输出端连接至第一驱动模块DRV1的输入端；The input power terminal of the first potential shift module LS1 is connected to VDR , the input ground terminal is grounded, the output power terminal is connected to the power terminal of the first driving module DRV1, and the output ground terminal of the first potential shift module LS1 is connected to the source of the first NMOS transistor MN1 , the input terminal of the first potential shifting module LS1 is connected to the output terminal of the seventh inverter INV7, and the output terminal of the first potential shifting module LS1 is connected to the input terminal of the first driving module DRV1;

第二电位平移模块LS2的输入电源端连接VDR、输入地端接地、输出电源端连接第二驱动模块DRV1的电源端，第二电位平移模块LS2的输出地端连接输入电压VIN，第二电位平移模块LS2的输入端接第二反相器的输出端，第二电位平移模块LS2的输出端连接至第二驱动模块DRV2的输入端；The input power terminal of the second potential translation module LS2 is connected to V DR , the input ground terminal is grounded, the output power terminal is connected to the power terminal of the second driving module DRV1, the output ground terminal of the second potential translation module LS2 is connected to the input voltage V IN , and the second The input terminal of the potential shift module LS2 is connected to the output terminal of the second inverter, and the output terminal of the second potential shift module LS2 is connected to the input terminal of the second driving module DRV2;

第三电位平移模块LS3的输入电源端连接VDR、输入地端接地、输出电源端连接第一驱动模块DRV1的电源端，第三电位平移模块LS3的输出地端连接第一NMOS管MN1源极，第三电位平移模块LS3的输入端接第三反相器INV3的输出端，第三电位平移模块LS3的输出端连接至第一PMOS管MSP1的栅极；The input power terminal of the third potential shift module LS3 is connected to VDR , the input ground terminal is grounded, the output power terminal is connected to the power supply terminal of the first drive module DRV1, and the output ground terminal of the third potential shift module LS3 is connected to the source of the first NMOS transistor MN1 , the input terminal of the third potential translation module LS3 is connected to the output terminal of the third inverter INV3, and the output terminal of the third potential translation module LS3 is connected to the gate of the first PMOS transistor MSP1;

第一自举电容CBoot1上极板连接第一驱动模块DRV1的电源端，下极板连接第一NMOS管MN1源极；The upper plate of the first bootstrap capacitor C Boot1 is connected to the power supply terminal of the first drive module DRV1, and the lower plate is connected to the source of the first NMOS transistor MN1;

第二自举电容CBoot2上极板连接至第二驱动模块DRV1的电源端，下极板与输入电压VIN相连；The upper plate of the second bootstrap capacitor C Boot2 is connected to the power supply terminal of the second drive module DRV1, and the lower plate is connected to the input voltage V IN ;

PMOS开关管的源极与第一驱动模块DRV1的电源端相连，PMOS开关管的栅极连接至第三电位平移模块LS3的输出，PMOS开关管的漏极连接第二驱动模块DRV1的电源端；二极管的到阳极连接第一NMOS管MN1源极，阴极连接第二PMOS管MSP2的源极；The source of the PMOS switch tube is connected to the power supply terminal of the first drive module DRV1, the gate of the PMOS switch tube is connected to the output of the third potential shifting module LS3, and the drain of the PMOS switch tube is connected to the power supply terminal of the second drive module DRV1; The anode of the diode is connected to the source of the first NMOS transistor MN1, and the cathode is connected to the source of the second PMOS transistor MSP2;

第一与非门NAND1的一个输入端接PWM信号，其另一个输入端接第一反相器INV1的输出端，第一与非门NAND1的输出端接第一延时模块DELAY1的输入端，第一反相器INV1的输入端接第七反相器INV7的输出端；第一延时模块DELAY1的输出端接第一电容C1的一端和第二延时模块DELAY2的输入端，第一电容C1的另一端接地；第二延时模块DELAY2的输出端接第二电容C2的一端和第二反相器INV2的输入端，第二电容C2的另一端接地；第二反相器INV2的输出端接第三反相器INV3的输入端，第三反相器INV3的输出端接第二与非门NAND2的一个输入端，第二与非门NAND2的另一个输入端接第四反相器INV4的输出端，第四反相器INV4的输入端接PWM信号；第二与非门NAND2的输出端接第五反相器INV5的输入端，第五反相器INV5的输出端接第三延时模块DELAY3的输入端，第三延时模块DELAY3的输出端接第三电容C2的一端和第四延时模块DELAY4的输入端，第三电容C3的另一端接地；第四延时模块DELAY4的输出端接第四电容C4的一端和第六反相器INV6的输入端，第四电容C4的另一端接地；第六反相器INV6的输出接第七反相器INV7的输入端。One input terminal of the first NAND gate NAND1 is connected to the PWM signal, the other input terminal thereof is connected to the output terminal of the first inverter INV1, the output terminal of the first NAND gate NAND1 is connected to the input terminal of the first delay module DELAY1, The input terminal of the first inverter INV1 is connected to the output terminal of the seventh inverter INV7; the output terminal of the first delay module DELAY1 is connected to one end of the first capacitor C1 and the input terminal of the second delay module DELAY2, the first capacitor The other end of C1 is grounded; the output terminal of the second delay module DELAY2 is connected to one end of the second capacitor C2 and the input end of the second inverter INV2, and the other end of the second capacitor C2 is grounded; the output of the second inverter INV2 The terminal is connected to the input terminal of the third inverter INV3, the output terminal of the third inverter INV3 is connected to one input terminal of the second NAND gate NAND2, and the other input terminal of the second NAND gate NAND2 is connected to the fourth inverter The output terminal of INV4, the input terminal of the fourth inverter INV4 is connected to the PWM signal; the output terminal of the second NAND gate NAND2 is connected to the input terminal of the fifth inverter INV5, and the output terminal of the fifth inverter INV5 is connected to the third The input terminal of the delay module DELAY3, the output terminal of the third delay module DELAY3 is connected to one end of the third capacitor C2 and the input terminal of the fourth delay module DELAY4, and the other end of the third capacitor C3 is grounded; the fourth delay module DELAY4 The output terminal of the fourth capacitor C4 is connected to the input terminal of the sixth inverter INV6, and the other end of the fourth capacitor C4 is grounded; the output of the sixth inverter INV6 is connected to the input terminal of the seventh inverter INV7.

本发明的有益效果为，混合升压变换器结合开关电容电压变换器以及开关电感电压变换器，通过飞电容CF降低电感平均电流以及开关节点的电压摆幅，从而减小了电感DCR损耗以及功率开关管的开关损耗，并同时增大了控制信号的占空比，实现高的电压转换比，适用于高变压比以及高频下的应用。The beneficial effect of the present invention is that the hybrid boost converter combines the switched capacitor voltage converter and the switched inductor voltage converter, and reduces the average current of the inductor and the voltage swing of the switch node through the flying capacitor CF , thereby reducing the DCR loss of the inductor and The switching loss of the power switch tube, and at the same time increase the duty cycle of the control signal to achieve a high voltage conversion ratio, which is suitable for applications with high transformation ratio and high frequency.

附图说明Description of drawings

图1为本发明提出的混合升压变换器的功率级拓扑；Fig. 1 is the power stage topology of the hybrid boost converter proposed by the present invention;

图2为本发明提出的混合升压变换器功率级拓扑的电路图；Fig. 2 is the circuit diagram of the hybrid boost converter power stage topology that the present invention proposes;

图3为本发明提出的混合升压变换器功率级拓扑的工作波形图；Fig. 3 is the working waveform diagram of the power stage topology of the hybrid boost converter proposed by the present invention;

图4为本发明实施例的电路图；Fig. 4 is the circuit diagram of the embodiment of the present invention;

图5为本发明实施例的时序逻辑图；FIG. 5 is a timing logic diagram of an embodiment of the present invention;

图6为本发明实施例与传统升压变换器效率曲线的对比图。Fig. 6 is a comparison chart of the efficiency curves of the embodiment of the present invention and the conventional boost converter.

具体实施方式Detailed ways

下面结合附图，对本发明技术方案进行详细描述：Below in conjunction with accompanying drawing, technical solution of the present invention is described in detail:

为便于描述，将本发明的混合升压变换器分为功率级拓扑、自举驱动电路模块以及死区产生电路三部分。其中，功率级拓扑包括三个功率开关管S1、S2以及S3、一个飞电容CF、一个电感L、一个输出电容CO和一个负载电阻RO，如图1。功率开关管可以采用NMOS管或PMOS管。以NMOS管为例，第一NMOS管MN1为开关S1，第二NMOS管MN2为开关S2，第三NMOS管MN3为开关S3，如图2。第一NMOS管MN1的源极与第二NMOS管MN2的漏极以及飞电容CF的一端相连，栅极连接驱动信号TG1，漏极连接至输出电容CO与负载电阻RO。第二NMOS管MN2的源极连接至输入，同时与电感L的一端相连，栅极接驱动信号TG2。第三NMOS管MN3的源极接地，栅极连接驱动信号BG1，漏极连接至电感L的另一端以及电容CF的另一端。输出电容CO与负载电阻RO的另一端均接地。For ease of description, the hybrid boost converter of the present invention is divided into three parts: power stage topology, bootstrap drive circuit module and dead zone generation circuit. Wherein, the power stage topology includes three power switch tubes S1, S2 and S3, a flying capacitor C F , an inductor L, an output capacitor C O and a load resistor R O , as shown in FIG. 1 . The power switch tube can be an NMOS tube or a PMOS tube. Taking NMOS transistors as an example, the first NMOS transistor MN1 is a switch S1 , the second NMOS transistor MN2 is a switch S2 , and the third NMOS transistor MN3 is a switch S3 , as shown in FIG. 2 . The source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2 and one end of the flying capacitor C F , the gate is connected to the driving signal TG1 , and the drain is connected to the output capacitor C O and the load resistor R O . The source of the second NMOS transistor MN2 is connected to the input and at the same time connected to one end of the inductor L, and the gate is connected to the driving signal TG2. The source of the third NMOS transistor MN3 is grounded, the gate is connected to the driving signal BG1 , and the drain is connected to the other end of the inductor L and the other end of the capacitor CF. The other ends of the output capacitor C O and the load resistor R O are both grounded.

自举驱动电路模块如图3，包括三个驱动模块DRV1、DRV2、DRV3，三个电位平移模块(Level Shift)LS1、LS2、LS3，两个自举电容CBoot1、CBoot2、开关PMOS管MSP1、PMOS调整管MSP2、二极管D1、运算放大器A1、反馈电阻R1、R2、电压源VREF1。第一驱动模块DRV1的电源端BST1连接自举电容CBoot1，地端连接第一开关节点SW1，输入端与第一Level Shift模块LS1的输出相连，输出接至第一NMOS管MN1的栅极TG1。第二驱动模块DRV2的电源端BST2接自举电容CBoot2，地端连接至输入电压VIN，输入端连接第二Level Shift模块LS2的输出，输出接至第二NMOS管MN2的栅极TG2。第三驱动模块DRV3的电源端连接至LDO模块的输出电压VDR，地端接地，其中VDR为开关管的驱动电压，当VIN小于5V时，VDR＝VIN；当VIN大于5V时，VDR＝5V。DRV3的输入端与死区产生电路模块的输出信号PWM1相连，输出连接至第三NMOS管MN3的栅极BG1。第一Level Shift模块LS1的输入电源端连接VDR，输入地端接地，输出电源端连接BST1，输出地端连接第一开关节点SW1，输入端与死区产生电路的输出信号NPWM1相连，输出端连接至第一驱动模块DRV1的输入端。第二Level Shift模块LS2的输入电源端连接VDR，输入地端接地，输出电源端连接BST2，输出地端连接输入电压VIN，输入端与死区产生电路的输出信号PWM1相连，输出端连接至第二驱动模块DRV2的输入端。第三Level Shift模块LS3的输入电源端连接VDR，输入地端接地，输出电源端连接BST1，输出地端连接第一开关节点SW1，输入端与死区产生电路的输出信号PWM2相连，输出端连接至第一PMOS管MSP1的栅极GP1第一自举电容CBoot1上极板连接BST1，下极板连接第一开关节点SW1。第二自举电容CBoot2上极板连接至BST2，下极板与输入电压VIN相连。第一PMOS管MSP1的源极与BST1相连，栅极GP1连接至第三Level Shift模块LS3的输出，漏极连接BST2。二极管D1的到阳极连接第一开关节点SW1，阴极连接第二PMOS管MSP2的源极。第二PMOS管MSP2的栅极连接运算放大器A1的输出端，漏极连接至BST2。运算放大器A1的同相输入端连接电阻R1、R2的一端，反相输入端与电压源VREF1的正极。电阻R1的另一端连接至BST2，电阻R2的另一端连接输入电压VIN。电压源VREF1的负极连接输入电压VIN。The bootstrap drive circuit module is shown in Figure 3, including three drive modules DRV1, DRV2, and DRV3, three potential shift modules (Level Shift) LS1, LS2, and LS3, two bootstrap capacitors C Boot1 , C Boot2 , and a switch PMOS tube MSP1 , PMOS adjustment tube MSP2, diode D1, operational amplifier A1, feedback resistors R1, R2, voltage source V REF1 . The power supply terminal BST1 of the first drive module DRV1 is connected to the bootstrap capacitor C Boot1 , the ground terminal is connected to the first switch node SW1, the input terminal is connected to the output of the first Level Shift module LS1, and the output is connected to the gate TG1 of the first NMOS transistor MN1 . The power terminal BST2 of the second driving module DRV2 is connected to the bootstrap capacitor C Boot2 , the ground terminal is connected to the input voltage V IN , the input terminal is connected to the output of the second Level Shift module LS2 , and the output is connected to the gate TG2 of the second NMOS transistor MN2 . The power supply terminal of the third drive module DRV3 is connected to the output voltage V DR of the LDO module, and the ground terminal is grounded, wherein V DR is the driving voltage of the switch tube. When V IN is less than 5V, V DR =V IN ; when V IN is greater than 5V , V DR =5V. The input terminal of DRV3 is connected to the output signal PWM1 of the dead zone generating circuit module, and the output is connected to the gate BG1 of the third NMOS transistor MN3. The input power terminal of the first Level Shift module LS1 is connected to VDR , the input ground terminal is connected to ground, the output power terminal is connected to BST1, the output ground terminal is connected to the first switch node SW1, the input terminal is connected to the output signal NPWM1 of the dead zone generation circuit, and the output terminal Connect to the input terminal of the first driving module DRV1. The input power terminal of the second Level Shift module LS2 is connected to V DR , the input ground terminal is connected to ground, the output power terminal is connected to BST2, the output ground terminal is connected to the input voltage V IN , the input terminal is connected to the output signal PWM1 of the dead zone generating circuit, and the output terminal is connected to To the input terminal of the second driving module DRV2. The input power terminal of the third Level Shift module LS3 is connected to VDR , the input ground terminal is connected to ground, the output power terminal is connected to BST1, the output ground terminal is connected to the first switch node SW1, the input terminal is connected to the output signal PWM2 of the dead zone generation circuit, and the output terminal Connected to the gate GP1 of the first PMOS transistor MSP1 , the upper plate of the first bootstrap capacitor C Boot1 is connected to BST1 , and the lower plate is connected to the first switch node SW1 . The upper plate of the second bootstrap capacitor C Boot2 is connected to BST2, and the lower plate is connected to the input voltage V IN . The source of the first PMOS transistor MSP1 is connected to BST1, the gate GP1 is connected to the output of the third Level Shift module LS3, and the drain is connected to BST2. The anode of the diode D1 is connected to the first switching node SW1, and the cathode is connected to the source of the second PMOS transistor MSP2. The gate of the second PMOS transistor MSP2 is connected to the output terminal of the operational amplifier A1, and the drain is connected to BST2. The non-inverting input terminal of the operational amplifier A1 is connected to one terminal of the resistors R1 and R2, and the inverting input terminal is connected to the anode of the voltage source V REF1 . The other end of the resistor R1 is connected to the BST2, and the other end of the resistor R2 is connected to the input voltage V IN . The negative pole of the voltage source V REF1 is connected to the input voltage V IN .

死区时间产生电路包括七个反相器INV1、INV2、INV3、INV4、INV5、INV6、INV7，两个与非门NAND1、NAND2，四个延时模块DELAY1、DELAY2、DELAY3、DELAY4以及四个电容C1、C2、C3、C4，如图4。第一反相器INV1的输入与第七反相器INV7的输出相连，输出端接至第一与非门NAND1的输入。第二反相器INV2的输入连接第二延时模块DELAY2的输出，同时与电容C2相连，输出连接第三反相器INV3的输入，并作为输出信号PWM1。第三反相器INV3的输入连接第二反相器INV2的输出，输出与第二与非门NAND2的输入相连，并作为输出信号PWM2。第四反相器INV4的输入端接输入信号PWM_IN，输出端与第二与非门NAND2的另一输入端相连。第五反相器INV5的输入连接至第二与非门NAND2的输出，输出端连接第三延时模块DELAY3的输入。第六反相器INV6的输入端连接至第四延时模块DELAY4的输出以及电容C4，输出端接至第七反相器INV7的输入端，并作为输出信号NPWM2。第七反相器INV7的输入端连接第六反相器INV6的输出端，输出端为输出信号NPWM1。第一延时模块DELAY1的输入连接至第一与非门NAND1的输出，输出端与第二延时模块DELAY2的输入端以及电容C1相连。第二延时模块DELAY2的输出连接第二反相器INV2的输入端以及电容C2的一端。第三延时模块DELAY3的输入接至第五反相器INV5的输出，输出端连接第四延时模块DELAY4的输入端以及电容C3。第四延时模块DELAY4的输出接至第六反相器INV6的输出端以及电容C4。电容C1、C2、C3、C4的另一端均接地。The dead time generation circuit includes seven inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, two NAND gates NAND1, NAND2, four delay modules DELAY1, DELAY2, DELAY3, DELAY4 and four capacitors C1, C2, C3, C4, as shown in Figure 4. The input of the first inverter INV1 is connected to the output of the seventh inverter INV7, and the output terminal is connected to the input of the first NAND gate NAND1. The input of the second inverter INV2 is connected to the output of the second delay module DELAY2 and the capacitor C2 at the same time, and the output is connected to the input of the third inverter INV3 as the output signal PWM1. The input of the third inverter INV3 is connected to the output of the second inverter INV2 , and the output is connected to the input of the second NAND gate NAND2 as the output signal PWM2 . The input terminal of the fourth inverter INV4 is connected to the input signal PWM_IN, and the output terminal is connected to the other input terminal of the second NAND gate NAND2. The input of the fifth inverter INV5 is connected to the output of the second NAND gate NAND2, and the output end is connected to the input of the third delay module DELAY3. The input terminal of the sixth inverter INV6 is connected to the output of the fourth delay module DELAY4 and the capacitor C4 , and the output terminal is connected to the input terminal of the seventh inverter INV7 as the output signal NPWM2 . The input terminal of the seventh inverter INV7 is connected to the output terminal of the sixth inverter INV6, and the output terminal is the output signal NPWM1. The input of the first delay module DELAY1 is connected to the output of the first NAND gate NAND1, and the output terminal is connected to the input terminal of the second delay module DELAY2 and the capacitor C1. The output of the second delay module DELAY2 is connected to the input terminal of the second inverter INV2 and one terminal of the capacitor C2. The input of the third delay module DELAY3 is connected to the output of the fifth inverter INV5, and the output terminal is connected to the input terminal of the fourth delay module DELAY4 and the capacitor C3. The output of the fourth delay module DELAY4 is connected to the output terminal of the sixth inverter INV6 and the capacitor C4. The other ends of the capacitors C1, C2, C3, and C4 are all grounded.

附图2为本发明提出的混合升压变换器功率级拓扑的电路图，包括第一NMOS管、第二NMOS管、第三NMOS管、电感L、飞电容CF、输出电容CO以及负载电阻RO。利用储能元件电感L电流不能突变以及电容CF电压不能突变的特性，实现从输入到输出的升压。由电容的特性可以得出飞电容CF两端的电压为输入电压VIN，由电感的伏秒平衡可以得到所述的升压变换器的电压转换比满足

Figure BDA0003282989500000061
其中D为控制信号占空比。在占空比0<D<1时，有CR>2。Accompanying drawing 2 is the circuit diagram of the power stage topology of the hybrid boost converter proposed by the present invention, including the first NMOS tube, the second NMOS tube, the third NMOS tube, the inductor L, the flying capacitor C F , the output capacitor C O and the load resistor R O . Utilizing the characteristics that the current of the inductance L of the energy storage element cannot change suddenly and the voltage of the capacitor C F cannot change suddenly, the voltage boost from input to output is realized. From the characteristics of the capacitor, it can be concluded that the voltage across the flying capacitor C F is the input voltage V IN , and from the volt-second balance of the inductor, it can be obtained that the voltage conversion ratio of the boost converter satisfies
Figure BDA0003282989500000061
Where D is the duty cycle of the control signal. When the duty cycle is 0<D<1, there is CR>2.

本发明提出的功率级拓扑共有两个工作状态，状态1时第一NMOS管MN1关断，第二NMOS管MN2、第三NMOS管MN3开启，此时开关节点SW1的电压为输入电压VIN、开关节点SW2的电压为0，电流从输入流经电感L、第三NMOS管MN3后导通至地，同时电流经过第二NMOS管MN2与飞电容CF以及第三NMOS管MN3至地。该状态下电感L与电容CF并联后同时被输入电压充电，此时电感L的电流线性增加。状态2时第二NMOS管MN2、第三NMOS管MN3关断，第一NMOS管MN1开启，此时开关节点SW1的电压为输出电压VOUT，开关节点SW2的电压为输出电压与输入电压的差值VOUT-VIN，电流从输入流经电感L、飞电容CF以及第一NMOS管MN1至输出电容CO与负载电阻RO。该状态下电感L与电容CF串联后放电，为输出电容CO与负载电阻RO供电，此时电感L的电流线性下降。The power stage topology proposed by the present invention has two working states. In state 1, the first NMOS transistor MN1 is turned off, and the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned on. At this time, the voltage of the switch node SW1 is the input voltage V IN , The voltage of the switch node SW2 is 0, and the current flows from the input through the inductor L and the third NMOS transistor MN3 to the ground, and at the same time, the current flows to the ground through the second NMOS transistor MN2, the flying capacitor CF and the third NMOS transistor MN3. In this state, the inductor L and the capacitor CF are connected in parallel and are charged by the input voltage at the same time, and the current of the inductor L increases linearly at this time. In state 2, the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned off, and the first NMOS transistor MN1 is turned on. At this time, the voltage of the switch node SW1 is the output voltage V OUT , and the voltage of the switch node SW2 is the difference between the output voltage and the input voltage. V OUT -V IN , the current flows from the input through the inductor L, the flying capacitor C F and the first NMOS transistor MN1 to the output capacitor C O and the load resistor R O . In this state, the inductor L and the capacitor C F are connected in series and then discharged to supply power to the output capacitor C O and the load resistor R O. At this time, the current of the inductor L decreases linearly.

由所述的功率级拓扑的两个工作状态可知，飞电容CF与电感L同时充放电，由于在想负载放电的过程中飞电容承担了一部分的电流，电感平均电流大幅减小，降低了DCR损耗，从而提高了能量转换效率。另外，开关节点SW1与SW2的电压摆幅与CBC相比较低，故而功率开关管的电压应力相应减小，实现了功率开关管开关损耗的降低，更进一步提高了能量转换效率。It can be seen from the two working states of the power stage topology that the flying capacitor C F and the inductor L are charged and discharged at the same time. Since the flying capacitor bears a part of the current during the load discharge process, the average current of the inductor is greatly reduced, reducing the DCR losses, thereby improving energy conversion efficiency. In addition, the voltage swing of the switch nodes SW1 and SW2 is lower than that of CBC, so the voltage stress of the power switch tube is correspondingly reduced, which reduces the switching loss of the power switch tube and further improves the energy conversion efficiency.

附图3为本发明提出的混合升压变换器功率级拓扑的工作波形图。当功率级拓扑工作在状态1时，第一开关节点SW1的电压为VIN，第二开关节点SW2的电压为0，电感L两端的电压为VIN，电感L电流线性上升，电容CF电流逐渐减小，此时输出电流IOUT为0。当功率级拓扑工作在状态2时，第一开关节点SW1的电压为VOUT，第二开关节点SW2的电压为VOUT-VIN，电感L两端的电压为2VIN-VOUT，电感L电流线性下降，电容CF电流与电感电流相等，输出电流IOUT与电感L电流相等。Accompanying drawing 3 is the working waveform diagram of the power stage topology of the hybrid boost converter proposed by the present invention. When the power stage topology works in state 1, the voltage of the first switch node SW1 is V IN , the voltage of the second switch node SW2 is 0, the voltage across the inductor L is V IN , the current of the inductor L rises linearly, and the current of the capacitor C F Decrease gradually, and the output current I OUT is 0 at this time. When the power stage topology works in state 2, the voltage of the first switch node SW1 is V OUT , the voltage of the second switch node SW2 is V OUT -V IN , the voltage across the inductor L is 2V IN -V OUT , and the current of the inductor L Decrease linearly, the capacitor C F current is equal to the inductor current, and the output current I OUT is equal to the inductor L current.

附图4为本发明实施例的电路图，包括功率级拓扑以及自举驱动电路模块。其中功率级拓扑电路图即为附图2所示的电路图，包括第一NMOS管MN1、第二NMOS管MN2、第三NMOS管MN3、电感L、飞电容CF、输出电容CO以及负载电阻RO。自举驱动电路模块包括三个驱动模块DRV1、DRV2、DRV3，三个电位平移模块LS1、LS2、LS3，两个自举电容CBoot1、CBoot2、开关PMOS管MSP1、PMOS调整管MSP2、二极管D1、运算放大器A1、反馈电阻R1、R1、电压源VREF1。所述的死区时间产生电路包括七个反相器INV1、INV2、INV3、INV4、INV5、INV6、INV7，两个与非门NAND1、NAND2，四个延时模块DELAY1、DELAY2、DELAY3、DELAY4以及四个电容C1、C2、C3、C4。Figure 4 is a circuit diagram of an embodiment of the present invention, including a power stage topology and a bootstrap drive circuit module. The topological circuit diagram of the power stage is the circuit diagram shown in Figure 2, including the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the inductor L, the flying capacitor C F , the output capacitor C O and the load resistor R O. The bootstrap drive circuit module includes three drive modules DRV1, DRV2, DRV3, three potential shift modules LS1, LS2, LS3, two bootstrap capacitors C Boot1 , C Boot2 , switch PMOS tube MSP1, PMOS adjustment tube MSP2, diode D1 , operational amplifier A1, feedback resistors R1, R1, voltage source V REF1 . The dead time generating circuit includes seven inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, two NAND gates NAND1, NAND2, four delay modules DELAY1, DELAY2, DELAY3, DELAY4 and Four capacitors C1, C2, C3, C4.

具体的，死区产生电路模块将输出信号PWM_IN通过两个支路进行延时，并利用第一与非门NAND1与第二与非门NAND2实现输出信号PWM1与NPWM1、PWM2与NPWM2之间死区时间的产生，避免功率级拓扑中功率开关管在工作状态切换时同时导通。Specifically, the dead zone generation circuit module delays the output signal PWM_IN through two branches, and uses the first NAND gate NAND1 and the second NAND gate NAND2 to realize the dead zones between the output signals PWM1 and NPWM1, PWM2 and NPWM2 The generation of time prevents the power switch tubes in the power stage topology from being turned on at the same time when the working state is switched.

具体的，自举驱动模块中第二自举电容CBoot2上的电压由第二PMOS管MSP2、运算放大器A1、电阻R1、R2、电压源VREF1组成的负反馈环路控制，在第一NMOS管MN1导通时，由第一开关节点SW1通过正向偏置的二极管D1充电。第二自举电容CBoot2上的电压作为第二驱动模块DRV2的电源驱动第二NMOS管MN2，实现第二NMOS管MN2的自举驱动。第一自举电容CBoot1通过第一PMOS管MSP1的控制，由第二自举电容CBoot2进行充电，其上电压作为第一驱动模块DRV1的电源电压并驱动第一NMOS管MN1，实现第一NMOS管MN1的自举驱动。自举驱动电路有两个工作状态，与功率级拓扑的两个工作状态协同工作。Specifically, the voltage on the second bootstrap capacitor C Boot2 in the bootstrap drive module is controlled by a negative feedback loop composed of the second PMOS transistor MSP2, operational amplifier A1, resistors R1, R2, and voltage source V REF1 . When the transistor MN1 is turned on, it is charged by the first switch node SW1 through the forward biased diode D1. The voltage on the second bootstrap capacitor C Boot2 is used as the power supply of the second driving module DRV2 to drive the second NMOS transistor MN2 to realize bootstrap driving of the second NMOS transistor MN2. The first bootstrap capacitor C Boot1 is controlled by the first PMOS transistor MSP1, and is charged by the second bootstrap capacitor C Boot2 . Bootstrap driver of NMOS tube MN1. The bootstrap drive circuit has two working states, which cooperate with the two working states of the power stage topology.

当输入控制信号PWM1为高电平时，功率级拓扑以及自举驱动模块均工作在状态1。由于第一NMOS管MN1关断，此时第一驱动模块DRV1不工作，第一PMOS管MSP1导通，故第二自举电容CBoot2放电，通过第一PMOS管MSP1为第一自举电容CBoot1充电，并同时为第二驱动模块DRV2供电。在状态1下第一开关节点SW1的电压等于输入电压VIN，二极管D1反偏截止，使得第二PMOS管MSP2上电流为零。同时，输入电压VIN为第三驱动模块DRV3供电，驱动第三NMOS管MN3。When the input control signal PWM1 is at a high level, both the power stage topology and the bootstrap drive module work in state 1. Since the first NMOS transistor MN1 is turned off, the first drive module DRV1 does not work at this time, and the first PMOS transistor MSP1 is turned on, so the second bootstrap capacitor C Boot2 is discharged, and the first bootstrap capacitor C Boot2 is discharged through the first PMOS transistor MSP1. Boot1 charges and supplies power to the second drive module DRV2 at the same time. In state 1, the voltage of the first switch node SW1 is equal to the input voltage V IN , and the diode D1 is reverse-biased and cut off, so that the current on the second PMOS transistor MSP2 is zero. At the same time, the input voltage V IN supplies power to the third driving module DRV3 to drive the third NMOS transistor MN3.

当输入控制信号PWM1为低电平时，功率级拓扑以及自举驱动模块均工作在状态2。由于第二NMOS管MN2与第三NMOS管MN3关断，此时第二驱动模块DRV2与第三驱动模块DRV3不工作，第一PMOS管MSP1关断，此时第一自举电容CBoot1放电，作为第一驱动模块DRV1的电源。在状态2下第一开关节点SW1的电压为VOUT，使二极管D1正偏导通，第一开关节点SW1通过二级管D1以及第二PMOS管MSP2、运算放大器A1、电阻R1、R2、电压源VREF1组成的负反馈环路控制第二自举电容CBoot2充电。电压源VREF1的值应为

Figure BDA0003282989500000081
负反馈环路将第二自举电容CBoot2两端的电压稳定在VDR，作为第二驱动模块DRV2的电源电压，以及第一自举电容CBoot1的充电电压。When the input control signal PWM1 is at low level, both the power stage topology and the bootstrap drive module work in state 2. Since the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned off, the second driving module DRV2 and the third driving module DRV3 do not work at this time, the first PMOS transistor MSP1 is turned off, and the first bootstrap capacitor C Boot1 is discharged at this time. As the power supply of the first drive module DRV1. In state 2, the voltage of the first switch node SW1 is V OUT , so that the forward bias of the diode D1 is turned on, and the first switch node SW1 passes through the diode D1, the second PMOS transistor MSP2, the operational amplifier A1, the resistors R1, R2, and the voltage The negative feedback loop formed by the source V REF1 controls the charging of the second bootstrap capacitor C Boot2 . The value of the voltage source V REF1 should be
Figure BDA0003282989500000081
The negative feedback loop stabilizes the voltage across the second bootstrap capacitor C Boot2 at V DR , which serves as the power supply voltage of the second driving module DRV2 and the charging voltage of the first bootstrap capacitor C Boot1 .

附图5为本发明实施例的时序逻辑图。当PWM1为高电平时，混合升压变换器工作在状态1，此时第二NMOS管MN2、第三NMOS管MN3、第一PMOS管MSP1导通，第一NMOS管MN1以及二极管D1关断。在此状态时，第一开关节点SW1电压为VIN，第二开关节点SW2的电压为0，此时BST1的电压为VIN+VDR，BST2的电压为VIN+VDR，TG1的电压为VIN，TG2的电压为BST2，BG1的电压为VDR，GP1的电压为VIN。当PWM1为低电平时，混合升压变换器工作在状态2，此时第二NMOS管MN2、第三NMOS管MN3以及第一PMOS管MSP1关断，第一NMOS管MN1、二极管D1、第二PMOS管MSP2导通。在此状态时，第一开关节点SW1电压为VOUT，第二开关节点SW2的电压为VOUT-VIN，此时BST1的电压为VOUT+VDR，BST2的电压为VIN+VDR，TG1的电压为BST1，TG2的电压为VIN，BG1的电压为0，GP1的电压为BST1。Accompanying drawing 5 is the sequential logic diagram of the embodiment of the present invention. When PWM1 is at high level, the hybrid boost converter works in state 1. At this time, the second NMOS transistor MN2, the third NMOS transistor MN3, and the first PMOS transistor MSP1 are turned on, and the first NMOS transistor MN1 and the diode D1 are turned off. In this state, the voltage of the first switch node SW1 is V IN , the voltage of the second switch node SW2 is 0, the voltage of BST1 is V IN +V DR , the voltage of BST2 is V IN +V DR , and the voltage of TG1 is V IN , the voltage of TG2 is BST2 , the voltage of BG1 is V DR , and the voltage of GP1 is V IN . When PWM1 is at low level, the hybrid boost converter works in state 2. At this time, the second NMOS transistor MN2, the third NMOS transistor MN3 and the first PMOS transistor MSP1 are turned off, and the first NMOS transistor MN1, the diode D1, the second The PMOS transistor MSP2 is turned on. In this state, the voltage of the first switch node SW1 is V OUT , the voltage of the second switch node SW2 is V OUT -V IN , at this time the voltage of BST1 is V OUT +V DR , and the voltage of BST2 is V IN +V DR , the voltage of TG1 is BST1, the voltage of TG2 is V IN , the voltage of BG1 is 0, and the voltage of GP1 is BST1.

从上述具体实施方式可知：混合升压型变换器结合了开关电容变换器与开关电感变换器，通过飞电容CF降低开关节点的电压摆幅以及电感平均电流，从而减小了功率开关管的开关损耗和电感的DCR损耗，进而提高能量转换效率。本发明提出的混合升压变换器与传统DC-DC升压变换器的效率对比如附图6所示。在电池电压输入范围内，混合升压变换器的效率相比于CBC变换器的效率有明显提高，并在重载时实现了效率的大幅提升。同时，所提出的混合变换器增大了控制信号的占空比，能够实现大于2的电压转换比，适用于便携式设备以及高频下的应用。It can be seen from the above specific implementation manners that: the hybrid boost converter combines the switched capacitor converter and the switched inductor converter, and the voltage swing of the switch node and the average current of the inductor are reduced by the flying capacitor CF , thereby reducing the power switching tube. The switching loss and the DCR loss of the inductor improve the energy conversion efficiency. The efficiency comparison between the hybrid boost converter proposed by the present invention and the traditional DC-DC boost converter is shown in Fig. 6 . In the range of battery voltage input, the efficiency of the hybrid boost converter is significantly improved compared with the efficiency of the CBC converter, and the efficiency is greatly improved under heavy load. At the same time, the proposed hybrid converter increases the duty cycle of the control signal and can achieve a voltage conversion ratio greater than 2, which is suitable for portable devices and applications at high frequencies.

Claims (1)

1. A mixed mode boost converter suitable for battery voltage supply is characterized by comprising a first NMOS (N-channel metal oxide semiconductor) tube MN1, a second NMOS tube MN2, a third NMOS tube MN3 and a flying capacitor C F An inductor L, a first output capacitor C O And a load resistor R O An operational amplifier, a PMOS switch tube, a PMOS adjusting tube, a first resistor R1, a second resistor R2, a first bootstrap capacitor C Boot1 A second bootstrap capacitor C Boot2 Voltage source V REF A diode, a first driving module DRV1, a second driving module DRV2, a third driving module DRV3, a first level shift module LS1 a second potential translation module LS2, a third potential translation module LS3, a first PMOS transistor MSP1, a second PMOS transistor MSP2,The DELAY circuit comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NAND gate NAND1, a second NAND gate NAND2, a first DELAY module DELAY1, a second DELAY module DELAY2, a third DELAY module DELAY3 and a fourth DELAY module DELAY4;
wherein, the source of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 and the flying capacitor C F The gate of the first NMOS transistor MN1 is connected to the first driving signal TG1 output by the first driving module DRV1, the drain of the first NMOS transistor MN1 is the output terminal of the boost converter and is connected to the output capacitor C O And a load resistance R O A first output capacitor C O And a load resistance R O The other ends of the two are grounded; the source of the second NMOS transistor MN2 is connected to the input voltage V IN The gate of the second NMOS transistor MN2 is connected to a second driving signal output by the second driving module DRV 2; the source electrode of the third NMOS transistor MN3 is grounded, the gate electrode is connected to the third driving signal output by the third driving module DRV3, and the drain electrode of the third NMOS transistor MN3 is connected to the other end of the inductor L and the flying capacitor C F The other end of (a);
the inverting input terminal of the operational amplifier is connected to a voltage source V REF The non-inverting input end of the positive electrode of the operational amplifier is connected with one end of a first resistor R1 and one end of a second resistor R2, and the output of the operational amplifier is connected to the grid electrode of the PMOS adjusting tube; the source of the PMOS adjusting tube is connected with the cathode of the diode, the drain of the PMOS adjusting tube is connected with the other end of the first resistor R1 and the second bootstrap capacitor C Boot2 And a power supply terminal of the second driving module DRV 2; the other end of the second resistor R2 and a second bootstrap capacitor C Boot2 And the other end of (V) and a voltage source V REF Negative poles of the two-phase current transformer are connected with an input voltage V IN ；
The power supply terminal of the first driving module DRV1 is connected with the first bootstrap capacitor C Boot1 The ground end of the first driving module DRV1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first driving module DRV1 is connected with the output of the first potential translation module LS1, and the output of the first driving module DRV1 is connected to the grid electrode of the first NMOS transistor MN 1;
the power supply of the second driving module DRV2 is connected with the second bootstrap capacitor C Boot2 The ground terminal is connected to the input voltage V IN The input end of the second driving module DRV2 is connected to the output of the second level shifting module LS2, and the output of the second driving module DRV2 is connected to the gate of the second NMOS transistor MN 2;
the power supply terminal of the third driving module DRV3 is connected to the voltage V DR The ground terminal is grounded, wherein V DR Is the driving voltage of the switching tube, when V IN When less than 5V, V DR ＝V IN (ii) a When V is IN When greater than 5V, V DR =5V; the input end of the third driving module DRV3 is connected to the output end of the second inverter INV2, and the output of the third driving module DRV3 is connected to the gate of the third NMOS transistor MN 3;
the input power supply terminal of the first level shift module LS1 is connected to V DR The input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the first potential translation module LS1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first potential translation module LS1 is connected with the output end of the seventh inverter INV7, and the output end of the first potential translation module LS1 is connected with the input end of the first driving module DRV 1;
the input power supply terminal of the second level shift module LS2 is connected to V DR The input ground terminal is grounded, the output power terminal is connected with the power terminal of the second driving module DRV1, and the output ground terminal of the second level shift module LS2 is connected with the input voltage V IN The input end of the second level shift module LS2 is connected to the output end of the second inverter, and the output end of the second level shift module LS2 is connected to the input end of the second driving module DRV 2;
the input power supply terminal of the third level shift module LS3 is connected to V DR The input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the third potential translation module LS3 is connected with the source electrode of the first NMOS transistor MN1, the input end of the third potential translation module LS3 is connected with the output end of the third inverter INV3, and the output end of the third potential translation module LS3 is connected with the grid electrode of the first PMOS transistor MSP 1;
a first bootstrap capacitor C Boot1 The upper polar plate is connected with a first driverThe lower electrode plate of the power supply end of the module DRV1 is connected with the source electrode of the first NMOS tube MN 1;
second bootstrap capacitor C Boot2 The upper electrode plate is connected to the power supply terminal of the second driving module DRV1, the lower electrode plate and the input voltage V IN Connecting;
the source electrode of the PMOS switching tube is connected with the power supply end of the first driving module DRV1, the grid electrode of the PMOS switching tube is connected to the output of the third potential translation module LS3, and the drain electrode of the PMOS switching tube is connected with the power supply end of the second driving module DRV 1;
the anode of the diode is connected with the source electrode of a first NMOS transistor MN1, and the cathode of the diode is connected with the source electrode of a second PMOS transistor MSP 2;
one input end of the first NAND gate NAND1 is connected with the PWM signal, the other input end of the first NAND gate NAND1 is connected with the output end of the first inverter INV1, the output end of the first NAND gate NAND1 is connected with the input end of the first DELAY module DELAY1, and the input end of the first inverter INV1 is connected with the output end of the seventh inverter INV 7; the output end of the first DELAY module DELAY1 is connected with one end of a first capacitor C1 and the input end of the second DELAY module DELAY2, and the other end of the first capacitor C1 is grounded; the output end of the second DELAY module DELAY2 is connected with one end of a second capacitor C2 and the input end of the second inverter INV2, and the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with one input end of the second NAND gate NAND2, the other input end of the second NAND gate NAND2 is connected with the output end of the fourth inverter INV4, and the input end of the fourth inverter INV4 is connected with the PWM signal; the output end of the second NAND gate NAND2 is connected with the input end of a fifth inverter INV5, the output end of the fifth inverter INV5 is connected with the input end of a third DELAY module DELAY3, the output end of the third DELAY module DELAY3 is connected with one end of a third capacitor C2 and the input end of a fourth DELAY module DELAY4, and the other end of the third capacitor C3 is grounded; the output end of the fourth DELAY module DELAY4 is connected to one end of the fourth capacitor C4 and the input end of the sixth inverter INV6, and the other end of the fourth capacitor C4 is grounded; an output of the sixth inverter INV6 is connected to an input of the seventh inverter INV 7.
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