CN114785114B - Mixed mode biphase power converter with high voltage transformation ratio - Google Patents

Mixed mode biphase power converter with high voltage transformation ratio Download PDF

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Publication number
CN114785114B
CN114785114B CN202210582219.1A CN202210582219A CN114785114B CN 114785114 B CN114785114 B CN 114785114B CN 202210582219 A CN202210582219 A CN 202210582219A CN 114785114 B CN114785114 B CN 114785114B
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module
output
nmos
tube
bootstrap capacitor
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CN114785114A (en
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甄少伟
赵冰清
孙怡宁
熊海亮
武宏阳
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention belongs to the technical field of integrated circuits and switching power supplies, and particularly relates to a mixed mode dual-phase power converter with a high voltage transformation ratio. The high-voltage transformation ratio mixed mode double-phase power converter combines the advantages of a switched capacitor converter and a traditional DC-DC buck converter, and reduces the average value of inductance current and the voltage stress of a power switch tube through a flying capacitor, so that the energy conversion efficiency is improved. Meanwhile, the flying capacitor realizes the expansion of the effective duty ratio of the converter, realizes higher voltage conversion ratio compared with the traditional DC-DC buck converter under the condition of equal duty ratio of control signals, improves the current output capacity of the converter in a biphase output mode, and doubles the equivalent switching frequency. Therefore, the mixed mode biphase buck converter with high voltage transformation ratio is more suitable for application under the conditions of large output current, high voltage transformation ratio and high switching frequency.

Description

Mixed mode biphase power converter with high voltage transformation ratio
Technical Field
The invention belongs to the technical field of integrated circuits and switching power supplies, and particularly relates to a mixed mode dual-phase power converter with a high voltage transformation ratio.
Background
With the rapid development of data centers, big data, and other applications, the demand for buck converters with high energy Conversion efficiency, high voltage transformation ratio (CR), high switching frequency, and large output current has increased. In order to increase the output current capability of DC-DC buck converters, current solutions are mostly implemented with parallel bi-phase conventional DC-DC buck converters (Conventional Buck Converter, CBC). However, as the output current increases, the conduction loss caused by the inductance direct current resistor (Direct Current Resistance, DCR) increases drastically, so that the energy conversion efficiency of the conventional DC-DC buck converter is reduced, and the heat generation of the converter is aggravated and serious heat dissipation problems are generated. In addition, for the traditional DC-DC buck converter, although the equivalent switching frequency of the converter can be improved to a certain extent by adopting a multiphase parallel connection mode, the limited voltage conversion ratio of the CBC converter and the influence caused by the delay of a control loop are still main factors for limiting the further improvement of the switching frequency of the traditional DC-DC buck converter.
Unlike conventional DC-DC buck converters, the mixed mode dual phase buck converter combines the advantages of conventional dual phase switched inductor buck converters and switched capacitor converters to reduce the DCR loss and the power switching tube switching loss of the inductor by reducing the inductor current average, inductor current ripple and power switching tube voltage stress, thereby improving the energy conversion efficiency. Meanwhile, the mixed mode buck converter realizes effective duty ratio expansion, realizes higher voltage transformation ratio than CBC under the condition of equal control signal duty ratio, is beneficial to the improvement of the switching frequency of the converter, and further realizes the miniaturization development of the converter.
Disclosure of Invention
The invention aims to provide a mixed mode dual-phase power converter with high voltage transformation ratio, which has stronger current output capability, reduces DCR loss of an inductor and switching loss of a power switch tube, thereby improving energy conversion efficiency, realizes effective duty ratio expansion effect through a flying capacitor, realizes higher voltage transformation ratio than a CBC converter under the condition of identical control signal duty ratio, and is suitable for application under large output current, high voltage transformation ratio and high switching frequency.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a mixed mode dual-phase power converter with high voltage transformation ratio comprises a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, and a first flying capacitor C F1 Second flying capacitor C F2 First inductor L 1 Second inductance L 2 Output capacitance C OUT Load resistor R LOAD The first PMOS switching tube MSP1, the second PMOS switching tube MSP2, the third PMOS switching tube MSP3, the fourth PMOS switching tube MSP4, the first NMOS switching tube MSN1, the second NMOS switching tube MSN2, the first driving module DRV1, the second driving module DRV2, the third driving module DRV3, the fourth driving module DRV4, the fifth driving module DRV5, the sixth driving module DRV6, the first potential translation module LS1, the second potential translation module LS2, the third potential translation module LS3, the fourth potential translation module LS4, the fifth potential translation module LS5, the sixth potential translation module LS6 and the first bootstrap capacitor C Boot1 A second bootstrap capacitor C Boot2 Third bootstrap capacitor C Boot3 Fourth bootstrap capacitor C Boot4 Fifth bootstrap capacitor C Boot5 Sixth bootstrap capacitor C Boot6 Seventh bootstrap capacitor C Boot7 Eighth bootstrap capacitor C Boot8 The first voltage regulator DB1, the second voltage regulator DB2, the first inverter INV1, the second inverter INV2, the first floating-ground low dropout linear regulator module LDO1, the second floating-ground low dropout linear regulator module LDO2 and the third low dropout linear regulator module LDO3.
Wherein, the source of the first NMOS transistor MN1 is connected with the drain of the third NMOS transistor MN3 and is connected to the first flying capacitor C F1 A gate of the first NMOS tube is connected with the output TG of the first driving module DRV1 1 The drain electrode of the first NMOS tube MN1 is connected with the input voltage V of the converter IN The method comprises the steps of carrying out a first treatment on the surface of the Second NMOS tubeSource of MN2 and second flying capacitor C F2 Is connected with the drain electrode of the fourth NMOS tube MN4, the grid electrode of the second NMOS tube MN2 is connected with the output TG of the second driving module DRV2 2 The drain electrode of the second NMOS tube MN2 is connected with the input voltage V of the converter IN The method comprises the steps of carrying out a first treatment on the surface of the The source of the third NMOS transistor MN3 and the source of the sixth NMOS transistor NM6, and the second flying capacitor C F2 Is connected to the other end of the second inductor L 2 A gate of the third NMOS transistor MN3 is connected with the output TG of the third driving module DRV3 3 The method comprises the steps of carrying out a first treatment on the surface of the The source of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5 and the first flying capacitor C F1 Is connected with the other end of the first inductor L 1 A gate of the fourth NMOS transistor MN4 is connected with the output TG of the fourth driving module DRV4 4 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the fifth NMOS tube MN5 is connected with the output TG of the fifth driving module DRV5 5 The drain electrode of the fifth NMOS transistor MN5 is connected to the converter output terminal V OUT And is connected with the output capacitor C OUT Load resistor R LOAD Is connected with one end of the connecting rod; the grid electrode of the sixth NMOS tube MN6 is connected with the output TG of the sixth driving module DRV6 6 The drain of the sixth NMOS transistor MN6 is connected to the converter output terminal V OUT Simultaneously connected with the output capacitor C OUT Load resistor R LOAD Is a member of the group; first inductance L 1 Second inductance L 2 Output capacitance C OUT Load resistor R LOAD The other ends of the two are grounded.
The power end of the first driving module DRV1 is connected to the first bootstrap capacitor C Boot1 The ground end of the first driving module DRV1, the source electrode of the first NMOS tube MN1 and the first bootstrap capacitor C Boot1 The input end of the first driving module DRV1 is connected to the output of the first potential translation module LS1, and the output of the first driving module DRV1 is connected to the grid electrode of the first NMOS tube MN 1; the power end of the second driving module DRV2 is connected to the second bootstrap capacitor C Boot2 The ground end of the second driving module DRV2, the source electrode of the second NMOS tube MN2 and the second bootstrap capacitor C Boot2 The input end of the second driving module DRV2 is connected to the output of the second potential translation module LS2, and the output of the second driving module DRV2 is connectedTo the gate of the second NMOS transistor MN 2; the power end of the third driving module DRV3 is connected to the third bootstrap capacitor C Boot3 The ground end of the third driving module DRV3, the source electrode of the third NMOS tube MN3 and the third bootstrap capacitor C Boot3 The input end of the third driving module DRV3 is connected to the output of the third potential translation module LS3, and the output of the third driving module DRV3 is connected to the grid electrode of the third NMOS tube MN 3; the power end of the fourth driving module DRV4 is connected to the fourth bootstrap capacitor C Boot4 The ground of the fourth driving module DRV4, the source of the fourth NMOS transistor MN4 and the fourth bootstrap capacitor C Boot4 The input end of the fourth driving module DRV4 is connected to the output of the fourth potential translation module LS4, and the output of the fourth driving module DRV4 is connected to the grid electrode of the fourth NMOS tube MN 4; the power supply end of the fifth driving module DRV5 is connected to the fifth bootstrap capacitor C Boot5 The ground of the fifth driving module DRV5, the source of the fifth NMOS MN5, and the fifth bootstrap capacitor C Boot5 The input end of the fifth driving module DRV5 is connected to the output of the fifth potential translation module LS5, and the output of the fifth driving module DRV5 is connected to the grid electrode of the fifth NMOS tube MN 5; the power supply end of the sixth driving module DRV6 is connected to the sixth bootstrap capacitor C Boot6 The ground of the sixth driving module DRV6, the source of the sixth NMOS transistor MN6, and the sixth bootstrap capacitor C Boot6 The input end of the sixth driving module DRV6 is connected to the output of the sixth potential translation module LS6, and the output of the sixth driving module DRV6 is connected to the grid electrode of the sixth NMOS tube MN 6;
the input power terminal of the first level shift module LS1 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the first potential translation module LS1 is connected to the first bootstrap capacitor C Boot1 The upper polar plate and the output ground end of the first potential translation module LS1 are connected with the source electrode of the first NMOS tube MN1, the input end of the first potential translation module LS1 is connected with the driving signal S1, and the output end of the first potential translation module LS1 is connected with the input end of the first driving module DRV 1;
the input power terminal of the second level shift module LS2 is connected to the driving voltage V DR Input ofThe ground is grounded, and the output power end of the second potential translation module LS2 is connected to the second bootstrap capacitor C Boot2 The upper polar plate and the output ground end of the second NMOS tube MN2 are connected, the input end of the second potential translation module LS2 is connected with a driving signal S2, and the output end of the second potential translation module LS2 is connected to the input end of the second driving module DRV 2;
the input power terminal of the third level shift module LS3 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the third potential translation module LS3 is connected to the third bootstrap capacitor C Boot3 The upper polar plate and the output ground end of the third potential translation module LS3 are connected with the source electrode of the third NMOS tube MN3, the input end of the third potential translation module LS3 is connected with the driving signal S3, and the output end of the third potential translation module LS3 is connected with the input end of the third driving module DRV 3;
the input power terminal of the fourth level shift module LS4 is connected to the driving voltage V DR The input ground is grounded, and the output power end of the fourth potential translation module LS4 is connected to the fourth bootstrap capacitor C Boot4 The upper polar plate and the output ground end of the fourth NMOS tube MN4 are connected, the input end of the fourth potential translation module LS4 is connected with a driving signal S4, and the output end of the fourth potential translation module LS4 is connected to the input end of the fourth driving module DRV 4;
the input power terminal of the fifth level shift module LS5 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the fifth potential translation module LS5 is connected to the fifth bootstrap capacitor C Boot5 The upper polar plate and the output ground end of the fifth NMOS tube MN5 are connected, the input end of the fifth potential translation module LS5 is connected with a driving signal S5, and the output end of the fifth potential translation module LS5 is connected to the input end of the fifth driving module DRV 5;
the input power terminal of the sixth potential shift module LS6 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the sixth potential translation module LS6 is connected to the sixth bootstrap capacitor C Boot6 The upper polar plate and the output ground end of the (E) are connected with the source electrode of a sixth NMOS tube MN6, the input end of a sixth potential translation module LS6 is connected with a driving signal S6, and the output end of the sixth potential translation module LS6 is connected with a sixth driving module DRV6An input end;
first bootstrap capacitor C Boot1 The upper polar plate of the first NMOS transistor MN1 is connected with the power end of the first driving module DRV 1; second bootstrap capacitor C Boot2 The upper polar plate of the second NMOS transistor MN2 is connected with the power end of the second driving module DRV 2; third bootstrap capacitor C Boot3 The upper polar plate of the first NMOS transistor is connected to the power end of the third driving module DRV3, and the lower polar plate of the first NMOS transistor is connected to the source electrode of the third NMOS transistor MN 3; fourth bootstrap capacitor C Boot4 The upper polar plate of the first NMOS transistor is connected to the power end of the fourth driving module DRV4, and the lower polar plate is connected to the source electrode of the fourth NMOS transistor MN 4; fifth bootstrap capacitor C Boot5 The upper polar plate of the first NMOS transistor is connected to the power end of the fifth driving module DRV5, and the lower polar plate of the first NMOS transistor is connected to the source electrode of the fifth NMOS transistor MN 5; sixth bootstrap capacitor C Boot6 The upper polar plate of the first NMOS transistor is connected to the power end of the sixth driving module DRV6, and the lower polar plate is connected to the source electrode of the sixth NMOS transistor MN 6; seventh bootstrap capacitor C Boot7 The upper polar plate of the first NMOS switch tube MSN1 is connected with the cathode of the first voltage stabilizing tube DB1, and the lower polar plate of the first NMOS switch tube MSN1 is connected with the output end of the first inverter INV 1; eighth bootstrap capacitor C Boot8 The upper polar plate of the second voltage stabilizing tube DB2 is connected with the cathode of the second NMOS switching tube MSN2, and the lower polar plate is connected with the output end of the second inverter INV 2;
source of first PMOS switch tube MSP1 and first bootstrap capacitor C Boot1 The upper polar plate of the first PMOS switch tube MSP1 is connected with a control signal G1, the drain electrode of the first PMOS switch tube MSP1 is connected with the source electrode of the third PMOS switch tube MSP3 and a third bootstrap capacitor C Boot3 The upper polar plate of the upper polar plate is connected; source electrode of second PMOS switch tube MSP2 and second bootstrap capacitor C Boot2 The upper polar plate of the second PMOS switch tube MSP2 is connected with a control signal G2, the drain electrode of the second PMOS switch tube MSP2 is connected with the source electrode of the fourth PMOS switch tube MSP4 and a fourth bootstrap capacitor C Boot4 The upper polar plate of the upper polar plate is connected; source electrode of third PMOS switch tube MSP3 and third bootstrap capacitor C Boot3 The upper polar plate of the third PMOS switch tube MSP3 is connected with a control signal G3, the drain electrode of the third PMOS switch tube MSP3 is connected with a fifth bootstrap capacitor C Boot5 Upper plate of (a) and first floating groundThe output end of the differential pressure linear voltage regulator module LDO1 is connected; source of fourth PMOS switch tube MSP4 and fourth bootstrap capacitor C Boot4 The upper polar plate of the fourth PMOS switch tube MSP4 is connected with a control signal G4, the drain electrode of the fourth PMOS switch tube MSP4 is connected with a sixth bootstrap capacitor C Boot6 The upper polar plate of the second floating ground low dropout linear regulator module LDO2 is connected with the output end of the second floating ground low dropout linear regulator module LDO;
the source electrode of the first NMOS switch tube MSN1 is connected to the output end of the third LDO3 and the anode of the first voltage stabilizing tube DB1, the grid electrode of the first NMOS switch tube MSN1 is connected to the cathode of the first voltage stabilizing tube DB1 and the seventh bootstrap capacitor C Boot7 The drain electrode of the first NMOS switch tube MSN1 is connected with the input end of the first floating-ground low-dropout linear regulator module LDO 1; the source electrode of the second NMOS switch tube MSN2 is connected to the output end of the third LDO3 and the anode of the second voltage stabilizing tube DB2, the grid electrode of the second NMOS switch tube MSN2 is connected to the cathode of the second voltage stabilizing tube DB2 and the eighth bootstrap capacitor C Boot8 The drain electrode of the second NMOS switch tube MSN2 is connected with the input end of the second floating ground low dropout linear voltage regulator module LDO 2;
the ground terminal of the first floating-ground low dropout linear regulator module LDO1 is connected to the fifth bootstrap capacitor C Boot5 Lower plate of (a); the ground terminal of the second floating-ground low dropout linear regulator module LDO2 is connected to the sixth bootstrap capacitor C Boot6 Lower plate of (a); the power end of the third low dropout linear regulator module LDO3 is connected with the input voltage V IN The ground of the third low dropout linear regulator module LDO3 is grounded, and the output end of the third low dropout linear regulator module LDO3 is connected to the source electrode of the first NMOS switch tube MSN1, the anode electrode of the first voltage regulator tube DB1, the source electrode of the second NMOS switch tube MSN2 and the anode electrode of the second voltage regulator tube DB 2.
An input end of the first inverter INV1 is connected with the control signal G5, and an output end is connected with the seventh bootstrap capacitor C Boot7 Lower plate of (a); the input end of the second inverter INV2 is connected with the control signal G6, and the output end is connected with the eighth bootstrap capacitor C Boot8 Lower plate of (a);
the invention has the beneficial effects that the mixed mode dual-phase buck converter combines the advantages of the traditional dual-phase DC-DC buck converter and the mixed mode buck converter, and reduces the average inductance current and the voltage stress of the power switch tube through the action of the flying capacitor, thereby reducing the inductance DCR loss and the power switch tube switching loss, realizing the effective duty ratio expansion of control signals, and being suitable for the application under the conditions of high voltage transformation ratio, high switching frequency and large output current.
Drawings
FIG. 1 is a power stage topology of a mixed mode bi-phase buck converter according to the present invention;
FIG. 2 is a circuit diagram of a mixed mode bi-phase buck converter power stage topology according to the present invention;
FIG. 3 is a schematic diagram of the current of the hybrid mode dual phase buck converter topology operating states 1-3 according to the present invention;
FIG. 4 is a waveform diagram illustrating the operation of a hybrid mode dual phase buck converter topology according to the present invention;
FIG. 5 is a circuit diagram of an embodiment of the present invention;
FIG. 6 is a schematic diagram of the operating current at State1 according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the operating current at State2 according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of the operating current at State3 according to an embodiment of the present invention;
FIG. 9 is a timing logic diagram of control signals according to an embodiment of the invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
for ease of description, the mixed mode bi-phase buck converter of the present invention is divided into two parts, a power stage topology and a bootstrap drive circuit module. Wherein the power stage topology comprises six power switching tubes S1, S2, S3, S4, S5 and S6, two flying capacitors C F1 、C F2 Two inductances L 1 、L 2 An output capacitor C OUT And a load resistor R LOAD As shown in figure 1. The power switch tube can adopt an NMOS tube or a PMOS tube. Taking NMOS tube as an exampleThe first NMOS transistor MN1 is a switch S1, the second NMOS transistor MN2 is a switch S2, the third NMOS transistor MN3 is a switch S3, the fourth NMOS transistor MN4 is a switch S4, the fifth NMOS transistor MN5 is a switch S5, and the sixth NMOS transistor MN6 is a switch S6, as shown in fig. 2. The source of the first NMOS transistor MN1 and the drain of the third NMOS transistor NM3, and the first flying capacitor C F1 Is connected to the upper plate of the switch node SW 1 The gate of the first NMOS transistor MN1 is connected with a driving signal TG 1 The drain of the first NMOS transistor MN1 is connected to the input voltage V of the converter IN . The source electrode of the second NMOS transistor MN2 is connected with the drain electrode of the fourth NMOS transistor MN4 and the second flying capacitor C F2 Is denoted as switch node SW 2 The gate of the second NMOS transistor MN2 is a driving signal TG 2 The drain of the second NMOS transistor MN2 and the input voltage V of the converter IN Are connected. The source of the third NMOS transistor MN3 is connected to the source of the sixth NMOS transistor MN6 and the second flying capacitor C F2 Lower plate of (2) and second inductor L 2 Is denoted as switch node SW 3 The gate of the third NMOS transistor MN3 is a driving signal TG 3 The drain of the third NMOS transistor MN3 is connected to the switch node SW 1 . The source of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5 and the first flying capacitor C F1 Lower plate of (a) and first inductor L 1 Is denoted as switch node SW 4 The gate of the fourth NMOS transistor MN4 is a driving signal TG 4 The drain of the fourth NMOS transistor MN4 is connected to the switch node SW 2 . Source of fifth NMOS transistor MN5 is connected to switch node SW 4 The gate of the fifth NMOS transistor MN5 is a driving signal TG 5 The drain of the fifth NMOS transistor MN5 is connected to the output V of the converter OUT And output capacitance C OUT Upper plate of (2) and load resistor R LOAD Is provided. Source of sixth NMOS transistor MN6 is connected to switch node SW 3 The gate of the sixth NMOS transistor MN6 is a driving signal TG 6 The drain of the sixth NMOS transistor MN6 is connected to the output V of the converter OUT And output capacitance C OUT Upper plate of (2) and load resistor R LOAD Is provided. First inductance L 1 Second inductance L 2 Output capacitance C OUT Load resistor R LOAD The other ends of the two are grounded.
The bootstrap driving circuit module is shown in fig. 5, and comprises six driving modules DRV1, DRV2, DRV3, DRV4, DRV5, DRV6, six potential shifting modules LS1, LS2, LS3, LS4, LS5, LS6, and eight bootstrap driving capacitors C Boot1 、C Boot2 、C Boot3 、C Boot4 、C Boot5 、C Boot6 、C Boot7 、C Boot8 Four PMOS switching tubes MSP1, MSP2, MSP3, MSP4, two NMOS switching tubes MSN1, MSN2, two floating-ground low dropout linear regulator modules LDO1, LDO2, one low dropout linear regulator module LDO3, two voltage regulator tubes DB1, DB2 and two inverters INV1, INV2. The power end of the first driving module DRV1 is connected to the first bootstrap capacitor C Boot1 Is connected to the first switching node SW in the power stage topology 1 An input end connected with the output end of the first potential translation module LS1, and an output end outputting a driving signal TG 1 And is connected to the gate of the first NMOS transistor MN1 in the power stage topology. The power end of the second driving module DRV2 is connected to the second bootstrap capacitor C Boot2 Is connected to the second switching node SW in the power stage topology 2 An input end connected with the output end of the second potential translation module LS2, and an output end outputting a driving signal TG 2 And to the gate of the second NMOS transistor MN2 in the power stage topology. The power end of the third driving module DRV3 is connected to the third bootstrap capacitor C Boot3 Is connected to the third switching node SW in the power stage topology 3 An input end connected with the output end of the third potential translation module LS3, and an output end outputting a driving signal TG 3 And to the gate of the third NMOS transistor MN3 in the power stage topology. The power end of the fourth driving module DRV4 is connected to the fourth bootstrap capacitor C Boot4 Is connected to the fourth switching node SW in the power stage topology 4 An input end is connected with the output end of the fourth potential translation module LS4, and an output end outputs a driving signal TG 4 And to the gate of the fourth NMOS transistor MN4 in the power stage topology. The power supply end of the fifth driving module DRV5 is connected to the fifth bootstrap capacitor C Boot5 Upper plate BST5, groundFourth switching node SW in an end-connected power stage topology 4 An input end connected with the output end of the fifth potential shift module LS5, and an output end outputting a driving signal TG 5 And to the gate of the fifth NMOS transistor MN5 in the power stage topology. The power supply end of the sixth driving module DRV6 is connected to the sixth bootstrap capacitor C Boot6 Is connected to the first switching node SW in the power stage topology 3 An input end connected with the output end of the sixth potential shift module LS6, and an output end outputting a driving signal TG 6 And to the gate of the sixth NMOS transistor MN6 in the power stage topology.
The input power end of the first potential translation module LS1 is connected with the driving voltage V DR The input ground is grounded, the output power supply end is connected with BST1, and the output ground end is connected with a switch node SW 1 The input end is a control signal S1, and the output end is connected with the input end of the first driving module DVR 1. Wherein the driving voltage V DR Generated by the first LDO1 and the second LDO2, when the voltage V is input to the converter IN When the voltage is less than 5V, V DR Equal to the input voltage V IN The method comprises the steps of carrying out a first treatment on the surface of the When the input voltage V IN Above 5V, V DR Equal to 5V. The input power end of the second potential translation module LS2 is connected with the driving voltage V DR The input ground is grounded, the output power supply end is connected with BST2, and the output ground end is connected with a switch node SW 2 The input end is a control signal S2, and the output end is connected with the input end of the second driving module DVR 2. The input power end of the third potential translation module LS3 is connected with the driving voltage V DR The input ground is grounded, the output power end is connected with BST3, and the output ground is connected with a switch node SW 3 The input end is a control signal S3, and the output end is connected with the input end of the third driving module DVR 3. The input power end of the fourth potential translation module LS4 is connected with the driving voltage V DR The input ground is grounded, the output power end is connected with BST4, and the output ground is connected with a switch node SW 4 The input end is a control signal S4, and the output end is connected with the input end of the fourth driving module DVR 4. The input power end of the fifth potential translation module LS5 is connected with the driving voltage V DR The input ground is grounded, the output power supply is connected with BST5 and the outputGround connection switch node SW 4 The input end is a control signal S5, and the output end is connected with the input end of the fifth driving module DVR 5. The input power end of the sixth potential translation module LS6 is connected with the driving voltage V DR The input ground is grounded, the output power supply end is connected with BST6, and the output ground end is connected with a switch node SW 3 The input end is a control signal S6, and the output end is connected with the input end of the sixth driving module DVR 6.
First bootstrap driving capacitor C Boot1 The upper polar plate of the switch is connected with BST1, and the lower polar plate is connected with a first switch node SW 1 The method comprises the steps of carrying out a first treatment on the surface of the Second bootstrap driving capacitance C Boot2 The upper polar plate of the switch is connected with BST2, and the lower polar plate is connected with a second switch node SW 2 The method comprises the steps of carrying out a first treatment on the surface of the Third bootstrap driving capacitor C Boot3 The upper polar plate of the switch is connected with BST3, and the lower polar plate is connected with a third switch node SW 3 The method comprises the steps of carrying out a first treatment on the surface of the Fourth bootstrap driving capacitance C Boot4 The upper polar plate of the switch is connected with BST4, and the lower polar plate is connected with a fourth switch node SW 4 The method comprises the steps of carrying out a first treatment on the surface of the Fifth bootstrap driving capacitance C Boot5 The upper polar plate of the switch is connected with BST5, and the lower polar plate is connected with a fourth switch node SW 4 The method comprises the steps of carrying out a first treatment on the surface of the Sixth bootstrap driving capacitance C Boot6 The upper polar plate of the switch is connected with BST6, and the lower polar plate is connected with a third switch node SW 3 The method comprises the steps of carrying out a first treatment on the surface of the Seventh bootstrap driving capacitance C Boot7 The upper polar plate of the first NMOS switch tube MSN1 is connected with the cathode of the first voltage stabilizing tube DB1, and the lower polar plate of the first NMOS switch tube MSN1 is connected with the output of the first inverter INV 1; eighth bootstrap driving capacitance C Boot8 The upper electrode plate of the second voltage stabilizing tube DB2 is connected with the cathode of the second voltage stabilizing tube DB2, the grid electrode of the second NMOS switch tube MSN2 and the lower electrode plate of the second NMOS switch tube MSN2 is connected with the output of the second inverter INV 2.
The source electrode of the first PMOS switching tube MSP1 is connected with BST1, the grid electrode is a control signal G1, and the drain electrode is connected with BST 3; the source electrode of the second PMOS switch tube MSP2 is connected with BST2, the grid electrode is a control signal G2, and the drain electrode is connected with BST 4; the source electrode of the third PMOS switch tube MSP3 is connected with BST3, the grid electrode is a control signal G3, and the drain electrode is connected with BST 5; the source electrode of the fourth PMOS switch tube MSP4 is connected with BST4, the grid electrode is a control signal G4, and the drain electrode is connected with BST 6.
The source electrode of the first NMOS switch tube MSN1 is connected with the output end V of the third low dropout linear voltage regulator module LDO3 DR And an anode, gate of the first regulator DB1Electrode and seventh bootstrap driving capacitance C Boot7 The drain electrode is connected to the input end of the first floating-ground low dropout linear regulator LDO 1; the source electrode of the second NMOS switch tube MSN2 is connected with the output end V of the third low dropout linear voltage regulator module LDO3 DR And the anode, the grid and the eighth bootstrap driving capacitor C of the second voltage stabilizing tube DB2 Boot8 The drain electrode is connected to the input end of the second floating-ground low dropout linear regulator LDO 2.
The input end of the first floating-ground low dropout linear regulator LDO1 is connected with the drain electrode of the first NMOS switch tube MSN1, the output end is connected to BST5, and the ground end is connected with the switch node SW 4 The method comprises the steps of carrying out a first treatment on the surface of the The input end of the second floating-ground low dropout linear regulator LDO2 is connected with the drain electrode of the second NMOS switch tube MSN2, the output end is connected to BST6, and the ground end is connected with the switch node SW 3 The method comprises the steps of carrying out a first treatment on the surface of the The input end of the third LDO3 is connected to the input voltage V of the converter IN The ground is grounded, the output end is connected with the source electrode of the first NMOS switch tube MSN1, the anode electrode of the first voltage stabilizing tube DB1, the source electrode of the second NMOS switch tube MSN2 and the anode electrode of the second voltage stabilizing tube DB2, wherein the output voltage V of the third low dropout linear voltage regulator module LDO3 DR As driving voltages for the control signals S1, S2, S3, S4, S5, S6, G5, G6.
The anode of the first voltage stabilizing tube DB1 is connected with the output voltage V of the third low dropout linear voltage regulator module LDO3 DR And the source electrode of the first NMOS switch tube MSN1, the cathode is connected with the seventh bootstrap driving capacitor C Boot7 Upper plate of (a); the anode of the second voltage stabilizing tube DB2 is connected with the output voltage V of the third low dropout linear voltage regulator module LDO3 DR And the source electrode of the second NMOS switch tube MSN2, the cathode is connected with the eighth bootstrap driving capacitor C Boot8 Is arranged on the upper polar plate of the upper polar plate.
The input end of the first inverter INV1 is a control signal G5, and the output end is connected with a seventh bootstrap driving capacitor C Boot7 The lower polar plate of the upper electrode is connected; the input end of the second inverter INV2 is a control signal G6, and the output end is connected with the eighth bootstrap driving capacitor C Boot8 Is connected with the lower polar plate.
FIG. 2 shows the power of the mixed-mode dual-phase buck converter according to the present inventionThe circuit diagram of the stage topology comprises a first NMOS switch tube MN1, a second NMOS switch tube MN2, a third NMOS switch tube MN3, a fourth NMOS switch tube MN4, a fifth NMOS switch tube MN5, a sixth NMOS switch tube MN6 and a first flying capacitor C F1 Second flying capacitor C F2 First inductor L 1 Second inductance L 2 Output capacitance C OUT And a load resistor R LOAD . The converter combines the advantages of a switched capacitor converter and a traditional switched inductor converter, utilizes flying capacitors to reduce the voltage swing of a switch node, the average value of inductor current and inductor current ripple, and realizes the expansion of effective duty ratio and the improvement of energy conversion efficiency. In addition, two phases in the mixed mode double-phase converter provided by the invention work alternately, and the phase difference is 180 degrees, so that the equivalent switching frequency is doubled and the output ripple is reduced.
The mixed mode dual-phase buck converter provided by the invention has three working states, namely a State1 (State 1), a State2 (State 2) and a State3 (State 3), as shown in figure 3. In the operating state1, the switches S1, S4, S5 are opened, the switches S2, S3, S6 are closed, and the two flying capacitors C are known according to the characteristic that the capacitor voltage cannot be suddenly changed F1 And C F2 The voltages at both ends are V IN -V OUT At this time, the switch node SW 1 Is of the voltage V OUT Switch node SW 2 Is the input voltage V IN Switch node SW 3 The voltage of (2) is the output voltage V OUT Switch node SW 4 Is 2V OUT -V IN . In this state, the inductance L 1 And flying capacitor C F1 In series and by flying capacitor C F1 Charging, at this time, inductance L 1 The current on the capacitor increases linearly and is output to the output capacitor C through the switch S3 and the switch S6 OUT And a load resistor R LOAD . At the same time, inductance L 2 To the output capacitor C through the switch S6 OUT And a load resistor R LOAD Discharging, the current on it decreases linearly; flying capacitor C F2 From input voltage V IN Charging through switch S2 and simultaneously discharging through switch S6 to the output. In the operating state 2, the switches S2, S3, S6 are open, the switches S1, S4, S5 are closed,at this time, the switch node SW 1 Is the input voltage V IN Switch node SW 2 The voltage of (2) is the output voltage V OUT Switch node SW 3 Is 2V OUT -V IN Switch node SW 4 The voltage of (2) is the output voltage V OUT . At this time, the inductance L 1 And is applied to the output capacitor C via the switch S5 OUT And a load resistor R LOAD Discharging; flying capacitor C F1 From input voltage V IN Charging, the current of which likewise flows to the output via the switch S5. At the same time, inductance L 2 And flying capacitor C F2 In series and by flying capacitor C F2 Charging, at this time, inductance L 2 The current on increases linearly and flows through switch S4 and switch S5 to output capacitor C OUT And a load resistor R LOAD . In the operating state 3, the switches S3, S4 are opened and the switches S1, S2, S5, S6 are closed, at which time the switch node SW 1 、SW 2 Is the input voltage V IN Switch node SW 3 、SW 4 The voltage of (2) is the output voltage V OUT . Inductance L 1 And inductance L 2 All are in a discharge state, the current on the two is linearly reduced, and the current is discharged to the output through a switch S5 and a switch S6 respectively; flying capacitor C F1 And flying capacitor C F2 Are all input by the converter IN Charging, wherein charging current flows to the output capacitor C through the switch S5 and the switch S6 respectively OUT And a load resistor R LOAD 。
The three states of the mixed mode dual-phase buck converter power stage topology work sequentially in a state1, a state 3, a state 2 and a state 3, the three working states work circularly according to the sequence, the buck conversion of the converter is realized through the energy storage effect of an inductor and a capacitor, and the working waveform is shown in figure 4. When the control signal D1 is high and the control signal D2 is low, the converter is operated in State1 (State 1) and the switch node SW 1 Is of the voltage V OUT Switch node SW 2 Is the input voltage V IN Switch node SW 3 The voltage of (2) is the output voltage V OUT Switch node SW 4 Is 2V OUT -V IN The method comprises the steps of carrying out a first treatment on the surface of the Inductance L 1 The current on the capacitor increases linearly, flying capacitor C F1 Current and inductance L 1 The upper currents are equal in magnitude and opposite in direction; inductance L 2 The current on the capacitor decreases linearly and the flying capacitor C F2 The circuit is exponentially reduced, and the output current I OUT Increase and is inductance L 1 Current and inductance L 2 Current and flying capacitor C F2 The sum of the currents. When the control signals D1 and D2 are both low, the converter operates in State3 (State 3), and the switch node SW 1 、SW 2 Is the input voltage V IN Switch node SW 3 、SW 4 Is of the voltage V OUT The method comprises the steps of carrying out a first treatment on the surface of the Inductance L 1 、L 2 The current on the capacitor drops linearly, flying capacitor C F1 、C F2 The current on the current is reduced exponentially; output current I OUT From inductance L 1 、L 2 Current and flying capacitor C F1 、C F2 The current composition of the converter and gradually decreases when the converter is operating in state 3. When the control signal D1 is low and the control signal D2 is high, the converter is operated in State2 (State 2) and the switch node SW 1 Is of the voltage V IN Switch node SW 2 The voltage of (2) is the output voltage V OUT Switch node SW 3 Is 2V OUT -V IN Switch node SW 4 The voltage of (2) is the output voltage V OUT The method comprises the steps of carrying out a first treatment on the surface of the Inductance L 1 The current on drops linearly, flying capacitor C F1 The current on the current is exponentially reduced; simultaneous inductance L 2 The current on the capacitor increases linearly, flying capacitor C F2 Current and inductance L 2 The current I is output at the moment of the same magnitude and opposite directions OUT From inductance L 1 Current and inductance L 2 Current on and flying capacitor C F1 And the current composition is gradually increased in state 2.
As can be seen from the above-mentioned power stage topology operation mode and fig. 4, the output current of the mixed mode dual-phase buck converter according to the present invention is composed of inductor current and capacitor current, and is composed of flying capacitor C F1 And flying capacitor C F2 Can be calculated from the charge balance of the inductor current average I L Average value of load current I LOAD The relation of (2) satisfies
Figure BDA0003664477180000101
Wherein D is the duty cycle of the control signals D1 and D2 and its range satisfies 0<D<0.5. Therefore, the average value of the inductance current is effectively reduced, thereby greatly reducing the loss of the inductance DCR and improving the energy conversion efficiency. Meanwhile, the flying capacitor bears a part of voltage drop, so that the voltage swing of the switching node is reduced, and the switching loss caused by the switching process of the power switching tube is reduced. In addition, the voltage conversion ratio of the converter can be obtained by volt-second balance of the inductor as +. >
Figure BDA0003664477180000102
The range of the voltage conversion ratio of the converter is 0<CR<0.5, and compared with the traditional DC-DC buck converter, the effective duty ratio is expanded, and the higher voltage conversion ratio is realized.
Fig. 5 is a circuit diagram of an embodiment of the present invention, which includes two parts, namely a power stage topology circuit and a bootstrap driving circuit. The power stage topology circuit is the circuit shown in the above figure 2, and comprises six power switching tubes MN1, MN2, MN3, MN4, MN5 and MN6, and two flying capacitors C F1 、C F2 Two inductances L 1 、L 2 An output capacitor C OUT And a load resistor R LOAD . The bootstrap driving circuit comprises six driving modules DRV1, DRV2, DRV3, DRV4, DRV5 and DRV6, six potential shifting modules LS1, LS2, LS3, LS4, LS5 and LS6 and eight bootstrap driving capacitors C Boot1 、C Boot2 、C Boot3 、C Boot4 、C Boot5 、C Boot6 、C Boot7 、C Boot8 Four PMOS switching tubes MSP1, MSP2, MSP3 and MSP4, two NMOS switching tubes MSN1 and MSN2, two floating-ground low dropout linear voltage regulator modules LDO1 and LDO2, one low dropout linear voltage regulator module LDO3, and two voltage regulator tubes DB1 and DB2And two inverters INV1, INV2.
Specifically, the bootstrap driving circuit has three working states, namely a State1 (State 1), a State2 (State 2) and a State3 (State 3), respectively, and is cooperated with the three working states of the power stage topology circuit to realize the bootstrap driving of the power tube in the power stage topology. The six driving modules DRV1, DRV2, DRV3, DRV4, DRV5, DRV6 are respectively used as on-off driving circuits of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 in the power stage topology circuit. The first level shift module LS1 shifts the control signal S1 from the driving voltage V DR To ground voltage domain shift to BST1 to SW 1 The voltage domain, the second level shift module LS2 shifts the control signal S2 from the driving voltage V DR To ground voltage domain shift to BST2 to SW 2 The third level shift module LS3 shifts the control signal S3 from the driving voltage V DR To ground voltage domain shift to BST3 to SW 3 The fourth voltage shift module LS4 shifts the control signal S4 from the driving voltage V DR To ground voltage domain shift to BST4 to SW 4 The fifth voltage shift module LS5 shifts the control signal S5 from the driving voltage V DR To ground voltage domain shift to BST5 to SW 5 The sixth voltage shift module LS6 shifts the control signal S6 from the driving voltage V DR To ground voltage domain shift to BST6 to SW 6 Voltage domain. First bootstrap driving capacitor C Boot1 The third bootstrap capacitor C is driven by the control of the first PMOS switch tube MSP1 Boot3 Charging, wherein the voltage at two ends of the first NMOS transistor serves as the power supply voltage and the ground voltage of the first driving module DRV1 to drive the first NMOS transistor MN1, so that bootstrap driving of the first NMOS transistor MN1 is realized; second bootstrap driving capacitance C Boot2 The fourth bootstrap capacitor C is driven by the control of the second PMOS switch tube MSP2 Boot4 Charging, wherein the voltage at two ends of the second NMOS transistor serves as the power supply voltage and the ground voltage of the second driving module DRV2 to drive the second NMOS transistor MN2, so that bootstrap driving of the second NMOS transistor MN2 is realized; third bootstrap driving capacitor C Boot3 The capacitor C is driven by the fifth bootstrap by the control of the third PMOS switch tube MSP3 Boot5 Charging the battery with the voltage at both endsThe third NMOS tube MN3 is driven by the power supply voltage and the ground voltage of the third driving module DRV3, so that bootstrap driving of the third NMOS tube MN3 is realized; fourth bootstrap driving capacitance C Boot4 The capacitor C is driven by a sixth bootstrap by the control of the fourth PMOS switch tube MSP4 Boot6 Charging, wherein the voltage at two ends of the charging is used as the power supply voltage and the ground voltage of the fourth driving module DRV4 to drive the fourth NMOS tube MN4, so that bootstrap driving of the fourth NMOS tube MN4 is realized; fifth bootstrap driving capacitance C Boot5 The first floating-ground low-dropout linear regulator module LDO1 charges under the control of the first NMOS switch tube MSN1, and the voltage difference between two ends is the driving voltage V DR The fifth NMOS tube MN5 is driven by the power supply voltage and the ground voltage of the fifth driving module DRV5, so that bootstrap driving of the fifth NMOS tube MN5 is realized; sixth bootstrap driving capacitance C Boot6 The second floating-ground low-dropout linear regulator module LDO2 charges under the control of the second NMOS switch tube MSN2, and the voltage difference between two ends is the driving voltage V DR The power supply voltage and the ground voltage of the sixth driving module DRV6 are used for driving the sixth NMOS tube MN6, so that bootstrap driving of the sixth NMOS tube MN6 is realized; seventh bootstrap driving capacitance C Boot7 From input voltage V IN The bootstrap driving of the first NMOS switch tube MSN1 is realized through the charging of the first voltage stabilizing tube DB 1; eighth bootstrap driving capacitance C Boot8 From input voltage V IN The bootstrap driving of the second NMOS switching tube MSN2 is realized by the charging of the second voltage stabilizing tube DB 2.
When the control signal D1 is at a high level and the control signal D2 is at a low level, both the bootstrap driving circuit and the power stage topology operate in State1 (State 1), as shown in fig. 6. In this working state, the first NMOS MN1 is turned off, so the first driving module DRV1 and the first potential shifting module LS1 do not work, the third NMOS MN3 and the first PMOS MSP1 are turned on, and the third bootstrap capacitor C Boot3 The first bootstrap capacitor C is connected to the first PMOS switch tube MSP1 through the first PMOS switch tube MSP1 Boot1 Charging and supplying power to the third driving module DRV3 and the third potential shifting module LS 3. Meanwhile, since the second NMOS tube MN2 is conducted with the sixth NMOS tube MN6 in the state1, the second bootstrap capacitor C Boot2 And a sixth bootstrap capacitor C Boot6 The second driving module DRV2, the second potential translation module LS2, the sixth driving module DRV6 and the sixth potential translation module LS6 are respectively powered. In addition, since the first NMOS switch tube MSN1 is turned on, the output voltage V of the third LDO3 is DR The fifth bootstrap driving capacitor C is provided by the first floating-ground low dropout linear regulator module LDO1 Boot5 At this time, the first regulator DB1 is reverse biased and is turned off. At the same time, the second NMOS switch tube MSN2 is turned off, the second voltage stabilizing tube DB2 is in a forward bias state, and the output voltage V of the third low dropout linear voltage stabilizer module LDO3 DR The eighth bootstrap driving capacitor C is provided by the second voltage stabilizing tube DB2 Boot8 And (5) charging.
When the control signal D1 is at a low level and the control signal D2 is at a high level, both the bootstrap driving circuit and the power stage topology operate in State2 (State 2), as shown in fig. 7. In this working state, the second NMOS MN2 is turned off, so the second driving module DRV2 and the second potential shifting module LS2 do not work, the fourth NMOS MN4 and the second PMOS MSP2 are turned on, and the fourth bootstrap capacitor C Boot4 The second bootstrap capacitor C is connected to the second bootstrap capacitor C through the second PMOS switching tube MSP2 Boot2 Charging and powering the fourth driving module DRV4 and the fourth potential translation module LS 4. Meanwhile, since the first NMOS tube MN1 and the fifth NMOS tube MN5 are conducted in the state2, the first bootstrap capacitor C Boot1 And a fifth bootstrap capacitor C Boot5 The first driving module DRV1, the first potential translation module LS1, the fifth driving module DRV5 and the fifth potential translation module LS5 are respectively powered. In addition, since the second NMOS switch tube MSN2 is turned on, the output voltage V of the third LDO3 is reduced DR The sixth bootstrap driving capacitor C is provided by the second floating-ground low dropout linear regulator module LDO2 Boot6 At this time, the second regulator DB2 is reverse biased and is turned off. At the same time, the first NMOS switch tube MSN1 is turned off, the first voltage stabilizing tube DB1 is in a forward bias state, and the output voltage V of the third low dropout linear voltage regulator module LDO3 DR The seventh bootstrap driving capacitor C is provided by the first voltage stabilizing tube DB1 Boot7 And (5) charging.
When the control signals D1 and D2 are low powerAt ordinary times, the bootstrap driving circuit and the power stage topology circuit both operate in State3 (State 3), as shown in fig. 8. At this time, the first bootstrap capacitor C is formed by conducting the first NMOS transistor MN1 and the second NMOS transistor MN2 Boot1 And a second bootstrap capacitor C Boot2 The first driving module DRV1, the first potential translation module LS1, the second driving module DRV2 and the second potential translation module LS2 are respectively powered. At the same time, the fifth NMOS tube MN5 is conducted with the third PMOS switch tube MSP3, and the fifth bootstrap capacitor C Boot5 The third bootstrap capacitor C is used as the third bootstrap capacitor C through a third PMOS switching tube MSP3 Boot3 Charging and simultaneously supplying power to the fifth driving module DRV5 and the fifth potential shifting module LS 5. Similarly, the sixth NMOS transistor MN6 is turned on with the fourth PMOS switch transistor MSP4, and the sixth bootstrap capacitor C Boot6 The fourth bootstrap capacitor C is provided by a fourth PMOS switch tube MSP4 Boot4 Charging and simultaneously supplying power to the sixth driving module DRV6 and the sixth potential shifting module LS 6. In this state, the first NMOS switch MSN1 and the second NMOS switch MSN2 are turned off, the first voltage regulator DB1 and the second voltage regulator DB2 are both in a forward bias state, and the output voltage V of the third low dropout linear regulator module LDO3 is at this time DR The seventh bootstrap capacitor C is respectively formed by the first voltage stabilizing tube DB1 and the second voltage stabilizing tube DB2 Boot7 And an eighth bootstrap capacitor C Boot8 And (5) charging.
FIG. 9 is a timing logic diagram of control signals according to an embodiment of the present invention. The S1, S2, S3, S4, S5 and S6 are input control signals of a first potential translation module LS1, a second potential translation module LS2, a third potential translation module LS3, a fourth potential translation module LS4, a fifth potential translation module LS5 and a sixth potential translation module LS6 respectively; TG (TG) 1 、TG 2 、TG 3 、TG 4 、TG 5 、TG 6 Gate signals of the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are respectively obtained; g1, G2, G3 and G4 are gate signals of the first PMOS switch tube MSP1, the second PMOS switch tube MSP2, the third PMOS switch tube MSP3 and the fourth PMOS switch tube MSP4 respectively, and G5 and G6 are input signals of the first inverter INV1 and the second inverter INV2 respectively.
When the control signal D1 is at a high level and the control signal D2 is at a low level, the converter operates in the state 1, and at this time, the first NMOS transistor MN1, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are turned off, and the second NMOS transistor MN2, the third NMOS transistor MN3 and the sixth NMOS transistor MN6 are turned on, so that S1, S4 and S5 are at a low level, and S2, S3 and S6 are at a high level. In this state, TG 1 Is of the voltage V OUT ，TG 2 Is of the voltage V IN +V DR ，TG 3 Is of the voltage V OUT +V DR ，TG 4 Is 2V IN -V OUT ，TG 5 Is 2V IN -V OUT ，TG 6 Is of the voltage V OUT +V DR The voltage of G1 is V OUT The voltage of G2 is V IN +V DR The voltage of G3 is V OUT +V DR The voltage of G4 is 2V IN -V OUT +V DR The voltage of G5 is 0 and the voltage of G6 is V DR 。
When the control signals D1 and D2 are both low, the converter operates in state 3, and at this time, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on, so that S3 and S4 are low, and S1, S2, S5 and S6 are high. In this state, TG 1 Is of the voltage V IN +V DR ，TG 2 Is of the voltage V IN +V DR ，TG 3 Is of the voltage V OUT ，TG 4 Is of the voltage V OUT ，TG 5 Is of the voltage V OUT +V DR ，TG 6 Is of the voltage V OUT +V DR The voltage of G1 is V IN +V DR The voltage of G2 is V IN +V DR The voltage of G3 is V OUT The voltage of G4 is V OUT The voltage of G5 is V DR The voltage of G6 is V DR 。
When the control signal D1 is low and the control signal D2 is high, the converter operates in state 2, and the second, third and sixth NMOS transistors MN2, MN3 and MN6 are turned off, and the first, fourth and fifth NMOS transistors MN1, MN4 and MN5 are turned on, so that S2, S3 and S6 are low and S1, S4 and S5 are low Is high. In this state, TG 1 Is of the voltage V IN +V DR ，TG 2 Is of the voltage V OUT ，TG 3 Is 2V IN -V OUT ，TG 4 Is of the voltage V OUT +V DR ，TG 5 Is of the voltage V OUT +V DR ，TG 6 Is 2V IN -V OUT The voltage of G1 is V IN +V DR The voltage of G2 is V OUT The voltage of G3 is 2V IN -V OUT +V DR The voltage of G4 is V OUT +V DR The voltage of G5 is V DR The voltage of G6 is 0.
From the above detailed description, it is apparent that: the mixed mode biphase buck converter with high voltage transformation ratio reduces inductance average current through the flying capacitor, thereby improving the energy conversion efficiency of the converter. Meanwhile, the voltage swing of the switch node of the converter is greatly reduced through the action of the flying capacitor, the expansion of the effective duty ratio is realized, and under the condition that the duty ratio of control signals is the same, the voltage conversion ratio is higher than that of the traditional DC-DC converter. On the other hand, the biphase output characteristic of the converter improves the output current capacity of the converter, so that the equivalent switching frequency is increased to twice that of a traditional DC-DC converter, and meanwhile, inductance current ripple and output ripple are reduced, so that the energy conversion efficiency of the converter is further improved. Due to the high voltage bit-changing property and the biphase output property, the high voltage bit-changing ratio mixed mode biphase buck converter provided by the invention is more suitable for the application under the conditions of high voltage bit-changing ratio, high switching frequency and large output current.

Claims (1)

1. The mixed mode biphase power converter with high voltage transformation ratio is characterized by comprising a power stage topology and a bootstrap driving circuit;
the power stage topology includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first flying capacitor C F1 Second flying capacitor C F2 First inductor L 1 Second inductance L 2 Output capacitance C OUT Load resistor R LOAD ；
Wherein, the source of the first NMOS transistor MN1 is connected with the drain of the third NMOS transistor MN3 and is connected to the first flying capacitor C F1 A gate of the first NMOS tube is connected with the output TG of the first driving module DRV1 1 The drain electrode of the first NMOS tube MN1 is connected with the input voltage V of the converter IN The method comprises the steps of carrying out a first treatment on the surface of the The source of the second NMOS transistor MN2 and the second flying capacitor C F2 Is connected with the drain electrode of the fourth NMOS tube MN4, the grid electrode of the second NMOS tube MN2 is connected with the output TG of the second driving module DRV2 2 The drain electrode of the second NMOS tube MN2 is connected with the input voltage V of the converter IN The method comprises the steps of carrying out a first treatment on the surface of the The source of the third NMOS transistor MN3 and the source of the sixth NMOS transistor NM6, and the second flying capacitor C F2 Is connected to the other end of the second inductor L 2 A gate of the third NMOS transistor MN3 is connected with the output TG of the third driving module DRV3 3 The method comprises the steps of carrying out a first treatment on the surface of the The source of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5 and the first flying capacitor C F1 Is connected with the other end of the first inductor L 1 A gate of the fourth NMOS transistor MN4 is connected with the output TG of the fourth driving module DRV4 4 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the fifth NMOS tube MN5 is connected with the output TG of the fifth driving module DRV5 5 The drain electrode of the fifth NMOS transistor MN5 is connected to the converter output terminal V OUT And is connected with the output capacitor C OUT Load resistor R LOAD Is connected with one end of the connecting rod; the grid electrode of the sixth NMOS tube MN6 is connected with the output TG of the sixth driving module DRV6 6 The drain of the sixth NMOS transistor MN6 is connected to the converter output terminal V OUT Simultaneously connected with the output capacitor C OUT Load resistor R LOAD Is a member of the group; first inductance L 1 Second inductance L 2 Output capacitance C OUT Load resistor R LOAD The other ends of the two electrodes are grounded;
the bootstrap driving circuit comprises a first PMOS switch tube MSP1, a second PMOS switch tube MSP2, a third PMOS switch tube MSP3, a fourth PMOS switch tube MSP4, a first NMOS switch tube MSN1, a second NMOS switch tube MSN2, a first driving module DRV1, a second driving module DRV2, a third driving module DRV3, a fourth driving module DRV4, a fifth driving module DRV5,Sixth driving module DRV6, first potential shift module LS1, second potential shift module LS2, third potential shift module LS3, fourth potential shift module LS4, fifth potential shift module LS5, sixth potential shift module LS6, and first bootstrap capacitor C Boot1 A second bootstrap capacitor C Boot2 Third bootstrap capacitor C Boot3 Fourth bootstrap capacitor C Boot4 Fifth bootstrap capacitor C Boot5 Sixth bootstrap capacitor C Boot6 Seventh bootstrap capacitor C Boot7 Eighth bootstrap capacitor C Boot8 The first voltage regulator DB1, the second voltage regulator DB2, the first inverter INV1, the second inverter INV2, the first floating-ground low-dropout linear regulator module LDO1, the second floating-ground low-dropout linear regulator module LDO2 and the third low-dropout linear regulator module LDO3;
wherein, the power end of the first driving module DRV1 is connected to the first bootstrap capacitor C Boot1 The ground end of the first driving module DRV1, the source electrode of the first NMOS tube MN1 and the first bootstrap capacitor C Boot1 The input end of the first driving module DRV1 is connected to the output of the first potential translation module LS1, and the output of the first driving module DRV1 is connected to the grid electrode of the first NMOS tube MN 1; the power end of the second driving module DRV2 is connected to the second bootstrap capacitor C Boot2 The ground end of the second driving module DRV2, the source electrode of the second NMOS tube MN2 and the second bootstrap capacitor C Boot2 The input end of the second driving module DRV2 is connected to the output of the second potential translation module LS2, and the output of the second driving module DRV2 is connected to the grid electrode of the second NMOS tube MN 2; the power end of the third driving module DRV3 is connected to the third bootstrap capacitor C Boot3 The ground end of the third driving module DRV3, the source electrode of the third NMOS tube MN3 and the third bootstrap capacitor C Boot3 The input end of the third driving module DRV3 is connected to the output of the third potential translation module LS3, and the output of the third driving module DRV3 is connected to the grid electrode of the third NMOS tube MN 3; the power end of the fourth driving module DRV4 is connected to the fourth bootstrap capacitor C Boot4 The ground of the fourth driving module DRV4, the source of the fourth NMOS transistor MN4 and the fourth bootstrap circuitCapacitor C Boot4 The input end of the fourth driving module DRV4 is connected to the output of the fourth potential translation module LS4, and the output of the fourth driving module DRV4 is connected to the grid electrode of the fourth NMOS tube MN 4; the power supply end of the fifth driving module DRV5 is connected to the fifth bootstrap capacitor C Boot5 The ground of the fifth driving module DRV5, the source of the fifth NMOS MN5, and the fifth bootstrap capacitor C Boot5 The input end of the fifth driving module DRV5 is connected to the output of the fifth potential translation module LS5, and the output of the fifth driving module DRV5 is connected to the grid electrode of the fifth NMOS tube MN 5; the power supply end of the sixth driving module DRV6 is connected to the sixth bootstrap capacitor C Boot6 The ground of the sixth driving module DRV6, the source of the sixth NMOS transistor MN6, and the sixth bootstrap capacitor C Boot6 The input end of the sixth driving module DRV6 is connected to the output of the sixth potential translation module LS6, and the output of the sixth driving module DRV6 is connected to the grid electrode of the sixth NMOS tube MN 6;
the input power terminal of the first level shift module LS1 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the first potential translation module LS1 is connected to the first bootstrap capacitor C Boot1 The upper polar plate and the output ground end of the first potential translation module LS1 are connected with the source electrode of the first NMOS tube MN1, the input end of the first potential translation module LS1 is connected with the driving signal S1, and the output end of the first potential translation module LS1 is connected with the input end of the first driving module DRV 1;
the input power terminal of the second level shift module LS2 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the second potential translation module LS2 is connected to the second bootstrap capacitor C Boot2 The upper polar plate and the output ground end of the second NMOS tube MN2 are connected, the input end of the second potential translation module LS2 is connected with a driving signal S2, and the output end of the second potential translation module LS2 is connected to the input end of the second driving module DRV 2;
the input power terminal of the third level shift module LS3 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the third potential translation module LS3 is connected to the third bootstrap capacitor C Boot3 Upper polar plate and output ground end are connectedThe source electrode of the third NMOS tube MN3, the input end of the third potential translation module LS3 is connected with a driving signal S3, and the output end of the third potential translation module LS3 is connected to the input end of the third driving module DRV 3;
the input power terminal of the fourth level shift module LS4 is connected to the driving voltage V DR The input ground is grounded, and the output power end of the fourth potential translation module LS4 is connected to the fourth bootstrap capacitor C Boot4 The upper polar plate and the output ground end of the fourth NMOS tube MN4 are connected, the input end of the fourth potential translation module LS4 is connected with a driving signal S4, and the output end of the fourth potential translation module LS4 is connected to the input end of the fourth driving module DRV 4;
the input power terminal of the fifth level shift module LS5 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the fifth potential translation module LS5 is connected to the fifth bootstrap capacitor C Boot5 The upper polar plate and the output ground end of the fifth NMOS tube MN5 are connected, the input end of the fifth potential translation module LS5 is connected with a driving signal S5, and the output end of the fifth potential translation module LS5 is connected to the input end of the fifth driving module DRV 5;
the input power terminal of the sixth potential shift module LS6 is connected to the driving voltage V DR The input ground is grounded, and the output power supply end of the sixth potential translation module LS6 is connected to the sixth bootstrap capacitor C Boot6 The upper polar plate and the output ground end of the sixth NMOS tube MN6 are connected, the input end of the sixth potential translation module LS6 is connected with a driving signal S6, and the output end of the sixth potential translation module LS6 is connected to the input end of the sixth driving module DRV 6;
first bootstrap capacitor C Boot1 The upper polar plate of the first NMOS transistor MN1 is connected with the power end of the first driving module DRV 1; second bootstrap capacitor C Boot2 The upper polar plate of the second NMOS transistor MN2 is connected with the power end of the second driving module DRV 2; third bootstrap capacitor C Boot3 The upper polar plate of the first NMOS transistor is connected to the power end of the third driving module DRV3, and the lower polar plate of the first NMOS transistor is connected to the source electrode of the third NMOS transistor MN 3; fourth bootstrap capacitor C Boot4 The upper polar plate of the first transistor is connected to the power end of the fourth driving module DRV4, and the lower polar plate is connected to the fourth NMOS transistor MN4A source electrode; fifth bootstrap capacitor C Boot5 The upper polar plate of the first NMOS transistor is connected to the power end of the fifth driving module DRV5, and the lower polar plate of the first NMOS transistor is connected to the source electrode of the fifth NMOS transistor MN 5; sixth bootstrap capacitor C Boot6 The upper polar plate of the first NMOS transistor is connected to the power end of the sixth driving module DRV6, and the lower polar plate is connected to the source electrode of the sixth NMOS transistor MN 6; seventh bootstrap capacitor C Boot7 The upper polar plate of the first NMOS switch tube MSN1 is connected with the cathode of the first voltage stabilizing tube DB1, and the lower polar plate of the first NMOS switch tube MSN1 is connected with the output end of the first inverter INV 1; eighth bootstrap capacitor C Boot8 The upper polar plate of the second voltage stabilizing tube DB2 is connected with the cathode of the second NMOS switching tube MSN2, and the lower polar plate is connected with the output end of the second inverter INV 2;
source of first PMOS switch tube MSP1 and first bootstrap capacitor C Boot1 The upper polar plate of the first PMOS switch tube MSP1 is connected with a control signal G1, the drain electrode of the first PMOS switch tube MSP1 is connected with the source electrode of the third PMOS switch tube MSP3 and a third bootstrap capacitor C Boot3 The upper polar plate of the upper polar plate is connected; source electrode of second PMOS switch tube MSP2 and second bootstrap capacitor C Boot2 The upper polar plate of the second PMOS switch tube MSP2 is connected with a control signal G2, the drain electrode of the second PMOS switch tube MSP2 is connected with the source electrode of the fourth PMOS switch tube MSP4 and a fourth bootstrap capacitor C Boot4 The upper polar plate of the upper polar plate is connected; source electrode of third PMOS switch tube MSP3 and third bootstrap capacitor C Boot3 The upper polar plate of the third PMOS switch tube MSP3 is connected with a control signal G3, the drain electrode of the third PMOS switch tube MSP3 is connected with a fifth bootstrap capacitor C Boot5 The upper polar plate of the first floating ground low dropout linear regulator module LDO1 is connected with the output end of the first floating ground low dropout linear regulator module LDO; source of fourth PMOS switch tube MSP4 and fourth bootstrap capacitor C Boot4 The upper polar plate of the fourth PMOS switch tube MSP4 is connected with a control signal G4, the drain electrode of the fourth PMOS switch tube MSP4 is connected with a sixth bootstrap capacitor C Boot6 The upper polar plate of the second floating ground low dropout linear regulator module LDO2 is connected with the output end of the second floating ground low dropout linear regulator module LDO;
the source electrode of the first NMOS switch tube MSN1 is connected to the output end of the third LDO3 and the anode of the first voltage stabilizing tube DB1, and the grid electrode of the first NMOS switch tube MSN1 is connected to the cathode of the first voltage stabilizing tube DB1Seventh bootstrap capacitor C Boot7 The drain electrode of the first NMOS switch tube MSN1 is connected with the input end of the first floating-ground low-dropout linear regulator module LDO 1; the source electrode of the second NMOS switch tube MSN2 is connected to the output end of the third LDO3 and the anode of the second voltage stabilizing tube DB2, the grid electrode of the second NMOS switch tube MSN2 is connected to the cathode of the second voltage stabilizing tube DB2 and the eighth bootstrap capacitor C Boot8 The drain electrode of the second NMOS switch tube MSN2 is connected with the input end of the second floating ground low dropout linear voltage regulator module LDO 2;
the ground terminal of the first floating-ground low dropout linear regulator module LDO1 is connected to the fifth bootstrap capacitor C Boot5 Lower plate of (a); the ground terminal of the second floating-ground low dropout linear regulator module LDO2 is connected to the sixth bootstrap capacitor C Boot6 Lower plate of (a); the power end of the third low dropout linear regulator module LDO3 is connected with the input voltage V IN The ground terminal of the third low-dropout linear voltage regulator module LDO3 is grounded, and the output terminal of the third low-dropout linear voltage regulator module LDO3 is connected to the source electrode of the first NMOS switch tube MSN1, the anode electrode of the first voltage regulator tube DB1, the source electrode of the second NMOS switch tube MSN2 and the anode electrode of the second voltage regulator tube DB 2;
an input end of the first inverter INV1 is connected with the control signal G5, and an output end is connected with the seventh bootstrap capacitor C Boot7 Lower plate of (a); the input end of the second inverter INV2 is connected with the control signal G6, and the output end is connected with the eighth bootstrap capacitor C Boot8 Is arranged on the lower polar plate.
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