CN116505774B - Hybrid buck converter with fast transient high voltage conversion ratio - Google Patents

Hybrid buck converter with fast transient high voltage conversion ratio Download PDF

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Publication number
CN116505774B
CN116505774B CN202310796464.7A CN202310796464A CN116505774B CN 116505774 B CN116505774 B CN 116505774B CN 202310796464 A CN202310796464 A CN 202310796464A CN 116505774 B CN116505774 B CN 116505774B
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power tube
power
inductor
tube
flying capacitor
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CN116505774A (en
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李斌
蔡浩鑫
吴朝晖
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South China University of Technology SCUT
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South China University of Technology SCUT
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a hybrid buck converter with a fast transient high voltage conversion ratio, which aims at solving the problems of slower transient response and larger undershoot voltage of a DSD architecture in the prior art. Comprises a first inductor and a second inductor; the first inductor and the second inductor are respectively arranged in two crossed branches, the current input of the two branches is obtained from input voltage or from the ground, and the current of the two branches is output through the load module. The switching device has the advantages that the duty ratio is larger under the same voltage conversion ratio, so that the switching device can be applied to higher switching frequency, and the inductance size and the output ripple are reduced. In transient state, the first inductor and the second inductor are charged simultaneously through state superposition, the maximum slew rate of the inductor current is increased by two times, and the charging current supplied to the output capacitor is rapidly increased, so that undershoot voltage is reduced.

Description

Hybrid buck converter with fast transient high voltage conversion ratio
Technical Field
The invention relates to a voltage conversion device, in particular to a hybrid buck converter with a fast transient high voltage conversion ratio.
Background
The server requires a large number of high-performance CPUs to complete a huge data processing, with a supply voltage in the low voltage domain between 0.8V and 1.8V. With the high-speed development of new technologies such as big data, cloud computing and internet of things, in order to alleviate path loss caused by rapid increase of load current, bus voltage needs to develop to a higher voltage domain, so that a buck converter bridging a bus and a load needs to cope with challenges of a higher voltage conversion ratio.
Fig. 1 is a schematic diagram of a conventional half bridge buck converter, in which a high input voltage makes it necessary to use high-voltage tubes capable of withstanding the input voltage for both the upper and lower power tubes in an application scenario of a high voltage conversion ratio. The parasitic capacitance and the on-resistance of the high-voltage tube are larger, and the on-loss and the switching loss are multiplied. And secondly, the conduction time of the upper tube in a steady state is inversely proportional to the input voltage, and the conduction time of the upper tube is extremely small when the high voltage conversion ratio is realized. Therefore, the conventional half-bridge buck converter is greatly affected by driving and loop delay, and the influence is aggravated by the large delay caused by the large parasitic capacitance of the high-voltage tube. To reduce the effect of the delay, increasing the on-time can only reduce the switching frequency, but this in turn leads to the use of large inductances and to a deterioration of the ripple. In addition, the inductor is positioned on the output current path, and the current flowing through the inductor is load current, so that the direct current loss of the inductor is extremely large.
Fig. 2 is a schematic diagram of a conventional DSD buck converter (DSD) configured by using a Dual inductor to shunt current and a branch of the Dual inductor is serially connected to a flying capacitor. The working process is as shown in fig. 3 to 5, and the working state changes cyclically: s11→s13→s12→s13→s11.
The DSD structure has the following advantages:
1) V CF0 =1/2 V IN the voltage stress of M1, M3 and M4 can be reduced from V IN Reduced to 1/2V IN ；
2) V O /V IN =d/2, the duty cycle D is twice that of a conventional buck converter;
3) The inductor current is reduced to half of the load current;
4) The currents of the two inductors can realize self-balancing.
The defects are as follows:
1) M2 still requires the use of tolerating V IN High pressure tube of (2);
2) D<0.5, limited duty cycle range, maximum slew rate of inductor currentThe transient response is slower and the undershoot voltage is greater.
Disclosure of Invention
The present invention is directed to a hybrid buck converter with fast transient high voltage conversion ratio to solve the above problems of the prior art.
The invention discloses a hybrid buck converter with a fast transient high voltage conversion ratio, which comprises a first inductor and a second inductor; the first inductor and the second inductor are respectively arranged in two crossed branches, the current input of the two branches is obtained from input voltage or from the ground, and the current of the two branches is output through the load module;
the specific structure is as follows:
one of the branches:
the drain electrode of the first power tube is connected with the input voltage, and the source electrode of the first power tube is respectively connected with the drain electrode of the fourth power tube and the first polar plate of the first flying capacitor;
the source electrode of the fourth power tube is respectively connected with the drain electrode of the fifth power tube and the drain electrode of the eighth power tube;
the source electrode of the fifth power tube is grounded;
the source electrode of the eighth power tube is respectively connected with the first polar plate of the fourth flying capacitor and the drain electrode of the twelfth power tube;
the source electrode of the twelfth power tube is respectively connected with the output end of the second inductor and the first polar plate of the output capacitor;
the source electrode of the tenth power tube is grounded, and the drain electrode of the tenth power tube is respectively connected with the second polar plate of the fourth flying capacitor and the input end of the second inductor;
the second plate of the first flying capacitor is connected with the drain electrode of the seventh power tube;
another branch:
the drain electrode of the second power tube is connected with the input voltage, and the source electrode of the second power tube is respectively connected with the drain electrode of the third power tube and the first polar plate of the second flying capacitor;
the source electrode of the third power tube is respectively connected with the drain electrode of the sixth power tube and the drain electrode of the seventh power tube;
the source electrode of the sixth power tube is grounded;
the source electrode of the seventh power tube is respectively connected with the first polar plate of the third flying capacitor and the drain electrode of the eleventh power tube;
the source electrode of the eleventh power tube is respectively connected with the output end of the first inductor and the first polar plate of the output capacitor;
the source electrode of the ninth power tube is grounded, and the drain electrode of the ninth power tube is respectively connected with the second polar plate of the third flying capacitor and the input end of the first inductor;
the second plate of the second flying capacitor is connected with the drain electrode of the eighth power tube;
the load resistor is connected in parallel with two ends of the output capacitor, and the voltage of the first polar plate of the output capacitor is the output voltage;
the grid electrodes of the power tubes are respectively and independently externally connected with control voltage.
The gate control voltage timing sequence of each power tube is specifically as follows:
in the first 1/4 period, the grid voltages of the first power tube, the third power tube, the fifth power tube, the seventh power tube, the tenth power tube and the twelfth power tube are all high, and the grid voltages of the second power tube, the fourth power tube, the sixth power tube, the eighth power tube, the ninth power tube and the eleventh power tube are all low;
in the second 1/4 period, the grid voltages of the ninth power tube, the tenth power tube, the eleventh power tube and the twelfth power tube are all high, and the grid voltages of the first power tube, the second power tube, the third power tube, the fourth power tube, the fifth power tube, the sixth power tube, the seventh power tube and the eighth power tube are all low;
the third 1/4 cycle is inverted from the first 1/4 cycle;
the fourth 1/4 cycle is in phase with the second 1/4 cycle.
The hybrid buck converter with the fast transient high voltage conversion ratio has the advantages that the duty ratio is larger under the same voltage conversion ratio, so that the hybrid buck converter can be applied to higher switching frequency, and the inductance size and the output ripple are reduced. In transient state, the first inductor and the second inductor are charged simultaneously through state superposition, the maximum slew rate of the inductor current is increased by two times, and the charging current supplied to the output capacitor is rapidly increased, so that undershoot voltage is reduced.
Drawings
Fig. 1 is a schematic diagram of a prior art half bridge buck converter.
Fig. 2 is a schematic diagram of a prior art DSD hybrid buck converter.
Fig. 3 is a schematic diagram of the current direction of the DSD hybrid buck converter operating state S11 shown in fig. 2.
Fig. 4 is a schematic diagram of the current direction of the DSD hybrid buck converter operating state S13 shown in fig. 2.
Fig. 5 is a schematic diagram of the current direction of the DSD hybrid buck converter operating state S12 shown in fig. 2.
Fig. 6 is a schematic diagram of the configuration of the hybrid buck converter of the present invention.
Fig. 7 is a schematic diagram of the current direction of the hybrid buck converter operating state S21 according to the present invention.
Fig. 8 is a schematic diagram of the current direction of the hybrid buck converter operating state S22 according to the present invention.
Fig. 9 is a schematic diagram of the current direction of the hybrid buck converter operating state S23 according to the present invention.
Fig. 10 is a schematic diagram of the current direction of the hybrid buck converter operating state S24 according to the present invention.
Fig. 11 is a timing diagram of a hybrid buck converter according to the present invention.
Reference numerals:
V IN : an input voltage;
V O : outputting a voltage;
V CF1 ～V CF4 : the voltages at two ends of the first to fourth flying capacitors;
V g1 ～V g12 : gate voltages of the first to twelfth power transistors;
I L1 、I L2 : current flowing through the first and second inductors;
I 1 、I 2 : the current direction of the working branch circuit where the first inductor and the second inductor are positioned; l (L) 1 ～L 2 : first to second inductors;
M 1 ～M 12 : first to twelfth power transistors;
C F1 ～C F4 : first to fourth flying capacitors;
C F0 : a fifth flying capacitor;
C O : an output capacitance;
R L : load resistance.
Detailed Description
As shown in fig. 6, a hybrid buck converter with a fast transient high voltage conversion ratio according to the present invention includes a first inductor L 1 And a second inductance L 2 The method comprises the steps of carrying out a first treatment on the surface of the First inductance L 1 And a second inductance L 2 Are respectively arranged in two crossed branches, and the current input of the two branches is controlled by the input voltage V IN The current of the two branches is output through the load module.
One of the branches: first power tube M 1 Is connected with the input voltage V IN First power tube M 1 The source electrodes of the power supply are respectively connected with a fourth power tube M 4 Drain of (C) and first flying capacitor C F1 Is a first plate of (a); fourth power tube M 4 The source electrodes of the power supply are respectively connected with a fifth power tube M 5 Drain electrode of (c) and eighth power tube M 8 A drain electrode of (2); fifth power tube M 5 The source electrode of the transistor is grounded; eighth power tube M 8 The source electrodes of the capacitors are respectively connected with a fourth flying capacitor C F4 First electrode plate and twelfth power tube M 12 A drain electrode of (2); twelfth power tube M 12 The source electrodes of the first and second inductors are respectively connected with the second inductor L 2 Output terminal of (2) and output capacitance C O Is a first plate of (a); tenth power tube M 10 Source electrode of the tenth power tube M is grounded 10 The drains of the capacitors are respectively connected with a fourth flying capacitor C F4 And a second electrode plate and a second inductance L 2 Is provided; first flying capacitor C F1 Is connected with a seventh power tube M 7 Is formed on the drain electrode of the transistor.
Another branch: second power tube M 2 Is connected with the input voltage V IN Second power tube M 2 The source electrodes of the power supply are respectively connected with a third power tube M 3 Drain of (C) and second flying capacitor C F2 Is a first plate of (a); third power tube M 3 The source electrodes of the power supply are respectively connected with a sixth power tube M 6 Drain electrode of (d) and seventh power tube M 7 A drain electrode of (2); sixth power tube M 6 The source electrode of the transistor is grounded; seventh power tube M 7 The source electrodes of the capacitors are respectively connected with a third flying capacitor C F3 First electrode plate and eleventh power tube M 11 A drain electrode of (2); eleventh power tube M 11 The source electrodes of the first inductor L are respectively connected with 1 Output terminal of (2) and output capacitance C O Is a first plate of (a); ninth power tube M 9 Source electrode of the ninth power tube M is grounded 9 The drains of the capacitors are respectively connected with a third flying capacitor C F3 And a first inductance L 1 Is provided; second flying capacitor C F2 Is connected with an eighth power tube M 8 Is formed on the drain electrode of the transistor.
Load resistor R L And output capacitance C O And the load module is formed by the following steps: load resistor R L Parallel connected to the output capacitor C O Two ends, output capacitor C O The voltage of the first polar plate is the output voltage V O 。
The grid electrodes of the power tubes are respectively and independently externally connected with control voltage.
The gate control voltage timing of each power tube is shown in fig. 11, and is specifically as follows:
in the first 1/4 period, the first power tube M 1 Third power tube M 3 Fifth power tube M 5 Seventh power tube M 7 Tenth power tube M 10 Twelfth power tube M 12 The gate voltages of the second power tube M are all high 2 Fourth power tube M 4 Sixth power tube M 6 Eighth power tube M 8 Ninth power tube M 9 Eleventh power tube M 11 The gate voltages of (2) are all low;
in the second 1/4 period, the ninth power tube M 9 Tenth power tube M 10 Eleventh power tube M 11 Twelfth power tube M 12 The gate voltages of the first power tube M are all high 1 Second power tube M 2 Third power tube M 3 Fourth power tube M 4 Fifth power tube M 5 Sixth power tube M 6 Seventh power tube M 7 Eighth power tube M 8 The gate voltages of (2) are all low;
the third 1/4 cycle is inverted from the first 1/4 cycle;
the fourth 1/4 cycle is in phase with the second 1/4 cycle.
Working principle:
the operation state S21 is shown in FIG. 7, the first power tube M 1 Third power tube M 3 Fifth power tube M 5 Seventh power tube M 7 Tenth power tube M 10 Twelfth power tube M 12 Conduction, second power tube M 2 Fourth power tube M 4 Sixth power tube M 6 Eighth power tube M 8 Ninth power tube M 9 Eleventh power tube M 11 And (5) switching off. Input voltage V IN Through a first flying capacitor C F1 Third flying capacitor C F3 To the first inductance L 1 And (5) charging. Second flying capacitor C F2 Fourth flying capacitor C F4 Discharge, second inductance L 2 Through a tenth power tube M 10 And (5) freewheeling.
The working state S22 is shown in FIG. 8, the second power tube M 2 Fourth power tube M 4 Sixth power tube M 6 Eighth power tube M 8 Ninth power tube M 9 Eleventh power tube M 11 Conduction, first power tube M 1 Third power tube M 3 Fifth power tube M 5 Seventh power tube M 7 Tenth power tube M 10 Twelfth power tube M 12 And (5) switching off. Input voltage V IN Through a second flying capacitor C F2 Fourth flying capacitor C F4 To the second inductance L 2 And (5) charging. First flying capacitor C F1 Third flying capacitor C F3 Discharging, first inductance L 1 Through a ninth power tube M 9 And (5) freewheeling.
Operating state S23 as shown in FIG. 9, ninth power tube M 9 Tenth power tube M 10 Eleventh power tube M 11 Twelfth power tube M 12 Conduction, first power tube M 1 Second power tube M 2 Third power tube M 3 Fourth power tube M 4 Fifth power tube M 5 Sixth power tube M 6 Seventh power tube M 7 Eighth power tube M 8 And (5) switching off. First inductance L 1 Second inductance L 2 Respectively through a ninth power tube M 9 Tenth power tube M 10 And (5) freewheeling. Third flying capacitor C F3 Fourth flying capacitor C F4 Discharge and first inductance L 1 Second inductance L 2 Forming a four-path discharge path.
The working state S24 is as shown in FIG. 10, the first power tube M 1 Second power tube M 2 Seventh power tube M 7 Eighth power tube M 8 Conduction, third power tube M 3 Fourth power tube M 4 Fifth power tube M 5 Sixth power tube M 6 Ninth power tube M 9 Tenth power tube M 10 Eleventh power tube M 11 Twelfth power tube M 12 And (5) switching off. Input voltage V IN Through a first flying capacitor C F1 Third flying capacitor C F3 To the first inductance L 1 Charging by a second flying capacitor C F2 Fourth flying capacitor C F4 To the second inductance L 2 And (5) charging.
In steady state, the working state is circularly switched from S21 to S23 to S22 to S23 to S21, the working state S21 and the working state S22 are out of phase by 180 degrees, the frequency of the output voltage is doubled, and the ripple wave is reduced.
According to volt-second equilibrium:it can be seen that the duty cycle is further extended based on DSD, and the on time is longer under the same VCR, so that it is more suitable for high voltage conversion ratio. VCR is the voltage conversion ratio.
In the transient state, the operating state S21 and the operating state S22 overlap to form an operating state S24. At this time, the first inductance L 1 And a second inductance L 2 Are all charging, and the maximum slew rate of the inductance currentTwice as much as the conventional DSD, is provided to the output capacitor C O The charging current of (c) increases rapidly, thereby reducing the undershoot voltage.
It will be apparent to those skilled in the art from this disclosure that various other changes and modifications can be made which are within the scope of the invention as defined in the appended claims.

Claims (2)

1. A hybrid buck converter with fast transient high voltage conversion ratio includes a first inductor (L 1 ) And a second inductance (L 2 ) The method comprises the steps of carrying out a first treatment on the surface of the Characterized in that the first inductance (L 1 ) And a second inductance (L 2 ) Are respectively arranged in two crossed branches, and the current input of the two branches is controlled by the input voltage (V IN ) The current of the two branches is output through the load module;
the specific structure is as follows:
one of the branches:
first power tube (M) 1 ) Is connected to the input voltage (V) IN ) First power tube (M 1 ) The source electrodes of the power supply are respectively connected with a fourth power tube (M 4 ) And a first flying capacitor (C) F1 ) Is a first plate of (a);
fourth power tube (M) 4 ) The source electrodes of the first and second power transistors are respectively connected with a fifth power tube (M 5 ) Drain of (c) and eighth power transistor (M 8 ) A drain electrode of (2);
fifth power tube (M) 5 ) The source electrode of the transistor is grounded;
eighth power tube (M) 8 ) The sources of the capacitor (C) are respectively connected with a fourth flying capacitor (C) F4 ) And a twelfth power tube (M) 12 ) A drain electrode of (2);
twelfth power tube (M) 12 ) The source electrodes of the first and second inductors are respectively connected with a second inductor (L 2 ) And output capacitance (C) O ) Is a first plate of (a);
tenth power tube (M) 10 ) Is grounded, a tenth power tube (M 10 ) The drains of the capacitors are respectively connected with a fourth flying capacitor (C F4 ) And a second electrode plate and a second inductance (L 2 ) Is provided;
first flying capacitor (C) F1 ) Is connected with a seventh power tube (M) 7 ) A drain electrode of (2);
another branch:
second power tube (M) 2 ) Is connected to the input voltage (V) IN ) Second power tube (M) 2 ) The source electrodes of the first and second power transistors are respectively connected with a third power tube (M 3 ) And a second flying capacitor (C) F2 ) Is a first plate of (a);
third power tube (M) 3 ) The source electrodes of the power supply are respectively connected with a sixth power tube (M 6 ) And a seventh power tube (M) 7 ) A drain electrode of (2);
sixth power tube (M) 6 ) The source electrode of the transistor is grounded;
seventh power tube (M) 7 ) The source electrodes of the capacitors are respectively connected with a third flying capacitor (C F3 ) And an eleventh power tube (M) 11 ) A drain electrode of (2);
eleventh power tube (M) 11 ) The source electrodes of the first inductor (L) 1 ) And output capacitance (C) O ) Is a first plate of (a);
ninth power tube (M) 9 ) Is grounded, a ninth power tube (M 9 ) The drains of the capacitors are respectively connected with a third flying capacitor (C F3 ) And a first inductance (L) 1 ) Is provided;
second flying capacitor (C) F2 ) Is connected with an eighth power tube (M) 8 ) A drain electrode of (2);
load resistor (R) L ) Connected in parallel with the output capacitor (C O ) Two ends, output capacitance (C O ) The voltage of the first polar plate is the output voltage (V O ）；
The grid electrodes of the power tubes are respectively and independently externally connected with control voltage.
2. The hybrid buck converter of claim 1, wherein the gate control voltage timing of each power transistor is as follows:
in the first 1/4 period, the first power tube (M 1 ) Third power tube (M) 3 ) Fifth power tube (M) 5 ) Seventh power tube (M) 7 ) Tenth power tube (M) 10 ) Twelfth power tube (M) 12 ) Is high, the second power tube (M 2 ) Fourth power tube (M) 4 ) Sixth power tube (M) 6 ) Eighth power tube (M) 8 ) Ninth power tube (M) 9 ) Eleventh power tube (M) 11 ) The gate voltages of (2) are all low;
in the second 1/4 cycle, the ninth power tube (M 9 ) Tenth power tube (M) 10 ) Eleventh power tube (M) 11 ) Twelfth power tube (M) 12 ) The gate voltages of the first power tube (M 1 ) Second power tube (M) 2 ) Third power tube (M) 3 ) Fourth power tube (M) 4 ) Fifth power tube (M) 5 ) Sixth power tube (M) 6 ) Seventh power tube (M) 7 ) Eighth power tube (M) 8 ) The gate voltages of (2) are all low;
the third 1/4 cycle is inverted from the first 1/4 cycle;
the fourth 1/4 cycle is in phase with the second 1/4 cycle.
CN202310796464.7A 2023-07-03 2023-07-03 Hybrid buck converter with fast transient high voltage conversion ratio Active CN116505774B (en)

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