JP2019205333A - Rapid transient response circuit applied to dc-dc converter - Google Patents
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Abstract
Description
本発明は電源管理分野を取り上げて、具体的にはDC-DCコンバータチップに適用する快速過渡応答回路である。 The present invention is a fast transient response circuit applied to a DC-DC converter chip, specifically in the field of power management.
直流−直流コンバータチップ（DC-DC converter chip）は高集積化と、大駆動電流と高効率などのメリットを有する。DC-DCコンバータチップは電源管理チップの中の非常に重要なモジュールである。携帯電子製品設備の普及につれて、DC-DCの性能にもより高い集積度と、より高い効率と、より良い過渡応答とより大きい出力電流という新たな要求を提出した。
DC-DCコンバータチップの過渡応答は負荷過渡応答と線形過渡応答とを含み、その負荷過渡応答は出力電流が急変する時に引き起こす出力電圧の変化状況を指し、線形過渡応答は入力電圧が急変する時に引き起こす出力電圧の変化状況を指す。DC-DCを使用することが多い携帯製品の中、一般的に入力電圧が急変することがまれであるが、負荷電流が急変することが普通であるので、DC-DCコンバータチップの負荷過渡応答に対しての研究が重要視されてきた。
電流モードのDC-DCコンバータには比較的に大きいオフチップフィルタコンデンサがあり、負荷ジャンプ時に「貯水池」のような作用を奏でき、出力電圧の波動を低下させることができ、しかし、電流モードDC-DCコンバータが天然に良好な過渡応答を有するというわけではない。実際に、以下の二つの原因が電流モードDC-DCコンバータの限られた過渡応答性能に繋がる。1）電圧ループの単位利得帯域幅が通常1/5のスイッチング周波数より小さく、DC-DCコンバータのスイッチング周波数が高くなく、一般的に2MHz以下であり、低帯域幅が過渡の応答速度を制限する；2）演算増幅器の出力端のPI零点補償には大きな電気容量が必要であり、低消費電力の設計の制約のもとで、当該電気容量は演算増幅器のスルーレートを制限する。これ以外に、電流モードDC-DCコンバータは本質的に非線形システムであるので、適用される快速過渡技術と汎用の線形システムとは相違する。
上記従来技術の欠点に基づき、電流モードbuck型DC-DCコンバータチップの快速過渡応答回路への改良と革新は現在の急務である。
A DC-DC converter chip has advantages such as high integration, large driving current and high efficiency. The DC-DC converter chip is a very important module in the power management chip. With the proliferation of portable electronic product facilities, DC-DC performance also submitted new requirements for higher integration, higher efficiency, better transient response and higher output current.
The transient response of a DC-DC converter chip includes a load transient response and a linear transient response. The load transient response refers to the output voltage change caused when the output current changes suddenly, and the linear transient response corresponds to when the input voltage changes suddenly. Refers to the change in the output voltage caused. Among portable products that often use DC-DC, the input voltage rarely changes suddenly, but the load current usually changes suddenly, so the load transient response of the DC-DC converter chip Research has been emphasized.
Current mode DC-DC converters have a relatively large off-chip filter capacitor that can act like a “reservoir” during load jumps and reduce the output voltage wave, but current mode DC -DC converters do not naturally have a good transient response. In fact, the following two causes lead to the limited transient response performance of current mode DC-DC converters. 1) Voltage loop unit gain bandwidth is usually less than 1/5 switching frequency, DC-DC converter switching frequency is not high, generally less than 2MHz, low bandwidth limits transient response speed 2) PI zero compensation at the output end of the operational amplifier requires a large capacitance, and the capacitance limits the slew rate of the operational amplifier under the constraints of low power consumption design. Besides this, current mode DC-DC converters are essentially non-linear systems, so the applied fast transient technology differs from general purpose linear systems.
Based on the above-mentioned drawbacks of the prior art, improvement and innovation of a current mode buck type DC-DC converter chip to a fast transient response circuit is an urgent task.
本発明は従来技術における問題に対して、DC-DCコンバータチップに適用する快速過渡応答回路を提案し、当該回路は消費電力が低く、安定性が良く、過渡応答に優れる等のメリットを有する。 The present invention proposes a rapid transient response circuit applied to a DC-DC converter chip for the problems in the prior art, and the circuit has advantages such as low power consumption, good stability, and excellent transient response.
上記の目的を実現するために、本発明が提供した技術プランは以下の通りである： In order to achieve the above object, the technical plan provided by the present invention is as follows:
電流モードbuck型DC-DCコンバータチップに適用する快速過渡応答回路は：誤差増幅器と、リミッタ回路と、マルチプレクサと過渡検出回路、その中、 The fast transient response circuit applied to the current mode buck type DC-DC converter chip is: error amplifier, limiter circuit, multiplexer, transient detection circuit, among them,
前記誤差増幅器が外部フィードバック入力と接続し、前記誤差増幅器が外部フィードバックを増幅し、また電圧安定信号を出力する； The error amplifier is connected to an external feedback input, the error amplifier amplifies the external feedback and outputs a voltage stabilization signal;
前記リミッタ回路が前記誤差増幅器と接続し、前記リミッタ回路の上限電圧はVHであり、下限電圧はVLであり、前記リミッタ回路が前記誤差増幅器の出力電圧安定信号をVLとVHの間に限定する； The limiter circuit is connected to the error amplifier, the upper limit voltage of the limiter circuit is VH, the lower limit voltage is VL, and the limiter circuit limits the output voltage stabilization signal of the error amplifier between VL and VH. ;
前記マルチプレクサが前記リミッタ回路と接続し、前記マルチプレクサが前記誤差増幅器の出力電圧安定信号をVHあるいはVLに設定する； The multiplexer connects to the limiter circuit, and the multiplexer sets the output voltage stabilization signal of the error amplifier to VH or VL;
前記過渡検出回路が前記誤差増幅器と接続し、前記過渡検出回路が前記誤差増幅器の内部ノードを検出し、負荷電流に過渡急変があるかどうかを判断することを含む。 The transient detection circuit is connected to the error amplifier, and the transient detection circuit detects an internal node of the error amplifier and determines whether or not there is a transient transient change in the load current.
更に、前記誤差増幅器は：差動増幅部分と、ソフトスタート部分と電気容量倍増器、その中、 Further, the error amplifier includes: a differential amplification part, a soft start part and a capacitance multiplier,
前記差動増幅部分はMOS型FETM11と、M12と、M13と、M14と、M15と、M16 と、M17と、M18とを含み、フィードバック電圧VfbがM11のゲートと接続し、基準電圧VrefがM12のゲートと接続し、M11のソースがM12のドレインと接続し、M11のドレインがM13のドレインとゲートと接続し且つM16のゲートと接続し、M13とM16とのソースが接地し、M12のソースが同時に前記ソフトスタート部分のMC12のソースと接続し、M12のドレインが同時に前記ソフトスタート部分のMC12と接続し、M14のドレインがM12のドレインと接続し、M14のソースが接地し、M14のゲートがVNノードを引き出し、M15のソースが電圧VDDと接続し、M15のゲートがVPノードを引き出し、M15のゲートがM17のゲートと接続し、M15のドレインがM16のドレインと接続し、M17のソースが電圧VDDと接続し、M17のドレインがM18のドレインと接続し、M18のゲートがM14のゲートと接続し、M18のソースが接地する； The differential amplification part includes MOS type FETs M11, M12, M13, M14, M15, M16, M17, and M18, the feedback voltage V fb is connected to the gate of M11, and the reference voltage V ref Is connected to the gate of M12, the source of M11 is connected to the drain of M12, the drain of M11 is connected to the drain and gate of M13 and the gate of M16, the sources of M13 and M16 are grounded, and M12 The source of M12 is simultaneously connected to the source of MC12 of the soft start portion, the drain of M12 is simultaneously connected to MC12 of the soft start portion, the drain of M14 is connected to the drain of M12, the source of M14 is grounded, and M14 Pull the gate V N nodes, the source of M15 is connected to the voltage V DD, pull the V P node gate of M15 is connected the gate of M15 is the gate of M17, connected to the drains of M15 is M16 and, source of M17 is connected to the voltage V DD, the drain of M17 is M18 de Connected to the Inn, the gate of M18 is connected to the gate of M14, the source of M18 to ground;
前記ソフトスタート部分はMOS型FETMC12と、コンデンサーC10とMOS型FETMB13とを含み、MC12のソースが前記差動増幅部分のM11とM12とのソースと接続し、MC12のドレインが前記差動増幅部分のM12と、M14とのドレインと接続し、C10がMC12のゲートと接続し、MB13のソースが電圧VDDと接続し、MB13のドレインがC10と接続し、C10が接地する； The soft start part includes a MOS type FET MC12, a capacitor C10 and a MOS type FET MB13, the source of MC12 is connected to the sources of M11 and M12 of the differential amplification part, and the drain of MC12 is the differential amplification part. Connected to the drains of M12 and M14, C10 connected to the gate of MC12, the source of MB13 connected to voltage V DD , the drain of MB13 connected to C10, and C10 grounded;
前記電気容量倍増器はMOS型FETM19、M100と、MOS型FETMB15、MB16と、コンデンサーCm1とを含み、M19のドレインがMB15のドレインと接続し、M19のゲートがM100のゲートと接続し、M19のソースが接地し、M100のドレインがMB16のドレインと接続し、M100のソースが接地し、MB15のソースが電圧VDDと接続し、MB16のソースが電圧VDDと接続し、コンデンサーCm1がMB14とM19とのドレインと接続し、及びコンデンサーCm1がM19とM100とのゲートと接続することを含む。 The capacitance multiplier includes MOS type FETs M19, M100, MOS type FETs MB15, MB16, and a capacitor Cm1, the drain of M19 is connected to the drain of MB15, the gate of M19 is connected to the gate of M100, Source grounded, M100 drain connected to MB16 drain, M100 source grounded, MB15 source connected to voltage V DD , MB16 source connected to voltage V DD, and capacitor Cm1 connected to MB14 It includes connecting to the drain of M19, and connecting the capacitor Cm1 to the gates of M19 and M100.
更に、前記リミッタ回路は第一演算増幅器と第二演算増幅器とを含み、その中第一演算増幅器はMOS型FETM21と、M22と、M23と、M24と、M25とを含み、第二演算増幅器はMOS型FETM26と、M27と、M28と、M29と、M210と、M211とを含み、前記MOS型FETM21のゲートが上限電圧VHと接続し、前記MOS型FETM27のゲートが下限電圧VLと接続し、M21のソースがM22のソースと接続し、M21のドレインがM23のドレインと接続し、M22のドレインがM24のドレインと接続し、M23のゲートがM24のゲートと接続し、M23のソースが接地し、M24のソースが接地し、M25のゲートがM22と、M24とのドレインと接続し、M25のソースがM22のゲートと接続し、M25のドレインが接地し、M26のゲートがM22のゲートと接続し、M26のソースがM27のソースと接続し、M26のドレインがM28のドレインと接続し、M27のドレインがM29のドレインと接続し、M28のゲートがM29のゲートと接続し、M28のソースが接地し、M29のソースが接地し、M210のゲートがM27と、M29とのドレインと接続し、M210のドレインがM211のゲートと接続し、M210のソースが接地し、M211のソースが接地する。 Further, the limiter circuit includes a first operational amplifier and a second operational amplifier, in which the first operational amplifier includes MOS type FETs M21, M22, M23, M24, and M25, and the second operational amplifier includes MOS type FET M26, M27, M28, M29, M210, M211, the gate of the MOS type FET M21 is connected to the upper limit voltage VH, the gate of the MOS type FET M27 is connected to the lower limit voltage VL, The source of M21 is connected to the source of M22, the drain of M21 is connected to the drain of M23, the drain of M22 is connected to the drain of M24, the gate of M23 is connected to the gate of M24, and the source of M23 is grounded The source of M24 is grounded, the gate of M25 is connected to the drain of M22 and M24, the source of M25 is connected to the gate of M22, the drain of M25 is grounded, and the gate of M26 is connected to the gate of M22 M26 source connected to M27 source, M26 drain connected to M28 drain, M27 drain connected to M29 Connected to rain, M28 gate connected to M29 gate, M28 source grounded, M29 source grounded, M210 gate connected to M27 and M29 drain, M210 drain connected to M211 The source of M210 is grounded and the source of M211 is grounded.
更に、前記過渡検出回路が前記誤差増幅器の中のVPノード及びVNノードと接続し、前記過渡検出回路が前記誤差増幅器の内部ノードVPとVNの電圧によって負荷電流に過渡急変があるかどうかを判断する。 Further, the transient detection circuit is connected to a V P node and a V N node in the error amplifier, and the transient detection circuit has a transient change in the load current due to the voltage of the internal nodes V P and V N of the error amplifier. Determine whether or not.
従来技術と比べ、本発明が提供した回路は消費電力が低く、安定性が良く、過渡応答に優れる等のメリットを有する。 Compared with the prior art, the circuit provided by the present invention has advantages such as low power consumption, good stability, and excellent transient response.
以下は付図と実施例を交え、本発明の具体実施方式について更に詳しく説明する。以下の実施例は本発明を説明するためのものであり、本発明の範囲を限定するものではない。 The following is a more detailed description of the specific implementation method of the present invention with reference to the accompanying drawings and examples. The following examples are intended to illustrate the present invention and are not intended to limit the scope of the invention.
図1に示すのは、本発明の電流モードbuck型DC-DCコンバータチップに適用する快速過渡応答回路の実施例であり、当該快速過渡応答回路は： FIG. 1 shows an example of a fast transient response circuit applied to the current mode buck type DC-DC converter chip of the present invention.
誤差増幅器と、リミッタ回路と、マルチプレクサと過渡検出回路、その中、 Error amplifier, limiter circuit, multiplexer and transient detection circuit,
前記誤差増幅器が外部フィードバック入力と接続し、前記誤差増幅器が外部フィードバックを増幅し、また電圧安定信号を出力する； The error amplifier is connected to an external feedback input, the error amplifier amplifies the external feedback and outputs a voltage stabilization signal;
前記リミッタ回路が前記誤差増幅器と接続し、前記リミッタ回路の上限電圧はVHであり、下限電圧はVLであり、前記リミッタ回路が前記誤差増幅器の出力電圧安定信号をVLとVHの間に限定する；前記マルチプレクサが前記リミッタ回路と接続し、前記マルチプレクサが前記誤差増幅器の出力電圧安定信号をVHあるいはVLに設定する； The limiter circuit is connected to the error amplifier, the upper limit voltage of the limiter circuit is VH, the lower limit voltage is VL, and the limiter circuit limits the output voltage stabilization signal of the error amplifier between VL and VH. The multiplexer is connected to the limiter circuit, and the multiplexer sets the output voltage stabilization signal of the error amplifier to VH or VL;
前記過渡検出回路が前記誤差増幅器と接続し、前記過渡検出回路が前記誤差増幅器の内部ノードを検出し、負荷電流に過渡急変があるかどうかを判断することを含む。 The transient detection circuit is connected to the error amplifier, and the transient detection circuit detects an internal node of the error amplifier and determines whether or not there is a transient transient change in a load current.
本実施例の中、前記誤差増幅器は：差動増幅部分と、ソフトスタート部分と電気容量倍増器、その中、 In this embodiment, the error amplifier includes: a differential amplification part, a soft start part and a capacitance multiplier,
前記差動増幅部分はMOS型FETM11と、M12と、M13と、M14と、M15と、M16 と、M17と、M18とを含み、フィードバック電圧VfbがM11のゲートと接続し、基準電圧VrefがM12のゲートと接続し、M11のソースがM12のドレインと接続し、M11のドレインがM13のドレインとゲートと接続し且つM16のゲートと接続し、M13とM16とのソースが接地し、M12のソースが同時に前記ソフトスタート部分のMC12のソースと接続し、M12のドレインが同時に前記ソフトスタート部分のMC12と接続し、M14のドレインがM12のドレインと接続し、M14のソースが接地し、M14のゲートがVNノードを引き出し、M15のソースが電圧VDDと接続し、M15のゲートがVPノードを引き出し、M15のゲートがM17のゲートと接続し、M15のドレインがM16のドレインと接続し、M17のソースが電圧VDDと接続し、M17のドレインがM18のドレインと接続し、M18のゲートがM14のゲートと接続し、M18のソースが接地する； The differential amplification part includes MOS type FETs M11, M12, M13, M14, M15, M16, M17, and M18, the feedback voltage V fb is connected to the gate of M11, and the reference voltage V ref Is connected to the gate of M12, the source of M11 is connected to the drain of M12, the drain of M11 is connected to the drain and gate of M13 and the gate of M16, the sources of M13 and M16 are grounded, and M12 The source of M12 is simultaneously connected to the source of MC12 of the soft start portion, the drain of M12 is simultaneously connected to MC12 of the soft start portion, the drain of M14 is connected to the drain of M12, the source of M14 is grounded, and M14 Pull the gate V N nodes, the source of M15 is connected to the voltage V DD, pull the V P node gate of M15 is connected the gate of M15 is the gate of M17, connected to the drains of M15 is M16 and, source of M17 is connected to the voltage V DD, the drain of M17 is M18 de Connected to the Inn, the gate of M18 is connected to the gate of M14, the source of M18 to ground;
前記ソフトスタート部分はMOS型FETMC12と、コンデンサーC10とMOS型FETMB13とを含み、MC12のソースが前記差動増幅部分のM11とM12とのソースと接続し、MC12のドレインが前記差動増幅部分のM12と、M14とのドレインと接続し、C10がMC12のゲートと接続し、MB13のソースが電圧VDDと接続し、MB13のドレインがC10と接続し、C10が接地する； The soft start part includes a MOS type FET MC12, a capacitor C10 and a MOS type FET MB13, the source of MC12 is connected to the sources of M11 and M12 of the differential amplification part, and the drain of MC12 is the differential amplification part. Connected to the drains of M12 and M14, C10 connected to the gate of MC12, the source of MB13 connected to voltage V DD , the drain of MB13 connected to C10, and C10 grounded;
前記電気容量倍増器はMOS型FETM19、M100と、MOS型FETMB15、MB16と、コンデンサーCm1とを含み、M19のドレインがMB15のドレインと接続し、M19のゲートがM100のゲートと接続し、M19のソースが接地し、M100のドレインがMB16のドレインと接続し、M100のソースが接地し、MB15のソースが電圧VDDと接続し、MB16のソースが電圧VDDと接続し、コンデンサーCm1がMB14とM19とのドレインと接続し、及びコンデンサーCm1がM19とM100とのゲートと接続することを含む。 The capacitance multiplier includes MOS type FETs M19, M100, MOS type FETs MB15, MB16, and a capacitor Cm1, the drain of M19 is connected to the drain of MB15, the gate of M19 is connected to the gate of M100, Source grounded, M100 drain connected to MB16 drain, M100 source grounded, MB15 source connected to voltage V DD , MB16 source connected to voltage V DD, and capacitor Cm1 connected to MB14 It includes connecting to the drain of M19, and connecting the capacitor Cm1 to the gates of M19 and M100.
本実施例の中、前記リミッタ回路は第一演算増幅器と第二演算増幅器とを含み、その中第一演算増幅器はMOS型FETM21と、M22と、M23と、M24と、M25とを含み、第二演算増幅器はMOS型FETM26と、M27と、M28と、M29と、M210と、M211とを含み、前記MOS型FETM21のゲートが上限電圧VHと接続し、前記MOS型FETM27のゲートが下限電圧VLと接続し、M21のソースがM22のソースと接続し、M21のドレインがM23のドレインと接続し、M22のドレインがM24のドレインと接続し、M23のゲートがM24のゲートと接続し、M23のソースが接地し、M24のソースが接地し、M25のゲートがM22と、M24とのドレインと接続し、M25のソースがM22のゲートと接続し、M25のドレインが接地し、M26のゲートがM22のゲートと接続し、M26のソースがM27のソースと接続し、M26のドレインがM28のドレインと接続し、M27のドレインがM29のドレインと接続し、M28のゲートがM29のゲートと接続し、M28のソースが接地し、M29のソースが接地し、M210のゲートがM27と、M29とのドレインと接続し、M210のドレインがM211のゲートと接続し、M210のソースが接地し、M211のソースが接地する。 In this embodiment, the limiter circuit includes a first operational amplifier and a second operational amplifier, in which the first operational amplifier includes MOS type FET M21, M22, M23, M24, and M25, The two operational amplifiers include MOS type FET M26, M27, M28, M29, M210, and M211. The gate of the MOS type FET M21 is connected to the upper limit voltage VH, and the gate of the MOS type FET M27 is connected to the lower limit voltage VL. The source of M21 is connected to the source of M22, the drain of M21 is connected to the drain of M23, the drain of M22 is connected to the drain of M24, the gate of M23 is connected to the gate of M24, The source is grounded, the source of M24 is grounded, the gate of M25 is connected to the drain of M22 and M24, the source of M25 is connected to the gate of M22, the drain of M25 is grounded, and the gate of M26 is M22 M26 source is connected to M27 source, M26 drain is connected to M28 drain, and M27 drain is connected. Is connected to the drain of M29, the gate of M28 is connected to the gate of M29, the source of M28 is grounded, the source of M29 is grounded, the gate of M210 is connected to the drain of M27 and M29, The drain is connected to the gate of M211, the source of M210 is grounded, and the source of M211 is grounded.
本実施例の中、前記過渡検出回路が前記誤差増幅器の中のVPノード及びVNノードと接続し、前記過渡検出回路が前記誤差増幅器の内部ノードVPとVNの電圧によって負荷電流に過渡急変があるかどうかを判断する。 In this embodiment, the transient detection circuit is connected to a V P node and a V N node in the error amplifier, and the transient detection circuit is connected to a load current by the voltages of the internal nodes V P and V N of the error amplifier. Determine if there is a transient change.
従来技術の電流モードbuck型DC-DCコンバータチップの全体構成回路図を図2に示し、出力電圧が抵抗分圧した後、誤差増幅器のマイナス入力端にフィードバックし、参照電圧と一緒に演算増幅器により差動増幅した後で小信号電圧安定信号VCが得られ、それと同時に、被誘導回路がインダクタを流れる電流を比例して誘導抵抗に注入して誘導電圧VSを形成する。誘導電圧が電圧安定信号と比較し、デューティレシオと比較結果とが相関するという制御信号を出力し、この制御信号がデッドタイムにより制御と駆動をされた後、PWMスイッチの電流を制御し、この電流がLCフィルタを流れた後で出力電圧を形成し、出力電圧を調節して安定させることを実現する。電流が検出されたインダクタ電流信号をデューティレシオ変調モジュールにフィードバックすることによってデューティレシオ信号dが得られ、dがPWMスイッチのオン時間を制御し、PWMスイッチがインダクタ電流を決定するので、このループが電流内部ループを構成するということが見られる。その他、ランプ生成回路が鋸波信号を生成して電流ループにランプ補償を行う。同様に、出力電圧Voutが分圧した後で信号を誤差増幅器のマイナス入力端に送り、誤差増幅器がVfbと基準電圧との誤差電圧を増幅し、また電圧安定信号VCをデューティレシオ変調モジュールに送ってPWMスイッチを制御し、PWMスイッチのブレークオーバー電流がRCフィルタを経由して出力電圧を形成し、これによって電圧外部ループを構成し、電圧ループに複数の極が存在しているので震蕩する可能性があり、直列接続されたRzとCzとが比例積分（Proportional Integral，PI）を形成して零点を補償することによってループ安定を実現することが必要になる。電流モードDC-DCコンバータの限られた単位利得帯域幅と誤差増幅器出力端のPI零点補償に必要な大電気容量はその過渡応答の性能を制限する。 The overall configuration circuit diagram of the current mode buck type DC-DC converter chip of the prior art is shown in FIG. A small signal voltage stabilization signal VC is obtained after differential amplification, and at the same time, the induced circuit proportionally injects the current flowing through the inductor into the induction resistor to form the induced voltage VS. The induced voltage is compared with the voltage stabilization signal, and a control signal that the duty ratio and the comparison result correlate is output. After this control signal is controlled and driven by the dead time, the current of the PWM switch is controlled, The output voltage is formed after the current flows through the LC filter, and the output voltage is adjusted and stabilized. By feeding back the detected inductor current signal to the duty ratio modulation module, the duty ratio signal d is obtained, where d controls the on-time of the PWM switch, and the PWM switch determines the inductor current, so this loop It can be seen that it constitutes a current inner loop. In addition, the ramp generation circuit generates a sawtooth signal and performs lamp compensation on the current loop. Similarly, after the output voltage Vout is divided, the signal is sent to the negative input terminal of the error amplifier, the error amplifier amplifies the error voltage between Vfb and the reference voltage, and sends the voltage stabilization signal VC to the duty ratio modulation module. Can control the PWM switch, and the breakover current of the PWM switch forms an output voltage via the RC filter, thereby forming a voltage external loop, which can be shaken because there are multiple poles in the voltage loop Therefore, Rz and Cz connected in series form a proportional integral (Proportional Integral, PI) and it is necessary to realize loop stability by compensating for the zero point. The limited unity gain bandwidth of the current mode DC-DC converter and the large capacitance required to compensate the PI zero at the error amplifier output limit its transient response performance.
本発明が提案した快速過渡応答を有する電流モードbuck型DC-DCコンバータチップの全体構成回路図を図1に示す。改善として、リミッタ回路が誤差増幅器の出力端と接続し、リミッタ回路の上限電圧はVHであり、下限電圧はVLであり、リミッタ回路を通して誤差増幅器の出力をVLとVHとの間に限定する。同時に過渡検出回路を利用して誤差増幅器の内部ノードを検査し、負荷電流に過渡急変があるかどうかを判断する。もし過渡期間に入れば、マルチプレクサを利用して、誤差増幅器の出力電圧VCをVHあるいはVLに設定する。具体的には、出力電流に突然低下が発生する時、出力電圧に過渡オーバーシュートが発生する可能性があり、電圧が上昇し、過渡検出回路により判断した後、マルチプレクサがVCをVLに設定し、VCが直接最低値まで低下し、これによってデューティレシオを快速に減少し、快速過渡応答を実現する；出力電流に突然上昇が発生する時、出力電圧に過渡アンダシュートが発生する可能性があり、電圧が低下し、過渡検出回路により判断した後、マルチプレクサがVCをVHに設定し、VHが直接最高値まで増大し、これによってデューティレシオを快速に増大し、快速過渡応答を実現する。リミッタ回路の存在は電圧ループの不安定を効果的に防止できる。 FIG. 1 shows an overall configuration circuit diagram of a current mode buck type DC-DC converter chip having a fast transient response proposed by the present invention. As an improvement, the limiter circuit is connected to the output terminal of the error amplifier, the upper limit voltage of the limiter circuit is VH, the lower limit voltage is VL, and the output of the error amplifier is limited between VL and VH through the limiter circuit. At the same time, the internal node of the error amplifier is inspected using the transient detection circuit to determine whether or not there is a sudden change in the load current. If the transition period is entered, the multiplexer outputs the error amplifier output voltage VC to VH or VL. Specifically, when the output current suddenly drops, a transient overshoot may occur in the output voltage. After the voltage rises and is judged by the transient detection circuit, the multiplexer sets VC to VL. , VC directly decreases to the lowest value, thereby rapidly reducing the duty ratio and achieving a rapid transient response; when output current suddenly rises, transient undershoot may occur in output voltage After the voltage drops and determined by the transient detection circuit, the multiplexer sets VC to VH and VH directly increases to the maximum value, thereby rapidly increasing the duty ratio and realizing a rapid transient response. The presence of the limiter circuit can effectively prevent voltage loop instability.
本発明が設計した誤差増幅器を図3に示す。誤差増幅器は主に差動増幅部分と、ソフトスタート部分と電気容量倍増器という三つの部分から構成される。その中、M11-M18が差動増幅回路を構成し、Vfbが出力電圧が抵抗分圧した後のフィードバック電圧であり、誤差増幅器の反転入力端に接続し、参照電圧Vrefが誤差増幅器の非反転入力端に接続する。MB11-MB16がカレントミラーを構成してすべての回路にバイアス電流を提供する。MC12と、C10とMB13とがソフトスタート回路を構成し、ソフトスタート回路が通電する過程において過大な誤差増幅器出力VCを防止でき、これによって回路を保護する。M19-M100と、MB15-MB16とCm1とが電気容量倍増器を構成し、RZ1とCm1との接続端から見ると、Cm1の等価容量は（1+k）Cm1であり、これによって電気容量の増大を実現し、この増大された電気容量とRZ1とが零点を構成し、ことによって出力端の極を補償する。内部ノードVPとVNとの電圧が過渡検出に用いられることは、図5で説明する。 An error amplifier designed by the present invention is shown in FIG. The error amplifier is mainly composed of three parts: a differential amplification part, a soft start part, and a capacitance multiplier. Among them, M11-M18 constitute a differential amplifier circuit, Vfb is the feedback voltage after the output voltage is divided by resistance, connected to the inverting input terminal of the error amplifier, and the reference voltage Vref is non-inverted of the error amplifier Connect to the input end. MB11-MB16 form a current mirror to provide bias current for all circuits. MC12, C10, and MB13 constitute a soft start circuit, and an excessive error amplifier output VC can be prevented in the process of energizing the soft start circuit, thereby protecting the circuit. M19-M100, MB15-MB16, and Cm1 constitute an electric capacity multiplier, and when viewed from the connection end of RZ1 and Cm1, the equivalent capacity of Cm1 is (1 + k) Cm1, which An increase is realized, and this increased capacitance and RZ1 form a zero, thereby compensating for the pole at the output end. The fact that the voltages at the internal nodes VP and VN are used for transient detection will be described with reference to FIG.
本発明が設計したリミッタ回路を図4に示す。リミッタ回路が二つの演算増幅器から構成され、その中にM21-M25が演算増幅器を構成し、M26-M211が演算増幅器を構成する。第一演算増幅器に対して、非反転入力端が上限電圧VHと接続し、反転入力端が演算増幅器出力端と接続し、同時に前述誤差増幅器の出力端VCと接続し、単位利得ネガティブフィードバックを形成する。VCがVHより大きい場合、M25が飽和領域で動作し、ループが十分な利得を提供し、VCがVHにクランプさせられ、VCがVHより小さい場合、M25がオフ領域で動作し、ループが提供する利得が有限であり、VCがVHにクランプされない。第二演算増幅器に対して、非反転入力端が下限電圧VLと接続し、反転入力端が演算増幅器出力端と接続し、同時に前記誤差増幅器の出力端VCと接続し、利得ネガティブフィードバックを形成する。VCがVLより小さい場合、M211が飽和領域で動作し、ループが十分な利得を提供し、VCがVLにクランプさせられ、VCがVLより大きい場合、M211がオフ領域で動作し、ループが提供する利得が有限であり、VCがVLにクランプされない。このような回路設計に基き、VCがVLとVHとの間に制限され、リミッティング機能を実現する。 FIG. 4 shows a limiter circuit designed by the present invention. The limiter circuit is composed of two operational amplifiers, in which M21 to M25 constitute an operational amplifier, and M26 to M211 constitute an operational amplifier. For the first operational amplifier, the non-inverting input terminal is connected to the upper limit voltage VH, the inverting input terminal is connected to the operational amplifier output terminal, and at the same time is connected to the output terminal VC of the error amplifier to form unit gain negative feedback. To do. If VC is greater than VH, M25 operates in the saturation region, the loop provides sufficient gain, VC is clamped to VH, and if VC is less than VH, M25 operates in the off region and the loop provides Gain is limited and VC is not clamped to VH. For the second operational amplifier, the non-inverting input terminal is connected to the lower limit voltage VL, the inverting input terminal is connected to the operational amplifier output terminal, and at the same time is connected to the output terminal VC of the error amplifier to form a gain negative feedback. . If VC is less than VL, M211 operates in the saturation region, the loop provides sufficient gain, VC is clamped to VL, and if VC is greater than VL, M211 operates in the off region and the loop provides Gain is limited and VC is not clamped to VL. Based on such a circuit design, VC is limited between VL and VH to realize a limiting function.
本発明が設計した過渡検出回路とマルチプレクサとを図5に示す。本発明は前述誤差増幅器内部ノードVPとVNとの電圧によって負荷電流に過渡急変があるかどうかを判断する。もし負荷電流に過渡急変があれば、フィードバック電圧Vfbが変化し、VfbとVrefとの差がVPとVNとの電圧値を変化させる。且つ比較的に短い伝送路とVC端を駆動する必要がない大電気容量とのため、VPとVNとの変化はVCより遥かに早い。このため、VPとVNとを利用して回路が過渡変化に入るかどうか快速に検出できる。負荷電流が低負荷から高負荷へ変化する場合、出力電圧が低下し、Vfbが低下し、これによってVNとVPとの電圧が低下する；負荷電流が高負荷から低負荷へ変化する場合、出力電圧が上昇し、Vfbが上昇し、これによってVNとVPとの電圧が上昇する； FIG. 5 shows a transient detection circuit and a multiplexer designed by the present invention. The present invention determines whether or not there is a transient change in the load current according to the voltage of the error amplifier internal node VP and VN. If there is a transient change in the load current, the feedback voltage Vfb changes, and the difference between Vfb and Vref changes the voltage value between VP and VN. And because of the relatively short transmission path and the large capacitance that does not require driving the VC end, the change between VP and VN is much faster than VC. For this reason, it is possible to detect rapidly whether the circuit enters a transient change by using VP and VN. When the load current changes from low load to high load, the output voltage decreases and Vfb decreases, thereby decreasing the voltage between VN and VP; output when the load current changes from high load to low load The voltage rises and Vfb rises, thereby raising the voltage between VN and VP;
図5が示すように、コンバータが通電し、ソフトスタート状態にある時、VS電圧がVrefより小さく、コンパレータがローレベルを出力し、このローレベルが二つのアンドゲートをローレベル状態にさせるので、VE1がハイレベルであり、VE2がローレベルであり、この時マルチプレクサの二つのスイッチMS3とMS4とがいずれもオフ状態であり、誤差増幅器の出力電圧VCが誤差増幅器により決定され、且つMS1とMS2との二つのスイッチがオンする。MS1とMS2とがオンするので、余分な電流がMS1を通してVDに流れ込み、そこでVD電圧を電源電圧に近い電圧に設置し、即ちVDはハイレベルであり、同様に、余分な電流がMS2を通してVUから流れ出、そこでVU電圧を接地電圧に近い電圧に設置し、即ちVUはローレベルである。この簡単な設置を介して、過渡検出回路とマルチプレクサとをパワーオンリセットさせることができ、負荷過渡がない状況において、VCが誤差増幅器により決定される。通電終了後、ソフトスタート電圧がVrefより高く、コンパレータがハイレベルを出力し、VE1とVE2との電圧がVDとVUにより決定される。 As shown in FIG. 5, when the converter is energized and in the soft start state, the VS voltage is smaller than Vref, the comparator outputs a low level, and this low level causes the two AND gates to be in the low level state. VE1 is high, VE2 is low, the two switches MS3 and MS4 of the multiplexer are both off, the error amplifier output voltage VC is determined by the error amplifier, and MS1 and MS2 And the two switches turn on. Since MS1 and MS2 are turned on, an extra current flows into VD through MS1, where the VD voltage is placed close to the supply voltage, i.e. VD is at a high level, as well as an extra current through V2 to VU The VU voltage is set to a voltage close to the ground voltage, that is, VU is at a low level. Through this simple installation, the transient detection circuit and the multiplexer can be power-on reset, and VC is determined by the error amplifier in the absence of load transients. After energization, the soft start voltage is higher than Vref, the comparator outputs a high level, and the voltages at VE1 and VE2 are determined by VD and VU.
前述の通り、負荷電流が低負荷から高負荷へ変化する場合、VNとVPとの電圧が低下し、PMOS型FETM2のゲート電圧が低下し、M2を流れる電流が増大し、NMOS型FETM4のゲート電圧が低下し、M4を流れる電流が減少し、そこでVUの電圧が上昇し、VUが増大してインバータの切換閾値を超える時、VE1がハイレベルからローレベルへ変化し、これによってMS2をオフさせ、VUがもっと快速に増大し、ポジティブフィードバックのように、最後VE1がローレベル状態にあり、MS3をオンさせ、VC電圧がVHにプルアップされ、誤差増幅器の出力電圧が上限に達し、デューティレシオを迅速に増大し、快速過渡応答を実現し、Voutアンダシュート電圧が復帰する。負荷電流が高負荷から低負荷へ変化する場合、VNとVPとの電圧が上昇し、PMOS型FETM1のゲート電圧が低下し、M1を流れる電流が減少し、NMOS型FETM3のゲート電圧が上昇し、M3を流れる電流が増大し、そこでVPの電圧が低下し、VPがインバータの切換閾値まで低下し、VE2がローレベルからハイレベルへ変化し、これによってMS1をオフさせ、VPがもっと快速に減少し、ポジティブフィードバックのように、最後VE2がハイレベル状態にあり、MS4をオンさせ、VC電圧がVLに引き下げられ、誤差増幅器の出力電圧が下限に達し、デューティレシオを迅速に減少し、快速過渡応答を実現し、Voutオーバーシュート電圧が復帰する。過渡検出回路全体とマルチプレクサとが基本的にデジタル回路であるので、静態消費電力がとても低い。 As described above, when the load current changes from a low load to a high load, the voltage between VN and VP decreases, the gate voltage of the PMOS FET M2 decreases, the current flowing through M2 increases, and the gate of the NMOS FET M4 increases. When the voltage drops and the current through M4 decreases, where the voltage on VU rises and VU increases and exceeds the inverter switching threshold, VE1 changes from high to low, thereby turning off MS2. VU increases more quickly, as in positive feedback, the last VE1 is in the low state, MS3 is turned on, VC voltage is pulled up to VH, error amplifier output voltage reaches the upper limit, duty cycle The ratio is quickly increased, a fast transient response is realized, and the Vout undershoot voltage is restored. When the load current changes from high load to low load, the voltage between VN and VP increases, the gate voltage of PMOS FET M1 decreases, the current flowing through M1 decreases, and the gate voltage of NMOS FET M3 increases. , The current through M3 increases, where the voltage of VP decreases, VP decreases to the inverter switching threshold, VE2 changes from low level to high level, which turns off MS1, making VP faster Finally, like positive feedback, VE2 is in the high level state, MS4 is turned on, VC voltage is pulled down to VL, error amplifier output voltage reaches the lower limit, duty ratio is quickly reduced, and fast Transient response is realized and Vout overshoot voltage is restored. Since the entire transient detection circuit and the multiplexer are basically digital circuits, the static power consumption is very low.
本発明は電流モードbuck型DC-DCコンバータチップに適用する快速過渡応答回路を提供し、誤差増幅器内部ノードの電圧によって負荷電流に過渡急変が発生するかどうかを判断する。例えば負荷電流が過渡応答ステージに入り、出力電流が突然小さくなる時、マルチプレクサを利用して誤差増幅器の出力電圧を設定された最低値に設定し、この最低値をランプ電圧と比べ、デューティレシオを迅速に低下させ、これによって過渡反応の時間を減少して過渡オーバーシュート電圧を低下させる。出力電流が突然大きくなる時、マルチプレクサを利用して誤差増幅器の出力電圧を設定された最高値に設定し、この最高値をランプ電圧と比べ、デューティレシオを迅速に増加させ、これによって過渡反応の時間を減少して過渡アンダシュート電圧を低下させる。過渡回路がループ安定性に対する影響を低減するために、誤差増幅回路にリミッタモジュールを増加する。本発明は過渡時のPWMのデューティレシオを最大限に変化させることによって、DC-DCコンバータチップの過渡応答能力を高める。試験結果は、上記快速過渡応答回路は消費電力が低く、安定性が良く、過渡応答に優れる等のメリットを有する。 The present invention provides a rapid transient response circuit applied to a current mode buck type DC-DC converter chip, and determines whether or not a transient sudden change occurs in a load current due to a voltage of an error amplifier internal node. For example, when the load current enters the transient response stage and the output current suddenly decreases, the output voltage of the error amplifier is set to the set minimum value using a multiplexer, and this minimum value is compared with the lamp voltage, and the duty ratio is set. It quickly drops, thereby reducing the transient response time and reducing the transient overshoot voltage. When the output current suddenly increases, a multiplexer is used to set the output voltage of the error amplifier to the set maximum value, and this maximum value is compared with the lamp voltage to quickly increase the duty ratio, thereby reducing the transient response. Decrease time to lower transient undershoot voltage. In order to reduce the effect of the transient circuit on the loop stability, the limiter module is added to the error amplifier circuit. The present invention increases the transient response capability of the DC-DC converter chip by maximally changing the PWM duty ratio during the transition. The test results show that the rapid transient response circuit has advantages such as low power consumption, good stability, and excellent transient response.
以上に述べたのはただ本実用新型のより良い実施例で、本実用新型を限定することに使わないである。本実用新型の意義と原則のもとで行う全ての修正、同等の入れ替えと改善などは本実用新型の保護範囲に含まれる。 What has been described above is merely a better embodiment of the new utility model and should not be used to limit the new utility model. All modifications, equivalent replacements and improvements made under the meaning and principle of the new utility model are included in the protection scope of the new utility model.
Claims (1)
前記誤差増幅器が外部フィードバック入力と接続し、前記誤差増幅器が外部フィードバックを増幅し、また電圧安定信号を出力する；
前記リミッタ回路が前記誤差増幅器と接続し、前記リミッタ回路の上限電圧はVHであり、下限電圧はVLであり、前記リミッタ回路が前記誤差増幅器の出力電圧安定信号をVLとVHの間に限定する；前記マルチプレクサが前記リミッタ回路と接続し、前記マルチプレクサが前記誤差増幅器の出力電圧安定信号をVHあるいはVLに設定する；
前記過渡検出回路が前記誤差増幅器と接続し、前記過渡検出回路が前記誤差増幅器の内部ノードを検出し、負荷電流に過渡急変があるかどうかを判断することを含む；
前記誤差増幅器は：差動増幅部分と、ソフトスタート部分と電気容量倍増器、その中、
前記差動増幅部分はMOS型FETM11と、M12と、M13と、M14と、M15と、M16 と、M17と、M18とを含み、フィードバック電圧VfbがM11のゲートと接続し、基準電圧VrefがM12のゲートと接続し、M11のソースがM12のドレインと接続し、M11のドレインがM13のドレインとゲートと接続し且つM16のゲートと接続し、M13とM16とのソースが接地し、M12のソースが同時に前記ソフトスタート部分のMC12のソースと接続し、M12のドレインが同時に前記ソフトスタート部分のMC12と接続し、M14のドレインがM12のドレインと接続し、M14のソースが接地し、M14のゲートがVNノードを引き出し、M15のソースが電圧VDDと接続し、M15のゲートがVPノードを引き出し、M15のゲートがM17のゲートと接続し、M15のドレインがM16のドレインと接続し、M17のソースが電圧VDDと接続し、M17のドレインがM18のドレインと接続し、M18のゲートがM14のゲートと接続し、M18のソースが接地する；
前記ソフトスタート部分はMOS型FETMC12と、コンデンサーC10とMOS型FETMB13とを含み、MC12のソースが前記差動増幅部分のM11とM12とのソースと接続し、MC12のドレインが前記差動増幅部分のM12と、M14とのドレインと接続し、C10がMC12のゲートと接続し、MB13のソースが電圧VDDと接続し、MB13のドレインがC10と接続し、C10が接地する；
前記電気容量倍増器はMOS型FETM19、M100と、MOS型FETMB15、MB16と、コンデンサーCm1とを含み、M19のドレインがMB15のドレインと接続し、M19のゲートがM100のゲートと接続し、M19のソースが接地し、M100のドレインがMB16のドレインと接続し、M100のソースが接地し、MB15のソースが電圧VDDと接続し、MB16のソースが電圧VDDと接続し、コンデンサーCm1がMB14とM19とのドレインと接続し、及びコンデンサーCm1がM19とM100とのゲートと接続することを含む；
前記リミッタ回路は第一演算増幅器と第二演算増幅器とを含み、その中第一演算増幅器はMOS型FETM21と、M22と、M23と、M24と、M25とを含み、第二演算増幅器はMOS型FETM26と、M27と、M28と、M29と、M210と、M211とを含み、前記MOS型FETM21のゲートが上限電圧VHと接続し、前記MOS型FETM27のゲートが下限電圧VLと接続し、M21のソースがM22のソースと接続し、M21のドレインがM23のドレインと接続し、M22のドレインがM24のドレインと接続し、M23のゲートがM24のゲートと接続し、M23のソースが接地し、M24のソースが接地し、M25のゲートがM22と、M24とのドレインと接続し、M25のソースがM22のゲートと接続し、M25のドレインが接地し、M26のゲートがM22のゲートと接続し、M26のソースがM27のソースと接続し、M26のドレインがM28のドレインと接続し、M27のドレインがM29のドレインと接続し、M28のゲートがM29のゲートと接続し、M28のソースが接地し、M29のソースが接地し、M210のゲートがM27と、M29とのドレインと接続し、M210のドレインがM211のゲートと接続し、M210のソースが接地し、M211のソースが接地する；
前記過渡検出回路が前記誤差増幅器の中のVPノード及びVNノードと接続し、前記過渡検出回路が前記誤差増幅器の内部ノードVPとVNの電圧によって負荷電流に過渡急変があるかどうかを判断するということを特徴とする電流モードbuck型DC-DCコンバータチップに適用する快速過渡応答回路。 Error amplifier, limiter circuit, multiplexer and transient detection circuit,
The error amplifier is connected to an external feedback input, the error amplifier amplifies the external feedback and outputs a voltage stabilization signal;
The limiter circuit is connected to the error amplifier, the upper limit voltage of the limiter circuit is VH, the lower limit voltage is VL, and the limiter circuit limits the output voltage stabilization signal of the error amplifier between VL and VH. The multiplexer is connected to the limiter circuit, and the multiplexer sets the output voltage stabilization signal of the error amplifier to VH or VL;
The transient detection circuit is connected to the error amplifier, and the transient detection circuit detects an internal node of the error amplifier to determine whether there is a transient sudden change in load current;
The error amplifier includes: a differential amplification part, a soft start part and a capacitance multiplier,
The differential amplification part includes MOS type FETs M11, M12, M13, M14, M15, M16, M17, and M18, the feedback voltage V fb is connected to the gate of M11, and the reference voltage V ref Is connected to the gate of M12, the source of M11 is connected to the drain of M12, the drain of M11 is connected to the drain and gate of M13 and the gate of M16, the sources of M13 and M16 are grounded, and M12 The source of M12 is simultaneously connected to the source of MC12 of the soft start portion, the drain of M12 is simultaneously connected to MC12 of the soft start portion, the drain of M14 is connected to the drain of M12, the source of M14 is grounded, and M14 Pull the gate V N nodes, the source of M15 is connected to the voltage V DD, pull the V P node gate of M15 is connected the gate of M15 is the gate of M17, connected to the drains of M15 is M16 and, source of M17 is connected to the voltage V DD, the drain of M17 is M18 de Connected to the Inn, the gate of M18 is connected to the gate of M14, the source of M18 to ground;
The soft start part includes a MOS type FET MC12, a capacitor C10 and a MOS type FET MB13, the source of MC12 is connected to the sources of M11 and M12 of the differential amplification part, and the drain of MC12 is the differential amplification part. Connected to the drains of M12 and M14, C10 connected to the gate of MC12, the source of MB13 connected to voltage V DD , the drain of MB13 connected to C10, and C10 grounded;
The capacitance multiplier includes MOS type FETs M19, M100, MOS type FETs MB15, MB16, and a capacitor Cm1, the drain of M19 is connected to the drain of MB15, the gate of M19 is connected to the gate of M100, Source grounded, M100 drain connected to MB16 drain, M100 source grounded, MB15 source connected to voltage V DD , MB16 source connected to voltage V DD, and capacitor Cm1 connected to MB14 Including connecting to the drain of M19, and connecting capacitor Cm1 to the gate of M19 and M100;
The limiter circuit includes a first operational amplifier and a second operational amplifier, in which the first operational amplifier includes MOS type FETs M21, M22, M23, M24, and M25, and the second operational amplifier is a MOS type. FET M26, M27, M28, M29, M210, M211, the gate of the MOS type FET M21 is connected to the upper limit voltage VH, the gate of the MOS type FET M27 is connected to the lower limit voltage VL, The source is connected to the source of M22, the drain of M21 is connected to the drain of M23, the drain of M22 is connected to the drain of M24, the gate of M23 is connected to the gate of M24, the source of M23 is grounded, and M24 The source of M25 is connected to the drain of M22 and M24, the source of M25 is connected to the gate of M22, the drain of M25 is grounded, the gate of M26 is connected to the gate of M22, M26 source connected to M27 source, M26 drain connected to M28 drain, M27 drain connected to M29 drain M28 gate is connected to M29 gate, M28 source is grounded, M29 source is grounded, M210 gate is connected to M27 and M29 drain, M210 drain is M211 Connected to the gate, the source of M210 is grounded, the source of M211 is grounded;
Whether the transient detection circuit is connected to a V P node and a V N node in the error amplifier, and whether the transient detection circuit has a sudden change in the load current due to the voltage of the internal nodes V P and V N of the error amplifier A fast transient response circuit applied to a current mode buck type DC-DC converter chip.
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| JP2008125220A (en) * | 2006-11-10 | 2008-05-29 | Fujitsu Ltd | Control circuit and method of current mode dc-dc converter |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113489317A (en) * | 2021-05-26 | 2021-10-08 | 中国电子科技集团公司第四十一研究所 | Program-controlled output power control circuit |
| KR20230053474A (en) * | 2021-10-14 | 2023-04-21 | 국민대학교산학협력단 | Controlling apparatus and method of buck converter's maximum power point tracking for charging the battery |
| KR102556385B1 (en) | 2021-10-14 | 2023-07-17 | 국민대학교산학협력단 | Controlling apparatus and method of buck converter's maximum power point tracking for charging the battery |
| CN116505774A (en) * | 2023-07-03 | 2023-07-28 | 华南理工大学 | Hybrid buck converter with fast transient high voltage conversion ratio |
| CN116505774B (en) * | 2023-07-03 | 2023-09-26 | 华南理工大学 | Hybrid buck converter with fast transient high voltage conversion ratio |
| CN117578876A (en) * | 2023-07-17 | 2024-02-20 | 北京同芯科技有限公司 | Circuit for improving DC-DC linear transient response |
| CN117578876B (en) * | 2023-07-17 | 2024-04-23 | 北京同芯科技有限公司 | Circuit for improving DC-DC linear transient response |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108445947A (en) | 2018-08-24 |
| CN108445947B (en) | 2023-05-02 |
| JP6856259B2 (en) | 2021-04-07 |
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