CN109921641A - A kind of control circuit and its control method of adaptive difference current mould - Google Patents
A kind of control circuit and its control method of adaptive difference current mould Download PDFInfo
- Publication number
- CN109921641A CN109921641A CN201910217323.9A CN201910217323A CN109921641A CN 109921641 A CN109921641 A CN 109921641A CN 201910217323 A CN201910217323 A CN 201910217323A CN 109921641 A CN109921641 A CN 109921641A
- Authority
- CN
- China
- Prior art keywords
- enhanced
- tube
- side power
- pmos tube
- nmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
The control circuit and its control method of a kind of adaptive difference current mould disclosed by the invention, it include: high side power PMOS tube, low side power NMOS tube, feedback resistance R1, R2, adaptive error amplifier, sample the current sampling circuit of high side power PMOS tube and low side power NMOS tube electric current, for comparing the hysteresis comparator circuit of the signal of current sampling circuit and error amplifier output, the pwm control circuit for generating PWM output signal provides the power tube Driver circuit of driving signal to high side power PMOS tube and low side power NMOS tube.Transient response speed can be improved in the present invention, while simplified architecture reduces power consumption, saves oscillator and slope compensation circuit compared to traditional PWM peak value Current limited Control method, output voltage ripple can be greatly lowered, and improve system stability.
Description
Technical field
The invention belongs to the control circuit of the technical field of integrated circuit more particularly to a kind of adaptive difference current mould and
Its control method.
Background technique
LED (light emitting diode) backlight has better colour gamut and lower power consumption than cold light lamp backlight, while also having more
Fast response speed, booster type DC-DC converter are just widely used in LED backlight display system, low input are promoted to
High output voltage, to drive multiple concatenated LED.In LED application, boost converter needs to deal with a large amount of momentary loads and becomes
Change to guarantee picture quality, therefore the booster type DC-DC converter for being applied to similar applications needs outstanding transient response, simultaneously
Also power consumption is reduced, is improved efficiency.
Common PWM Peak Current Mode control circuit can be realized the output of degree of precision, but be greater than 50% in duty ratio
In the case where exist and be difficult to the error of the peak point current and average current corrected, will cause the unstable of circuit, while LED is applied
Occasion is also required to the transient response ability of higher speed.
Summary of the invention
Goal of the invention: cause that circuit is unstable, wink to solve the error of above-mentioned prior art peak point current and average current
The slow problem of state response speed, the present invention provide the control circuit and its control method of a kind of adaptive difference current mould.
Technical solution: the present invention provides a kind of control circuit of adaptive difference current mould, including the first inductance, capacitor,
First~3rd resistor, high side power PMOS tube, low side power NMOS tube, adaptive error amplifier, current sampling circuit, late
Stagnant comparator, pwm control logic circuit, power tube Driver circuit；The current sampling circuit includes the first current sample electricity
Road and the second current sampling circuit, current sample electricity during first current sampling circuit is the conducting of high side power PMOS tube
Road, current sampling circuit during second current sampling circuit is low side power NMOS transistor conduction, first current sample
Circuit includes the first operational amplifier；Second current sampling circuit includes second operational amplifier；
The capacitor latter end ground connection in parallel with 3rd resistor, other end is the output end of circuit；The one of first resistor
End connect respectively with the drain electrode of the output end of circuit, high side power PMOS tube, other end respectively with one end of second resistance, oneself
Adapt to the inverting input terminal connection of error amplifier；The other end of second resistance is grounded, the adaptive error amplifier
Output end connects the inverting input terminal of hysteresis comparator, and the non-inverting input terminal of the hysteresis comparator connects the first operational amplifier
Output end and second operational amplifier output end；The inverting input terminal of first operational amplifier connects low side power
The drain electrode of NMOS tube, non-inverting input terminal connect the drain electrode of high side power PMOS tube；The homophase input of the second operational amplifier
The drain electrode of end connection low side power NMOS tube, inverting input terminal connect the source electrode of low side power NMOS tube；The low side power
The source electrode of NMOS tube is grounded, and drain electrode is connect with one end of the source electrode of high side power PMOS tube, the first inductance respectively；The sluggishness ratio
Output end compared with device is connect with the input terminal of pwm control logic circuit；The output end and power tube of pwm control logic circuit
The input terminal of Driver circuit connects, the output end of power tube Driver circuit be separately connected low side power NMOS tube grid and
The grid of low side power NMOS tube.
Further, the adaptive error amplifier includes: the first~the eight enhanced PMOS tube, the 4th resistance,
One~the 6th enhanced NMOS tube, third operational amplifier, DC power supply；
The grid of the first enhanced PMOS tube and drain electrode are shorted, and connect the grid of the second enhanced PMOS tube, institute
State the drain electrode of drain electrode the first enhanced NMOS tube of connection of the first enhanced PMOS tube；The source electrode of first enhanced NMOS tube connects
The drain electrode of two enhanced NMOS tubes, the source electrode ground connection of the second enhanced NMOS tube, the grid of the first enhanced NMOS tube connect
The output end of third operational amplifier is connect, the inverting input terminal of the third operational amplifier is separately connected the second enhanced NMOS
The drain electrode of the enhanced PMOS tube of the grid of pipe, third and the drain electrode of the enhanced NMOS tube of third；The third operational amplifier
Non-inverting input terminal connects the grid of the enhanced NMOS tube of third and the grid of the 4th enhanced NMOS tube；Described 4th is enhanced
The grid of the enhanced NMOS tube of grid and third of NMOS tube is all connected with bias voltage；The grid of the enhanced PMOS tube of third
For the non-inverting input terminal of the adaptive error amplifier；The enhanced PMOS tube source electrode of the third connect the 4th resistance one end and
The drain electrode of second enhanced PMOS tube；The other end of 4th resistance connects the source electrode and the 5th of the 4th enhanced PMOS tube
The drain electrode of enhanced NMOS tube；The grid and the 4th of drain electrode the 5th enhanced NMOS tube of connection of the 4th enhanced PMOS tube
The drain electrode of enhanced NMOS tube；The grid of the 5th enhanced NMOS tube connects the grid of the 6th enhanced NMOS tube, described
The drain electrode of 6th enhanced NMOS tube be adaptive error amplifier out, and connect the 8th enhanced PMOS tube drain electrode and
The grid of 7th enhanced PMOS tube；The source electrode of the 7th enhanced PMOS tube connect the 6th enhanced PMOS tube drain electrode and
The grid of 8th enhanced PMOS tube；The grid of the 6th enhanced PMOS tube connects the grid of the 5th enhanced PMOS tube,
The drain electrode of the 5th enhanced PMOS tube and grid are shorted, and are connect with the cathode of DC source；The first enhanced PMOS
The source electrode of pipe, the source electrode of the second enhanced PMOS tube, the source electrode of the 5th enhanced PMOS tube, the 6th enhanced PMOS tube source
Pole, the 8th enhanced PMOS tube source electrode connect with supply voltage VDD；The source electrode of the enhanced NMOS tube of third, the 4th
The source electrode of enhanced NMOS tube, the source electrode of the 5th enhanced NMOS tube, DC source anode, the 7th enhanced PMOS tube leakage
Pole, the 6th enhanced PMOS tube source electrode ground connection.
Further, first current sampling circuit further includes the 9th enhanced PMOS tube, the 5th resistance；Described 9th
The inverting input terminal of drain electrode connection, the drain electrode and the first operational amplifier of the source electrode and low side power NMOS tube of enhanced PMOS tube
It is connected with one end of the 5th resistance, grid is connect with the grid of high side power PMOS tube, the other end of the 5th resistance and
The non-inverting input terminal of one operational amplifier connects.
Further, second current sampling circuit further includes the seven, the eight enhanced NMOS tubes；Described 7th is enhanced
The drain electrode of the source electrode connection low side power NMOS tube of NMOS tube；The non-inverting input terminal of drain electrode connection second operational amplifier, it is described
The grid of 7th enhanced NMOS tube and the grid of the 8th enhanced NMOS tube are all connected with the grid of low side power NMOS tube；It is described
The inverting input terminal of the drain electrode connection second operational amplifier of 8th enhanced NMOS tube；Source electrode connects low side power NMOS tube
Source electrode.
A kind of control method of adaptive difference current mould:
When the first inductive current rises, low side power NMOS transistor conduction, the shutdown of high side power PMOS tube, the first inductance
Electric current flows to ground terminal by low side power NMOS tube, and the variation that second operational amplifier rises the electric current of the first inductance is converted
At voltage signal VSENSE2, as VSENSE2=VC+Vhys, the electric current of the first inductance reaches maximum value；Power tube at this time
The electric signal control high side power PMOS tube conducting of Driver circuit output, the shutdown of low side power NMOS tube；VC is adaptive misses
Poor amplifier output voltage；Vhys is the hysteresis voltage that hysteresis comparator itself generates；
When high side power PMOS tube is connected, and low side power NMOS tube turns off, the first inductance L passes through high side power PMOS tube
To capacitor charging, the electric current of the first inductance is gradually reduced at this time, the change that the first operational amplifier declines the electric current of the first inductance
Change is converted into voltage signal VSENSE1, and as VSENSE1=VC-Vhys, the electric current of the first inductance reaches minimum value；Function at this time
The electric signal control high side power PMOS tube shutdown of rate pipe Driver circuit output, low side power NMOS transistor conduction.
The utility model has the advantages that reducing domain face this invention simplifies oscillator in the prior art and slope compensation part
Long-pending and current drain, and output voltage precision can be improved, reduce output voltage ripple, while further improving transient response speed
Degree, dynamic regulation inductive current difference, improves system stability under different load conditions.
Detailed description of the invention
Fig. 1 is the Peak Current Mode pwm control circuit schematic diagram of the prior art；
Fig. 2 is circuit theory of the invention；
Fig. 3 is adaptive error amplifier circuit diagram of the invention；
Current sampling circuit during Fig. 4 is high side power PMOS tube conducting of the invention；
Current sampling circuit during Fig. 5 is low side power NMOS transistor conduction of the invention.
Specific embodiment
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.
As shown in Figure 1, common PWM Peak Current Mode control circuit includes two negative feedback resistors, power tube PMOS, function
Rate NMOS tube, error amplifier, current sampling circuit, oscillator, Ramp generation circuit, PWM comparator, Driver module.On
It states shown circuit structure and obtains feedback voltage V by two negative feedback resistorsFB, error amplification signal is obtained by error amplifier
VC samples the Islope Signal averaging that inductance peak point current and oscillator generate by current sampling circuit and obtains VRamp, then by
PWM comparator is compared VC and VRamp, and obtained signal and oscillator clock signal co- controlling Driver module generates
The signal of driving power pipe grid.
The control circuit of the adaptive difference current mould of the present embodiment is improved in foregoing circuit, specifically such as Fig. 2 institute
Show, comprising: the first inductance L, capacitor C0, first~3rd resistor (R1, R2, R3), high side power PMOS tube, low side power NMOS
Pipe, adaptive error amplifier, current sampling circuit, hysteresis comparator, pwm control logic circuit, power tube Driver circuit；
The current sampling circuit includes the first current sampling circuit and the second current sampling circuit, and first current sampling circuit is
Current sampling circuit during high side power PMOS tube is connected, second current sampling circuit are the low side power NMOS transistor conduction phase
Between current sampling circuit, first current sampling circuit include the first operational amplifier OPA1；The second current sample electricity
Road includes second operational amplifier OPA2.
The capacitor C0 latter end ground connection in parallel with R3, other end is the output end of circuit；One end of first resistor R1
Connect respectively with the drain electrode of the output end of circuit, high side power PMOS tube, other end respectively with one end of second resistance R2, from
Adapt to the inverting input terminal connection of error amplifier；The other end of second resistance R2 is grounded, the adaptive error amplifier
Output end connection hysteresis comparator inverting input terminal, the non-inverting input terminal of the hysteresis comparator connects the first operation amplifier
The output end of device OPA1 and the output end of second operational amplifier OPA2；The inverting input terminal of the first operational amplifier OPA1
The drain electrode of low side power NMOS tube is connected, non-inverting input terminal connects the drain electrode of high side power PMOS tube；Second operation amplifier
The drain electrode of the non-inverting input terminal connection low side power NMOS tube of device OPA, inverting input terminal connect the source electrode of low side power NMOS tube；
The source electrode of the low side power NMOS tube is grounded, and drain electrode connects with one end of the source electrode of high side power PMOS tube, the first inductance L respectively
It connects；The output end of the hysteresis comparator is connect with the input terminal of pwm control logic circuit；The output of pwm control logic circuit
End is connect with the input terminal of power tube Driver circuit, and the output end of power tube Driver circuit is separately connected low side power NMOS
The grid of pipe and the grid of low side power NMOS tube.
Feedback resistance R1, R2 sampling and outputting voltage passes through adaptively with from using the reference voltage Vref inside amplifier
Error amplifier obtains the VC signal adaptively adjusted with load variation, passes through the high side power PMOS in current sampling module
Current sampling circuit carries out complete cycle to inductive current during current sampling circuit and low side power NMOS transistor conduction during pipe is connected
Phase samples and is converted to voltage signal VSENSE1/VSENSE2, and VC signal and VSENSE1/VSENSE2 signal are sent into sluggish ratio
VPWM signal is obtained compared with device, obtains driving high side power using pwm control logic circuit and power tube Driver circuit
The signal of PMOS tube and low side power NMOS tube grid, to control inductive current difference to realize the stabilization of system.Compared to normal
The PWM Peak Current Mode control method of rule, adaptive difference current mould eliminate oscillator and due to system instability
And the slope compensation circuit introduced, it saves chip area while reducing power consumption, further, adaptive difference current mould will
The difference of inductive current is set as definite value, and as load changes automatic adjusument inductive current difference, due to inductive current difference
Fixed rather than inductive current has to reach maximum value in PWM Peak Current Mode, the response speed of adaptive difference current mould is more
Fast and output voltage ripple is also smaller.
As shown in figure 3, it includes: that the adaptive error amplifier of the present embodiment, which includes: the adaptive error amplifier,
One~the eight enhanced PMOS tube (MP1~MP8), the 4th resistance R4, the first~the six enhanced NMOS tube (MN1~MN6),
Three operational amplifier OPA3, DC power supply Ib1.
The grid of the first enhanced PMOS tube MP1 and drain electrode are shorted, and connect the grid of the second enhanced PMOS tube MP2
Pole, the drain electrode of the first enhanced NMOS tube MN1 of drain electrode connection of the first enhanced PMOS tube MP1；First enhanced NMOS
The source electrode of pipe MN1 connects the drain electrode of the second enhanced NMOS tube MN2, and the source electrode of the second enhanced NMOS tube MN2 is grounded, and described first
The output end of the grid connection third operational amplifier OPA3 of enhanced NMOS tube MN1, the third operational amplifier OPA3's
Inverting input terminal is separately connected the grid of the second enhanced NMOS tube MN2, the drain electrode of the enhanced PMOS tube MP3 of third and third and increases
The drain electrode of strong type NMOS tube MN3；The non-inverting input terminal of the third operational amplifier OPA3 connects the enhanced NMOS tube MN3 of third
Grid and the 4th enhanced NMOS tube MN4 grid；The grid and third of the 4th enhanced NMOS tube MN4 is enhanced
The grid of NMOS tube MN3 is all connected with bias voltage；The grid of the enhanced PMOS tube MP3 of third is adaptive error amplification
The non-inverting input terminal of device；The source electrode of the enhanced PMOS tube MP3 of third connects one end of the 4th resistance R4 and second enhanced
The drain electrode of PMOS tube MP2；The other end of the 4th resistance R4 connects the source electrode of the 4th enhanced PMOS tube MP4 and the 5th and increases
The drain electrode of strong type NMOS tube MN5；The grid of the 5th enhanced NMOS tube MN5 of drain electrode connection of the 4th enhanced PMOS tube MP4
The drain electrode of pole and the 4th enhanced NMOS tube MN4；The grid of the 5th enhanced NMOS tube MN5 connects the 6th enhanced NMOS
The grid of pipe MN6, the drain electrode of the 6th enhanced NMOS tube MN6 is adaptive error amplifier out, and connects the 8th
The drain electrode of enhanced PMOS tube MP8 and the grid of the 7th enhanced PMOS tube MP7；The source of the 7th enhanced PMOS tube MP7
Pole connects drain electrode and the grid of the 8th enhanced PMOS tube MP8 of the 6th enhanced PMOS tube MP6；The 6th enhanced PMOS
The grid of pipe MP6 connects the grid of the 5th enhanced PMOS tube MP5, the drain electrode of the 5th enhanced PMOS tube MP5 and grid
It is shorted, and is connect with the cathode of DC source；The source electrode of the first enhanced PMOS tube MP1, the second enhanced PMOS tube MP2
Source electrode, the source electrode of the 5th enhanced PMOS tube MP5, the 6th enhanced PMOS tube MP6 source electrode, the 8th enhanced PMOS tube MP8
Source electrode connect with supply voltage VDD；The source electrode of the enhanced NMOS tube MN3 of third, the 4th enhanced NMOS tube MN4
Source electrode, the source electrode of the 5th enhanced NMOS tube MN5, the anode of DC source, the drain electrode of the 7th enhanced PMOS tube MP7, the 6th increase
The source electrode of strong type PMOS tube MP6 is grounded.
When load current increases, VFB voltage is reduced, and is equivalent to the raising of Vref voltage, is flowed into the enhanced NMOS tube of third
The electric current of MN3 reduces, and the inverting input terminal voltage of third operational amplifier OPA3 reduces, and will make third operational amplifier OPA3's
Output increases, and the electric current of the enhanced PMOS tube MP2 of the first enhanced PMOS tube MP1 and second of current mirror is increased, due to third
The grid of the enhanced enhanced NMOS tube MN4 of NMOS tube MN3 and the 4th connect Vbias voltage (bias voltage) and be in
Saturation region, then flow into the enhanced enhanced NMOS tube MN4 of NMOS tube MN3 and the 4th of third electric current may be considered it is identical,
When VFB voltage reduces, the electric current for flowing into the 4th enhanced NMOS tube MN4 increases, the 5th enhanced NMOS tube MN5 grid
Voltage increases, therefore increased electric current △ I is all enhanced to the 5th from the 4th resistance R4 on the second enhanced PMOS tube MP2
It is flowed out on the path of NMOS tube MN5, so producing potential difference between A point and B point, VA-VB=△ I*R4 is equal to adaptive
One is introduced in error amplifier can be with the sluggishness of self-adapting load electric current.The output of the adaptive error amplifier is finally led to
Cross the 6th enhanced NMOS tube MN6 and obtain voltage VC, obtained in hysteresis comparator later with sample rate current circuit by electricity
The voltage signal changed into that circulates compares, and controls the switch of power tube to reach output and stablize.
The 5th enhanced PMOS tube MP5, the 6th enhanced PMOS tube MP6, the 7th enhanced PMOS tube MP7, the 8th
Enhanced PMOS tube MP8 forms peak value current-limiting circuit；When load current rises, VFB voltage declines, the 6th enhanced PMOS tube
The gate input voltage of MN6 increases, and VC voltage is caused to decline, then the source voltage of the 7th enhanced PMOS tube MP7 reduces, i.e., and the
The grid potential of eight enhanced PMOS tube MP8 reduces, and the enhanced PMOS tube MP8 of the 8th at this time forms VC voltage high negative
Feedback carries out the control of peak point current by limiting the potential minimum of VC.
As shown in figure 4, first current sampling circuit further includes the 9th enhanced PMOS tube MP9, the 5th resistance R5；Institute
The source electrode for stating the 9th enhanced PMOS tube MP9 connect with the drain electrode of low side power NMOS tube, drains and the first operational amplifier
The inverting input terminal of OPA1 is connected with one end of the 5th resistance R5, and grid is connect with the grid of high side power PMOS tube, and described
The other end of five resistance R5 is connect with the non-inverting input terminal of the first operational amplifier OPA1.
As shown in figure 5, second current sampling circuit further include the 7th enhanced NMOS tube MN7, it is the 8th enhanced
NMOS tube MN8；The drain electrode of the source electrode connection low side power NMOS tube of the 7th enhanced NMOS tube MN7；Drain electrode connection second
The non-inverting input terminal of operational amplifier OPA2, the grid and the 8th enhanced NMOS tube MN8 of the 7th enhanced NMOS tube MN7
Grid be all connected with the grid of low side power NMOS tube；The drain electrode of the 8th enhanced NMOS tube MN8 connects the second operation and puts
The inverting input terminal of big device OPA2；The source electrode of source electrode connection low side power NMOS tube.
A kind of control method of adaptive difference current mould: when the first inductance L electric current rises, low side power NMOS tube is led
Logical, high side power PMOS tube shutdown, the electric current of the first inductance L flows to ground terminal by low side power NMOS tube, and the second operation is put
The variation that the electric current of first inductance L rises is converted into voltage signal VSENSE2 by big device OPA2；VSENSE2=K2*IL*ROUT21；
K2 is proportionality coefficient, ILFor the electric current of the first inductance, ROUT21For in second operational amplifier (OPA2) afterbody it is equivalent defeated
Impedance out；As VSENSE2=VC+Vhys, the electric current of the first inductance L reaches maximum value；Power at this time
The electric signal control high side power PMOS tube conducting of pipe Driver circuit output, the shutdown of low side power NMOS tube；VC is adaptive
Output voltage error amplifier；Vhys is the hysteresis voltage that hysteresis comparator itself generates；
When high side power PMOS tube is connected, and low side power NMOS tube turns off, the first inductance L passes through high side power PMOS tube
To capacitor charging, the electric current of the first inductance L is gradually reduced at this time, and the first operational amplifier OPA1 will be under the electric current of the first inductance L
The variation of drop is converted into voltage signal VSENSE1, VSENSE1=K1*IL*ROUT1, ROUT1For in the first operational amplifier (OPA1)
The equivalent output impedance of afterbody；As VSENSE1=VC-Vhys, the electric current of the first inductance L reaches minimum value；Function at this time
The electric signal control high side power PMOS tube shutdown of rate pipe Driver circuit output, low side power NMOS transistor conduction.
Claims (5)
1. a kind of control circuit of adaptive difference current mould, which is characterized in that including the first inductance, capacitor, first~third
Resistance, high side power PMOS tube, low side power NMOS tube, adaptive error amplifier, current sampling circuit, hysteresis comparator,
Pwm control logic circuit, power tube Driver circuit；The current sampling circuit includes the first current sampling circuit and the second electricity
Stream sample circuit, current sampling circuit during first current sampling circuit is the conducting of high side power PMOS tube, described second
Current sampling circuit during current sampling circuit is low side power NMOS transistor conduction, first current sampling circuit include first
Operational amplifier；Second current sampling circuit includes second operational amplifier；
The capacitor latter end ground connection in parallel with 3rd resistor, other end is the output end of circuit；One end of first resistor point
Do not connect with the drain electrode of the output end of circuit, high side power PMOS tube, other end respectively with one end of second resistance, adaptive
The inverting input terminal of error amplifier connects；The other end of second resistance is grounded, the output of the adaptive error amplifier
The inverting input terminal of end connection hysteresis comparator, the non-inverting input terminal of the hysteresis comparator connect the defeated of the first operational amplifier
The output end of outlet and second operational amplifier；The inverting input terminal of first operational amplifier connects low side power NMOS tube
Drain electrode, non-inverting input terminal connect high side power PMOS tube drain electrode；The non-inverting input terminal of the second operational amplifier connects
The drain electrode of low side power NMOS tube, inverting input terminal connect the source electrode of low side power NMOS tube；The low side power NMOS tube
Source electrode ground connection, drain electrode are connect with one end of the source electrode of high side power PMOS tube, the first inductance respectively；The hysteresis comparator it is defeated
Outlet is connect with the input terminal of pwm control logic circuit；The output end of pwm control logic circuit and power tube Driver circuit
Input terminal connection, the output end of power tube Driver circuit are separately connected the grid and low side power NMOS of low side power NMOS tube
The grid of pipe.
2. a kind of control circuit of adaptive difference current mould according to claim 1, which is characterized in that described adaptive
Error amplifier includes: the first~the 8th enhanced PMOS tube, the 4th resistance, the first~the 6th enhanced NMOS tube, third fortune
Calculate amplifier, DC power supply；
The grid of the first enhanced PMOS tube and drain electrode are shorted, and connect the grid of the second enhanced PMOS tube, and described the
The drain electrode of drain electrode the first enhanced NMOS tube of connection of one enhanced PMOS tube；The source electrode of first enhanced NMOS tube connects the second increasing
The drain electrode of strong type NMOS tube, the source electrode ground connection of the second enhanced NMOS tube, the grid connection the of the first enhanced NMOS tube
The output end of three operational amplifiers, the inverting input terminal of the third operational amplifier are separately connected the second enhanced NMOS tube
The drain electrode of the enhanced PMOS tube of grid, third and the drain electrode of the enhanced NMOS tube of third；The same phase of the third operational amplifier
Input terminal connects the grid of the enhanced NMOS tube of third and the grid of the 4th enhanced NMOS tube；The 4th enhanced NMOS tube
Grid and the grid of the enhanced NMOS tube of third be all connected with bias voltage；The grid of the enhanced PMOS tube of third is should be certainly
Adapt to the non-inverting input terminal of error amplifier；The enhanced PMOS tube source electrode of third connects one end of the 4th resistance and second and increases
The drain electrode of strong type PMOS tube；The other end of 4th resistance connects the source electrode of the 4th enhanced PMOS tube and the 5th enhanced
The drain electrode of NMOS tube；The grid of drain electrode the 5th enhanced NMOS tube of connection of the 4th enhanced PMOS tube and the 4th enhanced
The drain electrode of NMOS tube；The grid of the 5th enhanced NMOS tube connects the grid of the 6th enhanced NMOS tube, and the described 6th increases
The drain electrode of strong type NMOS tube is adaptive error amplifier out, and connects the drain electrode of the 8th enhanced PMOS tube and the 7th and increase
The grid of strong type PMOS tube；The source electrode of the 7th enhanced PMOS tube connects the drain electrode of the 6th enhanced PMOS tube and the 8th and increases
The grid of strong type PMOS tube；The grid of the 6th enhanced PMOS tube connects the grid of the 5th enhanced PMOS tube, and described the
The drain electrode of five enhanced PMOS tube and grid are shorted, and are connect with the cathode of DC source；The source of the first enhanced PMOS tube
Pole, the source electrode of the second enhanced PMOS tube, the source electrode of the 5th enhanced PMOS tube, the source electrode of the 6th enhanced PMOS tube, the 8th
The source electrode of enhanced PMOS tube is connect with supply voltage VDD；It is the source electrode of the enhanced NMOS tube of third, the 4th enhanced
The source electrode of NMOS tube, the source electrode of the 5th enhanced NMOS tube, the anode of DC source, the drain electrode of the 7th enhanced PMOS tube, the 6th
The source electrode of enhanced PMOS tube is grounded.
3. a kind of control circuit of adaptive difference current mould according to claim 1, which is characterized in that first electricity
Flowing sample circuit further includes the 9th enhanced PMOS tube, the 5th resistance；The source electrode and low side function of the 9th enhanced PMOS tube
Drain electrode connection, the drain electrode of rate NMOS tube are connect with one end of the inverting input terminal of the first operational amplifier and the 5th resistance, grid
It is connect with the grid of high side power PMOS tube, the other end of the 5th resistance and the non-inverting input terminal of the first operational amplifier connect
It connects.
4. a kind of control circuit of adaptive difference current mould according to claim 1, which is characterized in that second electricity
Flowing sample circuit further includes the seven, the eight enhanced NMOS tubes；The source electrode of the 7th enhanced NMOS tube connects low side power
The drain electrode of NMOS tube；Drain electrode connection second operational amplifier non-inverting input terminal, the grid of the 7th enhanced NMOS tube and
The grid of 8th enhanced NMOS tube is all connected with the grid of low side power NMOS tube；The drain electrode of the 8th enhanced NMOS tube connects
Connect the inverting input terminal of second operational amplifier；The source electrode of source electrode connection low side power NMOS tube.
5. based on a kind of control method of the control circuit of adaptive difference current mould described in claim 1, which is characterized in that
This method are as follows:
When the first inductive current rises, low side power NMOS transistor conduction, the shutdown of high side power PMOS tube, the electric current of the first inductance
Ground terminal is flowed to by low side power NMOS tube, the variation that the electric current of the first inductance rises is converted into electricity by second operational amplifier
Signal VSENSE2 is pressed, as VSENSE2=VC+Vhys, the electric current of the first inductance reaches maximum value；Power tube Driver at this time
The electric signal control high side power PMOS tube conducting of circuit output, the shutdown of low side power NMOS tube；VC is adaptive error amplification
Device output voltage；Vhys is the hysteresis voltage that hysteresis comparator itself generates；
When high side power PMOS tube is connected, and low side power NMOS tube turns off, the first inductance L passes through high side power PMOS tube to electricity
Capacity charge, the electric current of the first inductance is gradually reduced at this time, and the variation that the first operational amplifier declines the electric current of the first inductance turns
Change voltage signal VSENSE1 into, as VSENSE1=VC-Vhys, the electric current of the first inductance reaches minimum value；Power tube at this time
The electric signal control high side power PMOS tube shutdown of Driver circuit output, low side power NMOS transistor conduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910217323.9A CN109921641B (en) | 2019-03-21 | 2019-03-21 | Control circuit and control method of self-adaptive differential current mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910217323.9A CN109921641B (en) | 2019-03-21 | 2019-03-21 | Control circuit and control method of self-adaptive differential current mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109921641A true CN109921641A (en) | 2019-06-21 |
| CN109921641B CN109921641B (en) | 2021-02-12 |
Family
ID=66966134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910217323.9A Active CN109921641B (en) | 2019-03-21 | 2019-03-21 | Control circuit and control method of self-adaptive differential current mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109921641B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111729192A (en) * | 2020-06-16 | 2020-10-02 | 中南民族大学 | Neural front end closed loop stimulation circuit |
| CN112803736A (en) * | 2021-03-08 | 2021-05-14 | 江苏硅国微电子有限公司 | Circuit and method for reducing output ripple of DC-DC converter |
| CN113849028A (en) * | 2021-10-25 | 2021-12-28 | 杭州和利时自动化有限公司 | Current output type AO circuit |
| CN114640247A (en) * | 2022-04-26 | 2022-06-17 | 合肥工业大学 | Full-period inductive current sampling circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1763188A1 (en) * | 2005-09-09 | 2007-03-14 | Vrije Universiteit Brussel | Multistage tuning-tolerant equalizer filter with detection mechanisms for lower and higher frequency gain loops |
| CN103179751A (en) * | 2013-03-08 | 2013-06-26 | 上海晶丰明源半导体有限公司 | LED driving circuit capable of realizing complete-period sampling of inductive current |
| CN103813587A (en) * | 2014-01-22 | 2014-05-21 | 长安大学 | LED drive circuit with digital-analog hybrid dimming function |
| CN105932875A (en) * | 2016-05-09 | 2016-09-07 | 昌芯(西安)集成电路科技有限责任公司 | Adaptive external synchronization DC/DC converter with PLL latch function |
| CN106549639A (en) * | 2017-01-17 | 2017-03-29 | 桂林电子科技大学 | A kind of gain-adaptive error amplifier |
| CN107104595A (en) * | 2017-05-16 | 2017-08-29 | 电子科技大学 | The self-adaptable slop compensation circuit of buck converter is controlled suitable for Peak Current Mode |
-
2019
- 2019-03-21 CN CN201910217323.9A patent/CN109921641B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1763188A1 (en) * | 2005-09-09 | 2007-03-14 | Vrije Universiteit Brussel | Multistage tuning-tolerant equalizer filter with detection mechanisms for lower and higher frequency gain loops |
| CN103179751A (en) * | 2013-03-08 | 2013-06-26 | 上海晶丰明源半导体有限公司 | LED driving circuit capable of realizing complete-period sampling of inductive current |
| CN103813587A (en) * | 2014-01-22 | 2014-05-21 | 长安大学 | LED drive circuit with digital-analog hybrid dimming function |
| CN105932875A (en) * | 2016-05-09 | 2016-09-07 | 昌芯(西安)集成电路科技有限责任公司 | Adaptive external synchronization DC/DC converter with PLL latch function |
| CN106549639A (en) * | 2017-01-17 | 2017-03-29 | 桂林电子科技大学 | A kind of gain-adaptive error amplifier |
| CN107104595A (en) * | 2017-05-16 | 2017-08-29 | 电子科技大学 | The self-adaptable slop compensation circuit of buck converter is controlled suitable for Peak Current Mode |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111729192A (en) * | 2020-06-16 | 2020-10-02 | 中南民族大学 | Neural front end closed loop stimulation circuit |
| CN112803736A (en) * | 2021-03-08 | 2021-05-14 | 江苏硅国微电子有限公司 | Circuit and method for reducing output ripple of DC-DC converter |
| CN112803736B (en) * | 2021-03-08 | 2022-06-21 | 江苏硅国微电子有限公司 | Circuit and method for reducing output ripple of DC-DC converter |
| CN113849028A (en) * | 2021-10-25 | 2021-12-28 | 杭州和利时自动化有限公司 | Current output type AO circuit |
| CN114640247A (en) * | 2022-04-26 | 2022-06-17 | 合肥工业大学 | Full-period inductive current sampling circuit |
| CN114640247B (en) * | 2022-04-26 | 2024-03-29 | 合肥工业大学 | Full-period inductive current sampling circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109921641B (en) | 2021-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109921641A (en) | A kind of control circuit and its control method of adaptive difference current mould | |
| CN108445947B (en) | Quick transient response circuit applied to DC-DC converter chip | |
| CN109921639A (en) | A kind of Buck converter based on the control of variable turn-on time | |
| CN105517250A (en) | LED (Light-emitting Diode) constant current drive system and constant current control circuit thereof | |
| CN113067469B (en) | Quick response loop compensation circuit, loop compensation chip and switching power supply | |
| CN213934662U (en) | Linear voltage stabilizing circuit without off-chip capacitor | |
| CN112860002B (en) | Instantaneous response linear voltage regulator | |
| CN102411394A (en) | Linear voltage stabilizer with low pressure differential and Sink and Source current capabilities | |
| CN109101067A (en) | A kind of low pressure difference linear voltage regulator of dual power rail | |
| CN105848347B (en) | Control circuit, control chip and the LED light emission device of current ripples can be eliminated | |
| CN111313704A (en) | PWM comparator for controlling BUCK converter with forced continuous mode COT | |
| CN103631299A (en) | Constant-differential-pressure and variable-output-voltage low dropout regulator | |
| WO2022041592A1 (en) | Self-excited push-pull circuit and auxiliary power supply method therefor | |
| CN114204805A (en) | Power rail circuit for high-voltage Buck converter | |
| CN110399003A (en) | A kind of opposite negative supply rail and opposite positive supply rail generation circuit | |
| US20230344328A1 (en) | Current sampling circuit and multi-level converter | |
| CN114640247B (en) | Full-period inductive current sampling circuit | |
| CN110908427A (en) | Current-limiting protection circuit applied to high-voltage linear voltage stabilizer | |
| CN113970949B (en) | High-speed linear voltage stabilizer with quick response | |
| CN113741609B (en) | LDO circuit with adjustable output voltage and quick transient response | |
| CN109769323A (en) | A kind of LED drive circuit and control method | |
| CN208141252U (en) | A kind of fast transient response circuit applied to DC-DC converter chip | |
| CN114895743A (en) | Low starting current circuit for dynamic bias current LDO | |
| CN211207200U (en) | High power supply rejection ratio reference circuit | |
| CN114465305A (en) | Self-adaptive multi-segment rapid capacitor discharging method and discharging circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |