CN115833560B - SenseFET type full-wave inductance current sensor - Google Patents
SenseFET type full-wave inductance current sensor Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a SenseFET type full-wave inductive current sensor, and relates to the electronic technology. It includes a power stage for modulating the inductor current I L The method comprises the steps of carrying out a first treatment on the surface of the Valley current sensor for collecting valley inductance current signal I L,valley And outputs the drain voltage VX valley The method comprises the steps of carrying out a first treatment on the surface of the Peak current sensor for collecting and outputting sampling signal I Lsen ＝I L /A L The method comprises the steps of carrying out a first treatment on the surface of the A peak enable signal generator for generating an enable signal in the peak current sensor; and a valley enable signal generator for generating an enable signal in the valley current sensor. The invention ensures the output of the current sensor in the dead zone period through the setting of the dead zone sampling and holding capacitor, can reduce the slew rate requirement of the operational amplifier and the bandwidth requirement of the negative feedback closed loop, simultaneously avoids the limitation of the dead zone sampling and holding capacitor on the bandwidth of the negative feedback closed loop, and improves I Lsen Is used for the sampling accuracy of the (c).
Description
Technical Field
The present invention relates to electronics, and more particularly, to a sensor type full wave inductive current sensor.
Background
The inductive current sensor is used for collecting inductive current I in real time L Information and output of equal proportion I L /A L For the control system, A L Referred to as the sensing ratio and is a constant. Inductor current sensors are commonly used in control systems of current-mode switching inductors (DC-DC), play a role in modulating and limiting amplitude of inductor current, and are often independently researched as a relatively independent submodule of the control system. The SenseFET type current sensor has high integration level and low lossAnd the precision is controllable, and the like, and has the research heat.
As shown in fig. 1, in the DC-DC structure, input stage power transistors MP and MN are alternately turned on, and the conductive states of each other are not overlapped, inductance current necessarily flows through MP and MN, and the sensor-type current sensor uses this feature to obtain sensing inductance current by sampling drain currents of the power transistors MP and MN, respectively [1] . Assume that drain currents flowing through power transistors MP and MN are respectively I L,peak And I L,valley Respectively characterize I L Rise and fall phases of (I), i.e. I L ＝I L,peak +I L,valley By two negative feedback loops G peak And G valley Respectively make power tube MP and field effect tube MP m1 Power tube MN and field effect tube MN m1 The two sets of current mirrors are in the same bias state. At this time, if the current mirror size satisfies MP: MP m1 ＝MN:MN m1 ＝A L 1, MP m1 And MN (Mobile node) m1 The current of (a) is I respectively Lsen,peak ＝I L,peak /A L And I Lsen,valley ＝I L,valley /A L Will I Lsen,peak And I Lsen,valley The sensing current I can be obtained by direct addition Lsen ＝I L /A L 。
The conventional structure of the SenseFoet type current sensor has two problems:
1. the power tubes MP and MN are alternately conducted and are in negative feedback closed loop G peak During the stable period, the negative feedback loop G valley OPA of the op-amp in (a) valley In a saturated or cut-off state, the operational amplifier OPA is operated at the beginning of the conduction of the power tube MN each time valley It is necessary to go through a start-up procedure which takes a longer time and during which the error is larger. The same problem occurs at the beginning of the turn-on of the power transistor MP. The problem is to operational amplifier OPA peak And OPA valley Is a slew rate of (1) and a negative feedback closed loop G peak And G valley Is highly demanding.
2. Dead zones which are not conducted in the period of alternating conduction of the power tubes MP and MN exist, and a signal I is sampled in the dead zone period Lsen,peak And I Lsen,valley Are all 0, but I L And the sensing current is not 0, and no output and huge error are introduced.
For the above problems, publication [2-8]Optimizing turning process of SenseFoet type current sensor during alternate conduction period of power transistors MP and MN by adopting common output stage mode, and reducing operational amplifier OPA by keeping output stage in linear region peak And OPA valley Performance requirements for slew rate. Therein, publication [2-6]Shared operational amplifier structure (i.e. operational amplifier OPA) peak And OPA valley The same operational amplifier), and a dead zone sampling holding capacitor is added in the operational amplifier output stage, so that the problem that sensing current is not output in the dead zone period is solved, and the requirement on the operational amplifier slew rate is further reduced. But the dead zone sample-and-hold capacitor is present in the negative feedback closed loop G peak And G valley In the method, the bandwidth increase of the closed loop is limited, and the negative feedback of the closed loop G is not easy peak And G valley Fast and stable, and due to the common use of operational amplifiers, the negative feedback closed loop G valley Both the gain and bandwidth of the feedback loop G peak Reduce the inductance current I of the falling stage L,valley Is used for the sampling accuracy of the (c). And publication [7,8 ]]The structure of the common output stage but not the common operational amplifier is adopted, the problem that the sensing current is not output in the dead zone period is ignored, and the turning process of the current sensor from the cut-off of the power tube MN to the conduction of the power tube MP is only optimized, I L,valley The sampling accuracy of (a) is very low.
The following are 8 publications referred to above.
[1]Man T Y,Mok P K T,Chan M.Design of Fast-Response On-Chip Current Sensor for Current-Mode Controlled Buck Converters with MHz Switching Frequency[C].2007IEEE International Conference on Electron Devices and Solid-State Circuits,2007:389-392.
[2]Zhu L,Chen B,Zheng Y,et al.A Fast-Response Buck-Boost DC-DC Converter with Constructed Full-Wave Current Sensor[C].2016International Symposium on Integrated Circuits,2016.
[3]Li B,Yang J,Wu Z,et al.A Fast-Response Full-Wave Current-Sensing Circuit for DC-DC Converter Operating in 10MHz Switching Frequency[C].2017International Conference on Electron Devices and Solid-State Circuits,2017.
[4]Zhou Y,Zheng Y,Leung K N.Fast-Response Full-Wave Inductor Current Sensor for 10MHz Buck Converter[J].Electronics Letters,2018,54(6):379-380.
[5]Zhou Y,Lin X,Yang J,et al.Adaptive-Biased Sense-FET-Based Inductor-Current Sensor for 10-MHz Buck Converter[J].International Journal of Circuit Theory and Applications,2020,48(6):953-964.
[6]Zhou Y,Cheng Q,Li J,et al.Full-Wave Sense-FET-Based Inductor-Current Sensor With Wide Dynamic Range for Buck Converters[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2022,69(4):2041-2045.
[7]Jung-Woo H,Bai-Sun K,Jung-Hoon C,et al.A Fast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator[C].ESSCIRC 2014-40th European Solid State Circuits Conference,2014:155-8.
[8]Zhou M,Sun Z,Low Q W,et al.Multiloop Control for Fast Transient DC-DC Converter[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2019,27(1):219-228.
Disclosure of Invention
The invention aims to solve the technical problem of providing a SenseFET type full-wave inductance current sensor aiming at the defects of the prior art.
The technical scheme of the invention is as follows: a sensor eFET type full wave inductive current sensor comprising,
the power stage consists of a first power tube MP and a second power tube MN which are connected with each other by a drain electrode, and the drain electrode connecting ends of the first power tube MP and the second power tube MN output an inductance voltage signal VX;
valley current sensor comprising a first operational amplifier OPA valley Fourteenth field effect transistor M 14 First field effect transistor M 1 Second field effect transistor M 2 And a first control unit; the second field effect transistor M 2 Is connected with the input end of the power stage, the second field effect transistor M 2 The gate electrode of the second field effect transistor M is grounded 2 Is to output the drain voltage VX valley And the second field effect transistor M 2 Drain electrode of (d) and fourteenth field effect transistor M 14 Is connected with the source electrode of the transistor; the fourteenth field effect transistor M 14 Gate of (c) and first op-amp OPA valley The fourteenth field effect transistor M is connected with the output end of 14 The drain electrode of (a) is connected with the first operational amplifier OPA through the first control unit valley Is connected with the positive phase input end of the first negative feedback closed loop G valley The method comprises the steps of carrying out a first treatment on the surface of the The first control unit is also connected with a first operational amplifier OPA valley Is connected with the inverting input terminal of the first negative feedback closed loop G valley Is open loop or closed loop; the first field effect transistor M 1 The drain electrode of the first FET M inputs an inductance voltage signal VX 1 Is input into the first control unit for controlling the first negative feedback closed loop G valley Second enable signal PS being a closed loop n The source electrode of the first field effect transistor M1 is connected with the first control unit;
peak current sensor comprising a second operational amplifier OPA peak Sixth field effect transistor M 6 Third field effect transistor M 3 The mirror image tube pair and the second control unit; the output end of the second control unit and a second operational amplifier OPA peak Is connected to the inverting input terminal for time-sharing input of the drain voltage VX valley An inductance voltage signal VX; and the second operational amplifier OPA peak The inverting input end of (a) is connected with a dead zone sampling and holding capacitor C s The method comprises the steps of carrying out a first treatment on the surface of the The second operational amplifier OPA peak And a sixth field effect transistor M 6 Gate connection of the sixth field effect transistor M 6 The drain electrode of (a) passes through the second control unit and the second operational amplifier OPA peak Is connected with the positive phase input end of the second negative feedback closed loop G peak The method comprises the steps of carrying out a first treatment on the surface of the The sixth field effect transistor M 6 Drain electrode of (d) and third field effect transistor M 3 Is connected with the drain electrode of the third field effect transistor M 3 The gate electrode of the third field effect transistor M is grounded 3 The source electrode of the power stage is connected with the input end of the power stage; the sixth field effect transistor M 6 Source and mirror tube pairs of (c)The output end of the mirror image tube pair outputs a sampling signal I Lsen 。
The first power tube MP and the second field effect tube M 2 Is a mirror image ratio of A L 1, the first power tube MP and the third field effect tube M 3 Is a mirror image ratio of A L 1, the second power tube MN and the first field effect tube M 1 Is a mirror image ratio of A L :1。
The first power tube MP and the second field effect tube M 2 Third field effect transistor M 3 Are PMOS; the second power tube MN and the first field effect tube M 1 Are NMOS.
When the first power tube MP is turned on and the second power tube MN is turned off, the inductance current I L Through the first power tube MP, the inductance current is the peak value I L ＝I L,peak . The first control unit controls the first operational amplifier OPA valley The input ends of the first operational amplifier OPA are all grounded to the signal valley Operating in the linear region, a first negative feedback closed loop G valley Is open loop. The second control unit controls the second operational amplifier OPA peak The drain voltage of the first power transistor MP, i.e., the inductor voltage signal VX, is input to the inverting input terminal of the first power transistor MP. Due to the second negative feedback loop G peak Is closed loop, so that the third field effect transistor M 3 The third FET M is in the same bias state as the first power transistor MP 3 Is I L,peak /A L And is equal to the leakage current of the field effect transistor in the mirror image tube pair, namely I Lsen ＝I L,peak /A L 。
When the first power tube MP is turned off and the second power tube MN is turned on, the inductance current I L Through the second power tube MN, the inductance current is the valley value I L ＝I L,valley . The first control unit controls the first negative feedback closed loop G valley In a closed loop state to enable the first field effect transistor M to 1 The second power tube MN is in the same bias state, and the second field effect tube M 2 Drain current of (2) and first field effect transistor M 1 Is equal to the drain current of I L,valley /A L . The second control unit controls the second operational amplifier OPA peak Is input with drain voltage VX at the inverting input terminal valley Second operational amplifier OPA peak And a sixth field effect transistor M 6 A second negative feedback closed loop G peak Let the second field effect transistor M 2 And a third field effect transistor M 3 In the same bias state, the third FET M 3 Is I L,valley /A L I.e. I Lsen ＝I L,valley /A L 。
The first control unit comprises an eighth field effect transistor M 8 Ninth field effect transistor M 9 Tenth field effect transistor M 10 And an eleventh field effect transistor M 11 The method comprises the steps of carrying out a first treatment on the surface of the The ninth field effect transistor M 9 Gate of (c) and first field effect transistor M 1 The gates of (a) are all input with a second enable signal PS n The ninth FET M 9 Source electrode of (c) and fourteenth field effect transistor M 14 Is connected with the drain electrode of the ninth field effect transistor M 9 Drain electrode of (a) and first operational amplifier OPA valley Is connected with the non-inverting input end of the first operational amplifier OPA valley Is passed through eleventh field effect transistor M 11 Grounded, and the eleventh FET M 11 The grid electrode of the power stage is connected with the input end of the power stage; the first field effect transistor M 1 Source electrode of (c) and eighth field effect transistor M 8 Is connected with the drain electrode of the eighth field effect transistor M 8 The source electrode of the (a) is grounded; the first operational amplifier OPA valley And a tenth field effect transistor M 10 Is connected with the drain electrode of the tenth field effect transistor M 10 The source electrode of the (a) is grounded; and the eighth field effect transistor M 8 And tenth field effect transistor M 10 Is connected to the gate of the first transistor and inputs the signal state and the second enable signal PS n The opposite fifth enable signal-! PS (PS) n 。
The second control unit comprises a fourth field effect transistor M 4 Fifth field effect transistor M 5 And a seventh field effect transistor M 7 The method comprises the steps of carrying out a first treatment on the surface of the The fourth field effect transistor M 4 A third enable signal LVX is input to the gate of the fourth FET M 4 The source electrode of which is input with an inductance voltage signal VX; the fifth field effect transistor M 5 A gate of (a) inputs a fourth enable signal LVX valley The fifth field effect transistor M 5 Is input with the source-drain voltage VX valley The method comprises the steps of carrying out a first treatment on the surface of the The fourth field effect transistor M 4 Fifth field effect transistor M 5 Drain electrodes of the first and second operational amplifiers OPA peak Is connected with the inverting input end of the power supply; the seventh field effect transistor M 7 The gate of the seventh field effect transistor M is grounded 7 Drain electrode of (a) and second operational amplifier OPA peak Is connected with the non-inverting input end of the seventh field effect transistor M 7 Source electrode of (c) and sixth field effect transistor M 6 Is connected to the drain of the transistor.
The seneFet type full wave inductor current sensor further comprises,
a valley enable signal generator for generating a valley enable signal based on the inputted seventh enable signal-! BPS (binary phase shift keying) n Outputs a second enable signal PS n Fifth enable signal-! PS (PS) n And a fourth enable signal LVX valley ；
A peak enable signal generator for generating a peak enable signal according to the inputted sixth enable signal-! BPS (binary phase shift keying) p Outputs a first enable signal PS p And a third enable signal LVX.
The sixth enable signal-! BPS (binary phase shift keying) p A first delay t exists between the rising edge of the third enable signal LVX and the falling edge of the fourth enable signal LVX senlop And the falling edge of the third enable signal LVX lags behind the sixth enable signal-! BPS (binary phase shift keying) p Rising edge of (2);
the second enable signal PS n Rising edge of (v) and fourth enable signal LVX valley There is a second delay t between the falling edges of (a) senlov And the fourth enable signal LVX valley Is delayed from the falling edge of the second enable signal PS n Is provided for the rising edge of (a).
The peak enable signal generator comprises a fifteenth field effect transistor M 15 Sixteenth field effect transistor M 16 Seventeenth field effect transistor M 17 Eighteenth field effect transistor M 18 First inverter INV 1 First NAND gate NAND 1 A first resistor R senlop First capacitor C senlop The method comprises the steps of carrying out a first treatment on the surface of the The fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 The gates of (a) all input a sixth enable signal-! BPS (binary phase shift keying) p The fifteenth field effect transistor M 15 Is connected with the input end of the power stage, the fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 Is connected to the drain of (a) and is used as a first enable signal PS p A signal output terminal of (a); the seventeenth field effect transistor M 17 Source ground PGND; the sixteenth field effect transistor M 16 Eighteenth field effect transistor M 18 The gates of (a) are all connected with an enable signal-! BPS (binary phase shift keying) p The sixteenth field effect transistor M 16 Is connected with the input end of the power stage, the first resistor R senlop One end of (C) a first capacitor C senlop Sixteenth field effect transistor M 16 Drain electrodes of the first inverter INV 1 Is connected with the input end of the first resistor R senlop The other end and an eighteenth field effect transistor M 18 The eighteenth FET M is connected with the drain electrode of the transistor 18 Source of (C) first capacitor (C) senlop The other ends of the two terminals are all grounded; the first inverter INV 1 Is connected with the output end of the first NAND gate 1 Is connected with one input end of the first NAND gate 1 A sixth enable signal is input to the other input terminal of-! BPS (binary phase shift keying) p The first NAND gate NAND 1 The output terminal of (a) outputs a third enable signal LVX.
The valley enable signal generator comprises a second capacitor C senlov Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Second inverter INV 2 Third inverter INV 3 Fourth inverter INV 4 Fifth inverter INV 5 And a second NAND gate NAND 2 The method comprises the steps of carrying out a first treatment on the surface of the The nineteenth FET M 19 Twentieth field effect transistor M 20 The gates of (a) all input a seventh enable signal-! BPS (binary phase shift keying) n The nineteenth FET M 19 Is connected with the input end of the power stage, the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Drain phase of (a)Connected in parallel as a second enable signal PS n And the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 The drain electrode connection end of (a) is respectively connected with the third inverter INV 3 And a fifth inverter INV 5 Is connected with the input end of the twentieth field effect transistor M 20 Source ground PGND; the fifth inverter INV 5 As a fifth enable signal-! PS (PS) n A signal output terminal of (a); the third inverter INV 3 Output end of (a) and fourth inverter INV 4 Is connected with the input end of the second capacitor C senlov One end of (a) is connected with the third inverter INV 3 The output end of the second capacitor C is connected with senlov The other end of the first signal is grounded; the fourth inverter INV 4 Is connected with the output end of the second NAND gate 2 Is connected with one input end of the second NAND gate 2 Another input end of the second inverter INV 2 The output end of the second inverter INV is connected with 2 A seventh enable signal is input to the input terminal of-! BPS (binary phase shift keying) n The second NAND gate NAND 2 As the output of the fourth enable signal LVX valley Is provided.
Advantageous effects
The invention has the advantages that:
1. compared with a SenseFET type current sensor with a traditional structure, the invention has the characteristics of common output stage and dead zone sampling holding capacitor, and the operational amplifier OPA peak And OPA valley All are kept in the linear region, and the dead zone sampling and holding capacitor ensures the output of the current sensor during the dead zone period, so that the OPA can be reduced peak And OPA valley Is a slew rate requirement and a negative feedback closed loop G peak And G valley Is not required.
2. Compared with a SenseFoet type current sensor with a common output stage and a common operational amplifier structure, the invention has the advantages that the negative feedback closed loop G peak Is stable and can reduce the negative feedback closed loop G peak Is not required. Negative feedback closed loop G peak And G valley Relatively independent, avoid negative feedback closed loop G peak Bandwidth-to-negative feedback closed loop G valley Bandwidth limitations. The dead zone sampling holding capacitor is arranged in a negative feedback closed loop G peak And G valley Besides, the dead zone sampling and holding capacitor pair negative feedback closed loop G is avoided peak And G valley Bandwidth limitations.
3. Relative to a SenseFoet type current sensor with a common output stage but without a common operational amplifier structure, the operational amplifier OPA in the invention valley Is kept in a linear region and has a dead zone sampling and holding capacitor, thereby optimizing the turning process of the current sensor from the cut-off of the power tube MP to the conduction of the power tube MN and improving I L,valley Is used for the sampling accuracy of the (c).
Drawings
FIG. 1 is a schematic diagram of a conventional sense eFET type current sensing circuit;
FIG. 2 is a schematic diagram of a circuit configuration of a SenseFot type current sensor of the present invention;
FIG. 3 is a schematic timing diagram of the enable signal in the SenseeFET current sensor of the present invention;
FIG. 4 is a schematic diagram of a peak enable signal generator circuit according to the present invention;
fig. 5 is a schematic diagram of a valley-enable signal generator according to the present invention.
Detailed Description
The invention is further described below in connection with the examples, which are not to be construed as limiting the invention in any way, but rather as falling within the scope of the claims.
Referring to fig. 2, a SenseFET full-wave inductive current sensor of the present invention includes a power stage, a valley current sensor, a peak current sensor, a valley enable signal generator, and a peak enable signal generator.
Wherein the power stage is used for modulating the inductor current I L . The power stage consists of a first power tube MP and a second power tube MN which are connected with each other by a drain electrode. The first power tube MP is a PMOS tube, and the second power tube MN is an NMOS tube. The grid electrode of the first power tube MP inputs a first enabling signal PS p The gate of the second power transistor MN inputs the signal state and the first enable signal PS p The same second enable signal PS n The substrate of the first power tube MP is connected with the source electrode. The source of the first power tube MP is used as the input end of the power stage for inputting the voltage source signal V source The source electrode of the second power tube MN is grounded to the power PGND, and the substrate of the second power tube MN is grounded to the signal. The drain electrodes of the first power tube MP and the second power tube MN are connected to output an inductance current signal I L The output inductor voltage signal is denoted VX. The first power tube MP and the second power tube MN are alternately turned on, and the conductive states of each other do not overlap. Namely, a dead zone exists between the first power tube MP and the second power tube MN, and the first enable signal PS p And a second enable signal PS n Dead zones also exist between them.
Valley current sensor for collecting valley inductance current signal I L,valley And outputs a second field effect transistor M 2 Is set to the drain voltage VX of (2) valley . It comprises a first operational amplifier OPA valley Fourteenth field effect transistor M 14 First field effect transistor M 1 Second field effect transistor M 2 And a first control unit. The first control unit comprises an eighth field effect transistor M 8 Ninth field effect transistor M 9 Tenth field effect transistor M 10 And an eleventh field effect transistor M 11 . First field effect transistor M 1 Eighth field effect transistor M 8 Ninth field effect transistor M 9 Tenth field effect transistor M 10 And an eleventh field effect transistor M 11 Are NMOS transistors, and a second field effect transistor M 2 Fourteenth field effect transistor M 14 Is a PMOS tube. The specific circuit connection structure of the valley current sensor is as follows.
Second field effect transistor M 2 Is input with a voltage source signal V source The gate is grounded, the drain is used as the output drain voltage VX valley And is connected with the fourteenth field effect transistor M 14 Is connected to the source of the (c). First operational amplifier OPA valley Is connected with the inverting input terminal of the eleventh field effect transistor M 11 Drain electrode connection of eleventh field effect transistor M 11 Source electrode of the eleventh field effect transistor M is grounded 11 Is input with a voltage source signal V by the grid electrode source . First operational amplifier OPA valley Respectively with the ninth field effect transistor M 9 Tenth field effect transistor M 10 Drain electrode connection of tenth field effect transistor M 10 Source electrode of the tenth field effect transistor M is grounded 10 And eighth field effect transistor M 8 Is connected to the gate of (A) and inputs a fifth enable signal-! PS (PS) n . Ninth field effect transistor M 9 Gate input signal state and fifth enable signal-! PS (PS) n An opposite second enable signal PS n Ninth field effect transistor M 9 The source electrode of (a) is respectively connected with the first field effect transistor M 1 Source electrode of fourteenth field effect transistor M 14 Drain electrode of (c) and eighth field effect transistor M 8 Drain electrode connection of eighth field effect transistor M 8 The source of (c) is grounded. First field effect transistor M 1 A second enable signal PS is input to the gate of (C) n First field effect transistor M 1 The drain of which receives the inductor voltage signal VX. Fourteenth field effect transistor M 14 Gate of (c) and first op-amp OPA valley Is connected with the output end of the power supply. Fourteenth field effect transistor M 14 With a first operational amplifier OPA valley Form a first negative feedback closed loop G valley 。
The peak current sensor is used for collecting and outputting a sampling signal I Lsen . It comprises a second operational amplifier OPA peak Sixth field effect transistor M 6 Third field effect transistor M 3 Mirror tube pair, second control unit and dead zone sample-hold capacitor C s . The mirror image tube pair consists of a twelfth field effect tube M 12 And thirteenth field effect transistor M 13 Composition is prepared. The second control unit comprises a fourth field effect transistor M 4 Fifth field effect transistor M 5 And a seventh field effect transistor M 7 . Sixth field effect transistor M 6 Twelfth field effect transistor M 12 And thirteenth field effect transistor M 13 Are NMOS transistors, and a third field effect transistor M 3 Fourth field effect transistor M 4 Fifth field effect transistor M 5 Seventh field effect transistor M 7 Are PMOS tubes. The specific circuit connection structure of the peak current sensor is as follows.
Third field effect transistor M 3 The gate of (2) is grounded, and the source thereof inputs a voltage source signal V source The drain electrode of the transistor is respectively connected with a seventh field effect transistor M 7 Source electrode of (d), sixth field effect transistor M 6 Is connected to the drain of the transistor. Seventh field effect transistor M 7 The grid electrode of the transistor is grounded, and the drain electrode of the transistor is connected with the second operational amplifier OPA peak Is connected with the non-inverting input terminal of the circuit. Fifth field effect transistor M 5 Source electrode of (C) and second field effect transistor M 2 Is connected with the drain of the transistor to input the drain voltage VX valley . Fifth field effect transistor M 5 A gate of (a) inputs a fourth enable signal LVX valley . Fourth field effect transistor M 4 The gate of which is input with the third enable signal LVX and the source of which is input with the inductor voltage signal VX. Fourth field effect transistor M 4 Fifth field effect transistor M 5 Drain electrodes of the first and second operational amplifiers OPA peak Is connected with the inverting input terminal of the second operational amplifier OPA peak And dead zone sample-hold capacitor C s One end of the dead zone sampling holding capacitor C is connected with s The other end of which is grounded.
Here, the dead zone sample-and-hold capacitor C s Ensuring output during dead zone of current sensor, and reducing OPA of second operational amplifier peak And a first operational amplifier OPA valley Is a slew rate requirement and a negative feedback closed loop G peak And G valley Is not required. In addition, a dead zone sample-and-hold capacitor C s Is arranged in a negative feedback closed loop G peak And G valley Besides, the dead zone sampling and holding capacitor C is avoided s To negative feedback closed loop G peak And G valley Bandwidth limitations.
Second operational amplifier OPA peak And a sixth field effect transistor M 6 Is connected to the gate of the transistor. Sixth field effect transistor M 6 With a second operational amplifier OPA peak Form a second negative feedback closed loop G peak . Sixth field effect transistor M 6 Source electrode of (c) and twelfth field effect transistor M 12 Is connected with the drain electrode of the thirteenth field effect transistor M 13 Gate of (c) and twelfth field effect transistor M 12 Gate connection of thirteenth field effect transistor M 13 As the drain of the sampling signal I Lsen Is provided. Thirteenth field effect transistor M 13 And a twelfth field effect transistor M 12 The source of (c) is grounded.
In the present embodiment, a first power transistor MP and a second field effect transistor M 2 Is a mirror image ratio of A L 1, a second power tube MN and a first field effect tube M 1 Is a mirror image ratio of A L 1, a first power tube MP and a third field effect tube M 3 Is a mirror image ratio of A L 1, twelfth field effect transistor M 12 And thirteenth field effect transistor M 13 The mirror image ratio is 1:1.
At the enable signal PS p ＝PS n When=0, enable signal +.! PS (PS) n ＝！BPS p ＝！BPS n ＝LVX valley =1, lvx=0. At this time, the first power tube MP is turned on, the second power tube MN is turned off, and the inductance current I L Flows through the first power tube MP. Eighth field effect transistor M 8 Tenth field effect transistor M 10 And an eleventh field effect transistor M 11 All are in a conducting state, and the first operational amplifier OPA valley The input ends of (a) are grounded and operate in a linear region, a first negative feedback closed loop G valley Is open loop. Inductor current I L Through the first power tube MP, the inductance current is the peak value I L ＝I L,peak Second operational amplifier OPA peak An inductance voltage signal VX is input to the inverting input terminal of the second operational amplifier OPA peak And a sixth field effect transistor M 6 A second negative feedback closed loop G peak Let the third field effect transistor M 3 The third FET M is in the same bias state as the first power transistor MP 3 Is I L,peak /A L And is connected with a twelfth field effect transistor M 12 And thirteenth field effect transistor M 13 Is equal in leakage current, i.e. I Lsen ＝I Lsen,peak ＝I L,peak /A L 。
At the enable signal PS p ＝PS n When=1, enable signal +.! PS (PS) n ＝！BPS p ＝！BPS n ＝LVX valley =0, lvx=1. At this time, the first power tube MP is turned off, and the second power tube MN is turned on. Eighth field effect transistor M 8 Tenth field effect transistor M 10 In the cut-off state, the ninth field effect transistor M 9 In the on state, inductor current I L Through the second power tube MN, the inductance current is the valley value I L ＝I L,valley First operational amplifier OPA valley And a fourteenth field effect transistor M 14 First negative feedback closed loop G valley Make the first field effect transistor M 1 The first field effect transistor M is in the same bias state as the first power transistor MN 1 Is I L,valley /A L And is connected with a second field effect transistor M 2 Is equal. Second operational amplifier OPA peak Is connected to the drain voltage VX valley Second operational amplifier OPA peak And a sixth field effect transistor M 6 A second negative feedback closed loop G peak Let the third field effect transistor M 3 And a second field effect transistor M 2 In the same bias state, the third FET M 3 Is I L,valley /A L I.e. I Lsen ＝I Lsen,valley ＝I L,valley /A L 。
According to the invention, the operational amplifier in the peak current sensor and the valley current sensor is kept in a linear region, and the dead zone sampling and holding capacitor is combined to ensure the output of the current sensor in the dead zone period, so that the slew rate requirement of the two operational amplifiers can be reduced. By sampling signal I Lsen ＝I L /A L The stable output is at the output end of the peak current sensor, the negative feedback closed loop where the peak current sensor is located is stable all the time, and the dead zone sampling holding capacitor is arranged outside the negative feedback closed loop where the peak current sensor and the valley current sensor are respectively located, so that the limitation of the dead zone sampling holding capacitor to the bandwidths of the two closed loops is avoided, and the bandwidth requirements of the two closed loops can be reduced by combining the dead zone sampling holding capacitor with the negative feedback closed loop. Dead zone output of the current sensor, slew rate of the operational amplifier and bandwidth optimization of the closed loop can improve sampling signal I Lsen ＝I L /A L Is a precision of (a).
Referring to FIGS. 3-5, a peak enable signal generator is used for generating an enable signal in the peak current sensor, and is composed of a fifteenth FET M 15 Sixteenth field effect transistor M 16 Seventeenth field effect transistor M 17 Eighteenth field effect transistor M 18 First inverter INV 1 First NAND gateNAND 1 A first resistor R senlop First capacitor C senlop Composition is prepared. Which inputs a sixth enable signal-! BPS (binary phase shift keying) p Outputs a first enable signal PS p And a third enable signal LVX. As shown in fig. 3, the sixth enable signal ≡! BPS (binary phase shift keying) p Is a signal in the driving chain of the first power tube MP, which is a first enable signal PS in time sequence p Previously, the phase and the first enable signal PS p In contrast, edges differ only in delay. The third enable signal LVX is used for controlling the dead zone sample-and-hold capacitor C s The sampling and holding time of the inductance voltage signal VX output node is required to be high before the first power tube MP is turned off, and the fourth field effect tube M is turned off 4 Maintaining the inductor voltage signal VX; and the fourth field effect transistor M is turned on after the first power transistor MP is stably turned on 4 The inductor voltage signal VX is sampled.
In order to make the third enable signal LVX low after the first power transistor MP is turned on stably, the third enable signal LVX is low after the sixth enable signal-! BPS (binary phase shift keying) p A first delay t is set between the rising edge of the third enable signal LVX and the falling edge of the third enable signal LVX senlop And the falling edge of the third enable signal LVX lags behind the sixth enable signal-! BPS (binary phase shift keying) p A first delay t senlop From the resistance R senlop And capacitor C senlop And (3) generating. By a first delay t senlop The third enable signal LVX is set low after the first power transistor MP is turned on stably.
The peak enable signal generator of the present embodiment has a structure including a fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 The gates of (a) all input a sixth enable signal-! BPS (binary phase shift keying) p Fifteenth field effect transistor M 15 Is input with a voltage source signal V source Fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 Is connected to the drain of (a) and is used as a first enable signal PS p A signal output terminal of (a); seventeenth field effect transistor M 17 Source ground PGND; sixteenth field effect transistor M 16 Eighteenth field effect transistor M 18 The gates of (a) are all connected with an enable signal-! BPS (binary phase shift keying) p Sixteenth field effect transistor M 16 Is connected with the source electrode of the input voltage source signalV source First resistor R senlop One end of (C) a first capacitor C senlop Sixteenth field effect transistor M 16 Drain electrodes of the first inverter INV 1 Is connected with the input end of the first resistor R senlop The other end and an eighteenth field effect transistor M 18 Drain electrode connection of eighteenth field effect transistor M 18 Source of (C) first capacitor (C) senlop The other ends of the two terminals are all grounded; first inverter INV 1 Is connected with the output end of the first NAND gate 1 Is connected with one input end of the first NAND gate 1 A sixth enable signal is input to the other input terminal of-! BPS (binary phase shift keying) p First NAND gate NAND 1 The output terminal of (a) outputs a third enable signal LVX.
A valley enable signal generator for generating an enable signal in the valley current sensor, and a second capacitor C senlov Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Second inverter INV 2 Third inverter INV 3 Fourth inverter INV 4 Fifth inverter INV 5 And a second NAND gate NAND 2 Composition is prepared. Which inputs a seventh enable signal-! BPS (binary phase shift keying) n Outputs a second enable signal PS n Fifth enable signal-! PS (PS) n And a fourth enable signal LVX valley . As shown in fig. 3, the seventh enable signal ≡! BPS (binary phase shift keying) n Is a signal in the driving chain of the second power transistor MN, which is time-sequentially on the second enable signal PS n Previously, the phase and the second enable signal PS n In contrast, edges differ only in delay. First enable signal PS p And a second enable signal PS n There is a dead zone between, i.e. the sixth enable signal-! BPS (binary phase shift keying) p And a seventh enable signal-! BPS (binary phase shift keying) n There is a dead zone in between. Fifth enable signal-! PS (PS) n And a second enable signal PS n Only the phases are opposite, and the edge delay is extremely small and negligible. Fourth enable signal LVX valley For controlling dead zone sample-and-hold capacitance C s Is to the drain voltage VX valley The sampling and holding time of the output node is required to be high before the second power tube MN is turned off, and the fifth field effect tube M is turned off 5 Maintaining drain voltage VX valley The method comprises the steps of carrying out a first treatment on the surface of the And the valley inductance current signal I is required to be stably collected at the valley current sensor L,valley And outputs the drain voltage VX valley Rear low, turn on fifth FET M 5 Sampling drain voltage VX valley 。
Second enable signal PS n Rising edge of (v) and fourth enable signal LVX valley There is a second delay t between the falling edges of (a) senlov And fourth enable signal LVX valley Is delayed from the falling edge of the second enable signal PS n Is provided for the rising edge of (a). Second delay t senlov From a second capacitor C senlov Generating a second delay t senlov Enable the fourth enable signal LVX valley Stably collecting valley inductance current signal I in valley current sensor L,valley And outputs the drain voltage VX valley The rear position is low.
The valley enable signal generator of the present embodiment has a specific circuit structure of a nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 The gates of (a) all input a seventh enable signal-! BPS (binary phase shift keying) n Nineteenth field effect transistor M 19 Is input with a voltage source signal V source Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Is connected to the drain of (d) and is used as the second enable signal PS n And nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 The drain electrode connection end of (a) is respectively connected with the third inverter INV 3 And a fifth inverter INV 5 Is connected with the input end of the twentieth field effect transistor M 20 Is connected to the source terminal of PGND. Fifth inverter INV 5 As a fifth enable signal-! PS (PS) n A signal output terminal of (a); third inverter INV 3 Output end of (a) and fourth inverter INV 4 Is connected with the input end of the second capacitor C senlov One end of (a) is connected with the third inverter INV 3 Is connected with the output end of the second capacitor C senlov The other end of the first signal is grounded; fourth inverter INV 4 Is connected with the output end of the second NAND gate 2 Is connected with one input end of the second NAND gate 2 Another input end of the second inverter INV 2 Is connected with the output end of the second inverter INV 2 A seventh enable signal is input to the input terminal of-! BPS (binary phase shift keying) n Second NAND gate NAND 2 As the output of the fourth enable signal LVX valley Is provided.
While only the preferred embodiments of the present invention have been described above, it should be noted that modifications and improvements can be made by those skilled in the art without departing from the structure of the present invention, and these do not affect the effect of the implementation of the present invention and the utility of the patent.
Claims (6)
1. A sensor eFET type full wave inductive current sensor comprising,
the power stage consists of a first power tube MP and a second power tube MN which are connected with each other by a drain electrode, and the drain electrode connecting ends of the first power tube MP and the second power tube MN output an inductance voltage signal VX;
it is characterized in that the utility model also comprises,
valley current sensor comprising a first operational amplifier OPA valley Fourteenth field effect transistor M 14 First field effect transistor M 1 Second field effect transistor M 2 And a first control unit; the second field effect transistor M 2 Is connected with the input end of the power stage, the second field effect transistor M 2 The gate electrode of the second field effect transistor M is grounded 2 Is to output the drain voltage VX valley And the second field effect transistor M 2 Drain electrode of (d) and fourteenth field effect transistor M 14 Is connected with the source electrode of the transistor; the fourteenth field effect transistor M 14 Gate of (c) and first op-amp OPA valley The fourteenth field effect transistor M is connected with the output end of 14 The drain electrode of (a) is connected with the first operational amplifier OPA through the first control unit valley Is connected with the positive phase input end of the first negative feedback closed loop G valley The method comprises the steps of carrying out a first treatment on the surface of the The first control unit is also connected with a first operational amplifier OPA valley Is connected with the inverting input terminal of the first negative feedback closed loop G valley Is open loop or closed loop; the first field effect transistor M 1 The drain electrode of the first FET M inputs an inductance voltage signal VX 1 Is input into the first control unit for controlling the first negative feedback closed loop G valley Second enable signal PS being a closed loop n The source electrode of the first field effect transistor M1 is connected with the first control unit;
peak current sensor comprising a second operational amplifier OPA peak Sixth field effect transistor M 6 Third field effect transistor M 3 The mirror image tube pair and the second control unit; the output end of the second control unit and a second operational amplifier OPA peak Is connected to the inverting input terminal for time-sharing input of the drain voltage VX valley An inductance voltage signal VX; and the second operational amplifier OPA peak The inverting input end of (a) is connected with a dead zone sampling and holding capacitor C s The method comprises the steps of carrying out a first treatment on the surface of the The second operational amplifier OPA peak And a sixth field effect transistor M 6 Gate connection of the sixth field effect transistor M 6 The drain electrode of (a) passes through the second control unit and the second operational amplifier OPA peak Is connected with the positive phase input end of the second negative feedback closed loop G peak The method comprises the steps of carrying out a first treatment on the surface of the The sixth field effect transistor M 6 Drain electrode of (d) and third field effect transistor M 3 Is connected with the drain electrode of the third field effect transistor M 3 The gate electrode of the third field effect transistor M is grounded 3 The source electrode of the power stage is connected with the input end of the power stage; the sixth field effect transistor M 6 The source electrode of the mirror image tube pair is connected with the input end of the mirror image tube pair, and the output end of the mirror image tube pair outputs a sampling signal I Lsen ；
The first control unit comprises an eighth field effect transistor M 8 Ninth field effect transistor M 9 Tenth field effect transistor M 10 And an eleventh field effect transistor M 11 The method comprises the steps of carrying out a first treatment on the surface of the The ninth field effect transistor M 9 Gate of (c) and first field effect transistor M 1 The gates of (a) are all input with a second enable signal PS n The ninth FET M 9 Source electrode of (c) and fourteenth field effect transistor M 14 Is connected with the drain electrode of the ninth field effect transistor M 9 Drain electrode of (a) and first operational amplifier OPA valley Is connected with the non-inverting input end of the first operational amplifier OPA valley Is passed through eleventh field effect transistor M 11 Grounded, and the eleventh FET M 11 The grid electrode of the power stage is connected with the input end of the power stage; the first field effect transistor M 1 Source electrode of (c) and eighth field effect transistor M 8 Is connected with the drain electrode of the eighth field effect transistor M 8 The source electrode of the (a) is grounded; the first operational amplifier OPA valley And a tenth field effect transistor M 10 Is connected with the drain electrode of the tenth field effect transistor M 10 The source electrode of the (a) is grounded; and the eighth field effect transistor M 8 And tenth field effect transistor M 10 Is connected to the gate of the first transistor and inputs the signal state and the second enable signal PS n The opposite fifth enable signal-! PS (PS) n ；
The second control unit comprises a fourth field effect transistor M 4 Fifth field effect transistor M 5 And a seventh field effect transistor M 7 The method comprises the steps of carrying out a first treatment on the surface of the The fourth field effect transistor M 4 A third enable signal LVX is input to the gate of the fourth FET M 4 The source electrode of which is input with an inductance voltage signal VX; the fifth field effect transistor M 5 A gate of (a) inputs a fourth enable signal LVX valley The fifth field effect transistor M 5 Is input with the source-drain voltage VX valley The method comprises the steps of carrying out a first treatment on the surface of the The fourth field effect transistor M 4 Fifth field effect transistor M 5 Drain electrodes of the first and second operational amplifiers OPA peak Is connected with the inverting input end of the power supply; the seventh field effect transistor M 7 The gate of the seventh field effect transistor M is grounded 7 Drain electrode of (a) and second operational amplifier OPA peak Is connected with the non-inverting input end of the seventh field effect transistor M 7 Source electrode of (c) and sixth field effect transistor M 6 Is connected to the drain of the transistor.
2. The sensor of claim 1, wherein the first power transistor MP and the second field effect transistor M 2 Is a mirror image ratio of A L 1, the first power tube MP and the third field effect tube M 3 Is a mirror image ratio of A L 1, the second power tube MN and the first field effect tube M 1 Is a mirror image ratio of A L :1。
3. According to claim 1 or 2A sensor of full-wave inductance current of the sensor, characterized in that the first power tube MP and the second field effect tube M 2 Third field effect transistor M 3 Are PMOS; the second power tube MN and the first field effect tube M 1 Are NMOS.
4. The sensor of claim 1, wherein the sensor further comprises,
a valley enable signal generator for generating a valley enable signal based on the inputted seventh enable signal-! BPS (binary phase shift keying) n Outputs a second enable signal PS n Fifth enable signal-! PS (PS) n And a fourth enable signal LVX valley ；
A peak enable signal generator for generating a peak enable signal according to the inputted sixth enable signal-! BPS (binary phase shift keying) p Outputs a first enable signal PS p And a third enable signal LVX.
5. The sensor of claim 4, wherein the peak enable signal generator comprises a fifteenth fet M 15 Sixteenth field effect transistor M 16 Seventeenth field effect transistor M 17 Eighteenth field effect transistor M 18 First inverter INV 1 First NAND gate NAND 1 A first resistor R senlop First capacitor C senlop The method comprises the steps of carrying out a first treatment on the surface of the The fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 The gates of (a) all input a sixth enable signal-! BPS (binary phase shift keying) p The fifteenth field effect transistor M 15 Is connected with the input end of the power stage, the fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 Is connected to the drain of (a) and is used as a first enable signal PS p A signal output terminal of (a); the seventeenth field effect transistor M 17 Source ground PGND; the sixteenth field effect transistor M 16 Eighteenth field effect transistor M 18 The gates of (2) are connected with the sixth enable signal-! BPS (binary phase shift keying) p The sixteenth field effect transistor M 16 Source and power stage of (c)Is connected with the input end of the first resistor R senlop One end of (C) a first capacitor C senlop Sixteenth field effect transistor M 16 Drain electrodes of the first inverter INV 1 Is connected with the input end of the first resistor R senlop The other end and an eighteenth field effect transistor M 18 The eighteenth FET M is connected with the drain electrode of the transistor 18 Source of (C) first capacitor (C) senlop The other ends of the two terminals are all grounded; the first inverter INV 1 Is connected with the output end of the first NAND gate 1 Is connected with one input end of the first NAND gate 1 A sixth enable signal is input to the other input terminal of-! BPS (binary phase shift keying) p The first NAND gate NAND 1 The output terminal of (a) outputs a third enable signal LVX.
6. The sensor of claim 4, wherein the valley enable signal generator comprises a second capacitor C senlov Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Second inverter INV 2 Third inverter INV 3 Fourth inverter INV 4 Fifth inverter INV 5 And a second NAND gate NAND 2 The method comprises the steps of carrying out a first treatment on the surface of the The nineteenth FET M 19 Twentieth field effect transistor M 20 The gates of (a) all input a seventh enable signal-! BPS (binary phase shift keying) n The nineteenth FET M 19 Is connected with the input end of the power stage, the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Is connected to the drain of (d) and is used as the second enable signal PS n And the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 The drain electrode connection end of (a) is respectively connected with the third inverter INV 3 And a fifth inverter INV 5 Is connected with the input end of the twentieth field effect transistor M 20 Source ground PGND; the fifth inverter INV 5 As a fifth enable signal-! PS (PS) n A signal output terminal of (a); the third inverter INV 3 Output end of (a) and fourth inverter INV 4 Is connected with the input end of (a)The second capacitor C senlov One end of (a) is connected with the third inverter INV 3 The output end of the second capacitor C is connected with senlov The other end of the first signal is grounded; the fourth inverter INV 4 Is connected with the output end of the second NAND gate 2 Is connected with one input end of the second NAND gate 2 Another input end of the second inverter INV 2 The output end of the second inverter INV is connected with 2 A seventh enable signal is input to the input terminal of-! BPS (binary phase shift keying) n The second NAND gate NAND 2 As the output of the fourth enable signal LVX valley Is provided.
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