CN107659128B

CN107659128B - DC/DC switching converter power output transistor integrated drive circuit

Info

Publication number: CN107659128B
Application number: CN201710547844.1A
Authority: CN
Inventors: 黄令华; 张海波
Original assignee: SHENZHEN HOTCHIP TECHNOLOGY CO LTD
Current assignee: SHENZHEN HOTCHIP TECHNOLOGY CO LTD
Priority date: 2017-07-06
Filing date: 2017-07-06
Publication date: 2023-07-07
Anticipated expiration: 2037-07-06
Also published as: CN107659128A

Abstract

The integrated driving circuit for driving the power output transistor of the DC/DC switching converter comprises a high-order driving front-stage buffer, a bootstrap capacitor, a capacitive coupling driving circuit and a second inverter; the high-order drive control signal is input from the high-order drive front-stage buffer, and the high-order buffer drive signal is output to the bootstrap capacitor negative plate and the second inverter after buffering; the second inverter, the bootstrap capacitor and the capacitive coupling driving circuit work cooperatively to raise the signal potential of the high-order buffer driving signal, and after the high-order N-type power transistor is conducted, the capacitive coupling driving circuit outputs the high-order driving signal with high driving capability to the grid electrode of the high-order N-type power transistor. The complex supporting circuit in the prior art is simplified, so that an isolation device is not needed for high-order front-stage driving buffer, the device requirement is reduced, and the area of an integrated circuit is reduced; the high-level shift circuit and the high-level and low-level N-type power transistor anti-cross circuit are simplified, the circuit efficiency is improved, and the circuit delay is reduced.

Description

DC/DC switching converter power output transistor integrated drive circuit

Technical Field

The invention belongs to a direct current electric energy conversion circuit and a system; and more particularly to an integrated drive circuit for a DC/DC switching power converter employing dual NMOS power transistors as power output power circuit architectures.

Background

In the prior art, DC/DC switching converters for converting a known DC input voltage into a desired DC voltage can be classified into three types of BUCK, BOOST, BUCK-BOOST according to their peripheral topologies. In the prior art, the rectification mode of the DC/DC switching converter comprises two working modes of asynchronous rectification and synchronous rectification. In the prior art, the modulation mode of the control signal of the DC/DC switching converter comprises two types of pulse width modulation PWM and pulse frequency modulation PFM. In the asynchronous rectification mode, a diode is adopted as a rectifying tube, in the synchronous rectification mode, a low-conduction-resistance power tube MOSFET is adopted as the rectifying tube, and the low-resistance MOSFET rectification can effectively reduce conduction loss and improve the efficiency of the converter, so that the synchronous rectification mode is commonly adopted in portable electronic products. In order to improve the efficiency and the integration level of the switching converter, a dual N-type power transistor architecture is generally adopted, because the N-type MOS transistor generally has a smaller parasitic capacitance and occupies a smaller chip area than the P-type MOS transistor under the same on-resistance condition.

The DC/DC switching converter controls the on and off of the switching tube by generating square wave signals with certain frequency and duty ratio, and finally obtains the required direct current voltage by outputting the square wave signals to the inductor and the capacitor for power filtering.

A typical dual NMOS power transistor driving circuit structure and corresponding driving method in the prior art is shown in FIG. 6, and the circuit structure is suitable for BUCK, BOOST and BUCK-BOOST converters. The switching converter comprises a high-order N-type power transistor VT _h Low-order N-type power transistor VT _l High-order drive buffer 60, low-order drive buffer 66, high-order level shift circuit 61, low-order level shift circuit 65, inverter 64, bootstrap capacitor C _BOOT A ringing cancellation module 101 and a zero current detection ZCD module 105.

From the prior art typical dual NMOS power transistor driving circuit architecture shown in FIG. 6, the high-order driving buffer 60 and the high-order level shift circuit 61 operate at a voltage corresponding to the bootstrap capacitor C _BOOT Due to the voltage of the high-order N-type power transistor VT _h Most of the time during switching is at a non-zero potential, the potential requirements of the relevant switching tube body substrates in the high-order drive buffer 60 and the high-order level shift circuit 61, and the bootstrap capacitance C _BOOT The potential of the negative plate is equivalent, so that isolation devices are generally needed in the high-order drive buffer 60 and the high-order level shift circuit 61 to ensure that the high-order drive buffer 60 and the high-order level shift circuit 61 can work normally; the isolation device occupies larger chip area than the non-isolation device, and the parasitic capacitance of the isolation device causes more energy loss in the switching process, so that the overall efficiency of the DC/DC switching converter is affected, and particularly under the condition of light load, the influence on the efficiency is more obvious.

FIG. 9 shows a detailed circuit of a high level shifter 61 in a typical prior art dual NMOS power transistor driver circuit architecture, which is complex in structure and uses 8 transistors; requires the cooperative operation of the 8 transistors to input the first pulse width modulation signal u _PWM Raised to fit high-order N-type power transistor VT _h A potential of the gate drive; the high-order level shift circuit 61 not only consumes energy itself, but also introduces signal delay.

FIG. 10 shows a high-side N-type power transistor VT prevention commonly used in a prior art dual NMOS power transistor driver circuit architecture _h And a low-order N-type power transistor VT _l In order to ensure that the high-order driving circuit and the low-order driving circuit work at the time sequences corresponding to each other, the level shift circuits are arranged before the high-order driving circuit and before the low-order driving circuit in the circuit for preventing the power tube from being in series connection, and the circuit structure is complex.

Noun interpretation:

DCDC is an abbreviation of english Direct current Direct current, and chinese means that dc voltage is converted into dc voltage;

LDO is the abbreviation of English lowdropout regulator, and Chinese meaning refers to a low dropout linear voltage regulator;

MOSEFT is an abbreviation of English Metal-Oxide-Semiconductor Field-Effect Transistor, and Chinese meaning is a Metal Oxide field effect transistor;

the BUCK mode means in the present application a BUCK DC/DC converter circuit employing BUCK relator mode;

the BOOST mode means in the present application that a BOOST relator mode buck DC/DC conversion circuit is used;

the BUCK-BOOST mode means in the present application that a BUCK-BOOST DC/DC conversion circuit is employed with a BUCK-BOOST topology; the non-isolated DC converter has an output voltage which is lower than or higher than the input voltage, but has a polarity opposite to the input voltage.

PWM is an abbreviation for english Pulse Width Modulation, chinese meaning pulse width modulation; the Pulse Width Modulation (PWM) switch type voltage stabilizing circuit achieves the purpose of stabilizing output voltage by adjusting the duty ratio of the PWM switch type voltage stabilizing circuit under the condition that the output frequency of the control circuit is unchanged.

CCM is the abbreviation of English continuous current mode, chinese meaning is continuous conduction mode, meaning that the inductance current output by the DC/DC converter is continuous operation mode;

DCM is an abbreviation of English discontinuous current mode, chinese meaning discontinuous conduction mode, meaning discontinuous operation mode of inductor current output by DC/DC switching converter. When the DC/DC switching converter works in a DCM mode, namely an intermittent conduction mode, a time period when the inductance current is zero exists in the working process; when the inductance is small, the load current is small, or the switching period is long, the situation that the inductance current is reduced to zero when the period is not finished still occurs, and the inductance current is kept to zero until a new period comes, so that the intermittent working mode is realized; the output of a DC/DC switching converter operating in CCM mode is load independent and therefore its load regulation efficiency is relatively poor. The duty ratio, inductance and load will affect the output voltage of the DCM, so the load adjustment rate is worse, but the efficiency of the DCM mode will be higher in light load.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a more simplified high-order N-type power transistor VT by avoiding the above-mentioned shortcomings of the prior art _h The driving circuit of the circuit not only can simplify a complex high-level shift circuit in the prior art, but also can improve the circuit efficiency and reduce the circuit delay; and the corresponding supporting circuit can be simplified.

The technical scheme of the invention for solving the technical problems is that the integrated driving circuit for driving the power output transistor of the DC/DC switching converter comprises a high-order driving front-stage buffer for buffering the input of a high-order driving control signal, a bootstrap capacitor for elevating signal potential, a capacitive coupling driving circuit for signal coupling and a second inverter for driving the signal to be reversed by high-order buffering; the high-order drive control signal, namely a second pulse width modulation signal, is input from an input terminal of the high-order drive front-stage buffer; the high-order driving front-stage buffer outputs a high-order buffer driving signal to a negative plate of the bootstrap capacitor, and simultaneously, the high-order driving front-stage buffer outputs a high-order buffer driving signal to an input terminal of the second inverter; the positive plate of the bootstrap capacitor is electrically connected with the first input terminal of the capacitive coupling driving circuit; the output end of the second inverter is electrically connected with the second input terminal of the capacitive coupling driving circuit; the third input terminal of the capacitive coupling driving circuit is used for accessing a third direct-current voltage signal of an external third external input power supply; a first output terminal of the capacitive coupling driving circuit is electrically connected with the grid electrode of the high-order N-type power transistor, and a second output terminal of the capacitive coupling driving circuit is electrically connected with the source electrode of the high-order N-type power transistor; the second inverter, the bootstrap capacitor and the capacitive coupling driving circuit work cooperatively to raise the signal potential of the high-order buffer driving signal, and after the high-order N-type power transistor is conducted, the first output terminal of the capacitive coupling driving circuit can continuously provide the high-order N-type power transistor gate driving signal with proper potential, namely the high-order driving signal.

The capacitive coupling driving circuit comprises a first switch, a second switch, a first coupling capacitor and a second N-type MOS tube; one end of the second switch is used as a third input terminal of the capacitive coupling driving circuit, namely a third direct-current voltage signal connected to a third external input power supply; the other end of the second switch is electrically connected with one end of the first switch, meanwhile, the other end of the second switch is also used as a first input terminal of the capacitive coupling driving circuit, the first input terminal is electrically connected with a positive plate of the bootstrap capacitor, and is connected with a control signal of the coupling driving circuit; the other end of the first switch is used as a first output terminal of the capacitive coupling drive circuit for outputting a high-order N-type power transistor gate drive signal u _GP To the gate of the high-order N-type power transistor; meanwhile, the other end of the first switch is electrically connected with the drain electrode of the second N-type MOS tube; the coupling driving circuit control signal and the input first direct current voltage signal jointly control the switch of the first switch; the source electrode of the second N-type MOS transistor is used as a second output terminal of the capacitive coupling driving circuit and is electrically connected with the source electrode of the high-order N-type power transistor; grid electrode of second N-type MOS tubeOne end of the first coupling capacitor is electrically connected with the first capacitor; the other end of the first coupling capacitor is used as a second input terminal of the capacitive coupling driving circuit and is electrically connected with the output end of the second inverter; one end of the second switch is connected with a coupling driving circuit control signal from the bootstrap capacitor positive plate, the other end of the second switch is connected with a third direct-current voltage signal, and the coupling driving circuit control signal and the third direct-current voltage signal jointly control the switch of the second switch.

The first switch is a first P-type MOS tube, the grid electrode of the first P-type MOS tube is electrically connected with the drain electrode of the high-order N-type power transistor, the drain electrode of the first P-type MOS tube is electrically connected with the drain electrode of the second N-type MOS tube, and the source electrode of the first P-type MOS tube is used as a first input terminal of the capacitive coupling driving circuit;

the source electrode of the first P-type MOS tube is electrically connected with the positive plate of the bootstrap capacitor and is connected with a control signal of the coupling driving circuit; the grid electrode of the first P-type MOS tube is connected with a first direct current voltage signal; the coupling driving circuit control signal and the first direct current voltage signal jointly control the switching state of the first P-type MOS tube.

The second switch is a first diode, the positive electrode of the first diode is used as a third input terminal of the capacitive coupling driving circuit, and is connected with a third direct-current voltage signal of a third external input power supply; the negative electrode of the first diode is electrically connected with the positive plate of the bootstrap capacitor to be connected with a control signal of the coupling driving circuit; the coupling driving circuit control signal and the third direct current voltage signal jointly control the switch of the first diode.

The second switch comprises a fourth N-type MOS tube, a second coupling capacitor and a second diode, wherein the positive electrode of the second diode is used as a third input terminal of the capacitive coupling driving circuit and is connected with a third direct-current voltage signal of a third external input power supply; meanwhile, the anode of the second diode is electrically connected with the source electrode of the fourth N-type MOS tube; the cathode of the second diode is electrically connected with the grid electrode of the fourth N-type MOS tube; the grid electrode of the fourth N-type MOS tube is also electrically connected with one end of the second coupling capacitor; the other end of the second coupling capacitor is electrically connected with one end of the first coupling capacitor, the other end of the second coupling capacitor is used as a second input terminal of the capacitive coupling driving circuit, and the other end of the second coupling capacitor is electrically connected with an output terminal of the second inverter; the drain electrode of the fourth N-type MOS tube is used as a first input terminal of the capacitive coupling drive circuit, is electrically connected with the positive plate of the bootstrap capacitor, and is connected with a control signal of the capacitive coupling drive circuit; the coupling driving circuit control signal and the third direct current voltage signal jointly control the switching state of the second switch.

A clamping circuit controlled by gate-source voltage is arranged between the gate and the source of the second N-type MOS tube, and the clamping circuit comprises a first resistor and a second resistor which are connected in series between the gate and the source of the second N-type MOS tube; the clamping circuit also comprises a third N-type MOS tube arranged between the grid electrode and the source electrode of the second N-type MOS tube; the drain electrode of the third N-type MOS tube is electrically connected with the grid electrode of the second N-type MOS tube, the source electrode of the third N-type MOS tube is electrically connected with the source electrode of the second N-type MOS tube, and the grid electrode of the third N-type MOS tube is electrically connected with the first resistor and the second resistor at the same time.

The integrated driving circuit for driving the power output transistor of the DC/DC switching converter further comprises a first inverter, a low-level driving control signal level shifting circuit and a low-level driving buffer; the low-order driving control signal is a logic NOT signal of which the first pulse width modulation signal is a second pulse width modulation signal; the low-order drive control signal, namely, a first pulse width modulation signal is input to a low-order drive control signal level shift circuit to shift the signal potential, the pulse potential of the first pulse width modulation signal is converted from the high potential of a first input power supply to the fourth direct-current voltage signal potential of an external fourth external input power supply, and meanwhile, the space potential of the first pulse width modulation signal is converted from the ground potential of the first input power supply to the source potential of a low-order N-type power transistor by the low-order drive control signal level shift circuit; the low-order driving control signal level shift circuit outputs a signal to the low-order driving buffer, and the low-order driving buffer outputs a low-order driving signal to the grid electrode of the low-order N-type power transistor for driving the low-order N-type power transistor; the low-order driving control signal, namely a first pulse width modulation signal, is input to the first inverter, and the first inverter outputs the high-order driving control signal, namely a second pulse width modulation signal, to the high-order driving front-stage buffer.

The integrated driving circuit for driving the power output transistor of the DC/DC switching converter further comprises a ZCD module, wherein the ZCD module is used for detecting zero crossing current of a rectifying tube, namely a high-order N-type power transistor and/or a low-order N-type power transistor; when the DC/DC switching converter with the integrated driving circuit is used and works in a BUCK mode, namely is used as a BUCK system, two ends of the ZCD module are respectively and electrically connected with the drain electrode and the source electrode of the low-order N-type power transistor; the ZCD module detects a current signal between the drain electrode of the low-order N-type power transistor and the source electrode of the low-order N-type power transistor;

when the DC/DC switching converter with the integrated driving circuit is used as a BOOST system when working in a BOOST mode, two ends of the ZCD module are respectively and electrically connected with the drain electrode and the source electrode of the high-order N-type power transistor; the ZCD module detects a current signal between the drain electrode of the high-order N-type power transistor and the source electrode of the high-order N-type power transistor; when the DC/DC switching converter applying the integrated driving circuit works in a BUCK-BOOST mode, namely is used as a BUCK-BOOST system, two ends of the ZCD module are respectively and electrically connected with the drain electrode and the source electrode of the low-order N-type power transistor; the low-order N-type power transistor is a rectifier tube, and the ZCD module detects a current signal between the drain electrode of the low-order N-type power transistor and the source electrode of the low-order N-type power transistor.

The integrated driving circuit for driving the power output transistor of the DC/DC switching converter further comprises a ringing elimination module, wherein two ends of the ringing elimination module are respectively and electrically connected with two ends of the external inductor L1, and are used for eliminating ringing generated by self-oscillation of the external inductor L1 connected with the DC/DC switching converter; when the DC/DC switching converter applying the integrated driving circuit works in a DCM mode and the ZCD module detects that the current of the rectifying tube is zero, the high-order N-type power transistor and the low-order N-type power transistor are closed at the moment, and the ringing elimination module removes ringing generated by self-oscillation in the external inductance L1.

The technical scheme of the invention for solving the technical problems can also be that the DC/DC switching converter of the integrated driving circuit comprises a series-connection prevention circuit unit for preventing the series connection of a high-order N-type power transistor and a low-order N-type power transistor; the anti-cross circuit unit comprises a third level shift circuit, a third inverter, a first AND gate, a fourth inverter and a second AND gate; the low-level driving signal is input from an input terminal of a third level shifting circuit, an output terminal of the third level shifting circuit is electrically connected with an input terminal of a third inverter, an output terminal of the third inverter is electrically connected with a first input terminal of a first AND gate, a second input terminal of the first AND gate is used for inputting a low-level driving control signal, namely a first pulse width modulation signal, and the first AND gate outputs a signal to the first inverter; the high-order buffer driving signal is input from the input terminal of the fourth inverter, the output terminal of the fourth inverter is electrically connected with the first input terminal of the second AND gate, the second input terminal of the second AND gate is used for inputting the low-order driving control signal, namely the first pulse width modulation signal, and the second AND gate outputs the signal to the low-order driving control signal level shift circuit.

Compared with the prior art, the invention has the beneficial effects that: 1. the complex high-level shift circuit in the prior art is simplified, the circuit efficiency is improved, and the circuit delay is reduced; 2. the driving circuit has lower requirement on the circuit of the high-order front-stage driving buffer, so that the high-order front-stage driving buffer does not need to adopt isolation devices, the requirement on the devices is reduced, and the area of the integrated circuit is reduced; 3. for DC/DC switching converter using the driving circuit, its periphery prevents high-order N-type power transistor VT _h And a low-order N-type power transistor VT _l The level shift circuit in front of the low-order drive circuit can be simplified due to the change of the high-order drive circuit.

Drawings

FIG. 1 is a circuit block diagram of one of the preferred embodiments of the integrated drive circuit for DC/DC switching converter output transistor driving in accordance with the present invention;

FIG. 2 is a schematic diagram of a partial circuit of a second preferred embodiment of the present invention, showing only the partial circuit of the high-side drive;

FIG. 3 is a schematic diagram of a portion of a circuit of a third preferred embodiment of the present invention, showing only a portion of the circuit driven high;

FIG. 4 is a timing diagram of steady state signals for a DC/DC switching converter employing the integrated drive circuit of FIG. 1 in a CCM mode of operation;

FIG. 5 is a timing diagram of steady state signals for a DC/DC switching converter employing the integrated drive circuit of FIG. 1 in DCM operation; the left, middle and right three parts of fig. 4 and 5 represent steady-state signal timing diagrams of the DC/DC switching converter operating in three modes, BUCK mode, BOOST-BOOST mode, respectively;

FIG. 6 is a circuit block diagram of a typical dual NMOS power transistor driver circuit according to the prior art;

FIG. 7 is a timing diagram of steady state signals during CCM operation using the dual NMOS power transistor driver circuit of FIG. 6;

FIG. 8 is a timing diagram of steady state signals for the dual NMOS power transistor driving circuit of FIG. 6 in DCM operation; the left, middle and right three parts of fig. 7 and 8 represent steady-state signal timing diagrams of the DC/DC switching converter operating in three modes, BUCK mode, BOOST-BOOST mode, respectively;

FIG. 9 is a detailed schematic diagram of a high level shifter 61 in a typical prior art dual NMOS power transistor drive circuit architecture;

FIG. 10 shows a prior art high-side N-type power transistor VT prevention in a DC/DC switching converter based on the exemplary dual NMOS power transistor drive circuit of FIG. 4 _h And a low-order N-type power transistor VT _l A schematic diagram of a series circuit;

FIG. 11 shows a DC/DC switching converter employing an integrated drive circuit of the present invention, wherein high-side N-type power transistor VT is prevented _h And a low-order N-type power transistor VT _l A schematic diagram of the series circuit.

Detailed Description

Embodiments of the present invention are described in further detail below with reference to the drawings.

In the embodiment of the integrated drive circuit 200 for DC/DC switching converter power output transistor driving shown in FIG. 1, including for high-side drive controlSignal signal

An input buffered high-order driving pre-buffer 260 for bootstrap capacitor C with signal potential elevation _BOOT A capacitively coupled drive circuit 230 for signal coupling for high-order buffer drive signals u _DRP An inverted second inverter 268; the high-order drive control signal is the second pulse width modulation signal +>

Input from the input terminal of the high-driving front buffer 260; the high-order driving pre-stage buffer 260 outputs a high-order buffer driving signal u _DRP To bootstrap capacitor C _BOOT While the higher driving front buffer 260 outputs the higher buffering driving signal u _DRP An input terminal to a second inverter 268; bootstrap capacitor C _BOOT Is electrically connected to the positive plate of the capacitive coupling drive circuit 230; an output of the second inverter 268 is electrically connected to a second input terminal of the capacitive coupling drive circuit 230; a third input terminal of the capacitive coupling driving circuit 230 is used for accessing a third DC voltage signal u of an external third external input power VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the A first output terminal of the capacitive coupling driving circuit 230 and a high-order N-type power transistor VT _h The gate is electrically connected to the second output terminal of the capacitive coupling driving circuit 230 and the high N-type power transistor VT _h The source electrode is electrically connected; second inverter 268, bootstrap capacitor C _BOOT In conjunction with the capacitive coupling drive circuit 230, to buffer the high-order bits of the drive signal u _DRP Is raised at the high-order N-type power transistor VT _h After being conducted, the first output terminal of the capacitive coupling driving circuit 230 can continuously provide the high-order N-type power transistor VT with proper potential _h Gate drive signal, i.e. high drive signal u _GP 。

In the embodiment shown in fig. 1, the capacitive coupling driving circuit 230 includes a first switch K1, a second switch K2, and a first coupling capacitor C _BC1 And a second N-type MOS transistor Q2; one end of the second switch K2 is used as a third input terminal of the capacitive coupling driving circuit 230, i.e. connected inThird direct-current voltage signal u of third external input power supply VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the The other end of the second switch K2 is electrically connected with one end of the first switch K1, and the other end of the second switch K2 is also used as a first input terminal of the capacitive coupling driving circuit 230, and a bootstrap capacitor C _BOOT Is electrically connected with the positive plate; the other end of the first switch K1 is used as a first output terminal of the capacitive coupling driving circuit 230 for outputting a high-order N-type power transistor VT _h Gate driving signal u _GP To high-order N-type power transistor VT _h A gate electrode of (a); meanwhile, the other end of the first switch K1 is electrically connected with the drain electrode of the second N-type MOS tube Q2; coupled drive circuit control signal u _VBOOT And input a first direct current voltage signal u _P1 The switch of the first switch K1 is controlled jointly; the source of the second N-type MOS transistor Q2 is used as the second output terminal of the capacitive coupling driving circuit 230 and the high-order N-type power transistor VT _h Is electrically connected to the source electrode of the transistor; grid electrode of second N-type MOS tube Q2 and first coupling capacitor C _BC1 Is electrically connected to one end of the first circuit board; first coupling capacitor C _BC1 The other end of which serves as a second input terminal of the capacitive coupling drive circuit 230, is electrically connected to the output terminal of the second inverter 268; one end of the second switch K2 is connected with the bootstrap capacitor C _BOOT Is connected with the control signal u of the coupling driving circuit of the positive plate _VBOOT The other end of the second switch K2 is connected with a third direct-current voltage signal u _REG Coupled to the driving circuit control signal u _VBOOT And a third DC voltage signal u _REG The switches of the second switch K2 are commonly controlled.

In the embodiment shown in fig. 2 and 3, the first switch K1 is a first P-type MOS transistor Q1, and the gate of the first P-type MOS transistor Q1 and the high-order N-type power transistor VT _h The drain electrode of the first P-type MOS transistor Q1 is electrically connected with the drain electrode of the second N-type MOS transistor Q2, and the source electrode of the first P-type MOS transistor Q1 is used as a first input terminal of the capacitive coupling driving circuit 230 and a bootstrap capacitor C _BOOT Is electrically connected with the positive plate; source electrode of first P-type MOS tube Q1 and bootstrap capacitor C _BOOT Is electrically connected with the positive plate of the drive circuit and is connected with the control signal u of the coupling drive circuit _VBOOT The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the first P-type MOS tube Q1 is connected with a first direct current voltage communication to be converted from a circuit node P1Number u _P1 The method comprises the steps of carrying out a first treatment on the surface of the Coupled drive circuit control signal u _VBOOT And a first direct current voltage signal u _P1 The switching state of the first P-type MOS transistor Q1 is controlled together.

In the embodiment shown in fig. 2, the second switch K2 is a first diode D1, the positive electrode of the first diode D1 is used as the third input terminal of the capacitive coupling driving circuit 230, and is connected to the third dc voltage signal u of the third external input power VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the Negative electrode of first diode D1 and bootstrap capacitor C _BOOT Is connected with the control signal u of the coupling driving circuit _VBOOT The method comprises the steps of carrying out a first treatment on the surface of the Coupled drive circuit control signal u _VBOOT And a third DC voltage signal u _REG The switch of the first diode D1 is commonly controlled.

In the embodiment shown in fig. 3, the second switch K2 includes a fourth N-type MOS transistor Q4 and a second coupling capacitor C _BC2 And a second diode D2, the anode of the second diode D2 is used as a third input terminal of the capacitive coupling driving circuit 230, and is connected with a third direct-current voltage signal u of a third external input power supply VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the Meanwhile, the anode of the second diode D2 is electrically connected with the source electrode of the fourth N-type MOS transistor Q4; the cathode of the second diode D2 is electrically connected with the grid electrode of the fourth N-type MOS tube Q4; the grid electrode of the fourth N-type MOS tube Q4 is also connected with a second coupling capacitor C _BC2 Is electrically connected to one end of the first circuit board; second coupling capacitor C _BC2 And the other end of (C) and the first coupling capacitance C _BC1 Is electrically connected with one end of the second coupling capacitor C _BC2 The other end of (a) is used as a second input terminal of the capacitive coupling driving circuit 230, the second coupling capacitance C _BC2 Is electrically connected to the other end of the second inverter 268; the drain of the fourth N-type MOS transistor Q4 is used as the first input terminal of the capacitive coupling driving circuit 230, and bootstrap capacitor C _BOOT Is electrically connected with the positive plate of the drive circuit and is connected with the control signal u of the coupling drive circuit _VBOOT The method comprises the steps of carrying out a first treatment on the surface of the Coupled drive circuit control signal u _VBOOT And a third DC voltage signal u _REG The switch states of the second switch K2 are controlled jointly.

As can be seen in the signal timing diagrams shown in FIGS. 4 and 5, when the voltage signal u at the circuit node DRP _DRP To ground potential of V _DD At this time, the voltage signal u at the circuit node DRP_N is passed through the second inverter 268 _DRP-N Zero potential V to ground potential _GND Voltage signal u _DRP-N Is connected to the first coupling capacitor C _BC1 Then due to the first coupling capacitance C _BC1 The grid electrode of the second N-type MOS tube Q2 has zero potential V to the ground potential _GND The second N-type MOS transistor Q2 is closed; bootstrap capacitor C _BOOT Is bootstrapped to raise the positive plate potential to V _REG +V _DD The method comprises the steps of carrying out a first treatment on the surface of the In this state, the second switch K2 is opened, the electrical connection of the two circuits is broken, the first switch K1 is closed and turned on, and the bootstrap capacitor C _BOOT The positive plate, namely the circuit node VBOOT is directly communicated with the circuit node GP, and the capacitor C is bootstrapped _BOOT Voltage signal u of positive plate _VBOOT Directly input to high-order N-type power transistor VT _h The gate of (2) becomes a high-order drive signal u _GP At this time, the high-order driving signal u _GP Is V to ground potential _REG +V _DD Can make high-order N-type power transistor VT _h After the high-order N-type power transistor is turned on, the capacitive coupling driving circuit can output a high-order driving signal with high driving capability to the grid electrode of the high-order N-type power transistor.

As can be seen in the signal timing diagrams shown in FIGS. 4 and 5, when the voltage signal u at the circuit node DRP _DRP Zero potential V to ground potential _GND Bootstrap capacitor C _BOOT The negative plate potential is pulled down to zero potential V _GND Bootstrap capacitor C _BOOT Is coupled to V _REG The first switch K1 is opened, the second switch K2 is closed, and the bootstrap capacitor C is used for the voltage control _BOOT The positive plate of (i.e., circuit node VBOOT) is disconnected from circuit node GP, and the voltage signal u on circuit node drp_n is passed through second inverter 268 _DRP-N The ground potential is V _DD Is connected with a first coupling capacitor C _BC1 Then due to the first coupling capacitance C _BC1 The grid electrode of the second N-type MOS tube Q2 is V to the ground potential _DD The second N-type MOS transistor Q2 is opened, and the high-order N-type power transistor VT _h Is pulled down by the gate-source voltage difference of the high-order N-type power transistor VT _h And closing.

As shown in fig. 5, when the DC/DC switching converter operates in the BUCK mode, the circuit node P1 is an externally input DC voltage signal u _IN The input terminal of the circuit node P1, the voltage signal u _P1 ＝u _IN The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P2 is denoted as u _P2 The potential is the ground potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P3 is denoted as u _P3 The circuit node P3 is a terminal of the output voltage of the DC/DC switching converter, and outputs a converted DC voltage signal u _OUT U is namely _P3 ＝u _OUT . The working process is that the first pulse width modulation signal u is output by a control loop of a DC/DC switching converter _PWM Used as a high-order driving control signal by a first pulse width modulation signal u _PWM Control of high-order N-type power transistor VT by the level of the pulse phase and the space phase _h And a low-order N-type power transistor VT _l Is turned on alternately. First pulse width modulation signal u _PWM And a second pulse width modulation signal

The pulse potential of (2) is the high potential V of the first input power supply VDD _DD The space potential is the ground potential V of the first input power supply VDD _GND The method comprises the steps of carrying out a first treatment on the surface of the Second pulse width modulation signal->

And a first pulse width modulation signal u _PWM Are logically non-signal with each other.

As shown in fig. 5, in the first pulse width modulation signal u _PWM Is the first phase of the first pulse width modulation signal u _PWM When the potential of the pulse is space potential, the first pulse width modulation signal u _PWM The signal potential of (2) is zero potential V _GND After passing through the first inverter 264, a second pulse width modulation signal is output

Second pulse width modulation signal->

The signal potential of (2) is high potential V _DD The method comprises the steps of carrying out a first treatment on the surface of the Second pulse width modulation signal->

After passing through the high-order driving front buffer 260, the high-order driving front buffer 260 outputs a high-order buffer driving signal u _DRP The method comprises the steps of carrying out a first treatment on the surface of the High-order buffer driving signal u _DRP And a second pulse width modulation signal->

In-phase, high-order buffer driving signal u _DRP The pulse potential of (2) is high potential V _DD Space potential is zero potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the The control signals of the first switch K1 and the second switch K2 are opposite in phase, namely the switch states of the first switch K1 and the second switch K2 are mutually exclusive, and one switch is closed and the other switch is opened under the control of the control signals; when the high bit buffers the driving signal u _DRP At pulse potential, i.e. signal potential is at high potential V _DD Due to bootstrap capacitance C _BOOT Is a bootstrap capacitor C _BOOT The potential of the positive plate is coupled to V _REG +V _DD At this time, the first switch K1 is closed, the second switch K2 is opened, the second N-type MOS transistor Q2 is closed, and the capacitor C is bootstrapped _BOOT The positive plate is directly communicated with the circuit node GP, and the capacitor C is bootstrapped _BOOT Voltage signal u of positive plate _VBOOT Directly input to high-order N-type power transistor VT _h The gate of (2) becomes a high-order drive signal u _GP Its potential is V _REG +V _DD High-order N-type power transistor VT _h Opening; similarly, the first pulse width modulation signal u _PWM After passing through the low-order drive control signal level shift circuit 265 and the low-order drive buffer 266, u is obtained _GN In u _GP To ground potential of V _REG +V _DD When u _GN Is zero potential V to ground potential _GND Low-order N-type power transistor VT _l Closing; thus modulating the signal u at the first pulse width _PWM In the first phase of (a), the voltage signal at the circuit node SW is the voltage signal u at the circuit node P1 _P1 The current flowing through the external inductance L1 enters the rising period.

As shown in FIG. 5, at the firstPulse width modulation signal u _PWM A second phase of the (a) first pulse width modulation signal u _PWM When the potential of the pulse signal is pulse potential, the first pulse width modulation signal u _PWM The signal potential of (2) is high potential V _DD After passing through the first inverter 264, a second pulse width modulation signal is output

Second pulse width modulation signal- >

The signal potential of (2) is zero potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the Second pulse width modulation signal->

In-phase, high-order buffer driving signal u _DRP The pulse potential of (2) is high potential V _DD Space potential is zero potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the At this time, the high-order buffer driving signal u _DRP At a space potential of zero potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the When the high bit buffers the driving signal u _DRP At pulse potential, i.e. signal potential is zero potential V _GND When the first switch K1 is opened, the second switch K2 is closed, the second N-type MOS transistor Q2 is opened, and the high-order N-type power transistor VT _h Is pulled low, high-order N-type power transistor VT _h Closing; at the same time bootstrap capacitor C _BOOT The ground potential of the positive plate is V _REG The second switch K2 is closed to supplement energy to the bootstrap capacitor C _BOOT A positive plate; similarly, the first pulse width modulation signal u _PWM After passing through the low-order driving control signal level shift circuit 265 and the low-order driving buffer 266, the low-order driving signal u is obtained _GN Low-order drive signal u _GN Is a potential V to the ground potential _VNCLP Low-order N-type power transistor VT _l Opening; thus modulating the signal at the first pulse width u _PWM In the second phase of (a), the voltage signal at the circuit node SW is the voltage signal u at the circuit node P1 _P1 The current flowing through the external inductance L1 enters the falling period.

As shown in fig. 5, in the first pulse width modulation signal u _PWM Followed by a third phase in which the first pulse width modulated signal u _PWM The pulse potential V of the second phase is still maintained _DD The method comprises the steps of carrying out a first treatment on the surface of the When the ZCD module 105 detects that the inductance current drops to 0, the ZCD module 105 or other control circuits in the DC/DC switching converter control the low-level N-type power transistor VT _l Turned off when the high driving signal u _GP And a low-order drive signal u _GN The potential of (2) is zero potential V _GND The signal of the circuit node SW is u _P3 The inductor current is 0.

In the embodiment shown in fig. 2 and 3, the gate of the first switch K1, i.e. the first P-type MOS transistor Q1, is connected to the first dc voltage signal u input from the circuit node P1 _P1 . As can be seen in the signal timing diagrams shown in fig. 4 and 5, when the voltage signal u at the circuit node DRP _DRP To ground potential of V _DD Bootstrap capacitor C _BOOT Voltage signal u of positive plate, i.e. circuit node VBOOT _VBOOT Is coupled to a second DC voltage signal u _P1 The higher ground potential is achieved, the first P-type MOS tube Q1 is automatically closed, and the capacitor C is bootstrapped _BOOT The positive plate is directly communicated with the circuit node GP, and the capacitor C is bootstrapped _BOOT Voltage signal u of positive plate _VBOOT Directly input to high-order N-type power transistor VT _h The gate of (2) becomes a high-order drive signal u _GP The method comprises the steps of carrying out a first treatment on the surface of the When the voltage signal u on the circuit node DRP _DRP Zero potential V to ground potential _GND Bootstrap capacitor C _BOOT Voltage signal u of positive plate _VBOOT The potential is pulled down to a third DC voltage signal u _REG To ground potential V _REG The pair of ground potentials V _REG Is smaller than the first direct current voltage signal u _P1 To ground potential V _P1 The method comprises the steps of carrying out a first treatment on the surface of the The first P-type MOS transistor Q1 is automatically disconnected and bootstrapped with a capacitor C _BOOT The connection between the positive plate and the circuit node GP is in an open state.

As shown in figures 2 and 3In the illustrated embodiment, the second switch K2 is a first diode D1, or the second switch K2 is a fourth N-type MOS transistor Q4 and a second coupling capacitor C _BC2 And a second diode D2. As can be seen in the signal timing diagrams shown in connection with fig. 4 and 5, the function of the second switch K2 is to realize a third dc voltage signal u _REG Input terminal and bootstrap capacitor C _BOOT Single-phase conduction between positive plates; third DC voltage signal u _REG Input terminal and bootstrap capacitor C _BOOT Single-phase conduction between positive plates for supplementing bootstrap capacitance C during switching _BOOT Energy loss on the positive plate.

As shown in fig. 2, in the embodiment of the integrated driving circuit 200 for driving the power output transistor of the DC/DC switching converter, when the DC/DC switching converter is operating normally in the first Phase1, that is, when the high-order driving control signal, i.e., the second pulse width modulation signal, is at the pulse potential, the potential V of the circuit node VBOOT _VBOOT Will be raised when V _VBOOT >V _P1 +V _TH When V is _P1 At the potential of the circuit node P1, V _TH The threshold value of the first P-type MOS transistor Q1, namely the absolute value of the gate-source opening voltage, is the high-order driving signal u _GP Potential V of potential quilt circuit node VBOOT _VBOOT Pulling high to make high-order N-type power transistor VT _h Opening; at the same time due to the first coupling capacitance C _BC1 The gate signal of the second N-type MOS transistor Q2 is the signal of the circuit node SW, so that the second N-type MOS transistor Q2 is closed; when the DC/DC switching converter normally works in the second Phase2, namely when the high-order driving control signal, namely the second pulse width modulation signal, is at pulse potential, the potential V of the circuit node VBOOT _VBOOT Re-descend to V _REG -V _D1 ，V _D1 The value of (1) is the forward conduction voltage of the first diode D1, the second switch K2 is turned off for the first P-type MOS transistor Q1, the signal potential of the circuit node VBC is coupled to the high bit, the second N-type MOS transistor Q2 is turned on, and the high bit driving signal u _GP The potential is pulled low to enable the high-order N-type power transistor VT _h And closing.

In the embodiment shown in FIG. 2, when self-containedLifting capacitor C _BOOT The earth potential of the positive plate is lower than V _REG -V _D1 When the bootstrap capacitor C is charged with energy _BOOT A positive plate; wherein V is _REG For the third DC voltage signal u _REG To ground potential, V _D1 The starting voltage for forward conduction of the first diode D1; the advantage of this embodiment is that it is simple, and that there is a voltage drop of about 0.7V across the diode at the disadvantage, which affects efficiency and driving voltage.

As shown in fig. 3, in an embodiment of the integrated driving circuit 200 for driving the power output transistor of the DC/DC switching converter, the first switch K1 includes a fourth N-type MOS transistor Q4 and a second coupling capacitor C _BC2 And a second diode D2, the anode of the second diode D2 is used as a third output terminal of the capacitive coupling driving circuit 230, and is connected with a second direct-current voltage signal u input from the outside _REG The method comprises the steps of carrying out a first treatment on the surface of the Meanwhile, the anode of the second diode D2 is electrically connected with the source electrode of the fourth N-type MOS tube Q4, and the cathode of the second diode D2 is electrically connected with the grid electrode of the fourth N-type MOS tube Q4; the grid electrode of the fourth N-type MOS tube Q4 is also connected with a second coupling capacitor C _BC2 Is electrically connected to one end of the first circuit board; second coupling capacitor C _BC2 And the other end of (C) and the first coupling capacitance C _BC1 Is electrically connected with one end of the second coupling capacitor C _BC2 The other end of which serves as a second input terminal of the capacitive coupling drive circuit 230, is electrically connected to the output terminal of the second inverter 268; the second switch K2 is a first P-type MOS transistor Q1, the grid electrode of the first P-type MOS transistor Q1 and a high-order N-type power transistor VT _h The drain electrode of the first P-type MOS transistor Q1 is electrically connected with the drain electrode of the second N-type MOS transistor Q2, and the source electrode of the first P-type MOS transistor Q1 is used as a first input terminal of the capacitive coupling driving circuit 230 and a bootstrap capacitor C _BOOT Is electrically connected with the positive plate; a first resistor R1 and a second resistor R2 which are connected in series are arranged between the grid electrode and the source electrode of the second N-type MOS tube Q2, and a third N-type MOS tube Q3 is also arranged between the grid electrode and the source electrode of the second N-type MOS tube Q2; the drain electrode of the third N-type MOS tube Q3 is electrically connected with the grid electrode of the second N-type MOS tube Q2, the source electrode of the third N-type MOS tube Q3 is electrically connected with the source electrode of the second N-type MOS tube Q2, and the grid electrode of the third N-type MOS tube Q3 is electrically connected with the first resistor R1 and the second resistor R2 at the same time.

In the embodiment shown in FIG. 3, a fourth controlled N-type MOS transistor Q4, a second coupling capacitor C _BC2 And a second diode D2 realizes the switch control of a second switch K2; when the ground potential of the circuit node DRP is V _DD At the time, a second coupling capacitor C _BC2 The capacitor can make the gate of the fourth N-type MOS transistor Q4 coupled to the ground potential downwards, and the fourth N-type MOS transistor Q4 is turned off when the ground potential of the circuit node DRP is zero potential V _GND At the time, a second coupling capacitor C _BC2 The grid electrode of the fourth N-type MOS tube Q4 is coupled to high potential, the fourth N-type MOS tube Q4 is completely opened, and the bootstrap capacitor C can be realized _BOOT Positive plate and third dc voltage signal u _REG The input terminal of (2) is directly conducted, and the capacitor C is bootstrapped _BOOT Energy is supplied. FIG. 3 shows the use of a second coupling capacitor C _BC2 The working principle of the diode is that when the fourth N-type MOS transistor Q4 is required to be opened, the diode D2 and the fourth N-type MOS transistor Q4 are used for stabilizing voltage, and the diode D2 and the fourth N-type MOS transistor Q4 pass through a second coupling capacitor C _BC2 The fourth N-type MOS transistor Q4 is completely opened, and the effect on efficiency and driving voltage is avoided.

As shown in fig. 3, in the embodiment of the integrated driving circuit 200 for driving the power output transistor of the DC/DC switching converter, when the DC/DC switching converter is operating normally in the first Phase1, that is, when the high-order driving control signal, i.e., the second pulse width modulation signal, is at the pulse potential, the potential V of the circuit node VBOOT _VBOOT Will be raised when V _VBOOT >V _P1 +V _TH When V is _P1 At the potential of the circuit node P1, V _TH The threshold value of the first P-type MOS transistor Q1, namely the absolute value of the gate-source opening voltage, is the high-order driving signal u _GP Potential V of potential quilt circuit node VBOOT _VBOOT Pulling high to make high-order N-type power transistor VT _h Opening; at the same time due to the first coupling capacitance C _BC1 The grid signal potential of the second N-type MOS tube Q2 is V _REG -V _D2 Closing the second N-type MOS transistor Q2; when the DC/DC switching converter normally works in the second Phase2, namely when the high-order driving control signal, namely the second pulse width modulation signal, is at pulse potential, the potential V of the circuit node VBOOT _VBOOT Re-descend to V _REG At this time, the first P-type MOS transistor Q1 is turned off, the signal potential of the circuit node VBC is coupled to the high bit, the second N-type MOS transistor Q2 is turned on, and the high bit drives the signal u _GP The potential is pulled low to enable the high-order N-type power transistor VT _h And closing.

The difference between the embodiments of fig. 2 and fig. 3 is that the second switch K2 in the embodiment of fig. 2 is simply implemented by a diode, and the second switch K2 in the embodiment of fig. 3 is implemented by a fourth N-type MOS transistor Q4 and a second coupling capacitor C _BC2 And a second diode D2; the specific difference between the two embodiments is the bootstrap capacitance C _BOOT The ground potential of the upper precharge is different in size; the precharge potential in the embodiment shown in FIG. 2 has a magnitude of V _REG -V _D2 The precharge level in the embodiment shown in FIG. 3 is V _REG Resulting in the final driving of the high-order N-type power transistor VT _h The absolute values of the gate-source voltages are different and are respectively V _REG -V _D2 And V _REG Due to the high-order N-type power transistor VT in the embodiment shown in FIG. 3 _h The gate-source voltage is higher than that of the N-type power transistor VT in the embodiment shown in FIG. 2 _h Thus having a high-order N-type power transistor VT in the embodiment shown in FIG. 3 _h In the on state, the on-resistance is relatively smaller.

The embodiment of the integrated drive circuit 200 for DC/DC switching converter power output transistor driving shown in fig. 1 accomplishes the high-side N-type power transistor VT with a more simplified circuit _h And a low-order N-type power transistor VT _l Compared with the prior art driving circuit shown in fig. 4, the complex high-level shift circuit in the prior art is simplified, the circuit efficiency is improved, and the circuit delay is reduced; the driving circuit has lower circuit requirement on the high-order front-stage driving buffer, so that the high-order front-stage driving buffer does not need to adopt isolation devices, the requirement on the devices is reduced, and the area of the integrated circuit is reduced.

FIG. 6 shows a first PWM signal u in a prior art typical dual NMOS power transistor driving circuit configuration _PWM Is output by a closed-loop control circuit in a DC/DC switching converter applying the circuit architectureSquare wave signal for switching control of switching tube; in high-order N-type power transistor VT _h In the switch driving circuit of (a), the pulse width modulation signal u _PWM Input to an inverter 64 which outputs a second PWM signal which is a NOT signal of the first PWM signal

Second pulse width modulation signal->

Is input to the high level shift circuit 61, the second pulse width modulation signal +>

The pulse potential of (2) is the high potential V of the first external input power supply VDD _DD Second pulse width modulation signal->

Is the space potential of the first external input power supply VDD _GND The method comprises the steps of carrying out a first treatment on the surface of the The high level shift circuit 61 shifts the second pulse width modulation signal +.>

A high potential V of the first external input power supply VDD _DD Conversion to bootstrap capacitor positive plate potential V _BOOT While the high-level shift circuit 61 shifts the second pulse width modulation signal +>

The space potential of the first external input power supply VDD _GND Switching to high-order N-type power transistor VT _h Is the source potential V of (2) _SW The method comprises the steps of carrying out a first treatment on the surface of the The output u of the high level shift circuit 61 _DRP The signal is buffered in the high-order drive buffer 60, and the high-order drive buffer 60 outputs a signal u with strong driving capability _GP To high-order N-type power transistor VT _h Gate of high-order N-type power transistor VT _h Is driven by a switch of (a). Second pulse width modulation signal->

Is raised to a proper level as a whole, especially in the high-order N-type power transistor VT _h Is the source potential V of (2) _SW Ground potential V relative to first external input power supply VDD _GND Higher, so as to better perform the high-order N-type power transistor +.>

Is driven by a switch of (a).

The low-order N-type power transistor VT in the exemplary dual NMOS power transistor circuit architecture shown in FIG. 6 _h In the switch driving circuit of (a), a first pulse width modulation signal u _PWM Is input to the low level shift circuit 65, the first pulse width modulation signal u _PWM The pulse potential of (2) is the high potential V of the first external input power supply VDD _DD Pulse width modulation signal u _PWM Is the space potential of the first external input power supply VDD _GND The method comprises the steps of carrying out a first treatment on the surface of the The low level shift circuit 65 shifts the first pulse width modulation signal u _PWM A high potential V of the first external input power supply VDD _DD A potential V switched to a high potential of the fourth external input power supply VNCLP _NCLP While the low-level shift circuit 65 shifts the first pulse width modulation signal u _PWM The space potential of the first external input power supply VDD _GND Switching to low-order N-type power transistor VT _l Is the source potential V of (2) _P2 The method comprises the steps of carrying out a first treatment on the surface of the Output signal u of low level shift circuit 65 _DRN Is input into the low-order drive buffer 66 for buffering, and the low-order drive buffer 66 outputs a drive signal u with strong drive capability _GN To low-order N-type power transistor VT _l Gate of low-order N-type power transistor VT _l Is driven by a switch of (a).

In fig. 1 and 6, a fourth dc voltage signal u input from a fourth external input power VNCLP _NCLP Is a power signal for a low-order drive buffer, and in Buck mode, a fourth DC voltage signal u _NCLP Equal to the externally input voltage signal to be converted, i.e. the first DC voltage signal u _P1 Or a voltage signal generated by an LDO inside the DC/DC switching converter; in Boost mode, the fourth DC voltage signal u _NCLP Is input from circuit node P3Voltage signal u _P3 The voltage signal u output from the signal node P1 may be _P1-out Or a voltage signal generated by an LDO inside the DC/DC switching converter; in Buck-BOOST mode, the fourth DC voltage signal u _NCLP Is the difference signal between the voltage signal generated by the LDO inside the DC/DC switching converter and the signal node P2, which is a fixed level as the low-level drive buffer power supply.

Bootstrap capacitor C in FIG. 6 _BOOT Is electrically connected to one input terminal of the high-level shift circuit 61, one input terminal of the high-level drive buffer 60, and the negative electrode of the diode D1; bootstrap capacitor C _BOOT Negative plate of (2) and high-order N-type power transistor VT _h Is electrically connected to the source electrode of the transistor; u (u) _REG The signal is a third direct current voltage signal u obtained from an LDO provided in a DC/DC switching converter _REG Which has a potential V to the ground _REG ，u _REG The signal is reduced in voltage by the diode D1 to provide a working power supply for the high-order drive circuit.

In fig. 1 and 6, a third dc voltage signal u _REG Is used for supplementing energy loss caused by switching in each switching period of the CBOOT, and in the Buck mode, the third direct-current voltage signal u _REG Equal to the externally input voltage signal to be converted, i.e. the first DC voltage signal u _P1 Or a voltage signal generated by an LDO inside the DC/DC switching converter; in Boost mode, the third DC voltage signal u _REG Is equal to the voltage signal u input from the circuit node P3 _P3 The first DC voltage signal u may also be _P1 Or a voltage signal generated by an LDO inside the DC/DC switching converter; in Buck-BOOST mode, the VREG signal is a voltage signal generated by an LDO within the DC/DC switching converter.

As shown in fig. 7 to 8, when the DC/DC switching converter is operated in the BUCK mode, the circuit node P1 is an externally input DC voltage signal u in the prior art driving circuit _IN The first direct voltage signal u of the circuit node P1 _P1 ＝u _IN The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P2 is denoted as u _P2 The potential is the ground potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P3 is denoted as u _P3 The circuit node P3 isA terminal of the DC/DC switching converter output voltage, which outputs a converted DC voltage signal u _OUT U is namely _P3 ＝u _OUT 。

As shown in fig. 6 to 8, when the DC/DC switching converter operates in the BOOST mode, the circuit node P3 is an externally input DC voltage signal u in the prior art driving circuit _IN The input terminal of the circuit node P3 _P3 ＝u _IN The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P2 is denoted as u _P2 The potential is the ground potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P1 is denoted as u _P1 The circuit node P1 is a terminal of the output voltage of the DC/DC switching converter, and outputs a DC voltage signal u after conversion _OUT U is namely _P1 ＝u _OUT 。

As shown in fig. 6 to 8, when the DC/DC switching converter operates in the BUCK-BOOST mode, the circuit node P1 is an externally input DC voltage signal u in the prior art driving circuit _IN The input terminal of the circuit node P1, the voltage signal u _P1 ＝u _IN The method comprises the steps of carrying out a first treatment on the surface of the The potential being ground potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P3 is denoted as u _P3 The potential is the ground potential V _GND The method comprises the steps of carrying out a first treatment on the surface of the The signal at circuit node P2 is denoted as u _P2 The circuit node P2 is a terminal of the output voltage of the DC/DC switching converter, and outputs a converted DC voltage signal u _OUT U is namely _P2 ＝u _OUT 。

As shown in fig. 6 to 8, in the prior art driving circuit, taking the BUCK mode as an example, the voltage signal of the circuit node SW is denoted as u _SW This signal is a switching signal when the inductor current is non-zero. When the DC/DC switching converter operates in CCM mode, the two phase states of the first and second operating phases correspond to the first PWM signal u _PWM Space phase and pulse phase of (c). When the first pulse width modulation signal u _PWM When in space phase, high-order N-type power transistor VT _h Open, low-order N-type power transistor VT _l Shut down, circuit node SW signal u _SW The potential is equal to the input signal U of the circuit node P1 _P1 Potential V of (2) _P1 Bootstrap capacitor C _BOOT The positive plate, namely the circuit node VBOOT, has a potential V to ground _REG -V _D1 +V _P1 Bootstrap capacitor C _BOOT Is V at the voltage difference between two ends _REG -V _D1 Wherein V is _REG For the direct-current voltage signal u input from the diode anode _REG To ground potential, V _D1 For the voltage across the first diode D1, V _P1 Is a high-order N-type power transistor VT _h Is to the ground potential due to the high-order N-type power transistor VT _h On, high-order N-type power transistor VT _h Is the high-order N-type power transistor VT with the source electrode of the high-order N-type power transistor VT _h Is to ground potential V _P1 Thus, the high-order N-type power transistor VT _h Voltage V between gate and source of (C) _GS ＝V _REG -V _D1 . When the first pulse width modulation signal u _PWM When switching from pulse phase to space phase, signal u of circuit node SW _SW Potential slave node P2 to ground potential V _P2 In BUCK mode, the potential is ground potential V _P2 ＝V _GND Rapidly switching to potential V of circuit node P1 _P1 The method comprises the steps of carrying out a first treatment on the surface of the Bootstrap capacitor C _BOOT The potential on the positive plate of (2) is raised to V _REG -V _D1 +V _P1 Bootstrap capacitor C _BOOT The potential on the negative plate of the (B) is high-order N-type power transistor VT _h Drain potential V of (2) _P1 Bootstrap capacitor C _BOOT The voltage on is still kept at V _REG -V _D1 The method comprises the steps of carrying out a first treatment on the surface of the Drive signal u for buffering output of high-order drive _GN Is V to ground potential _REG -V _D1 +V _P1 So that the high-order N-type power transistor VT _h Gate-source voltage V between gate and source _GS ＝V _REG -V _D1 Such gate-source voltage can be maintained at high-order N-type power transistor VT _h Above the turn-on voltage of the high-order N-type power transistor VT _h The on state is continuously maintained.

As shown in fig. 6 to 8, in the prior art driving circuit, when the DC/DC switching converter operates in the DCM operation mode, for example, there are a first operation phase, a second operation phase and a third operation phaseBit these three phase states; wherein the first working phase corresponds to the first pulse width modulation signal u _PWM Space phase of (2); the second and third working phases correspond to the first pulse width modulation signal u _PWM Is used for the pulse phase of the pulse. The circuit operation time sequence and CCM operation mode of the first operation phase and the second operation phase are the same; the DCM operation mode is different from the CCM operation mode and only presents in a third operation phase state; in the third working phase state, the current of the external energy storage inductor can drop to zero, the ZCD module detects that the inductor current drops to 0, and then the low-order N-type power transistor VT can be closed _l Signal u of circuit node SW _SW The potential is equal to the ground potential V of the circuit node P3 at this time _P3 。

FIG. 9 shows a detailed circuit of a high level shifter 61 in a typical prior art dual NMOS power transistor driver circuit architecture, which is complex in structure and uses 8 transistors; requires the cooperative operation of the 8 transistors to modulate the input pulse width modulation signal u _PWM Raised to fit high-order N-type power transistor VT _h A potential of the gate drive; the high-order level shift circuit 61 not only consumes energy itself, but also introduces signal delay.

FIG. 10 shows a high-side N-type power transistor VT prevention commonly used in a prior art dual NMOS power transistor driver circuit architecture _h And a low-order N-type power transistor VT _l In order to ensure that the high-order driving circuit and the low-order driving circuit work at the corresponding time sequences, in fig. 8, the level shift circuits are arranged before the high-order driving circuit and before the low-order driving circuit in the circuit unit for preventing the power tube from being in series, which is marked by 80, and the circuit structure is complex.

Compared with the driving circuit in the prior art of fig. 6, the embodiment shown in fig. 1 does not have the complex high-level shift circuit 61, so that the circuit adopted by the corresponding circuit is simpler, and the chip area occupied by circuit elements is greatly reduced; the high-order level shift circuit 61 in the prior art needs to have higher voltage resistance to the circuits in the high-order front-stage driving buffer matched with the high-order level shift circuitThe circuit requirement of the stage driving buffer is lower, so that the high-order front stage driving buffer does not need to adopt isolation devices, the requirement on the devices is reduced, and the area of the integrated circuit is further reduced; furthermore, in the integrated driving circuit of the present invention, since the high-order level shift circuit 61 in the prior art shown in fig. 4 is eliminated, the high-order N-type power transistor VT is prevented from being generated in the periphery of the DC/DC switching converter to which the driving circuit is applied _h And a low-order N-type power transistor VT _l The level shift circuit in front of the low-order drive circuit can be simplified due to the change of the high-order drive circuit, so that the area of the integrated circuit can be further reduced.

In the embodiment of the integrated driving circuit 200 for driving the power output transistor of the DC/DC switching converter shown in fig. 1, a clamping circuit controlled by a gate-source voltage is disposed between the gate and the source of the second N-type MOS transistor Q2, and the clamping circuit includes a first resistor R1 and a second resistor R2 connected in series between the gate and the source of the second N-type MOS transistor Q2; the clamping circuit further comprises a third N-type MOS tube Q3 arranged between the grid electrode and the source electrode of the second N-type MOS tube Q2; the drain electrode of the third N-type MOS tube Q3 is electrically connected with the grid electrode of the second N-type MOS tube Q2, the source electrode of the third N-type MOS tube Q3 is electrically connected with the source electrode of the second N-type MOS tube Q2, and the grid electrode of the third N-type MOS tube Q3 is electrically connected with the first resistor R1 and the second resistor R2 at the same time. The clamping circuit is used for clamping the gate-source voltage of the second N-type MOS transistor Q2, so that when the first phase is switched to the second working phase, the second N-type MOS transistor Q2 is switched from off to on at the moment, and the signal u of the circuit node SW is used for _SW The potential drops rapidly, the gate voltage of the second N-type MOS transistor Q2 cannot be followed quickly, the gate-source voltage difference of the second N-type MOS transistor Q2 can be increased, in order to ensure that the gate-source voltage of the second N-type MOS transistor Q2 cannot exceed the working range of the process device, the gate-source voltage of the second N-type MOS transistor Q2 needs to be clamped, and the clamping voltage is V _TH X (R1+R2)/R2, wherein V _TH The turn-on threshold voltage of the third N-type MOS transistor Q3.

In the embodiment of the integrated drive circuit 200 for DC/DC switching converter power output transistor driving shown in FIG. 1, a first inverter 264, low-order bits are also includedA drive control signal level shift circuit 265 and a low-order drive buffer 266; the low-order driving control signal is the first pulse width modulation signal u _PWM Is a second pulse width modulation signal

Is a logical not signal of (a); the low-order driving control signal is the first pulse width modulation signal u _PWM The first pulse width modulation signal u is input to the low-level driving control signal level shift circuit 265 to shift the signal potential _PWM Is higher than the first input power supply VDD by a pulse potential V _DD Fourth direct voltage signal u converted to external fourth external input power VNCLP _NCLP Potential V of (2) _NCLP While the low-level driving control signal level shift circuit 265 shifts the first pulse width modulation signal u _PWM Space potential from the first input power supply VDD ground potential V _GND Switching to low-order N-type power transistor VT _l Is the source potential V of (2) _P2 The method comprises the steps of carrying out a first treatment on the surface of the The low-level driving signal level shift circuit 265 outputs a signal to the low-level driving buffer 266, and the low-level driving buffer 266 outputs a low-level driving signal u _GN To low-order N-type power transistor VT _l For low-order N-type power transistor VT _l Is driven by (a); the low-order driving control signal is the first pulse width modulation signal u _PWM Is input to the first inverter 264, and the first inverter 264 outputs a high-order driving control signal, i.e., a second PWM signal +>

To the high drive pre-stage buffer 260.

As shown in fig. 1, in an embodiment of the integrated driving circuit 200 for driving the power output transistor of the DC/DC switching converter, the ZCD module 105 is further included for detecting the rectifying tube, i.e. the high-order N-type power transistor VT _h And/or low-order N-type power transistor VT _l Is set to zero crossing current; when the DC/DC switching converter to which the integrated driving circuit 200 is applied operates in a BUCK mode, i.e., is used as a BUCK system, the low-order N-type power transistor VT _l As a rectifier, the ZCD module 105 detects the low-order N-type power transistor VT _l Drain and low-order N-type power transistorVT _l A current signal between the sources of (a); when the DC/DC switching converter to which the integrated driving circuit 200 is applied operates in a BOOST mode, i.e., is used as a BOOST system, the high-side N-type power transistor VT _h To be a rectifying tube, the ZCD module 105 detects the high-level N-type power transistor VT _h Drain of (c) and high-order N-type power transistor VT _h A current signal between the sources of (a); when the DC/DC switching converter using the integrated driving circuit 200 operates in the BUCK-BOOST mode, i.e., is used as a BUCK-BOOST system, the low-order N-type power transistor VT _l As a rectifier, the ZCD module 105 detects the low-order N-type power transistor VT _l Drain and low-order N-type power transistor VT _l Is provided.

As shown in fig. 1, in an embodiment of an integrated driving circuit 200 for DC/DC switching converter power output transistor driving, a ringing cancellation module 101 is further included for removing ringing due to self-oscillation at an external inductance L1; when the DC/DC switching converter of the integrated driving circuit 200 operates in DCM and the ZCD module 105 detects that the rectifier current is 0, the high-order N-type power transistor VT is operated _h And/or low-order N-type power transistor VT _l When turned off, the ringing removal module 101 removes ringing due to self-oscillation at the external inductance L1.

As shown in fig. 2, in the embodiment of the integrated driving circuit 200 for driving the power output transistor of the DC/DC switching converter, the first switch K1 is a first diode D1, the positive electrode of the first diode D1 is used as the third output terminal of the capacitive coupling driving circuit 230, and the second direct-current voltage signal u inputted from the outside is connected _REG The method comprises the steps of carrying out a first treatment on the surface of the The cathode of the first diode D1 is electrically connected with the source electrode of the first P-type MOS transistor Q1; the second switch K2 is a first P-type MOS transistor Q1, the grid electrode of the first P-type MOS transistor Q1 and a high-order N-type power transistor VT _h The drain electrode of the first P-type MOS transistor Q1 is electrically connected with the drain electrode of the second N-type MOS transistor Q2, and the source electrode of the first P-type MOS transistor Q1 is used as a first input terminal of the capacitive coupling driving circuit 230 and a bootstrap capacitor C _BOOT Is electrically connected with the positive plate; a first resistor connected in series is arranged between the grid electrode and the source electrode of the second N-type MOS tube Q2A third N-type MOS tube Q3 is arranged between the grid electrode and the source electrode of the second N-type MOS tube Q2; the drain electrode of the third N-type MOS tube Q3 is electrically connected with the grid electrode of the second N-type MOS tube Q2, the source electrode of the third N-type MOS tube Q3 is electrically connected with the source electrode of the second N-type MOS tube Q2, and the grid electrode of the third N-type MOS tube Q3 is electrically connected with the first resistor R1 and the second resistor R2 at the same time.

In addition, the negative electrode of the external power supply is a zero potential point of the circuit, and the potential values of other circuit nodes are relative to the zero potential point; the battery or external power supply voltage is the potential difference between its positive and negative electrodes. For ease of description, some modules are numbered in one, two, etc., and these serial numbers do not represent any positional or sequential limitations, but are for ease of description.

The foregoing description is only an embodiment of the present invention, and the circuit topology described above is only a specific embodiment of the present invention, and is not limited to the patent scope of the present invention, and all equivalent structures or equivalent flow changes made by the description of the invention and the content of the drawings, or direct or indirect application in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. An integrated drive circuit (200) for DC/DC switching converter power output transistor driving, comprising:

for high-order drive control signals

An input buffered high-order drive pre-buffer (260) for bootstrap capacitor C with signal potential elevation _BOOT A capacitively coupled drive circuit (230) for signal coupling for high-order buffer drive signals u _DRP An inverted second inverter (268);

high-order drive control signal, i.e. second pulse width modulation signal

The output of the front-end buffer (260) is driven from a high levelAn input terminal input; the high-order drive front-stage buffer (260) outputs a high-order buffer drive signal u _DRP To bootstrap capacitor C _BOOT While the high-order drive front-stage buffer (260) outputs a high-order buffer drive signal u _DRP An input terminal to a second inverter (268);

bootstrap capacitor C _BOOT Is electrically connected to the positive plate of the capacitive coupling drive circuit (230); an output of the second inverter (268) is electrically connected to a second input terminal of the capacitively coupled drive circuit (230); a third input terminal of the capacitive coupling drive circuit (230) is used for accessing a third direct-current voltage signal u of an external third external input power supply VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the A first output terminal of the capacitive coupling drive circuit (230) and a high-order N-type power transistor VT _h The grid electrode is electrically connected with the second output terminal of the capacitive coupling driving circuit (230) and the high-order N-type power transistor VT _h The source electrode is electrically connected;

a second inverter (268), a bootstrap capacitor C _BOOT Cooperate with a capacitive coupling drive circuit (230) to buffer the high-order bits of the drive signal u _DRP Is raised at the high-order N-type power transistor VT _h After conducting, the high-order N-type power transistor VT which can continuously provide proper potential for the first output terminal of the capacitive coupling driving circuit (230) _h Gate drive signal, i.e. high drive signal u _GP ；

The capacitive coupling driving circuit (230) comprises a first switch K1, a second switch K2 and a first coupling capacitor C _BC1 And a second N-type MOS transistor Q2;

one end of the second switch K2 is used as a third input terminal of the capacitive coupling driving circuit (230), namely a third direct-current voltage signal u connected to a third external input power supply VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the The other end of the second switch K2 is electrically connected with one end of the first switch K1, and the other end of the second switch K2 is also used as a first input terminal of the capacitive coupling driving circuit (230), and the first input terminal and the bootstrap capacitor C _BOOT Is electrically connected with the positive plate of the drive circuit and is connected with the control signal u of the coupling drive circuit _VBOOT The method comprises the steps of carrying out a first treatment on the surface of the The other end of the first switch K1 is used as a first output terminal of the capacitive coupling drive circuit (230) for outputting high bitsN-type power transistor VT _h Gate driving signal u _GP To high-order N-type power transistor VT _h A gate electrode of (a); meanwhile, the other end of the first switch K1 is electrically connected with the drain electrode of the second N-type MOS tube Q2; coupled drive circuit control signal u _VBOOT And input a first direct current voltage signal u _P1 The switch of the first switch K1 is controlled jointly;

the source of the second N-type MOS transistor Q2 is used as the second output terminal of the capacitive coupling driving circuit (230) and the high-order N-type power transistor VT _h Is electrically connected to the source electrode of the transistor; grid electrode of second N-type MOS tube Q2 and first coupling capacitor C _BC1 Is electrically connected to one end of the first circuit board; first coupling capacitor C _BC1 Is used as a second input terminal of the capacitive coupling drive circuit (230) and is electrically connected with the output terminal of the second inverter (268);

one end of the second switch K2 is connected with the bootstrap capacitor C _BOOT Positive plate access coupling drive circuit control signal u _VBOOT The other end of the second switch K2 is connected with a third direct-current voltage signal u _REG Coupled to the driving circuit control signal u _VBOOT And a third DC voltage signal u _REG The switch of the second switch K2 is controlled jointly;

the first switch K1 is a first P-type MOS transistor Q1, the grid electrode of the first P-type MOS transistor Q1 and a high-order N-type power transistor VT _h The drain electrode of the first P-type MOS transistor Q1 is electrically connected with the drain electrode of the second N-type MOS transistor Q2, and the source electrode of the first P-type MOS transistor Q1 is used as a first input terminal of a capacitive coupling driving circuit (230);

source electrode of first P-type MOS tube Q1 and bootstrap capacitor C _BOOT Is electrically connected with the positive plate of the drive circuit and is connected with the control signal u of the coupling drive circuit _VBOOT The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of the first P-type MOS tube Q1 is connected with a first direct current voltage signal u _P1 The method comprises the steps of carrying out a first treatment on the surface of the Coupled drive circuit control signal u _VBOOT And a first direct current voltage signal u _P1 The switching state of the first P-type MOS transistor Q1 is controlled together;

the second switch K2 comprises a fourth N-type MOS transistor Q4 and a second coupling capacitor C _BC2 And a second diode D2, the anode of the second diode D2 being used as a third input terminal of the capacitive coupling driving circuit (230), being connected to a thirdThird direct-current voltage signal u of external input power supply VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the Meanwhile, the anode of the second diode D2 is electrically connected with the source electrode of the fourth N-type MOS transistor Q4; the cathode of the second diode D2 is electrically connected with the grid electrode of the fourth N-type MOS tube Q4; the grid electrode of the fourth N-type MOS tube Q4 is also connected with a second coupling capacitor C _BC2 Is electrically connected to one end of the first circuit board; second coupling capacitor C _BC2 And the other end of (C) and the first coupling capacitance C _BC1 Is electrically connected with one end of the second coupling capacitor C _BC2 The other end of the capacitor is used as a second input terminal of the capacitive coupling driving circuit (230), and the second coupling capacitor C _BC2 Is electrically connected to the other end of the second inverter (268); the drain electrode of the fourth N-type MOS transistor Q4 is used as a first input terminal of the capacitive coupling driving circuit (230), and a bootstrap capacitor C _BOOT Is electrically connected with the positive plate of the drive circuit and is connected with the control signal u of the coupling drive circuit _VBOOT The method comprises the steps of carrying out a first treatment on the surface of the Coupled drive circuit control signal u _VBOOT And a third DC voltage signal u _REG The switch states of the second switch K2 are controlled jointly.

2. The integrated drive circuit (200) for DC/DC switching converter power output transistor driving of claim 1, wherein:

the second switch K2 is a first diode D1, the positive electrode of the first diode D1 is used as a third input terminal of the capacitive coupling driving circuit (230), and is connected to a third direct-current voltage signal u of a third external input power supply VREG _REG The method comprises the steps of carrying out a first treatment on the surface of the Negative electrode of first diode D1 and bootstrap capacitor C _BOOT Is connected with the control signal u of the coupling driving circuit _VBOOT ；

Coupled drive circuit control signal u _VBOOT And a third DC voltage signal u _REG The switch of the first diode D1 is commonly controlled.

3. The integrated drive circuit (200) for DC/DC switching converter power output transistor driving of claim 1, wherein:

a clamping circuit controlled by gate-source voltage is arranged between the gate and the source of the second N-type MOS tube Q2, and comprises a first resistor R1 and a second resistor R2 which are connected in series between the gate and the source of the second N-type MOS tube Q2; the clamping circuit also comprises a third N-type MOS tube Q3 arranged between the grid electrode and the source electrode of the second N-type MOS tube Q2; the drain electrode of the third N-type MOS tube Q3 is electrically connected with the grid electrode of the second N-type MOS tube Q2, the source electrode of the third N-type MOS tube Q3 is electrically connected with the source electrode of the second N-type MOS tube Q2, and the grid electrode of the third N-type MOS tube Q3 is electrically connected with the first resistor R1 and the second resistor R2 at the same time.

4. An integrated drive circuit (200) for DC/DC switching converter power output transistor driving according to claim 3, characterized in that:

also included are a first inverter (264), a low-level drive control signal level shift circuit (265) and a low-level drive buffer (266); the low-order driving control signal is the first pulse width modulation signal u _PWM Is a second pulse width modulation signal

Is a logical not signal of (a);

The low-order driving control signal is the first pulse width modulation signal u _PWM The first pulse width modulation signal u is input to a low-level drive control signal level shift circuit (265) for shifting the signal potential _PWM Is higher than the first input power supply VDD by a pulse potential V _DD Fourth direct voltage signal u converted to external fourth external input power VNCLP _NCLP Potential V of (2) _NCLP While the low-level driving control signal level shift circuit (265) shifts the first pulse width modulation signal u _PWM Space potential from the first input power supply VDD ground potential V _GND Switching to low-order N-type power transistor VT _l Is the source potential V of (2) _P2 ；

The low-level driving signal level shift circuit (265) outputs a signal to the low-level driving buffer (266), and the low-level driving buffer (266) outputs a low-level driving signal u _GN To low-order N-type power transistor VT _l For low-order N-type power transistor VT _l Is driven by (a); the low-order driving control signal is the first pulse width modulation signal u _PWM Input toA first inverter (264), the first inverter (264) outputting a high-order drive control signal, i.e., a second pulse width modulation signal

To the high drive front buffer (260).

5. The integrated drive circuit (200) for DC/DC switching converter power output transistor driving of claim 4, wherein:

The device also comprises a ZCD module (105) for detecting the rectifying tube, namely the high-order N-type power transistor VT _h And/or low-order N-type power transistor VT _l Is set to zero crossing current;

when the DC/DC switching converter using the integrated driving circuit (200) works in BUCK mode, namely is used as a BUCK system, two ends of the ZCD module (105) are respectively connected with the low-order N-type power transistor VT _l Is electrically connected with the drain electrode and the source electrode of the transistor; low-order N-type power transistor VT _l Is a rectifying tube, the ZCD module (105) detects the low-order N-type power transistor VT _l Drain and low-order N-type power transistor VT _l A current signal between the sources of (a);

when the DC/DC switching converter applying the integrated driving circuit (200) works in a BOOST mode, namely is used as a BOOST system, two ends of the ZCD module (105) are respectively connected with the high-order N-type power transistor VT _h Is electrically connected with the drain electrode and the source electrode of the transistor; high-order N-type power transistor VT _h As a rectifying tube, the ZCD module (105) detects the high-order N-type power transistor VT _h Drain of (c) and high-order N-type power transistor VT _h A current signal between the sources of (a);

when the DC/DC switching converter using the integrated driving circuit (200) works in a BUCK-BOOST mode, namely is used as a BUCK-BOOST system, two ends of the ZCD module (105) are respectively connected with the low-order N-type power transistor VT _l Is electrically connected with the drain electrode and the source electrode of the transistor; low-order N-type power transistor VT _l Is a rectifying tube, the ZCD module (105) detects the low-order N-type power transistor VT _l Drain and low-order N-type power transistor VT _l Is provided.

6. The integrated drive circuit (200) for DC/DC switching converter power output transistor driving of claim 5, wherein:

the device also comprises a ringing elimination module (101), wherein two ends of the ringing elimination module (101) are respectively and electrically connected with two ends of the external inductor L1, and are used for eliminating ringing generated by self-oscillation of the external inductor L1 connected with the DC/DC switching converter;

when the DC/DC switching converter applying the integrated driving circuit (200) works in a DCM mode and the ZCD module (105) detects that the current of the rectifying tube is zero, the high-order N-type power transistor VT _h And a low-order N-type power transistor VT _l When turned off, the ringing cancellation module (101) removes ringing due to self-oscillation at the external inductance L1.

7. A DC/DC switching converter comprising an integrated drive circuit (200) according to any one of claims 1 to 6,

including for preventing high-order N-type power transistors VT _h And a low-order N-type power transistor VT _l A series-connected anti-series circuit unit (300);

The anti-cross circuit unit (300) comprises a third level shift circuit (391), a third inverter (393), a first AND gate (395), a fourth inverter (394) and a second AND gate (396);

low level driving signal u _GN The output terminal of the third level shift circuit (391) is electrically connected with the input terminal of the third inverter (393), the output terminal of the third inverter (393) is electrically connected with the first input terminal of the first AND gate (395), and the second input terminal of the first AND gate (395) is used for inputting a low-order drive control signal, namely a first pulse width modulation signal u _PWM The first AND gate (395) outputs a signal to the first inverter (264);

high-order buffer driving signal u _DRP Is input from the input terminal of a fourth inverter (394), the output terminal of the fourth inverter (394) is electrically connected to the first input terminal of a second AND gate (396), the second input terminal of the second AND gate (396)The sub-unit is used for inputting a low-order driving control signal, namely a first pulse width modulation signal u _PWM The second AND gate 396 outputs a signal to the low driving control signal level shift circuit 265.