CN214014122U

CN214014122U - Low-cost synchronous rectification circuit

Info

Publication number: CN214014122U
Application number: CN202120057294.7U
Authority: CN
Inventors: 覃印
Original assignee: Shenzhen Jinquan Technology Co ltd
Current assignee: Shenzhen Jinquan Technology Co ltd
Priority date: 2021-01-09
Filing date: 2021-01-09
Publication date: 2021-08-20
Anticipated expiration: 2031-01-09

Abstract

The utility model belongs to the technical field of rectifier circuit's technique and specifically relates to a low-cost synchronous rectifier circuit is related to, it produces the module, upper and lower tub of complementary production module, upper and lower pipe drive output module including the PWM square wave that connects gradually to and BUCK topology module, upper and lower tub of complementary production module includes dead time control submodule piece and high low level separation submodule piece, the output that the PWM square wave produced the module is connected in dead time control submodule's input, dead time control submodule's output is connected with high low level separation submodule piece. This application has the effect of adjustable dead time.

Description

Low-cost synchronous rectification circuit

Technical Field

The application relates to the technical field of rectifier circuits, in particular to a low-cost synchronous rectifier circuit.

Background

In order to reduce power consumption, the supply voltage of various high-performance microprocessors is lower and lower, and therefore, low-voltage large-current DC-DC converters are becoming an important research direction. Since the secondary outputs a large current, the rectification loss becomes a major factor affecting the efficiency. The traditional Schottky diode has large on-resistance and can not meet the design requirement of a high-efficiency converter; and the MOSFET tube with low on-resistance can effectively reduce loss, namely the MOSFET tube is a synchronous rectification circuit. The traditional DC-DC topological structure is composed of a power MOS switch power tube and a freewheeling diode. The on-state voltage of the freewheeling diode is usually around 0.7V, and the on-state loss of the freewheeling diode is too large in the on-state stage, which may reduce the system operating efficiency. The current mainstream structure is a synchronous DC-DC topological structure, and a switching power tube and a power MOS follow current power tube are adopted in the traditional synchronous DC-DC topological structure, so that the synchronous topological structure can reduce the conduction loss of a follow current passage, the efficiency is improved, a synchronous rectifier can improve the conversion efficiency of a converter, and the synchronous rectifier is generally applied to the design of a low-voltage high-current converter at present.

In an ideal steady state, the power MOS switch power transistor and the power MOS freewheeling power transistor work in opposite states, that is, when one of the two is turned on, the other must be turned off, and vice versa. The pulse width modulation PWM signal output by the control circuit is divided into two clock square wave signals through a logic circuit to control the on and off of the two power tubes. Theoretically, the square wave signals respectively driving the power MOS switch power tube and the power MOS follow current power tube do not make the two power tubes conduct at the same time. In practice, however, since a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has a slight delay in driving the gate, in an undesired case, there may be a period of time during which two power transistors are simultaneously turned on, which is called a through state. Shorting the input to ground in the through state causes a large amount of current to be generated, which not only reduces the overall DC-DC efficiency, but also may damage the chip. In order to reduce the generation of the through state, a certain time delay is artificially introduced between the turning-off of one power tube and the turning-on of the other power tube, namely, square wave signals for driving a power MOS switch power tube and a power MOS follow current power tube are non-overlapping clock signals, and the time delay is called as the dead time of a DC-DC converter. However, during this time, the freewheeling current continues to freewheel through the parasitic diode of the freewheeling MOS transistor, and therefore there is also a diode conduction loss during the dead time. Furthermore, if the dead time is too short, a shoot-through condition may also occur.

The dead-time control of the DC-DC converter is to control the dead-time existing in two operation processes: the first is dead time between the closing of a power switch power tube and the opening of a power follow current power tube; the second is the dead time between the closing of the power follow current power tube and the opening of the power switch power tube. The traditional dead zone control is a fixed dead zone, but the set delay length must meet the application conditions of all DC-DC converters, such as the change of input and output voltages, the change of load current and the like, and the defect that the dead zone time is fixed and is not convenient for adapting to different application conditions exists.

SUMMERY OF THE UTILITY MODEL

In order to adjust the dead time, the present application provides a low-cost synchronous rectification circuit.

The application provides a low-cost synchronous rectification circuit adopts following technical scheme:

the low-cost synchronous rectification circuit comprises a PWM square wave generation module, an upper and lower tube complementary generation module, an upper and lower tube driving output module and a BUCK topology module which are sequentially connected, wherein the upper and lower tube complementary generation module comprises a dead time control submodule and a high and low level separation submodule, the output end of the PWM square wave generation module is connected to the input end of the dead time control submodule, and the output end of the dead time control submodule is connected with the high and low level separation submodule.

By adopting the technical scheme, the PWM square wave generating module generates PWM signals, the PWM signals enter the high-low level separation submodule after the dead zone control submodule generates dead zone time to form two complementary waveforms, so that the upper and lower pipe output modules are driven to start to drive the BUCK topology module to start, and the effect of adjusting the dead zone time is realized.

Preferably, the dead time control submodule comprises a first resistor R1 and a first capacitor C1 connected with the first resistor R1, and the output end of the square wave generating module is connected to the other end of the first resistor R1 away from the first capacitor C1; the high-low level separation sub-module comprises a first comparator U1 and a second comparator U2, wherein the forward end of the first comparator U1 and the reverse end of the second comparator U2 are connected between a first resistor R1 and a first capacitor C1, and the control threshold voltage connected to the reverse end of the first comparator U1 is larger than the control threshold voltage connected to the forward end of the second comparator U2.

By adopting the technical scheme, the first resistor R1 and the first capacitor C1 integrate the input PWM signal, so that the PWM signal is introduced into the first capacitor C1 and the second capacitor C2 after dead time is generated to realize high-low level separation and form two complementary waveforms, the dead time can be adjusted by adjusting the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1, and the effect of adjusting the dead time is achieved.

Preferably, the upper and lower tube complementation generation module further comprises a control threshold voltage generation submodule connected with the reverse terminal of the first comparator U1 and the forward terminal of the second comparator U2.

By adopting the technical scheme, the control threshold voltage generation submodule generates the control threshold voltage, and the control module has the effects of simplifying the module and facilitating maintenance.

Preferably, the control threshold voltage generation submodule includes a second resistor R2, a third resistor R3 and a fourth resistor R4, which are connected in sequence, one end of the third resistor R3 is grounded, one end of the fourth resistor R4, which is far away from the third resistor, is connected to a power supply, the reverse end of the first comparator U1 is connected between the third resistor R3 and the fourth resistor R4, and the forward end of the second comparator U2 is connected between the second resistor R2 and the third resistor R3.

By adopting the technical scheme, the control threshold voltage accessed by the forward end of the first comparator U1 and the reverse end of the second comparator U2 is different through the voltage division of the second resistor R2, the third resistor R3 and the fourth resistor R4, the control threshold voltage generation circuit is simplified, and the value of the control threshold voltage can be adjusted by adjusting the resistance values of the second resistor R2, the third resistor R3 and the fourth resistor R4.

Preferably, the upper and lower tube driving output module comprises an H-bridge rectifying circuit, and an output end of the H-bridge rectifying circuit is connected with an input end of the BUCK topology module respectively.

By adopting the technical scheme, the H-bridge rectifying circuit is matched with the high-low level conduction separated by the first comparator U1 and the second comparator U2, so that the effect of driving the BUCK topology module is realized.

Preferably, the output end of the first comparator U1 is connected to the input end of an upper tube in the H-bridge rectification circuit, and the output end of the second comparator U2 is connected to the input end of a lower tube in the H-bridge rectification circuit.

Through adopting above-mentioned technical scheme, the upper tube switches on in the high level drive H bridge rectifier circuit of first comparator U1 output, and the lower tube switches on in the high level drive H bridge rectifier circuit of second comparator U2 output to the effect that the realization drives H bridge rectifier circuit respectively and starts.

Preferably, the second resistor R2, the third resistor R3 and the fourth resistor R4 have the same resistance.

By adopting the technical scheme, the second resistor R2, the third resistor R3 and the fourth resistor R4 are set to have the same resistance value, so that the difference value between the voltage values of the forward end of the first comparator U1 and the reverse end of the second comparator U1 is in a reasonable interval range.

Preferably, the first resistor R1 has a resistance of 2K Ω, and the first capacitor C1 has a capacitance of 22 pF.

By adopting the technical scheme, the value of the first resistor R1 and the value of the first capacitor C1 are set to be the same value, and the dead time suitable for inputting a 12V PWM signal can be obtained by calculation under the condition of not applying a load.

Drawings

FIG. 1 is a schematic diagram of a low-cost synchronous rectification circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an upper and lower tube complementary generating module in the embodiment of the present application.

Description of reference numerals: 1. a PWM square wave generating module; 2. an upper pipe and a lower pipe are complementary to generate a module; 21. a dead time control submodule; 22. a high-low level separation submodule; 23. controlling a threshold voltage generation submodule; 3. the upper and lower tubes drive the output module; 4. and a BUCK topology module.

Detailed Description

The present application is described in further detail below with reference to figures 1-2.

The embodiment of the application discloses a low-cost synchronous rectification circuit. Referring to fig. 1 and 2, the low-cost synchronous rectification circuit comprises a PWM square wave generation module 1, an upper and lower tube complementary generation module 2, an upper and lower tube driving output module 3, and a BUCK topology module 4, which are connected in sequence, wherein the PWM square wave generation module 1 generates a PWM signal; the upper and lower tube complementary generation module 2 comprises a dead time control submodule 21 and a high and low level separation submodule 22, the output end of the PWM square wave generation module 1 is connected to the dead time control submodule 21, a PWM signal is input into the dead time control submodule 21, then the high and low level separation submodule 22 is input to realize the separation of high and low levels, then the high and low level separation submodule is output to the BUCK topology module 4 through the upper and lower tube drive output module 3, and the effects of high and low level low-cost separation and dead time control are realized.

Referring to fig. 2, the dead time control submodule 21 includes a first resistor R1 and a first capacitor C1 connected to the first resistor R1, the output terminal of the PWM square wave generating module 1 is connected to the end of the first resistor R1 away from the first capacitor C1, and the end of the first capacitor C1 away from the first resistor R1 is grounded.

The high-low level separation sub-module 22 includes a first comparator U1 and a second comparator U2 with the same model and parameter, a forward end of the first comparator U1 and a reverse end of the second comparator U2 are both connected between the first resistor R1 and the first capacitor C1, a reverse end of the first comparator U1 and a forward end of the second comparator U2 are respectively connected to control threshold voltages, the control threshold voltage connected to the reverse end of the first comparator U1 is greater than the control threshold voltage connected to the forward end of the second comparator U2, and all the control threshold voltages are smaller than the maximum value of the PWM signal.

The PWM signal is integrated by the first resistor R1 and the first capacitor C1 to generate a delay and then input to the forward terminal of the first comparator U1 and the reverse terminal of the second comparator U2, when the PWM signal is higher than the control threshold voltage connected to the reverse terminal of the first comparator U1, the output terminal of the first comparator U1 outputs a delayed high level signal, the output terminal of the second comparator U2 outputs a delayed low level signal, when the PWM signal is lower than the control threshold voltage connected to the forward terminal of the second comparator U2, the PWM signal is delayed due to the integration of the first resistor R1 and the first capacitor U1, so that the PWM signal exists in a voltage range that is smaller than the control threshold voltage of the first comparator U1 and larger than the control threshold voltage of the second comparator U2, and in this voltage range, the output terminals of the first comparator U1 and the second comparator U2 both output low levels, thereby creating dead time.

The upper and lower tube driving output module 3 comprises an H-bridge rectifying circuit, a specific circuit schematic diagram refers to fig. 1, the input end of an upper tube of the H-bridge rectifying circuit is connected with the output end of a first comparator U1, the input end of a lower tube of the H-bridge rectifying circuit is connected with the output end of a second comparator U2, the BUCK topology module 4 comprises two N-MOS type field effect tubes, the specific circuit schematic diagram refers to fig. 1, and the output end of the upper tube of the H-bridge rectifying circuit and the output end of the lower tube of the H-bridge rectifying circuit are respectively connected with the grid electrodes of the two N-MOS type field effect tubes.

When the output end of the first comparator U1 outputs high level, the upper tube of the H bridge rectification circuit is conducted, the high level signal output by the first comparator U1 is driven by the upper tube of the H bridge rectification circuit to start the N-MOS type field effect transistor connected with the upper tube of the H bridge rectification circuit, and then is amplified by the push-pull of the N-MOS type field effect transistor, the second comparator U2 is matched with the lower tube of the H bridge rectification circuit and the N-MOS type field effect transistor connected with the lower tube of the H bridge rectification circuit, the dead zone time formed by integrating the first resistor R1 and the first capacitor C1 is driven by the first comparator U1 and the second comparator U2 through two complementary signals of dust, and the N-MOS type field effect transistor in the BUCK topology module 4 is driven by the H bridge rectification circuit respectively, so that the dead zone time is controllable, and the purpose of high-efficiency rectification is realized.

Referring to fig. 2, a control threshold voltage generation submodule 23 is connected between a reverse end of the first comparator U1 and a forward end of the second comparator U2, the control threshold voltage generation submodule 23 includes a second resistor R2, a third resistor R3 and a fourth resistor R4 which are connected in sequence, one end of the third resistor R3 is grounded, one end of the fourth resistor R4, which is far away from the third resistor R3, is connected to a power supply, a reverse end of the first comparator U1 is connected between the third resistor R3 and the fourth resistor R4, and a forward end of the second comparator U2 is connected between the second resistor R2 and the third resistor R3.

In this embodiment, the amplitude of the PWM signal is 12V, the resistance of the first resistor R1 is 2K Ω, the capacitance of the first capacitor C1 is 22pF, the resistances of the second resistor R2, the third resistor R3 and the fourth resistor R4 are 10K Ω, and in this embodiment, the model of the comparator is LM358, through these combinations, the PWM signal is integrated by the first resistor R1 and the first capacitor C1 to generate a small delay, and is input to the positive terminals and the negative terminals of the two comparators of LM358, when the PWM signal is high level, the output terminal of the first comparator U1 outputs a delayed high level signal, when the output terminal of the second comparator U2 outputs a low level after low delay, when the PWM signal is low level, the first comparator U1 outputs a delayed low level signal, when the second comparator U2 outputs a high level after low delay, the phase inversion R2, the R3, and the R4 provide a control level for the three comparators 395925, if the power supply is 12V, the voltage corresponding to the reverse terminal of the first comparator U1 is 8V, the forward terminal voltage of the second comparator U2 is 4V, when the PWM signal is greater than 8V, the first comparator U1 outputs a high level, when the PWM signal is less than 4V, the second comparator U2 outputs a high level, when the PWM signal is greater than 4V and less than 8V, the first comparator U1 and the second comparator U2 output a low level at the same time, and a dead zone value time is generated, wherein the dead zone time is equal to the values of the first resistor R1 and the first capacitor C1.

The implementation principle of the low-cost synchronous rectification circuit in the embodiment of the application is as follows: the PWM signal is integrated by a first resistor R1 and a first capacitor C1 to generate time delay and is input to the positive terminals and the negative terminals of the two comparators, when the PWM signal is at high level, the output terminal of the first comparator U1 outputs a high level signal after time delay, the output terminal of the second comparator U2 outputs a low level after low time delay, when the PWM signal is at low level, the first comparator U1 outputs a low level signal after time delay, when the second comparator U2 outputs a high level after low time delay, three 10K resistors R2, R3 and R4 respectively provide a control level threshold for the comparators, when the PWM signal is greater than the control threshold voltage of the first comparator U1, the first comparator U1 outputs high level, when the PWM signal is greater than the control threshold voltage of the second comparator U2, the second comparator U2 outputs high level, when the PWM signal is greater than the control threshold voltage of the second comparator U2, when the voltage is less than the control threshold voltage of the first comparator U1, the first comparator U1 and the second comparator U2 output low level simultaneously, so that a dead time is generated, and the dead time can be controlled by adjusting the values of the first resistor R1 and the first capacitor C1.

The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims

1. Low-cost synchronous rectifier circuit, its characterized in that: the device comprises a PWM square wave generation module (1), an upper and lower tube complementary generation module (2), an upper and lower tube drive output module (3) and a BUCK topology module (4) which are sequentially connected, wherein the upper and lower tube complementary generation module (2) comprises a dead time control submodule (21) and a high and low level separation submodule (22), the output end of the PWM square wave generation module (1) is connected to the input end of the dead time control submodule (21), and the output end of the dead time control submodule (21) is connected with the high and low level separation submodule (22).

2. A low-cost synchronous rectification circuit according to claim 1, wherein: the dead time control submodule (21) comprises a first resistor R1 and a first capacitor C1 connected with a first resistor R1, and the output end of the square wave generation module is connected to the other end, away from the first capacitor C1, of the first resistor R1; the high-low level separation submodule (22) comprises a first comparator U1 and a second comparator U2, wherein the forward end of the first comparator U1 and the reverse end of the second comparator U2 are connected between a first resistor R1 and a first capacitor C1, and the control threshold voltage connected to the reverse end of the first comparator U1 is larger than the control threshold voltage connected to the forward end of the second comparator U2.

3. A low-cost synchronous rectification circuit according to claim 2, wherein: the upper and lower tube complementation generating module (2) also comprises a control threshold voltage generating submodule (23) which is connected with the reverse end of the first comparator U1 and the forward end of the second comparator U2.

4. A low cost synchronous rectification circuit according to claim 3 wherein: the control threshold voltage generation submodule (23) comprises a second resistor R2, a third resistor R3 and a fourth resistor R4 which are sequentially connected, one end of the third resistor R3 is grounded, one end, far away from the third resistor, of the fourth resistor R4 is connected to a power supply, the reverse end of the first comparator U1 is connected between the third resistor R3 and the fourth resistor R4, and the forward end of the second comparator U2 is connected between the second resistor R2 and the third resistor R3.

5. The low-cost synchronous rectification circuit of claim 4, wherein: the upper and lower tube driving output module (3) comprises an H-bridge rectifying circuit, and the output end of the H-bridge rectifying circuit is respectively connected with the input end of the BUCK topology module (4).

6. The low-cost synchronous rectification circuit of claim 4, wherein: the output end of the first comparator U1 is connected with the input end of an upper tube in the H-bridge rectification circuit, and the output end of the second comparator U2 is connected with the input end of a lower tube in the H-bridge rectification circuit.

7. The low-cost synchronous rectification circuit of claim 4, wherein: the second resistor R2, the third resistor R3 and the fourth resistor R4 have the same resistance.

8. A low-cost synchronous rectification circuit according to claim 2, wherein: the resistance of the first resistor R1 is 2K omega, and the capacitance of the first capacitor C1 is 22 pF.