JPH1141801A - Voltage clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage clamp circuit which can prevent variations in clamp voltage and is a smaller sized chip. SOLUTION: A three-terminal regulator 6 is connected to an output terminal of a generator 3, and then a clamp circuit (IC) 12 is connected to three terminals of the three-terminal regulator 6. The clamp circuit 12, being constituted of a transistor 10, three resistors 7, 8, 9 and a control circuit 11, clamp the voltage using the threshold voltage of the transistor 10 and prevents overvoltage from being applied to the control circuit 11. Since the clamp circuit 12 does not use a constant-voltage diode, it can prevent the variation in voltage to be clamped. It can also reduce the margin of withstanding voltage in the control circuit 11 and reduce the size of a chip and thereby prevent the decrease in operating speed, so that it can reduce the size and weight and increase the operating speed of the entire device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage clamp circuit for reducing an overvoltage such as a surge voltage to a certain voltage or less.

[0002]

2. Description of the Related Art Conventionally, as a clamp circuit of this type, there is one having a circuit configuration shown in FIG. This circuit is configured as a power supply circuit in which a diode 4 is connected in series to a generator 3 containing an inductance 1 and an AC power supply 2 and a battery 5 is connected in parallel to this series circuit. Is connected. And
In a state where the battery 5 is being charged from the generator 3 via the diode 4, if the line connected to the battery 5 is disconnected 13 due to loosening of the screw or the like, an overvoltage occurs in the generator 3 due to the inductance 1. For this reason, the connection points P1 and P3
An overvoltage is applied to the control circuit 11 connected therebetween,
The control circuit 11 may be destroyed. Therefore, in this circuit, the resistor 103 and the constant voltage diode 101 are connected in series between the connection points P1 and P3, and the control circuit 11 is connected to both ends of the constant voltage diode 101. Therefore, since the voltage at the connection point 18 to which the control circuit 11 is connected is clamped by the constant voltage diode 101, it is possible to prevent an overvoltage from being applied to the control circuit 11.

As shown in FIG. 6, a circuit described in Japanese Patent Application Laid-Open No. 6-89972 includes a DC power supply 201, an inductive load 204 composed of an inductance 202 and a resistor 203, and a field effect transistor 205. , Resistor 206
, A control circuit 209, a bipolar transistor 210, and a constant voltage diode 211.

In this circuit, the field effect transistor 20
When 5 is OFF, an overvoltage is generated by the inductance 202. At this time, the resistor 206, the base / emitter of the bipolar transistor 210, the constant voltage diode 21
1, the current flowing through the resistor 207 and the control circuit 209,
When the gate-source voltage of the field-effect transistor 205 exceeds V _TH , the field-effect transistor 205 changes to the ON state, and when it is lower than V _TH , the field-effect transistor 205 changes to the OFF state. Note that V _TH is a threshold voltage of the field-effect transistor 205. This clamps the drain-source voltage V _DS of the field-effect transistor 205 to V _DS = (V _TH + V _Z + V _BE ) × (R1 + R2) / R2 or less. Note that V _BE is the base-emitter voltage of the bipolar transistor 210, V _Z
Is a breakdown voltage of the constant voltage diode 211, and R1 and R2 are resistance values of the resistors 206 and 208. Also, “V _TH + V
Constant voltage diode 21 to withstand voltage to offset the temperature coefficient of _BE
1 is set.

However, in a circuit using such a constant voltage diode, the variation in the clamp voltage is large. For example, when the temperature dependency is ± 7%, the voltage is 20V ± 20.
%, So that it is necessary to increase the breakdown voltage margin of the control circuit 213, which causes a problem that the chip size increases and the operation speed decreases.

A circuit that does not use a constant voltage diode has been proposed in Japanese Patent Application Laid-Open No. 6-232646. As shown in FIG. 7, this circuit includes a DC power supply 301, a load 302, and field-effect transistors 303, 304, and 30.
5, resistors 306 and 307, and a control circuit 308. In this circuit, during energization of the field effect transistor 303, the overcurrent causes the field effect transistor 303
When the ON voltage of the transistor increases, the field effect transistor 305
Turns ON. As a result, the current from the control circuit 308 flows through the resistor 307, and when the gate-source voltage of the field effect transistor 304 exceeds V _TH , the field effect transistor 304 changes to the ON state, and conversely, V _TH
If it is smaller, the field effect transistor 304 changes to the OFF state. Thereby, the field effect transistor 30
4 to clamp the drain-source voltage V _DS to V _DS = V _TH × (R1 + R2) / R2. Note that R1 and R2 are resistance values of the resistors 306 and 307, respectively.

[0007]

As described above, FIG.
And the circuit using the constant voltage diode shown in FIG.
The variation in the clamp voltage of the constant voltage diode is remarkable, and in order to avoid this, it is necessary to increase the breakdown voltage margin of the control circuit, which increases the chip size and lowers the operation speed. Further, in the circuit without using the constant voltage diode shown in FIG. 7, although variations in the clamp voltage due to the Zener diode is avoided, manufacturing variations and temperature dependence of the threshold voltage V _TH of the field effect transistor in this circuit arrangement In consideration of the above, for example, a variation of ± 50% such as 0.8 V ± 0.4 V results. Therefore, the circuit of FIG. 7 is insufficient to solve the problems of the circuits of FIGS.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a voltage clamp circuit capable of preventing variations in the clamp voltage and reducing the chip size.

[0009]

SUMMARY OF THE INVENTION The present invention provides a power supply, a three-terminal constant voltage element having two terminals connected between output terminals of the power supply, and first to third elements of the three-terminal constant voltage element. A clamp circuit connected to each terminal to supply a constant voltage to the load circuit, wherein the clamp circuit includes a first resistor connected in series between the first and second terminals, and a first resistor connected between the first and second terminals. One transistor, the first resistor and the first resistor.
And a second resistor connected between the gate or base of the first transistor and a gate between the gate or base of the first transistor and the third terminal. A configuration including a third resistor, and a control circuit connected in parallel with the second resistor and the third resistor connected in series with each other. In this case, the gate or base of the first transistor and the third transistor
, A second transistor and a third resistor may be connected in series.

The clamp circuit includes a first resistor connected in series between the first and third terminals,
A first transistor and a third transistor, a connection point between the first resistor and the first transistor, a second resistor connected between a gate or a base of the first transistor, A third transistor connected between the gate or base of the first transistor and the third terminal;
And a second resistor and a third resistor connected in series with each other.
A control circuit connected in parallel with the third resistor, and fourth and fifth transistors and a fourth resistor connected in series between the second terminal and the third terminal. The gate or the base is connected to a connection point between the fifth transistor and the fourth transistor.

The power supply clamp circuit of the present invention uses a constant voltage circuit without using a constant voltage diode. In particular, as this constant voltage circuit, a commercially available three-terminal regulator that is normally used as a power supply on the low voltage side of the IC is used. Then, a clamp circuit composed of a transistor and a resistor is connected to the terminal of this three-terminal regulator, and the overvoltage is absorbed by using the threshold voltage of the transistor to reduce the voltage variation, and the constant voltage in the control circuit is reduced. Hold.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. In FIG. 1, a diode 4 is connected in series to a generator 3 containing an inductance 1 and an AC power supply 2, and a battery 5 and a constant voltage circuit 6 are connected in parallel to this series circuit. The constant voltage circuit is generally constituted by a commercially available three-terminal regulator (voltage variation: about ± 5%) used as a power supply on the low voltage side of the IC. Then, three terminals of the constant voltage circuit 6 are connected to ICs 12 constituting a clamp circuit as connection points P1, P2, and P3, respectively. The IC12
Is an N-channel field-effect transistor 10 whose source is connected to the connection point P2, whose drain is connected to the connection point P1 via the resistor 8, and whose gate is connected to the connection point P3 via the voltage dividing resistors 8 and 9, respectively. It is configured. A control circuit 11 is connected between the source and the drain of the field effect transistor 10.
Is connected.

The operation of the power supply circuit having the clamp circuit will be described with reference to FIG. Generator 3 to diode 4
When the battery 5 is charged and the circuit of the battery 5 is disconnected X due to loosening of the screw or the like, the generator 3
An overvoltage is generated by the inductance 1 of the IC 12, and the overvoltage is applied between the connection point P1 and the connection point P3 (GND) of the IC 12. However, the voltage at the connection point P2 is the output voltage E of the constant voltage circuit 6, and is maintained at a constant voltage. Therefore, the gate voltage of the field effect transistor 10 is “E +
_VTN ". Here, V _TN indicates a threshold voltage of the field effect transistor 10. Even if the gate voltage, that is, the voltage at the connection point P4 is about to rise, when the gate-source voltage of the field effect transistor 10 exceeds _VTN , the field effect transistor 10
Is turned ON, and conduction is established between the drain and the source, so that the voltage at the connection point P4 is returned to “E + V _TN ”. Therefore, the voltage V at the connection point P5, which is the voltage of the control circuit 11,
_P5 is V _P5 = (E + V _TN ) × (R8 + R9) / R9, and it is possible to prevent application of an overvoltage. R8 and R9 are resistance values of the resistors 8 and 9, respectively. For example, E = 5V ± 5%, V _TN = 0.8V ± 0.
When 4V, R8: R9 = 2.45: 1, the clamp voltage becomes 20V ± 2.3V, and it can be seen that the variation is suppressed.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, the IC 12A constituting the clamp circuit is connected between the gate and the resistor 9 of the field-effect transistor 10 via the source and the drain of the second field-effect transistor 13 whose gate and drain are connected. The second field effect transistor 13
An N-channel field-effect transistor of the same conductivity type as the field-effect transistor 10 is used.

In the second embodiment, when an overvoltage occurs in the generator 3 and the voltage at the connection point P4 is about to rise, the field-effect transistor 10 is turned on, so that the same as in the first embodiment. The voltage at the connection point P4 is maintained at "E + V _TN ". Here, a second field effect transistor 1 of the same conductivity type as the field effect transistor 10 is used.
3, the voltage EP4 at the node _P4 becomes "E + V
_TN1 - _VTN2 ". Therefore, by setting both the field effect transistors 10 and 13 to the same threshold voltage, the voltage VP6 at the node _P6 becomes "E + _VTN - _VTN =
E ". Therefore, the voltage V _{P5 at} the connection point P5 is V _P5 = E × (R8 + R9) / R9 + V _TN . Therefore, since the voltage is clamped, it is possible to prevent an overvoltage from being applied to the control circuit 11.
For example, E = 5V ± 5%, V _TN = 0.8V ± 0.4V,
If R8: R9 = 2.84: 1, the clamp voltage is 2
0V ± 1.4V, which indicates that the variation is suppressed as compared with the first embodiment.

FIG. 4 is a circuit diagram of a third embodiment of the present invention. In the figure, portions equivalent to those in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted.
In this embodiment, the IC 12B as a clamp circuit
Is the drain of a third field-effect transistor 14 of a P-channel type having a conductivity type opposite to that of the field-effect transistor 10.
The source is connected between the source of the field effect transistor 10 and the connection point P3. The source and drain of an N-channel fifth field-effect transistor 16, which is the same as the N-channel fourth field-effect transistor 15, and the opposite N-channel type fifth field-effect transistor 16, are connected in cascade. It is connected between connection points P2 and P3. The gates of the fourth and fifth field effect transistors 15 and 16 are respectively connected to the drain, and the gate of the third field effect transistor 14 is connected to the fifth field effect transistor 16 and the resistor 17. Is connected to the connection point P7.

[0017] In this configuration, when an overvoltage occurs in the generator 3, the voltage V _P7 of the connection point P7 is a '"E-V _TN one V _TP". Here, V _TN and V _TP are the absolute values of the threshold voltages of the N-channel type and P-channel type field effect transistors 10, 14, 15, and 16, respectively. The absolute values are assumed to be equal. Then, the voltage _VP4 at the connection point _P4 is the voltage at the connection point P7 + the threshold voltage of the field effect transistor 14 + the field effect transistor 10
_VP4 = E- _VTN - _VTP + _VTP + _VTN = E. If the voltage V _P4 at the connection point P4 is increased, i.e. as the voltage at the node P5 rises, since the field effect transistor 10 is turned ON, the voltage V _P4 connection point P4 is returned to "E". Thereby, the voltage V at the connection point P5 is obtained.
_P5 is given by V _P5 = E × (R8 + R9) / R9. Therefore, since the voltage is clamped, it is possible to prevent an overvoltage from being applied to the control circuit 11.
For example, E = 5V ± 5%, V _TN = 0.8V ± 0.4V,
When V _TP = 0.7V ± 0.4V and R8: R9 = 3: 1, the clamp voltage is 20V ± 1.0V, and it can be seen that the variation is suppressed as compared with the above embodiments. Further, since the current flowing when the voltage is clamped flows through the field effect transistor 10 and the field effect transistor 14, the current does not flow into the constant voltage circuit 6, and the stable clamp voltage is obtained regardless of the current absorbing capability of the constant voltage circuit. Can be obtained.

In the first to third embodiments, since the control circuit 11 to be protected is on the GND side,
The circuit is mainly composed of the constant voltage circuit 6 on the ND side and the N-channel type field effect transistor. However, when the circuit to be protected is on the power supply side, the constant voltage circuit on the power supply side and the P-channel type The clamp circuit may be formed by a field effect transistor. In each of the above embodiments, a field effect transistor is used as a transistor, but a bipolar transistor may be used in the same manner. In this case, an NPN bipolar transistor may be used as the N-channel field-effect transistor and a PNP bipolar transistor may be used as the P-channel field-effect transistor in each of the above embodiments.

[0019]

As described above, according to the present invention, a clamp circuit composed of a transistor and a resistor is connected to three terminals of a three-terminal regulator, and a clamp operation is performed by utilizing a threshold voltage of the transistor. Therefore, a constant voltage circuit can be configured without using a constant voltage diode, and the ratio of the threshold voltage of the transistor to the power supply voltage can be reduced, so that the variation in the clamp voltage can be reduced. This allows
Decreasing the withstand voltage margin of the control circuit becomes tired, and the chip size is reduced, the operating speed can be increased, and the size, weight, and speed can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

FIG. 5 is a circuit diagram of an example of a conventional clamp circuit.

FIG. 6 is a circuit diagram of another example of a conventional clamp circuit.

FIG. 7 is a circuit diagram of still another example of the conventional clamp circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Inductance 2 AC power supply 3 Generator 4 Diode 5 Battery 6 Constant voltage circuit 7, 8, 9 resistance 10 Field effect transistor 11 Control circuit 12, 12A, 12B IC 13, 14, 15, 16 Field effect transistor 17 Resistance

Claims (3)

[Claims] 1. A power supply, a three-terminal constant-voltage element having two terminals connected between output terminals of the power supply, and a clamp circuit connected to first to third terminals of the three-terminal constant-voltage element. Wherein the clamp circuit comprises: a first resistor and a first transistor connected in series between the first and second terminals; and a connection between the first resistor and the first transistor. A point, a second resistor connected between the gate or base of the first transistor, and a third resistor connected between the gate or base of the first transistor and the third terminal. And a control circuit connected in parallel with the second resistor and the third resistor connected in series. 2. The voltage clamp circuit according to claim 1, wherein a second transistor and a third resistor are connected in series between a gate or a base of the first transistor and the third terminal. 3. A power supply, a three-terminal constant-voltage element having two terminals connected between output terminals of the power supply, and a clamp circuit connected to each of first to third terminals of the three-terminal constant-voltage element. Wherein the clamp circuit includes a first resistor, a first transistor, and a third transistor connected in series between the first and third terminals, and the first resistor and the first transistor. And a second resistor connected between the gate or base of the first transistor and a gate between the gate or base of the first transistor and the third terminal. A third resistor, a second resistor connected in series with the third resistor, a control circuit connected in parallel with the third resistor, and a second terminal connected to the third terminal;
And a fourth resistor and a fourth resistor connected in series between the terminals of the third and fourth transistors, and a gate or a base of the third transistor is connected to a connection point between the fifth and fourth transistors. A voltage clamp circuit.