CN115833560A - SenseFET type full-wave inductive current sensor - Google Patents
SenseFET type full-wave inductive current sensor Download PDFInfo
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Abstract
The invention discloses a SenseFET type full-wave inductive current sensor, and relates to the electronic technology. It comprises a power stage for modulating the inductor current I L (ii) a A valley current sensor for collecting valley inductive current signal I L,valley And outputs drain voltage VX valley (ii) a A peak current sensor for collecting and outputting a sampling signal I Lsen ＝I L /A L (ii) a A peak enable signal generator for generating an enable signal in the peak current sensor; a valley enable signal generator for generating an enable signal in the valley current sensor. The invention ensures the output of the current sensor during the dead zone period by setting the dead zone sampling holding capacitor, and can reduce the voltage of the operational amplifierThe slew rate requirement and the bandwidth requirement of a negative feedback closed loop are met, the limitation of dead zone sampling holding capacitance on the bandwidth of the negative feedback closed loop is avoided, and I is improved Lsen The sampling accuracy of (2).
Description
Technical Field
The present invention relates to electronics, and more particularly, it relates to a SenseFET type full wave inductor current sensor.
Background
Inductive current sensor for real-time acquisition of inductive current I L Information, and output I of equal proportion L /A L To a control system, A L Referred to as the sensing ratio and is a constant. The inductive current sensor is commonly used in a control system of a current mode switch inductor DC-DC, plays a role in modulating and limiting the amplitude of inductive current, and is used as a relatively independent sub-module of the control system, and is often researched separately. The SenseFET type current sensor has the advantages of high integration level, low loss, controllable precision and the like, and has the research heat.
As shown in fig. 1, in the DC-DC structure, the input stage power transistors MP and MN are alternately turned on without overlapping with each other, and the inductor current necessarily flows through MP and MN, and the SenseFET type current sensor utilizes this feature to obtain the sense inductor current by sampling the drain currents of the power transistors MP and MN, respectively [1] . Suppose that drain currents flowing through power transistors MP and MN are I respectively L,peak And I L,valley Respectively characterize I L A rising phase and a falling phase of (I) L ＝I L,peak +I L,valley Through two negative feedback closed loops G peak And G valley Respectively make power tube MP and field effect tube MP m1 Power tube MN and field effect tube MN m1 The two sets of current mirrors are at the same bias state. At this time, if the size of the current mirror satisfies MP, MP m1 ＝MN:MN m1 ＝A L 1, then MP m1 And MN m1 Respectively is I Lsen,peak ＝I L,peak /A L And I Lsen,valley ＝I L,valley /A L Is shown by Lsen,peak And I Lsen,valley The sensing current I can be obtained by direct addition Lsen ＝I L /A L 。
There are two problems with the SenseFET type current sensor of the conventional structure:
1. the power tubes MP and MN are alternately conducted and are in a negative feedback closed loop G peak During settling, negative feedback closed loop G valley Operational amplifier (OPA) in (1) valley In saturation or cut-off state, the operational amplifier OPA is started every time the power tube MN is switched on valley A start-up procedure is required which takes a long time and has a large error during it. The same problem occurs at the beginning of the conduction of the power transistor MP. This problem amplifies OPA to fortune peak And OPA valley Slew rate and negative feedback closed loop G peak And G valley The bandwidth of (a) puts high demands.
2. The MP and MN of the power tube are alternately conducted, and a sampling signal I in the dead zone period Lsen,peak And I Lsen,valley Are all 0, but I L Not 0, the sensing current has no output and introduces a large error.
For the above problems, publications [2 to 8 ]]The turning process of the SenseFET type current sensor during the alternate conduction period of the power tube MP and the MN is optimized by adopting a mode of sharing an output stage, and the OPA of the operational amplifier is reduced by keeping the output stage in a linear region peak And OPA valley Performance requirements for slew rate. Among them, publications [2 to 6]Common operational amplifier structure (i.e., operational amplifier OPA) peak And OPA valley The same operational amplifier) is adopted, and a dead zone sampling holding capacitor is added in an operational amplifier output stage, so that the problem that sensing current is not output in the dead zone period is solved, and the requirement on the operational amplifier slew rate is further reduced. But the dead-zone sample-and-hold capacitor appears in the negative feedback closed loop G peak And G valley In the middle, the bandwidth increase of the closed loop is limited, and the closed loop G is not easy to be negatively fed back peak And G valley And the negative feedback closed loop G is enabled due to the sharing of operational amplifiers valley Is subject to the negative feedback closed loop G peak The inductive current I in the descending stage is reduced L,valley The sampling accuracy of (2). And publication [7,8 ]]The structure that the output stage is shared but the operational amplifier is not shared is adopted, the problem that sensing current is not output during the dead zone is ignored, and the switching-on from the power tube MN to the power tube MP is optimizedDuring the turning process of the current sensor, I L,valley The sampling accuracy of (2) is very low.
The following are the 8 publications referred to above.
[1]Man T Y,Mok P K T,Chan M.Design of Fast-Response On-Chip Current Sensor for Current-Mode Controlled Buck Converters with MHz Switching Frequency[C].2007IEEE International Conference on Electron Devices and Solid-State Circuits,2007:389-392.
[2]Zhu L,Chen B,Zheng Y,et al.AFast-Response Buck-Boost DC-DC Converter with Constructed Full-Wave Current Sensor[C].2016International Symposium on Integrated Circuits,2016.
[3]Li B,Yang J,Wu Z,et al.AFast-Response Full-Wave Current-Sensing Circuit for DC-DC Converter Operating in 10MHz Switching Frequency[C].2017International Conference on Electron Devices and Solid-State Circuits,2017.
[4]Zhou Y,Zheng Y,Leung K N.Fast-Response Full-Wave Inductor Current Sensor for 10MHz Buck Converter[J].Electronics Letters,2018,54(6):379-380.
[5]Zhou Y,Lin X,Yang J,et al.Adaptive-Biased Sense-FET-Based Inductor-Current Sensor for 10-MHz Buck Converter[J].International Journal of Circuit Theory and Applications,2020,48(6):953-964.
[6]Zhou Y,Cheng Q,Li J,et al.Full-Wave Sense-FET-Based Inductor-Current Sensor With Wide Dynamic Range for Buck Converters[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2022,69(4):2041-2045.
[7]Jung-Woo H,Bai-Sun K,Jung-Hoon C,et al.AFast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator[C].ESSCIRC2014-40th European Solid State Circuits Conference,2014:155-8.
[8]Zhou M,Sun Z,Low Q W,et al.Multiloop Control for Fast Transient DC-DC Converter[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2019,27(1):219-228.
Disclosure of Invention
The invention aims to solve the technical problem of providing a SenseFET type full-wave inductance current sensor aiming at the defects of the prior art.
The technical scheme of the invention is as follows: a SenseFET type full-wave inductor current sensor includes,
the power stage consists of a first power tube MP and a second power tube MN which are connected by drain electrodes, and the drain electrode connecting end of the first power tube MP and the second power tube MN outputs an inductance voltage signal VX;
valley current sensor including a first operational amplifier (OPA) valley Fourteenth field effect transistor M 14 A first field effect transistor M 1 A second field effect transistor M 2 And a first control unit; the second field effect transistor M 2 Is connected with the input end of the power stage, and the second field effect transistor M 2 The grid of the second field effect transistor M is connected with the signal ground 2 Drain output drain voltage Vx valley And the second field effect transistor M 2 Drain electrode of (1) and fourteenth field effect transistor M 14 Is connected to the source of (a); the fourteenth field effect transistor M 14 Gate of and first operational amplifier OPA valley Is connected with the output end of the fourteenth field effect transistor M 14 The drain electrode of the first operational amplifier OPA is connected with the first control unit valley Are connected to form a first negative feedback closed loop G valley (ii) a The first control unit also amplifies the OPA with the first fortune valley For controlling the first negative feedback closed loop G valley Is open-loop or closed-loop; the first field effect transistor M 1 The drain electrode of the first field effect transistor M is inputted with an inductive voltage signal VX 1 Is input into the first control unit for controlling the first negative feedback closed loop G valley For the enable signal of the closed loop, the first field effect transistor M 1 The source electrode of the transistor is connected with the control unit;
peak current sensor comprising a second OPA peak And a sixth field effect transistor M 6 And a third field effect transistor M 3 The mirror image tube pair and the second control unit; the output end of the second control unit and the second operational amplifier OPA peak Is connected with the negative phase input terminal and is used for inputting the drain voltage VX in a time-sharing way valley An inductor voltage signal VX; and the second operational amplifier OPA peak The negative phase input end of the capacitor is connected with a dead zone sampling holding capacitor C s (ii) a The second operational amplifier OPA peak And the output end of the sixth field effect transistor M 6 Is connected with the grid of the sixth field effect transistor M 6 The drain electrode of the first operational amplifier is connected with the OPA through the second control unit peak Are connected to form a second negative feedback closed loop G peak (ii) a The sixth field effect transistor M 6 And the third field effect transistor M 3 Of said third field effect transistor M 3 The grid of the first field effect transistor M is connected with the signal ground 3 Is connected with the input end of the power stage; the sixth field effect transistor M 6 The source electrode of the transistor pair is connected with the input end of the mirror image tube pair, and the output end of the mirror image tube pair outputs a sampling signal I Lsen 。
The first power tube MP and the second field effect tube M 2 Mirror ratio of L 1, the first power tube MP and the third field effect tube M 3 Mirror ratio of L 1, the second power tube MN and the first field effect tube M 1 Mirror ratio of L :1。
The first power tube MP and the second field effect tube M 2 And a third field effect transistor M 3 Are all PMOS; the second power tube MN and the first field effect tube M 1 Are all NMOS.
When the first power tube MP is switched on and the second power tube MN is switched off, the inductive current I L Flowing through the first power tube MP, the inductive current at this stage is the peak value I L ＝I L,peak . The first control unit controls the OPA of the first operational amplifier valley Are all grounded, so that the first operational amplifier OPA valley Operating in the linear region, a first closed negative feedback loop G valley Is open loop. The second control unit controls a second operational amplifier (OPA) peak The inverting input terminal of the first power transistor MP inputs the drain voltage of the first power transistor MP, i.e., the inductor voltage signal VX. Due to a second negative feedback closed loop G peak Is closed loop, so that the thirdField effect transistor M 3 The third field effect transistor M is in the same bias state as the first power transistor MP 3 Has a leakage current of I L,peak /A L And is equal to the leakage current of the FET in the mirror tube pair, i.e. I Lsen ＝I L,peak /A L 。
When the first power tube MP is turned off and the second power tube MN is turned on, the inductive current I L Flowing through the second power transistor MN, the inductive current at this stage is at the valley value I L ＝I L,valley . The first control unit controls a first negative feedback closed loop G valley In a closed loop state to make the first field effect transistor M 1 And a second field effect transistor M in the same bias state as the second power transistor MN 2 Drain current of and the first field effect transistor M 1 Is equal to the drain current of L,valley /A L . The second control unit controls a second operational amplifier (OPA) peak Is inputted with the drain voltage Vx valley Second operational amplifier OPA peak And a sixth field effect transistor M 6 Second negative feedback closed loop G peak Make the second field effect transistor M 2 And a third field effect transistor M 3 In the same bias state, the third field effect transistor M 3 Has a leakage current of I L,valley /A L I.e. I Lsen ＝I L,valley /A L 。
The first control unit comprises an eighth field effect transistor M 8 And a ninth field effect transistor M 9 The tenth field effect transistor M 10 And an eleventh field effect transistor M 11 (ii) a The ninth field effect transistor M 9 Gate and first field effect transistor M 1 Are all inputted with the second enabling signal PS n The ninth field effect transistor M 9 Source electrode of and fourteenth field effect transistor M 14 Is connected with the drain of the ninth field effect transistor M 9 And the first operational amplifier OPA valley Is connected with the positive input terminal of the first operational amplifier valley Through an eleventh field effect transistor M 11 Grounded, and the eleventh field effect transistor M 11 The grid of the power stage is connected with the input end of the power stage; the first fieldEffect tube M 1 Source electrode of and the eighth field effect transistor M 8 Of said eighth field effect transistor M 8 The source of the first transistor is connected with a signal ground; the OPA is put to the first fortune valley The positive phase input end of the first transistor M and the tenth field effect transistor M 10 The drain of the tenth field effect transistor M 10 The source of the first transistor is connected with a signal ground; and the eighth field effect transistor M 8 And a tenth field effect transistor M 10 Is connected to and inputs the signal state and the second enable signal PS n The opposite fifth enable signal! PS (polystyrene) with high sensitivity n 。
The second control unit comprises a fourth field effect transistor M 4 The fifth field effect transistor M 5 And a seventh field effect transistor M 7 (ii) a The fourth field effect transistor M 4 The grid of the first field effect transistor is inputted with a third enabling signal LVX, and the fourth field effect transistor M 4 The source inputs an inductive voltage signal Vx; the fifth field effect transistor M 5 Gate of the first transistor inputs a fourth enable signal LVX valley Said fifth field effect transistor M 5 Source input drain voltage Vx valley (ii) a The fourth field effect transistor M 4 The fifth field effect transistor M 5 And the drain electrodes of the first and second operational amplifiers OPA peak The inverting input end of the first switch is connected; the seventh field effect transistor M 7 The grid of the first field effect transistor M is connected with the signal ground 7 And the second operational amplifier OPA peak Is connected with the positive input end of the seventh field effect transistor M 7 Source electrode of and the sixth field effect transistor M 6 Is connected to the drain of (c).
The SenseFET type full wave inductor current sensor further comprises,
a valley enable signal generator for generating a valley enable signal according to the input seventh enable signal! BPS n Outputs a second enable signal PS n The fifth enable signal! PS (polystyrene) with high sensitivity n And a fourth enable signal LVX valley ；
A peak enable signal generator for generating a sixth enable signal according to the input! BPS p Outputs a first enable signal PS p And a third enable signal LVX.
The sixth enable signal! BPS p Rising edge of and third enable signalThere is a first delay t between falling edges of LVX senlop And the falling edge of the third enable signal LVX lags behind the sixth enable signal! BPS p The rising edge of (d);
the second enable signal PS n And the fourth enable signal LVX valley Has a second delay t between falling edges senlov And the fourth enable signal LVX valley Lags behind the second enable signal PS n The rising edge of (c).
The peak enable signal generator comprises a fifteenth field effect transistor M 15 Sixteenth field effect transistor M 16 Seventeenth field effect transistor M 17 Eighteenth field effect transistor M 18 A first inverter INV 1 A first NAND gate NAND 1 A first resistor R senlop A first capacitor C senlop (ii) a The fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 The gates of the first and second transistors are all inputted with a sixth enable signal! BPS p The fifteenth field effect transistor M 15 Source input voltage source signal V source The fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 Is connected to and serves as a first enable signal PS p A signal output terminal of (a); the seventeenth field effect transistor M 17 The source of the first transistor is connected with a power ground PGND; the sixteenth field effect transistor M 16 Eighteenth field effect transistor M 18 The gates of the first and second transistors are all connected with an enable signal! BPS p The sixteenth field effect transistor M 16 Source electrode of the transistor is connected with an input voltage source signal V source The first resistor R senlop One terminal of (1), a first capacitor C senlop One end of (1), sixteenth field effect transistor M 16 And the drain electrodes of the first and second inverters INV 1 Is connected to the input terminal of the first resistor R senlop The other end of the transistor is connected with an eighteenth field effect transistor M 18 Is connected with the drain electrode of the eighteenth field effect transistor M 18 Source electrode, first capacitor C senlop The other ends of the two-way switch are connected with a signal ground; the first inverter INV 1 And the first NAND gate NAND 1 Is connected to the first NAND gate NAND 1 Input a sixth enable signal! BPS p The first NAND gate NAND 1 Outputs the third enable signal LVX.
The valley enable signal generator comprises a second capacitor C senlov Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 A second inverter INV 2 A third inverter INV 3 And a fourth inverter INV 4 The fifth inverter INV 5 And a second NAND gate NAND 2 (ii) a The nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 All input a seventh enable signal! BPS n The nineteenth field effect transistor M 19 Source input voltage source signal V source The nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Is connected as a second enable signal PS n And the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Respectively connected with the third inverter INV 3 And a fifth inverter INV 5 Is connected with the input end of the twentieth field effect transistor M 20 The source of the first transistor is connected with a power ground PGND; the fifth inverter INV 5 As a fifth enable signal! PS (polystyrene) with high sensitivity n A signal output terminal of (a); the third inverter INV 3 And the fourth inverter INV 4 Is connected to the input terminal of the second capacitor C senlov And a third inverter INV 3 Is connected to the output terminal of the second capacitor C senlov The other terminal of (a) is connected to signal ground; the fourth inverter INV 4 And the output end of the first NAND gate NAND 2 Is connected to the second NAND gate NAND 2 And the other input end of the first inverter INV 2 Is connected with the output end of the second inverter INV 2 Input terminal of the first power supply voltage! BPS n Said second NAND gate NAND 2 As a fourth enable signal LVX valley A signal output terminal of (2).
Advantageous effects
The invention has the advantages that:
1. compared with a SenseFET type current sensor with a traditional structure, the invention has the characteristics of common output stage and dead zone sampling holding capacitance, and the operational amplifier OPA peak And OPA valley All are kept in a linear region, and the dead-zone sampling holding capacitor ensures the output of the current sensor during the dead zone, thereby reducing the OPA peak And OPA valley Slew rate requirement and negative feedback closed loop G peak And G valley The bandwidth requirement of (c).
2. Compared with a SenseFET type current sensor sharing an output stage and an operational amplifier structure, the negative feedback closed loop G of the invention peak Keep stable and reduce the negative feedback closed loop G peak The bandwidth requirement of (c). Negative feedback closed loop G peak And G valley Relatively independent, avoids negative feedback closed loop G peak Bandwidth pair negative feedback closed loop G valley The limitation of the bandwidth. Dead zone sampling holding capacitor placed in negative feedback closed loop G peak And G valley Besides, the dead zone sampling holding capacitance pair negative feedback closed loop G is avoided peak And G valley The limitation of the bandwidth.
3. Compared with a SenseFET type current sensor sharing an output stage but not sharing an operational amplifier structure, the operational amplifier OPA of the invention valley Is kept in a linear region and is provided with a dead-zone sampling holding capacitor, so that the turning process of the current sensor during the period from the cut-off of the power tube MP to the conduction of the power tube MN is optimized, and I is improved L,valley The sampling accuracy of (2).
Drawings
FIG. 1 is a schematic diagram of a SenseFET type current sensing circuit of conventional construction;
FIG. 2 is a schematic diagram of a SenseFET type current sensor circuit according to the present invention;
FIG. 3 is a schematic diagram of a timing waveform of an enable signal in the SenseFET type current sensor according to the present invention;
FIG. 4 is a schematic diagram of a peak enable signal generator circuit according to the present invention;
fig. 5 is a schematic circuit diagram of the valley enable signal generator according to the present invention.
Detailed Description
The invention is further described below with reference to examples, but not to be construed as in any way limiting the invention, which is intended to be covered by the claims of the invention, with only a limited number of modifications being possible by anyone within the scope of the claims.
Referring to fig. 2, the SenseFET type full-wave inductor current sensor of the present invention includes a power stage, a valley current sensor, a peak current sensor, a valley enable signal generator, and a peak enable signal generator.
Wherein the power stage is used for modulating the inductive current I L . The power stage is composed of a first power tube MP and a second power tube MN which are connected by drain electrodes. The first power tube MP is a PMOS tube, and the second power tube MN is an NMOS tube. The grid of the first power tube MP inputs the first enable signal PS p The state of the gate input signal of the second power transistor MN and the first enable signal PS p The same second enable signal PS n And the substrate of the first power tube MP is connected with the source electrode. The source of the first power transistor MP is used as the input terminal of the power stage, which inputs the voltage source signal V source The source of the second power transistor MN is connected to the power ground PGND, and the substrate of the second power transistor MN is connected to the signal ground. The drain electrodes of the first power tube MP and the second power tube MN are connected to output an inductive current signal I L The output inductor voltage signal is denoted as VX. The first power tube MP and the second power tube MN are alternately conducted, and conduction states of each other are not overlapped. That is, there is a dead zone between the first power transistor MP and the second power transistor MN, and the first enable signal PS p And a second enable signal PS n There is also a dead zone in between.
A valley current sensor for collecting valley inductive current signal I L,valley And outputs the second field effect transistor M 2 Drain voltage Vx of valley . It comprises a first operational amplifier (OPA) valley Fourteenth field effect transistor M 14 A first field effect transistor M 1 A second field effect transistor M 2 And a first control unit. The first control unit comprises an eighth field effect transistor M 8 And a ninth field effect transistor M 9 The tenth field effect transistor M 10 And an eleventh field effect transistor M 11 . First field effect transistor M 1 Eighth field EffectPipe M 8 And a ninth field effect transistor M 9 The tenth field effect transistor M 10 And an eleventh field effect transistor M 11 Are NMOS transistors, the second field effect transistor M 2 Fourteenth field effect transistor M 14 Is a PMOS tube. The specific circuit connection structure of the valley current sensor is as follows.
Second field effect transistor M 2 Source input voltage source signal V source Its gate is connected to signal ground and its drain is used as output drain voltage VX valley And the fourteenth field effect transistor M 14 Is connected to the source of (a). First operational amplifier OPA valley And the eleventh field effect transistor M 11 Is connected to the drain of the eleventh field effect transistor M 11 Is grounded, an eleventh field effect transistor M 11 Gate input voltage source signal V source . First operational amplifier OPA valley The positive phase input end of the first transistor is respectively connected with the ninth field effect transistor M 9 The tenth field effect transistor M 10 Is connected to the drain of the tenth field effect transistor M 10 Source of (3) is connected with signal ground, tenth field effect transistor M 10 And an eighth field effect transistor M 8 Is connected to and inputs a fifth enable signal! PS (polystyrene) with high sensitivity n . Ninth field effect transistor M 9 The state of the gate input signal and the fifth enable signal! PS (polystyrene) with high sensitivity n The opposite second enable signal PS n Ninth field effect transistor M 9 Respectively with the first field effect transistor M 1 Source electrode of (1), fourteenth field effect transistor M 14 And the eighth field effect transistor M 8 Is connected to the drain of the eighth field effect transistor M 8 The source of (2) is connected to signal ground. First field effect transistor M 1 Gate of the first transistor is inputted with a second enable signal PS n First field effect transistor M 1 The drain of (a) is input with an inductor voltage signal VX. Fourteenth field effect transistor M 14 Gate of and first operational amplifier OPA valley Is connected with the output end of the power supply. Fourteenth field effect transistor M 14 And a first operational amplifier (OPA) valley Form a first negative feedback closed loop G valley 。
The peak current sensor is used for collecting and outputting a sampling signal I Lsen . It includes a second operational amplifier OPA peak And a sixth field effect transistor M 6 And a third field effect transistor M 3 Mirror image tube pair, second control unit and dead zone sampling holding capacitor C s . The mirror image tube pair consists of a twelfth field effect tube M 12 And a thirteenth field effect transistor M 13 And (4) forming. The second control unit comprises a fourth field effect transistor M 4 The fifth field effect transistor M 5 And a seventh field effect transistor M 7 . Sixth field effect transistor M 6 Twelfth field effect transistor M 12 And a thirteenth field effect transistor M 13 Are NMOS tubes, and the third field effect tube M 3 And a fourth field effect transistor M 4 The fifth field effect transistor M 5 And a seventh field effect transistor M 7 Are all PMOS tubes. The specific circuit connection structure of the peak current sensor is as follows.
Third field effect transistor M 3 The gate of which is connected to the signal ground and the source of which is connected to the voltage source signal V source The drain electrode of which is respectively connected with the seventh field effect transistor M 7 Source electrode of, sixth field effect transistor M 6 Is connected to the drain of (1). Seventh field effect transistor M 7 The gate of which is connected to signal ground, the drain of which is connected to the second operational amplifier OPA peak Is connected with the non-inverting input terminal of the switch. Fifth field effect transistor M 5 Source electrode of and the second field effect transistor M 2 Is connected to the drain of the transistor, receives the drain voltage Vx valley . Fifth field effect transistor M 5 Gate of the first transistor inputs a fourth enable signal LVX valley . Fourth field effect transistor M 4 The gate of (a) inputs a third enable signal LVX, and the source of (b) inputs an inductor voltage signal VX. Fourth field effect transistor M 4 The fifth field effect transistor M 5 And the drain electrodes of the first and second operational amplifiers OPA peak Is connected to the inverting input terminal of the second operational amplifier, and the second operational amplifier OPA peak And a dead-zone sample-and-hold capacitor C s Is connected with a dead zone sample-and-hold capacitor C s And the other end of the same is grounded.
Here, the dead zone sample-and-hold capacitor C s Ensuring the output of the current sensor during the dead zone and reducing the OPA of the second operational amplifier peak And a first operational amplifier OPA valley Slew rate requirement and negative feedback closed loop G peak And G valley The bandwidth requirement of (c). In addition, dead zone sample-and-hold capacitor C s Placed in a negative feedback closed loop G peak And G valley In addition, dead zone sample-and-hold capacitance C is avoided s For negative feedback closed loop G peak And G valley The limitation of the bandwidth.
Second operational amplifier OPA peak And the output end of the sixth field effect transistor M 6 Is connected to the gate of (a). Sixth field effect transistor M 6 And a second operational amplifier (OPA) peak Form a second negative feedback closed loop G peak . Sixth field effect transistor M 6 Source electrode of and the twelfth field effect transistor M 12 Is connected with the grid electrode, a thirteenth field effect transistor M 13 Grid and twelfth field effect transistor M 12 Is connected to the gate of a thirteenth field effect transistor M 13 As the sampling signal I Lsen The sampling output terminal. Thirteenth field effect transistor M 13 And the twelfth field effect transistor M 12 The source of (2) is connected to signal ground.
In this embodiment, the first power transistor MP and the second field effect transistor M 2 Mirror ratio of L 1, a second power tube MN and a first field effect tube M 1 Mirror image ratio of A L 1, a first power tube MP and a third field effect tube M 3 Mirror ratio of L 1, a twelfth field effect transistor M 12 And a thirteenth field effect transistor M 13 The mirror ratio is 1.
In the enabling signal PS p ＝PS n When =0, enable signal! PS (polystyrene) with high sensitivity n ＝！BPS p ＝！BPS n ＝LVX valley =1,lvx =0. At this time, the first power tube MP is turned on, the second power tube MN is turned off, and the inductive current I is L Flows through the first power transistor MP. Eighth field-effect transistor M 8 The tenth field effect transistor M 10 And an eleventh field effect transistor M 11 Are all in a conducting state, and the first operational amplifier (OPA) valley All input terminals of which are grounded and which operate in a linear region, a first negative feedback closed loop G valley Is open loop. Inductive current I L Flowing through the first power tube MP, the inductive current at this stage is the peak value I L ＝I L,peak Second operational amplifier OPA peak The inverting input terminal of the second operational amplifier inputs the inductor voltage signal VX and the second operational amplifier OPA peak And a sixth field effect transistor M 6 Second negative feedback closed loop G peak Let the third field effect transistor M 3 The third field effect transistor M is in the same bias state with the first power transistor MP 3 Has a leakage current of I L,peak /A L And is connected with the twelfth field effect transistor M 12 And a thirteenth field effect transistor M 13 Equal leakage current, i.e. I Lsen ＝I Lsen,peak ＝I L,peak /A L 。
In the enabling signal PS p ＝PS n When =1, enable signal! PS (polystyrene) with high sensitivity n ＝！BPS p ＝！BPS n ＝LVX valley =0,lvx =1. At this time, the first power transistor MP is turned off, and the second power transistor MN is turned on. Eighth field-effect transistor M 8 And a tenth field effect transistor M 10 In a cut-off state, the ninth field effect transistor M 9 In the on state, the inductor current I L Flowing through the second power transistor MN, the inductive current at this stage is at the valley value I L ＝I L,valley First operational amplifier OPA valley And a fourteenth field effect transistor M 14 Formed first negative feedback closed loop G valley Make the first field effect transistor M 1 The first field effect transistor M is in the same bias state with the first power transistor MN 1 Has a leakage current of I L,valley /A L And is connected with the second field effect transistor M 2 The leakage currents are equal. Second operational amplifier OPA peak Is connected to the drain voltage Vx valley Second operational amplifier OPA peak And a sixth field effect transistor M 6 Second negative feedback closed loop G peak Let the third field effect transistor M 3 And a second field effect transistor M 2 In the same bias state, the third field effect transistor M 3 Has a leakage current of I L,valley /A L I.e. I Lsen ＝I Lsen,valley ＝I L,valley /A L 。
According to the invention, the operational amplifier in the peak current sensor and the valley current sensor is kept in the linear region, and the dead zone sampling holding capacitor is combined to ensure the output of the current sensor in the dead zone period, so that the slew rate requirements of the two operational amplifiers can be reduced. By sampling the signal I Lsen ＝I L /A L Stable output at peakThe output end of the value current sensor, the negative feedback closed loop where the peak current sensor is located is always stable, and the dead zone sampling holding capacitor is arranged outside the negative feedback closed loops where the peak current sensor and the valley current sensor are respectively located, so that the limitation of the dead zone sampling holding capacitor on the bandwidth of the two closed loops is avoided, and the bandwidth requirements of the two closed loops can be reduced by combining the two closed loops. Dead zone output of the current sensor, slew rate of operational amplifier and bandwidth optimization of closed loop can improve sampling signal I Lsen ＝I L /A L The accuracy of (2).
Referring to fig. 3-5, the peak enable signal generator is used to generate an enable signal in the peak current sensor, which is provided by the fifteenth fet M 15 Sixteenth field effect transistor M 16 Seventeenth field effect transistor M 17 Eighteenth field effect transistor M 18 First inverter INV 1 A first NAND gate NAND 1 A first resistor R senlop A first capacitor C senlop And (4) forming. It inputs the sixth enable signal! BPS p Outputs a first enable signal PS p And a third enable signal LVX. As shown in fig. 3, a sixth enable signal! BPS p Is a signal in the driving chain of the first power tube MP which is in the first enabling signal PS in time sequence p Before, the phase and the first enable signal PS p In contrast, edges have only a delay difference. The third enable signal LVX is used to control the dead-zone sample-and-hold capacitor C s The sampling and holding time of the output node of the inductive voltage signal VX needs to be preset high when the first power tube MP is turned off, and the fourth field effect tube M is turned off 4 Maintaining the inductor voltage signal Vx; and the fourth field effect transistor M needs to be conducted after the first power transistor MP is stably conducted and is low 4 The inductor voltage signal VX is sampled.
In order to make the third enable signal LVX low after the first power transistor MP is turned on stably, the sixth enable signal! BPS p A first delay t is set between the rising edge of the third enable signal LVX and the falling edge of the third enable signal LVX senlop And the falling edge of the third enable signal LVX lags behind the sixth enable signal! BPS p Rising edge of, first delay t senlop By a resistance R senlop And a capacitor C senlop And (4) generating. By a first delayTime t senlop The third enable signal LVX is set to low after the first power transistor MP is stably turned on.
The specific circuit structure of the peak enable signal generator in this embodiment is that the fifteenth fet M 15 Seventeenth field effect transistor M 17 All input the sixth enable signal! BPS p Fifteenth field effect transistor M 15 Source input voltage source signal V source Fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 Is connected to and serves as a first enable signal PS p A signal output terminal of (a); seventeenth field effect transistor M 17 The source of the first transistor is connected with a power ground PGND; sixteenth field effect transistor M 16 Eighteenth field effect transistor M 18 The gates of the first and second transistors are all connected with an enable signal! BPS p Sixteenth field effect transistor M 16 Source electrode of the transistor is connected with an input voltage source signal V source First resistance R senlop One terminal of (1), a first capacitor C senlop One end of (1), sixteenth field effect transistor M 16 And the drain electrodes of the first and second inverters INV 1 Is connected to the first resistor R senlop The other end of the transistor is connected with an eighteenth field effect transistor M 18 Is connected to the drain of the eighteenth field effect transistor M 18 Source electrode, first capacitor C senlop The other ends of the two-way switch are connected with a signal ground; first inverter INV 1 And the first NAND gate NAND 1 Is connected with the first NAND gate 1 Input a sixth enable signal! BPS p First NAND gate NAND 1 Outputs the third enable signal LVX.
The valley enable signal generator is used for generating an enable signal in the valley current sensor and is composed of a second capacitor C senlov Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 A second inverter INV 2 A third inverter INV 3 And a fourth inverter INV 4 The fifth inverter INV 5 And a second NAND gate NAND 2 And (4) forming. It inputs the seventh enable signal! BPS n Outputs a second enable signal PS n The fifth enable signal! PS (polystyrene) with high sensitivity n And a fourth enable signal LVX valley . As shown in FIG. 3, a seventh enable signal! BPS n Is a signal in the drive chain of the second power tube MN, which is in the second enabling signal PS in time sequence n Before, the phase and the second enable signal PS n In contrast, edges have only a delay difference. The first enable signal PS p And a second enable signal PS n There is a dead zone in between, i.e., the sixth enable signal! BPS p And a seventh enable signal! BPS n With dead zones in between. A fifth enable signal! PS (polystyrene) with high sensitivity n And a second enable signal PS n Only the phases are opposite and the edge delay is negligible. Fourth enable signal LVX valley For controlling the dead-zone sample-and-hold capacitor C s To drain voltage Vx valley The sampling and holding time of the output node needs to be preset when the second power tube MN is turned off and the fifth field effect tube M is turned off 5 Maintaining the drain voltage VX valley (ii) a And a valley current sensor is required to stably acquire a valley inductive current signal I L,valley And outputs drain voltage VX valley Rear low, conducting fifth field effect transistor M 5 Sampling the drain voltage VX valley 。
The second enable signal PS n And the fourth enable signal LVX valley Has a second delay t between falling edges senlov And the fourth enable signal LVX valley Lags behind the second enable signal PS n The rising edge of (c). Second delay time t senlov From a second capacitor C senlov Generating, a second delay t senlov Make the fourth enable signal LVX valley Stably collecting valley inductive current signal I at valley current sensor L,valley And outputs drain voltage VX valley The rear position is low.
The specific circuit structure of the valley enable signal generator in this embodiment is that the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 All input a seventh enable signal! BPS n Nineteenth field effect transistor M 19 Source input voltage source signal V source Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Is connected as a second enable signal PS n And a nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Drain electrode connection ends of the first and second inverters INV 3 And a fifth inverter INV 5 Is connected to the twentieth field effect transistor M 20 Is connected to power ground PGND. Fifth inverter INV 5 As a fifth enable signal! PS (polystyrene) with high sensitivity n A signal output terminal of (a); third inverter INV 3 And the fourth inverter INV 4 Is connected to the input terminal of a second capacitor C senlov And a third inverter INV 3 Is connected to the output terminal of a second capacitor C senlov The other terminal of (a) is connected to signal ground; fourth inverter INV 4 And the output end of the second NAND gate NAND 2 Is connected with the first NAND gate 2 And the other input end of the first inverter INV 2 Is connected to the output end of the second inverter INV 2 Input terminal of the first power supply voltage | a seventh enable signal is input! BPS n The second NAND gate NAND 2 As a fourth enable signal LVX valley A signal output terminal of (2).
The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various changes and modifications without departing from the structure of the invention, which will not affect the effect of the invention and the practicability of the patent.
Claims (8)
1. A SenseFET type full-wave inductor current sensor includes,
the power stage consists of a first power tube MP and a second power tube MN which are connected by drain electrodes, and the drain electrode connecting end of the first power tube MP and the second power tube MN outputs an inductance voltage signal VX;
it is characterized by also comprising the following steps of,
valley current sensor including a first operational amplifier (OPA) valley Fourteenth field effect transistor M 14 A first field effect transistor M 1 A second field effect transistor M 2 And a first control unit; the second field effect transistor M 2 Is connected to the input of the power stage, saidSecond field effect transistor M 2 The grid of the second field effect transistor M is connected with the signal ground 2 Drain output drain voltage Vx valley And the second field effect transistor M 2 And the fourteenth field effect transistor M 14 Is connected to the source of (a); the fourteenth field effect transistor M 14 Gate of and first operational amplifier OPA valley Is connected with the output end of the fourteenth field effect transistor M 14 The drain electrode of the first operational amplifier OPA is connected with the first control unit valley Are connected to form a first negative feedback closed loop G valley (ii) a The first control unit also amplifies the OPA with the first fortune valley For controlling the first negative feedback closed loop G valley Is open-loop or closed-loop; the first field effect transistor M 1 The drain electrode of the first field effect transistor M inputs an inductive voltage signal VX 1 Is input into the first control unit for controlling the first negative feedback closed loop G valley For the closed loop enable signal, the first field effect transistor M 1 The source electrode of the transistor is connected with the control unit;
peak current sensor comprising a second operational amplifier (OPA) peak And a sixth field effect transistor M 6 And a third field effect transistor M 3 The mirror image tube pair and the second control unit; the output end of the second control unit and the second operational amplifier OPA peak Is connected with the negative phase input terminal and is used for inputting the drain voltage VX in a time-sharing way valley An inductor voltage signal VX; and the second operational amplifier OPA peak The negative phase input end of the capacitor is connected with a dead zone sampling holding capacitor C s (ii) a The second operational amplifier OPA peak And the output end of the sixth field effect transistor M 6 Is connected with the grid of the sixth field effect transistor M 6 The drain electrode of the first operational amplifier (OPA) is connected with the second operational amplifier (OPA) through a second control unit peak Are connected to form a second negative feedback closed loop G peak (ii) a The sixth field effect transistor M 6 And the third field effect transistor M 3 Of said third field effect transistor M 3 The grid of the first field effect transistor M is connected with the signal ground 3 Is connected with the input end of the power stage; the sixth field effect transistor M 6 Source electrode and mirror image tubeThe input ends of the pairs are connected, and the output end of the image tube pair outputs a sampling signal I Lsen 。
2. A SenseFET-type full-wave inductor current sensor according to claim 1, wherein said first power transistor MP and said second field effect transistor M 2 Mirror ratio of L 1, the first power tube MP and the third field effect tube M 3 Mirror ratio of L 1, the second power tube MN and the first field effect tube M 1 Mirror ratio of L :1。
3. A SenseFET-type full-wave inductor current sensor according to claim 1 or 2, characterized in that the first power transistor MP, the second field effect transistor M 2 And a third field effect transistor M 3 Are all PMOS; the second power tube MN and the first field effect tube M 1 Are all NMOS.
4. A SenseFET-type full-wave inductor current sensor according to claim 1, characterized in that said first control unit comprises an eighth field-effect transistor M 8 And a ninth field effect transistor M 9 The tenth field effect transistor M 10 And an eleventh field effect transistor M 11 (ii) a The ninth field effect transistor M 9 Gate and first field effect transistor M 1 Are all inputted with the second enabling signal PS n The ninth field effect transistor M 9 Source electrode of and fourteenth field effect transistor M 14 Of said ninth field effect transistor M 9 And the first operational amplifier OPA valley Is connected with the positive input terminal of the first operational amplifier valley Through an eleventh field effect transistor M 11 Grounded, and the eleventh field effect transistor M 11 The grid of the power stage is connected with the input end of the power stage; the first field effect transistor M 1 Source electrode of and the eighth field effect transistor M 8 Of said eighth field effect transistor M 8 The source of the first transistor is connected with a signal ground; the OPA is put to first fortune valley The positive phase input end of the first transistor M and the tenth field effect transistor M 10 The tenth field effect transistor M 10 The source of the first transistor is connected with a signal ground; and the eighth field effect transistor M 8 And a tenth field effect transistor M 10 Is connected to and inputs the signal state and the second enable signal PS n The opposite fifth enable signal! PS (polystyrene) with high sensitivity n 。
5. A SenseFET-type full-wave inductor current sensor as claimed in claim 4, wherein said second control unit comprises a fourth field effect transistor M 4 The fifth field effect transistor M 5 And a seventh field effect transistor M 7 (ii) a The fourth field effect transistor M 4 The grid of the first field effect transistor is inputted with a third enabling signal LVX, and the fourth field effect transistor M 4 The source inputs an inductive voltage signal Vx; the fifth field effect transistor M 5 Gate of the first transistor inputs a fourth enable signal LVX valley Said fifth field effect transistor M 5 Source input drain voltage Vx valley (ii) a The fourth field effect transistor M 4 The fifth field effect transistor M 5 And the drain electrodes of the first and second operational amplifiers OPA peak The inverting input end of the first switch is connected; the seventh field effect transistor M 7 The grid of the first field effect transistor M is connected with the signal ground 7 And the second operational amplifier OPA peak Is connected with the positive input end of the seventh field effect transistor M 7 Source electrode of (1) and sixth field effect transistor M 6 Is connected to the drain of (1).
6. A SenseFET-type full-wave inductor current sensor in accordance with claim 5, wherein the SenseFET-type full-wave inductor current sensor further comprises,
a valley enable signal generator for generating a valley enable signal according to the input seventh enable signal! BPS n Outputs a second enable signal PS n The fifth enable signal! PS (polystyrene) with high sensitivity n And a fourth enable signal LVX valley ；
A peak enable signal generator for generating a sixth enable signal according to the input! BPS p Outputs a first enable signal PS p And a third enable signal LVX.
7. A SenseFET-type full-wave inductor current sensor as claimed in claim 6, wherein said peak enable signal generator comprises a fifteenth FET M 15 Sixteenth field effect transistor M 16 Seventeenth field effect transistor M 17 Eighteenth field effect transistor M 18 A first inverter INV 1 A first NAND gate NAND 1 A first resistor R senlop A first capacitor C senlop (ii) a The fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 The gates of the first and second transistors are all inputted with a sixth enable signal! BPS p The fifteenth field effect transistor M 15 Source input voltage source signal V source The fifteenth field effect transistor M 15 Seventeenth field effect transistor M 17 Is connected to and serves as a first enable signal PS p A signal output terminal of (a); the seventeenth field effect transistor M 17 The source of the first transistor is connected with a power ground PGND; the sixteenth field effect transistor M 16 Eighteenth field effect transistor M 18 The gates of the first and second transistors are all connected with an enable signal! BPS p The sixteenth field effect transistor M 16 Source electrode of the transistor is connected with an input voltage source signal V source The first resistor R senlop One terminal of (1), a first capacitor C senlop One end of (1), sixteenth field effect transistor M 16 And the drain electrodes of the first and second inverters INV 1 Is connected to the input terminal of the first resistor R senlop The other end of the transistor is connected with an eighteenth field effect transistor M 18 Is connected with the drain electrode of the eighteenth field effect transistor M 18 Source electrode, first capacitor C senlop The other ends of the two-way switch are connected with signal ground; the first inverter INV 1 And the first NAND gate NAND 1 Is connected to the first NAND gate NAND 1 Input a sixth enable signal! BPS p The first NAND gate NAND 1 Outputs the third enable signal LVX.
8. A SenseFET-type full-wave inductor current sensor as claimed in claim 6, wherein said valley enable signal generator comprises a second capacitor C senlov Nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 A second inverter INV 2 A third inverter INV 3 And a fourth inverter INV 4 The fifth inverter INV 5 And a second NAND gate NAND 2 (ii) a The nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 All input a seventh enable signal! BPS n The nineteenth field effect transistor M 19 Source input voltage source signal V source The nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Is connected as a second enable signal PS n And the nineteenth field effect transistor M 19 Twentieth field effect transistor M 20 Respectively connected with the third inverter INV 3 And a fifth inverter INV 5 Is connected with the input end of the twentieth field effect transistor M 20 The source of the second transistor is connected with a power ground PGND; the fifth inverter INV 5 As a fifth enable signal! PS (polystyrene) system n A signal output terminal of (a); the third inverter INV 3 And the fourth inverter INV 4 Is connected to the input terminal of the second capacitor C senlov And a third inverter INV 3 Is connected to the output terminal of the second capacitor C senlov The other terminal of (a) is connected to signal ground; the fourth inverter INV 4 And the output end of the first NAND gate NAND 2 Is connected to the second NAND gate NAND 2 And the other input end of the first inverter INV 2 Is connected with the output end of the second inverter INV 2 Input terminal of the first power supply voltage | a seventh enable signal is input! BPS n Said second NAND gate NAND 2 As a fourth enable signal LVX valley A signal output terminal of (2).
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