CN219918721U - Power converter and control circuit thereof - Google Patents
Power converter and control circuit thereof Download PDFInfo
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- CN219918721U CN219918721U CN202321369435.4U CN202321369435U CN219918721U CN 219918721 U CN219918721 U CN 219918721U CN 202321369435 U CN202321369435 U CN 202321369435U CN 219918721 U CN219918721 U CN 219918721U
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Abstract
The utility model provides a power converter and a control circuit thereof, wherein the control circuit comprises: a mode control circuit for controlling the power converter to switch between a bypass mode and a switch operation mode according to the input voltage and/or the output voltage; the mode control circuit outputs a first mode switching instruction when detecting that the change rate of the input voltage and/or the output voltage is greater than a certain threshold before the input voltage and/or the output voltage reaches the expected value of the output voltage, and the control circuit controls the power converter to exit the bypass mode according to the first mode switching instruction. When the control circuit can detect that the input voltage and/or the output voltage of the power converter quickly jumps in the bypass mode, the control circuit controls the power converter to exit the bypass mode in advance, so that the deviation amplitude of the output voltage relative to the output set voltage when the input voltage fluctuates is greatly reduced, the stability of the output voltage of the power converter when the mode is switched is improved, and the reliable operation of a load is ensured.
Description
Technical Field
The present utility model relates to the field of power converters, and in particular, to a power converter and a control circuit thereof.
Background
With the development of power electronics and semiconductor technology, power management chips are widely used in the fields of communication, consumption, computing, and the like. Taking a DC-DC converter as an example, which is one of the most common types in power management chips, typically comprises one or more switches selectively actuated to provide a controlled DC output voltage or current based on a received DC input, by controlling the output power of a duty cycle adjustable circuit of a signal provided to one or more switching transistors of the converter.
In order to ensure normal operation and high efficiency when the input voltage Vin provided by the input power supply and the output voltage Vout of the converter are close to or equal to each other, a bypass unit (such as a bypass switch) is usually disposed between the input and the output of the converter, and when the bypass switch is turned on, a current path of the power inductor is bypassed to realize a low-impedance pass-through of the input and the output, i.e., a bypass (bypass) operation mode. Along with the rapid change of the input voltage, the output voltage also changes with steps, and generally, when the output voltage drops to the set output voltage, the bypass mode is switched to the switch working mode, but the output voltage Vout can drop greatly in the transient process of switching, so that the working performance of an output load and a system is affected. Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the utility model provides a power converter and a control circuit thereof, which can control the power converter to exit from a bypass mode in advance when detecting that the input voltage and/or the output voltage of the power converter are in rapid jump in the bypass mode, thereby greatly reducing the deviation amplitude of the output voltage relative to the output set voltage when the input voltage fluctuates, improving the stability of the output voltage of the power converter when the mode is switched, and ensuring the reliable operation of a load.
According to a first aspect of the present utility model, there is provided a control circuit of a power converter, the power converter comprising a power unit and a bypass unit coupled to each other, the control circuit being adapted to generate a first control signal and a second control signal to control on and off of switching transistors in the bypass unit and the power unit, respectively, the control circuit comprising:
the mode control circuit is used for generating a mode switching instruction according to the input voltage and/or the output voltage of the power converter and controlling the power converter to switch between a bypass mode and a switch working mode;
the control signal generation circuit is used for generating the first control signal according to the mode switching instruction, wherein the first control signal is in an effective state in the bypass mode and is in an ineffective state in the switch working mode;
And the mode control circuit outputs a first mode switching instruction when detecting that the change rate of the input voltage and/or the output voltage is greater than a certain threshold before the input voltage and/or the output voltage reaches the expected value of the output voltage, and the control circuit controls the power converter to exit the bypass mode according to the first mode switching instruction.
Optionally, the mode control circuit includes a comparator circuit, a first input terminal of the comparator circuit is connected to a first voltage threshold, a second input terminal of the comparator is connected to the input voltage or the divided voltage of the output voltage, a capacitor is disposed between the input voltage or the output voltage and the second input terminal, and the first voltage threshold is set according to an expected value of the output voltage.
Optionally, the mode control circuit includes a differentiating circuit, a proportional circuit, a comparing circuit, and a logic gate circuit;
the input voltage or the output voltage is connected with the input end of the differentiating circuit, the output end of the differentiating circuit is connected with the input end of the proportional circuit, the output end of the proportional circuit is connected with the input ends of the comparing circuit and the logic gate circuit, the input ends of the comparing circuit and the logic gate circuit are also connected with a change rate setting threshold value, a second voltage threshold value, the input voltage or the output voltage, and the comparing circuit and the logic gate circuit output a mode switching instruction.
Optionally, the comparison circuit and the logic gate circuit include a first comparator circuit, a second comparator circuit, and a logic gate circuit;
the output end of the proportional circuit is connected with the first input end of the first comparator circuit, and the second input end of the first comparator circuit is connected with the change rate setting threshold value;
the first input end of the second comparator circuit is connected with the input voltage or the output voltage, and the second input end of the second comparator circuit is connected with a second voltage threshold value;
the two input ends of the logic gate circuit are respectively connected with the output ends of the first comparator circuit and the second comparator circuit, and the logic gate circuit outputs a mode switching instruction based on the output values of the first comparator circuit and the second comparator circuit.
Optionally, when the power converter is a boost power converter, and the input voltage or the output voltage drops to be smaller than the second voltage threshold when the dropping rate of the input voltage or the output voltage is larger than the change rate setting threshold, the mode control circuit outputs a first mode switching instruction, and the control circuit controls the power converter to exit from a bypass mode and enter into a switch working mode based on the first mode switching instruction; the second voltage threshold is set based on a desired value greater than the output voltage.
Optionally, when the power converter is a buck power converter, and the input voltage or the output voltage rises to be greater than the second voltage threshold when the rising rate of the input voltage or the output voltage is greater than the change rate setting threshold, the mode control circuit outputs a first mode switching instruction, and the control circuit controls the power converter to exit from a bypass mode and enter into a switching operation mode based on the first mode switching instruction; the second voltage threshold is set based on a desired value that is less than the output voltage.
Optionally, the control signal generating circuit generates the second control signal according to the mode switching instruction and a current reference signal;
the current reference signal is defined in the switching mode by a compensation signal obtained by compensating an error amplification signal representing difference information of the output voltage and a reference voltage.
Optionally, the switching operation mode includes a transition mode and a normal switching operation mode, and the power converter enters the transition mode after exiting the bypass mode;
the control circuit further comprises a clamping voltage generation module, the output end of the mode control circuit is connected with the input end of the clamping voltage generation module, and in a bypass mode, the clamping voltage generation module generates clamping voltage based on the detected current flowing through a bypass unit or the sum of the detected currents flowing through the bypass unit and the power unit;
In the transient mode, the current reference signal is defined by a clamp compensation signal obtained after clamping the compensation signal via a clamp voltage;
in the normal switching mode of operation, the current reference signal is defined by a compensation signal.
Optionally, the switching operation mode includes a transition mode and a normal switching operation mode, and the power converter enters the transition mode after exiting the bypass mode;
the control circuit also comprises a clock signal generating circuit, wherein the clock signal generating circuit determines the working frequency of the power converter; the frequency of the clock signal generated by the clock signal generating circuit in the transition mode is a first working frequency, the frequency of the clock signal generated by the clock signal generating circuit in the normal switch working mode is a second working frequency, and the first working frequency is larger than the second working frequency; or alternatively
The control circuit also comprises a timer circuit, wherein the time generated by the timer circuit is inversely related to the frequency of the power converter; the time generated by the timer circuit in the transition mode is a first time, the time generated by the timer circuit in the normal switch working mode is a second time, and the first time is smaller than the second time.
According to a second aspect of the present utility model, there is provided a power converter comprising a power cell and a bypass cell coupled to each other, the power cell comprising an inductance and a switching transistor coupled to the inductance;
the control circuit is used for providing control signals to control the switching transistors in the power unit and the bypass unit to be turned on and off.
The beneficial effects of the utility model at least comprise:
the utility model provides a power converter and a control circuit thereof, which comprises a mode control circuit, wherein the mode control circuit is used for controlling the power converter to switch between a bypass mode and a switch working mode according to input voltage and/or output voltage; the mode control circuit outputs a first mode switching instruction when detecting that the change rate of the input voltage and/or the output voltage is greater than a certain threshold before the input voltage and/or the output voltage reaches the expected value of the output voltage, and the control circuit controls the power converter to exit the bypass mode according to the first mode switching instruction. When the control circuit can detect that the input voltage and/or the output voltage of the power converter quickly jumps in the bypass mode, the control circuit controls the power converter to exit the bypass mode in advance, so that the deviation amplitude of the output voltage relative to the output set voltage when the input voltage fluctuates is greatly reduced, the stability of the output voltage of the power converter when the mode is switched is improved, and the reliable operation of a load is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the utility model as claimed.
Drawings
FIG. 1 illustrates a schematic diagram of a power converter provided by the present utility model;
FIG. 2 shows a schematic diagram of a control circuit of a power converter according to the present utility model;
FIG. 3 shows a schematic diagram of a mode control circuit provided by the present utility model;
FIG. 4 shows a schematic diagram of another mode control circuit provided by the present utility model;
FIG. 5 shows a specific schematic diagram of another mode control circuit provided by the present utility model;
fig. 6 shows a schematic diagram of a control circuit of another power converter according to the present utility model.
Detailed Description
In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. Preferred embodiments of the present utility model are shown in the drawings. The utility model may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The power converter provided by the embodiment of the present utility model, among various exemplary examples illustrated and described hereinafter, is merely exemplary of an example of a power converter system of a boost type, which is a DC-DC converter, and the control circuit provided by the embodiment of the present utility model is used for PWM control of the DC-DC converter. The utility model is not limited in this regard and the various concepts disclosed herein may be used in connection with any type of DC-DC converter architecture, including Buck-Boost (Buck) converters, boost-Boost (Boost) converters, flyback (Flyback) converters, buck-Boost (Buck-Boost) converters, etc., for example, depending on the topology classification of the power circuit. Furthermore, while complementary PWM control of the high-side switching devices and the low-side switching devices is utilized in the illustration of an embodiment of the present utility model, the concepts described herein can be implemented in power converters that use only a single switching device and/or in power converters that employ more than two pulse width modulations.
As shown in fig. 1, a schematic diagram of a power converter according to the present utility model includes a power unit 20, a bypass unit 10, and a control circuit 30 coupled to the power unit 20 and the bypass unit 10, respectively. The power unit 20 is coupled between an input and an output, and the bypass unit 10 is connected between the input and the output, receives an input voltage Vin, and provides an output voltage Vout to the load RL. The control circuit 30 is configured to generate control signals Vgs1, vgs2, and Vgs3 to control on and off of each of the switching transistors in the bypass unit 10 and the power unit 20. It should be noted that the first control signal described herein corresponds to the control signal Vgs3. The second control signal described herein corresponds to the complementary control signal Vgs1 and Vgs2 in complementary PWM control (such as the embodiment shown in fig. 1) using a high side switching device and a low side switching device, and to the control signal Vgs1 in a power converter embodiment using a single switching device (such as the switching transistor Q2 of fig. 1 replaced with a diode).
In the example shown in fig. 1, the bypass unit 10 includes a switching transistor Q3, the power unit 20 includes an inductance L, and a switching transistor Q1 and a switching transistor Q2 coupled to the inductance L, the switching transistor Q3 is coupled between the input and the output, the inductance L and the switching transistor Q2 are sequentially coupled in series between the input and the output, and the switching transistor Q1 is coupled between a connection node of the inductance L and the switching transistor Q2 and a reference ground. The control signal Vgs1 is used for controlling the on and off of the switching transistor Q1, the control signal Vgs2 is used for controlling the on and off of the switching transistor Q2, and the control signal Vgs3 is used for controlling the on and off of the switching transistor Q3. Wherein the switching transistors Q1, Q2 and Q3 are NMOS devices, but the utility model is not limited thereto, and other embodiments are possible in which different types of switching transistors are used, such as at least one of the switching transistors Q1, Q2 and Q3 may also be selected as PMOS devices, etc. The power converter 20 also includes other components, such as a capacitor CIN and a capacitor CO, with the capacitor CIN being connected in parallel across the input and the capacitor CO being connected in parallel across the output.
It will be appreciated that the power converter shown in fig. 1 is of an input-output common-negative structure, for example, the inductor L, the switching transistor Q2 and the bypass unit 10 in the power converter are coupled between the positive input terminal and the output terminal of the input, but other examples are possible, and the power converter may also be of an input-output common-positive structure, for example, the inductor L, the switching transistor Q2 and the bypass unit 10 in the power converter are coupled between the negative input terminal and the output terminal of the input. At least one of the switching transistors, the inductance L, the capacitance CIN, and the capacitance CO components included in the power converter shown in fig. 1 may be integrated in the control circuit 30 or may be provided outside the control circuit 30. Furthermore, fig. 1 shows only an example of a single-phase power converter in which the control circuit 30 is coupled to one power cell 20 and one bypass cell 10, but other examples are possible, and the control circuit scheme provided by the present utility model is also applicable to multiphase control of multiphase power converters.
As shown in fig. 1, the control circuit 30 includes a mode control circuit 40 and a control signal generation circuit 50, the mode control circuit 40 outputting a mode switching instruction EN based on an input voltage and/or an output voltage, the control signal generation circuit 50 receiving the mode switching instruction EN while receiving a feedback voltage V FB Reference voltage V REF And a signal representing the inductor current obtained by sampling the inductor current I1/I2, wherein the feedback voltage V FB The control signal generation circuit 50 outputs control signals Vgs1, vgs2, vgs3 based on the signals received by the control signal generation circuit to control the switching transistors Q1 to Q3 based on the output voltage Vout.
Further, as shown in fig. 2, a schematic diagram of a control circuit 30 is provided according to an embodiment of the present utility model, wherein the control signal generating circuit 50 includes a feedback control circuit, a sampling circuit, a current comparator circuit, a clock signal generating circuit/timer circuit, a controller circuit, a driving circuit and a logic control circuit. The feedback control circuit receives the reference voltage Vref and the feedback signal FB and outputs a compensation signal V COMP . The sampling circuit is used for sampling the inductive current in the power unit 20 and outputting a sampling signal Vs, and the sampling circuit can sample the current I1 flowing through the switching transistor Q1 to obtain The current I2 flowing through the switching transistor Q2 may also be sampled to obtain the sampling signal Vs, which may be specifically selected according to the actual application requirement. The input end of the current comparator circuit is respectively coupled with the output end of the feedback control circuit and the output end of the sampling circuit, and the current comparator circuit is used for comparing the sampling signal with the current reference signal (i.e. the output end signal V of the feedback control circuit COMP ) And outputting a comparison signal after the comparison. The controller circuit receives the comparison signal output by the current comparator circuit and the clock pulse signal CLK output by the clock signal generating circuit, and is used for generating complementary control signals Vgs1 and Vgs2 to the switching transistors Q1 and Q2 respectively through the driving circuit under the triggering of the clock pulse signal CLK and the comparison signal. In some embodiments, the controller circuit may implement the corresponding function using, for example, an RS flip-flop, although the application is not limited in this regard. As other embodiments of the present application, the controller circuit may also receive the comparison signal output by the current comparator circuit and the timing signal generated by the timer circuit, for generating complementary control signals Vgs1 and Vgs2 to the switching transistors Q1 and Q2, respectively, via the driving circuit under the triggering of the timing signal and the comparison signal. As some embodiments of the present application, constant on-time or constant off-time control or fixed frequency control of the power converter may be achieved by a timer circuit versus time timing function.
The mode control circuit outputs a mode switching instruction EN based on the input voltage and/or the output voltage, and in the bypass mode, the mode control circuit outputs the mode switching instruction EN having a first instruction state (one of a high level or a low level), the logic control circuit receives the mode switching instruction EN having the first instruction state, and outputs a control signal Vgs3 to make the switching transistor Q3 in an active state (on); the mode switching command EN having the first command state also causes the switching transistor Q2 to be in an active state and the switching transistor Q1 to be in an inactive state (off), and specifically, as shown in fig. 2, as one embodiment of the present application, the mode switching command EN may be input to the controller circuit and/or the driving circuit, and in the bypass mode, the mode switching command EN having the first command state acts on the controller circuit and/or the driving circuit to cause the switching transistor Q2 to be active and the switching transistor Q1 to be inactive. In the switching operation mode, the mode control circuit outputs a mode switching instruction EN having a second instruction state (the other of the high level or the low level), the logic control circuit receives the mode switching instruction EN having the second instruction state, and the control signal Vgs3 is outputted to make the switching transistor Q3 in an inactive state (off); the mode switching command EN having the second command state causes the switching transistors Q1 and Q2 to be complementarily turned on based on the control signals Vgs1 and Vgs2 generated as described above. In fig. 2, only one embodiment in which the mode switching command EN is input to the controller circuit and/or the driving circuit is illustrated, and as other embodiments of the present application, it is within the scope of the embodiments of the present application that the switching transistor Q2 is turned on and the switching transistor Q1 is turned off as long as it is possible to turn on the switching transistor Q1 in the bypass mode, and that the switching transistors Q1 and Q2 are complementarily turned on based on the control signals Vgs1 and Vgs2 in the switching operation mode.
As shown in fig. 3, a schematic diagram of a mode control circuit provided by the application comprises a comparator circuit, wherein a first input end of the comparator circuit is connected with a first voltage threshold V1, a second input end of the comparator circuit is connected with a voltage division of an input voltage or an output voltage, specifically, as shown in fig. 3, the input voltage or the output voltage is connected to the ground through a resistor R1 and a resistor R2, a common node N of the resistor R1 and the resistor R2 is connected to the second input end of the comparator circuit, and a capacitor C1 is arranged between the input voltage or the output voltage and the second input end of the comparator; wherein the first voltage threshold is set according to a desired value of the output voltage, as an example, the first voltage threshold may be set to a value proportional to the desired value of the output voltage. The working principle is as follows: in fig. 3, when the input voltage or the output voltage changes slowly, the voltage at the second input end of the comparator circuit can be regarded as the partial voltage of the input voltage or the output voltage across the resistor R2 through the resistor R1 and the resistor R2, and when the partial voltage reaches the first voltage threshold, the comparator circuit outputs a mode switching command EN with a second command state, and the power converter exits the bypass mode and enters the switch operation mode according to the mode switching command EN. When the voltage value of the second input end of the comparator does not reach the first voltage threshold value, the comparator circuit outputs a mode switching command EN with a first command state, and at the moment, the power converter is in a bypass mode. Because the voltage on the capacitor C1 cannot change suddenly due to the characteristic of the capacitor C1, when the change rate of the input voltage or the output voltage is relatively fast, the voltage at the second input end of the comparator can reach the first threshold voltage in advance relative to the slow change rate of the input voltage or the output voltage, that is, when the change rate of the input voltage or the output voltage is relatively fast, the voltage at the second input end of the comparator circuit reaches the first voltage threshold value when the input voltage or the output voltage is not changed more yet, which is equivalent to exiting the bypass mode in advance and entering the switch working mode. When the input voltage or the change rate of the output voltage is detected to be faster, the bypass mode is exited in advance before the expected value of the output voltage is reached, so that the deviation amplitude of the output voltage relative to the output set voltage can be greatly reduced, and the stability of the output voltage and the reliability of load operation of the power converter in the transient state process of mode switching are improved. In the bypass mode, since the input power source and the output are connected through the bypass unit (e.g., the switching transistor Q3), the operation state thereof may be determined based on the input voltage, the output voltage, or both, and the setting may be selected according to the actual situation by changing the corresponding voltage determination threshold value.
As shown in fig. 4, a schematic diagram of another mode control circuit provided by the present application includes a differentiating circuit 60, a proportional circuit 70, a comparing circuit and a logic gate circuit; the input voltage or the output voltage is connected with the input end of the differentiating circuit, the output end of the differentiating circuit is connected with the input end of the proportional circuit, the output end of the proportional circuit is connected with the input ends of the comparing circuit and the logic gate circuit, the input ends of the comparing circuit and the logic gate circuit are also connected with the change rate set threshold value, the second voltage threshold value, the input voltage or the output voltage, and the comparing circuit and the logic gate circuit output a mode switching instruction according to signals received by the input ends of the comparing circuit and the logic gate circuit. By detecting the change rate of the input voltage or the output voltage and comparing the change rate with a change rate set threshold, when the change rate of the input voltage or the output voltage reaches the change rate set threshold and the input voltage or the output voltage reaches a second voltage threshold, the comparison circuit and the logic gate circuit output a mode switching instruction with a second instruction state, exit the bypass mode and enter the switch working mode.
Further, as shown in fig. 5, which is an embodiment of the specific schematic diagram of the mode control circuit in fig. 4, one input terminal of the differentiating circuit 60 is connected to an input voltage or an output voltage through a capacitor C2, a resistor R3 is further connected between the input terminal and the output terminal of the differentiating circuit, the other input terminal of the differentiating circuit 60 is connected to a low potential ground, and the relationship between the output of the differentiating circuit and the input voltage or the output voltage is determined based on the capacitor C2, the resistor R1, and the rate of change of the input voltage or the output voltage; the proportional circuit 70 is an inverting proportional circuit, the relationship between its output and input being based on the ratio between the resistor R5 and the resistor R4; the comparison circuit and the logic gate circuit comprise a first comparator circuit, a second comparator circuit and a logic gate circuit; the output end of the proportional circuit is connected with the first input end of the first comparator circuit, and the second input end of the first comparator circuit is connected with the change rate setting threshold VS; the first input end of the second comparator circuit is connected with the input voltage or the output voltage, and the second input end of the second comparator circuit is connected with the second voltage threshold V2; the two input ends of the logic gate circuit are respectively connected with the output ends of the first comparator circuit and the second comparator circuit, and the logic gate circuit outputs a mode switching instruction based on the output values of the first comparator circuit and the second comparator circuit. When the change rate of the input voltage or the output voltage is larger than the change rate setting threshold value VS and the input voltage or the output voltage reaches the second voltage threshold value, the logic gate circuit outputs a mode switching instruction with a second instruction state, exits from the bypass mode and enters into the switch working mode. Before detecting that the input voltage or the output voltage reaches a second voltage threshold, the logic gate circuit outputs a mode switching instruction with a first instruction state and works in a bypass mode; when the input voltage or the output voltage reaches the second voltage threshold, and the change rate of the input voltage or the output voltage is not detected to be faster, the bypass mode is exited when the input voltage or the output voltage reaches the corresponding output set voltage, and a specific circuit thereof can be selected and set by a person skilled in the art according to actual conditions.
Further, taking the power converter in fig. 1 as a boost power converter as an example, in the bypass mode, when the falling rate of the input voltage or the output voltage is greater than the change rate setting threshold value and the input voltage or the output voltage falls below the second voltage threshold value, the mode control circuit outputs a first mode switching instruction, where the first mode switching instruction is a mode switching instruction having a second instruction state, and the control circuit controls the power converter to exit the bypass mode and enter the switching operation mode based on the first mode switching instruction; wherein the second voltage threshold is set based on a desired value greater than the output voltage. As another embodiment of the present utility model, when the power converter is a buck power converter, the mode control circuit outputs a first mode switching instruction when the rising rate of the input voltage or the output voltage is greater than the change rate setting threshold and the input voltage or the output voltage rises to be greater than the second voltage threshold, and the control circuit controls the power converter to exit the bypass mode and enter the switching operation mode based on the first mode switching instruction; wherein the second voltage threshold is set based on a desired value that is less than the output voltage. According to the utility model, by detecting the change rate of the input voltage or the output voltage, when the change rate of the input voltage or the output voltage reaches a change rate set threshold value and the input voltage or the output voltage reaches a second voltage threshold value, the bypass mode is exited, namely the bypass mode is exited in advance before the expected value of the output voltage is reached, so that the deviation amplitude of the output voltage relative to the output set voltage can be greatly reduced, and the stability of the output voltage and the reliability of load operation of the power converter in the transient state process of mode switching are improved.
Further, as shown in FIG. 6, the control circuit is further provided with a clamp voltage generating module, an output terminal of the mode control circuit and a clampThe input end of the voltage generating module is connected; when the mode control circuit outputs a mode switching command EN having a first command state based on the input voltage and/or the output voltage, the power converter operates in a bypass mode, and the clamp voltage generating module generates the clamp voltage V based on a current (denoted as I3) flowing through the bypass unit and a current (denoted as I2) flowing through the switching transistor Q2 in the bypass mode, or based on only a current (denoted as I3) flowing through the bypass unit CLAMP The clamp voltage V CLAMP Compensation signal V for a system COMP Clamping is performed. As one embodiment of the present application, the clamp voltage generation module is specifically configured to: the current I2 flowing through the power cell and the current I3 flowing through the bypass cell are sampled, summed and sample-and-hold in the bypass mode, thereby generating a clamp voltage V CLAMP . The clamping voltage generation module comprises a sampling and summing circuit and a sampling and holding circuit, wherein the sampling and summing circuit is used for respectively sampling and summing the current I2 flowing through the power unit and the current I3 flowing through the bypass unit by the clamping voltage generation module, and a sampling and summing signal is output; the sampling and holding circuit is used for sampling and holding the sampling and summing signal output by the sampling and summing circuit and outputting the clamping voltage V CLAMP . As one embodiment of the utility model, after the sampling summation of I3 and I2, the sampling summation can be output to a sampling hold circuit after a certain delay to generate a clamping voltage V CLAMP The clamping effect is better. Whether or not to set the delay is selectable by those skilled in the art according to the actual situation. As other embodiments of the present utility model, the clamp voltage generation module may also be configured to: by sampling and holding the current I3 flowing through the bypass unit in the bypass mode, the clamp voltage V is generated CLAMP . At this time, the clamp voltage generating module can sample and hold the current I3 flowing through the bypass unit by using a sample and hold circuit to output the clamp voltage V CLAMP . Wherein the sample-and-hold circuit is enabled in the bypass mode and disabled in the normal switching mode under the control of the mode switching instruction EN. The utility model sets the switch operation mode to include a transition mode and a normal switch operation modeIn the transition mode, the clamping voltage V generated in the bypass mode based on the clamping voltage generation module CLAMP Compensation signal V output by feedback control circuit COMP Clamping is performed. After the power converter is operated in the transition mode for a predetermined time (denoted as t 1), the power converter is controlled to switch from the transition mode to the normal switching mode. In practical application, the predetermined time t1 may be set differently according to different application scenarios. It should be noted that the clamp voltage generating module outputs the clamp voltage V after the power converter exits the bypass mode CLAMP Corresponds to the predetermined time t1 set as described above. During the transient (corresponding to the transition mode) of the mode switch, the compensation signal V COMP A certain time is required for the establishment of the response of the system, and the recovery speed of the system to the output voltage Vout or the output current in the transient process is influenced, so that the output voltage Vout is easy to deviate greatly. And due to the clamping voltage V generated by the clamping voltage generating module CLAMP Can also be used to characterize the load current information required for steady operation of the load, and therefore, during transients in mode switching, the present embodiment uses this clamp voltage V CLAMP For compensation signal V COMP The voltage signals obtained after clamping are used as reference signals for generating control signals Vgs1 and Vgs2, so that the system can still perform quick and even faster feedback response on output information of the power converter in the transient process, the recovery speed of the output voltage Vout or the output current is improved, the inductance current of the converter can reach a value corresponding to the load current in a short time, the deviation amplitude of the output voltage Vout relative to the output set voltage during mode switching is greatly reduced, and the stability of the output voltage and the reliability of load operation of the power converter during mode switching are further improved.
Further, the clock signal generating circuit may also receive a mode switching instruction EN output from the mode control circuit, the clock signal generating circuit being configured to output the clock pulse signal CLK having the first operating frequency or the second operating frequency according to the mode switching instruction EN. In the transition mode, the clock signal generating circuit outputs a clock pulse signal CLK having a first operating frequency, and in the normal switching mode, the clock signal generating circuit outputs a clock pulse signal CLK having a second operating frequency, wherein the first operating frequency is greater than the second operating frequency. As other embodiments of the present application, the first operating frequency and the second operating frequency may be set so that the first operating frequency is twice or more as high as the second operating frequency. The application obtains faster system response based on the clock pulse signal CLK with higher frequency (such as the first working frequency) output by the clock signal generating circuit, thereby enabling the inductance current of the power converter to reach the value corresponding to the load current in a short time, greatly reducing the deviation amplitude of the output voltage Vout relative to the output set voltage when the bypass mode is switched to the normal switch working mode, and improving the stability of the output voltage Vout and the reliability of the load operation of the power converter in the transient process of the mode switching.
Further, as another embodiment of the present application, the timer circuit may also receive a mode switching command EN output by the mode control circuit, and the timer circuit is configured to output a timing signal having a first time T1 or a second time T2 according to the mode switching command EN, where a time generated by the timer circuit may be set to be inversely related to a frequency of the power converter. In the transition mode, the timer circuit outputs a time signal having a first time T1, and in the normal switching mode, the timer circuit outputs a time signal having a second time T2, wherein the first time T1 is smaller than the second time T2. Namely, when the mode switching command EN has the second command state, the timer circuit starts timing according to the comparison signal output by the current comparator circuit, and outputs a trigger signal corresponding to the first time T1 in the transition mode, and when the mode switching command EN is in the second command state for a predetermined time, in the normal switch operation mode, the timer circuit starts timing according to the comparison signal output by the current comparator circuit, and outputs a trigger signal corresponding to the second time T2. Timer circuit 2438 also clears the timing value when the trigger signal is output. As other embodiments of the present application, the first time T1 and the second time T2 may be set such that the frequencies of the control signals Vgs1 and Vgs2 in the transition mode are more than twice the frequencies of the control signals Vgs1 and Vgs2 in the normal switching operation mode. The application obtains faster system response based on the trigger signal of the timer circuit output corresponding to smaller time (such as the first time T1), thereby enabling the inductance current of the power converter to reach the value corresponding to the load current in a short time, greatly reducing the deviation amplitude of the output voltage Vout relative to the output set voltage during mode switching, and improving the stability of the output voltage Vout and the reliability of load operation of the power converter during the transient state of mode switching.
As other embodiments of the present application, in the control circuit, a mode switching instruction may be simultaneously output to the clamp voltage generating module and the clock generating circuit/timer circuit, the control signal generating circuit may be capable of controlling the power converter to exit the bypass mode in advance based on the mode switching instruction EN provided by the mode control circuit when the input voltage or the output voltage is detected to be rapidly hopped in the bypass mode, or to enter a transition mode before the normal switching operation mode in advance when the input voltage or the output voltage is not detected to be rapidly hopped in the bypass mode, and in the transition mode, obtaining a faster system response based on a trigger signal corresponding to a smaller time (e.g., a first time T1) output from the timer circuit or obtaining a faster system response based on a clock pulse signal CLK having a higher frequency (e.g., a first operation frequency) output from the clock signal generating circuit, and obtaining a clamp voltage V generated already in the bypass mode based on the clamp voltage generating circuit CLAMP Compensation signal V output by feedback control circuit COMP The clamping of the output voltage Vout relative to the output set voltage during mode switching is greatly reduced, and the stability of the output voltage Vout and the reliability of load operation of the power converter during transient state of mode switching are improved.
The application also provides a power converter, which comprises a power unit and a bypass unit which are coupled with each other, wherein the power unit comprises an inductor and a switching transistor coupled with the inductor, and the power converter further comprises the control circuit which is used for providing a control signal to control the switching transistors in the power unit and the bypass unit to be turned on and off.
In summary, the control circuit provided by the embodiment of the application can control the power converter to exit the bypass mode in advance based on the mode switching instruction EN provided by the mode control circuit when the rapid jump of the input voltage or the output voltage is detected in the bypass mode, so that the deviation amplitude of the output voltage relative to the output set voltage can be greatly reduced, and the stability of the output voltage and the reliability of load operation of the power converter in the transient state process of mode switching are improved.
Further, on the basis of exiting the bypass mode in advance or when no rapid jump in the input voltage is detected, a transition mode is entered before the normal switching operation mode, in which a faster system response is obtained based on a trigger signal output by the timer circuit for a correspondingly smaller time (e.g., the first time T1), or a faster system response is obtained based on a clock signal CLK output by the clock signal generating circuit and having a higher frequency (e.g., the first operation frequency), and/or based on a clamp voltage V already generated by the clamp voltage generating circuit in the bypass mode CLAMP Compensation signal V output by feedback control circuit COMP The clamping of the output voltage Vout relative to the output set voltage during mode switching is greatly reduced, and the stability of the output voltage Vout and the reliability of load operation of the power converter during transient state of mode switching are improved.
Claims (10)
1. A control circuit of a power converter, the power converter comprising a power cell and a bypass cell coupled to each other, the control circuit for generating a first control signal and a second control signal for controlling on and off of switching transistors in the bypass cell and the power cell, respectively, the control circuit comprising:
the mode control circuit is used for generating a mode switching instruction according to the input voltage and/or the output voltage of the power converter and controlling the power converter to switch between a bypass mode and a switch working mode;
the control signal generation circuit is used for generating the first control signal according to the mode switching instruction, wherein the first control signal is in an effective state in the bypass mode and is in an ineffective state in the switch working mode;
And the mode control circuit outputs a first mode switching instruction when detecting that the change rate of the input voltage and/or the output voltage is greater than a certain threshold before the input voltage and/or the output voltage reaches the expected value of the output voltage, and the control circuit controls the power converter to exit the bypass mode according to the first mode switching instruction.
2. The control circuit of claim 1, wherein,
the mode control circuit comprises a comparator circuit, a first input end of the comparator circuit is connected with a first voltage threshold, a second input end of the comparator circuit is connected with the input voltage or the voltage division of the output voltage, a capacitor is arranged between the input voltage or the output voltage and the second input end, and the first voltage threshold is set according to an expected value of the output voltage.
3. The control circuit of claim 1, wherein,
the mode control circuit comprises a differentiating circuit, a proportional circuit, a comparing circuit and a logic gate circuit;
the input voltage or the output voltage is connected with the input end of the differentiating circuit, the output end of the differentiating circuit is connected with the input end of the proportional circuit, the output end of the proportional circuit is connected with the input ends of the comparing circuit and the logic gate circuit, the input ends of the comparing circuit and the logic gate circuit are also connected with a change rate setting threshold value, a second voltage threshold value, the input voltage or the output voltage, and the comparing circuit and the logic gate circuit output a mode switching instruction.
4. The control circuit of claim 3, wherein,
the comparison circuit and the logic gate circuit comprise a first comparator circuit, a second comparator circuit and a logic gate circuit;
the output end of the proportional circuit is connected with the first input end of the first comparator circuit, and the second input end of the first comparator circuit is connected with the change rate setting threshold value;
the first input end of the second comparator circuit is connected with the input voltage or the output voltage, and the second input end of the second comparator circuit is connected with a second voltage threshold value;
the two input ends of the logic gate circuit are respectively connected with the output ends of the first comparator circuit and the second comparator circuit, and the logic gate circuit outputs a mode switching instruction based on the output values of the first comparator circuit and the second comparator circuit.
5. The control circuit of claim 3, wherein,
when the power converter is a boost type power converter, and the input voltage or the output voltage drops to be smaller than the second voltage threshold value when the dropping speed of the input voltage or the output voltage is larger than the change speed setting threshold value, the mode control circuit outputs a first mode switching instruction, and the control circuit controls the power converter to exit from a bypass mode and enter into a switch working mode based on the first mode switching instruction; the second voltage threshold is set based on a desired value greater than the output voltage.
6. The control circuit of claim 3, wherein,
when the power converter is a step-down power converter, and the rising rate of the input voltage or the output voltage is larger than the change rate set threshold value, and when the input voltage or the output voltage rises to be larger than the second voltage threshold value, the mode control circuit outputs a first mode switching instruction, and the control circuit controls the power converter to exit from a bypass mode and enter into a switch working mode based on the first mode switching instruction; the second voltage threshold is set based on a desired value that is less than the output voltage.
7. The control circuit of claim 1, wherein,
the control signal generating circuit generates the second control signal according to the mode switching instruction and a current reference signal;
the current reference signal is defined in the switching mode by a compensation signal obtained by compensating an error amplification signal representing difference information of the output voltage and a reference voltage.
8. The control circuit of claim 7, wherein,
the switching operation mode comprises a transition mode and a normal switching operation mode, and the power converter enters the transition mode after exiting the bypass mode;
The control circuit further comprises a clamping voltage generation module, the output end of the mode control circuit is connected with the input end of the clamping voltage generation module, and in a bypass mode, the clamping voltage generation module generates clamping voltage based on the detected current flowing through a bypass unit or the sum of the detected currents flowing through the bypass unit and the power unit;
in the transient mode, the current reference signal is defined by a clamp compensation signal obtained after clamping the compensation signal via a clamp voltage;
in the normal switching mode of operation, the current reference signal is defined by a compensation signal.
9. The control circuit of any one of claims 1-8, wherein,
the switching operation mode comprises a transition mode and a normal switching operation mode, and the power converter enters the transition mode after exiting the bypass mode;
the control circuit also comprises a clock signal generating circuit, wherein the clock signal generating circuit determines the working frequency of the power converter; the frequency of the clock signal generated by the clock signal generating circuit in the transition mode is a first working frequency, the frequency of the clock signal generated by the clock signal generating circuit in the normal switch working mode is a second working frequency, and the first working frequency is larger than the second working frequency; or alternatively
The control circuit also comprises a timer circuit, wherein the time generated by the timer circuit is inversely related to the frequency of the power converter; the time generated by the timer circuit in the transition mode is a first time, the time generated by the timer circuit in the normal switch working mode is a second time, and the first time is smaller than the second time.
10. A power converter comprising a power cell and a bypass cell coupled to each other, the power cell comprising an inductance and a switching transistor coupled to the inductance;
the control circuit of any of claims 1-9, the control circuit to provide control signals to control switching transistors in the power cell and the bypass cell to turn on and off.
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| CN202321369435.4U CN219918721U (en) | 2023-05-30 | 2023-05-30 | Power converter and control circuit thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117917851A (en) * | 2024-03-15 | 2024-04-23 | 无锡力芯微电子股份有限公司 | Direct current boost circuit with bypass direct-pass function |
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- 2023-05-30 CN CN202321369435.4U patent/CN219918721U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117917851A (en) * | 2024-03-15 | 2024-04-23 | 无锡力芯微电子股份有限公司 | Direct current boost circuit with bypass direct-pass function |
| CN117917851B (en) * | 2024-03-15 | 2024-05-28 | 无锡力芯微电子股份有限公司 | Direct current boost circuit with bypass direct-pass function |
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