CN115912867A

CN115912867A - Band-gap reference stabilizing circuit for providing refreshing logic based on power supply fluctuation

Info

Publication number: CN115912867A
Application number: CN202110897250.XA
Authority: CN
Inventors: 崔先宇
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2021-08-05
Filing date: 2021-08-05
Publication date: 2023-04-04

Abstract

A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple, comprising: the circuit comprises a rising edge identification unit, a falling edge identification unit, a logic trigger unit and a clock generation unit; the device comprises a rising edge identification unit, a first identification signal generation unit and a second identification signal generation unit, wherein the rising edge identification unit is used for identifying the rising edge of the power supply voltage and generating a first identification signal; the falling edge identification unit is used for identifying the falling edge of the power supply voltage and generating a second identification signal; the logic trigger unit is used for receiving the first and second identification signals from the rising edge and falling edge identification units and a clock refresh signal fed back from the clock generation unit and generating a switch control signal based on the first and second identification signals; and the clock generation unit is used for controlling the crystal oscillator and the D trigger to generate clock period refreshing signals based on the switch control signals.

Description

Band-gap reference stabilizing circuit for providing refreshing logic based on power supply fluctuation

Technical Field

The invention relates to the field of integrated circuits, in particular to a band-gap reference stabilizing circuit for providing refreshing logic based on power supply fluctuation.

Background

In a low-voltage low-power chip, a Current Pump (CP) is usually used to drive a Bandgap reference source (BG) circuit. This results in that in such a circuit, if the current pump is always in an operating state, the static operating current of the bandgap reference source circuit will gradually increase, thereby resulting in an increase in chip power consumption.

In the prior art, a fixed refresh logic is usually adopted to refresh an input signal of a bandgap reference source circuit at a fixed time interval, and meanwhile, the stability of an output signal of the bandgap reference source circuit is realized by slowing down the discharge speed of a charge pump. In practical applications, however, the output signal of the bandgap reference source circuit may slightly jitter with power supply fluctuation, and the time delay of the jitter usually exceeds the duration of the high level refresh signal generated by the fixed refresh logic. Therefore, when the refresh logic of one period is finished, the refresh signal is at a low level, the bandgap reference source circuit cannot receive the input signal, but the jitter of the output end signal is not recovered, and a certain error occurs in the stable bandgap output signal generated in the next period according to the characteristics of the bandgap reference source circuit. Meanwhile, if the power supply voltage happens to be greatly floated, a comparator at the rear end of the band-gap reference source circuit may malfunction, thereby causing bit errors and causing serious influence on the rear end circuit. Therefore, a new auxiliary circuit or auxiliary method for a bandgap reference circuit is needed to enable the bandgap reference circuit to generate an accurate bandgap reference signal.

Disclosure of Invention

In order to solve the defects in the prior art, the invention aims to provide a bandgap reference stabilizing circuit for providing refresh logic based on power supply fluctuation, which realizes the frequency reduction of a clock signal generated by a crystal oscillator by identifying the rising edge and the falling edge of the power supply voltage, and avoids the error of a bandgap reference signal by means of frequency reduction.

The invention adopts the following technical scheme.

A band-gap reference stabilizing circuit for providing refreshing logic based on power supply fluctuation comprises a rising edge identification unit, a falling edge identification unit, a logic trigger unit and a clock generation unit; a rising edge identification unit for identifying a rising edge of the power supply voltage and generating a first identification signal; a falling edge identification unit for identifying a falling edge of the power supply voltage and generating a second identification signal; the logic trigger unit is used for receiving the first and second identification signals from the rising edge and falling edge identification units and the clock refreshing signal fed back from the clock generation unit and generating a switch control signal based on the first and second identification signals; and the clock generation unit is used for controlling the crystal oscillator and the D flip-flop to generate a clock period refreshing signal based on the switch control signal.

Preferably, the rising edge identification unit includes a first detection capacitor C1, a first detection resistor R1, a first current source I1, and a first field NMOS transistor NMOS1; the first detection capacitor C1 is connected in series with the first detection resistor R1, one end of the first detection capacitor C1 is connected with a power supply voltage Vdd, and one end of the first detection resistor R1 is grounded; the first current source I1 is connected with the NMOS1 of the first field effect transistor in series, one end of the first current source is connected with a power voltage Vdd, the other end of the first current source is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is grounded, and the grid electrode of the first current source is respectively connected with the other ends of the first detection capacitor C1 and the first detection resistor R1; and the connection part of the first current source I1 and the first field effect transistor NMOS1 is used as the output end of the rising edge identification unit, and outputs a first identification signal of the rising edge identification unit.

Preferably, the falling edge identification unit includes a first PMOS transistor PMOS1, a second PMOS transistor PMOS2, a second current source I2, and a second detection capacitor C2; the source electrode of the first PMOS tube PMOS1 is connected with a power supply voltage Vdd, the drain electrode of the first PMOS tube PMOS1 is respectively connected with the source electrode of the second PMOS tube PMOS2 and one end of the second detection capacitor C2, and the grid electrodes of the first PMOS tube and the second PMOS tube are both connected with a first band gap voltage Vbp1; the drain electrode of the second PMOS tube PMOS2 is connected with one end of a second current source I2, and the other end of the second current source I2 is grounded; the other end of the second detection capacitor C2 is grounded; and the drain electrode of the second PMOS tube PMOS2 and one end of the second current source I2 are used as the output end of the falling edge identification unit, and a second identification signal of the falling edge identification unit is output.

Preferably, the logic trigger unit comprises a first not gate, a nor gate, a second not gate and an RS flip-flop; the input end of the first NOT gate is connected with the output end of the rising edge identification unit, and the output end of the first NOT gate is connected with one input end of the NOR gate; the other input end of the NOR gate is connected with the output end of the falling edge identification unit, and the output end of the NOR gate is connected with the input end of the second NOR gate; the input end of the second NOT gate is connected with one input end of the RS trigger, and the other input end of the RS trigger inputs the clock refreshing signal fed back by the clock generating unit; the output end of the RS trigger outputs a switch control signal and is connected with the clock generation unit.

Preferably, the clock generation unit comprises a first input branch, a second input branch and a crystal oscillator branch; the first input branch circuit is used for realizing the on-off of the branch circuit based on a switch control signal output by the logic trigger unit and providing a part of input current I4 for the crystal oscillator branch circuit when the first input branch circuit is on; the second input branch is used for receiving a clock signal CLK fed back by the crystal oscillator branch, controlling the magnitude of the branch current I5 based on feedback, and providing partial input current I5 for the crystal oscillator branch; and the crystal oscillator branch is used for generating a clock signal CLK and a delayed clock refreshing signal.

Preferably, the first input branch comprises a third PMOS transistor PMOS3, a fifth PMOS transistor PMOS5 and a third capacitor C3; the source electrode of the third PMOS tube PMOS3 is connected with a power supply voltage Vdd, the grid electrode of the third PMOS tube PMOS3 is connected with a second band gap voltage Vbp2, and the drain electrode of the third PMOS tube PMOS3 is connected with the source electrode of the fifth PMOS tube PMOS 5; the grid electrode of the fifth PMOS tube PMOS5 is connected with the output end of the logic trigger unit, receives a switch control signal output by the logic trigger unit, and the drain electrode of the fifth PMOS tube PMOS5 is connected with one end of a third capacitor C3; the other end of the third capacitor is grounded.

Preferably, the second input branch comprises a fourth PMOS transistor PMOS4, a sixth PMOS transistor PMOS6 and a second NMOS transistor NMOS2; the source electrode of the fourth PMOS tube is connected with a power supply voltage Vdd, the grid electrode of the fourth PMOS tube is connected with a second band gap voltage Vbp2, and the drain electrode of the fourth PMOS tube is connected with the source electrode of a sixth PMOS tube PMOS 6; the drain electrode of the sixth PMOS tube PMOS6 is connected with the drain electrode of the second NMOS tube, and the grid electrode of the sixth PMOS tube PMOS6 is connected with the grid electrode of the second NMOS tube; the source electrode of the second NMOS tube is grounded.

Preferably, the crystal oscillator branch comprises a crystal oscillator OSC, a D flip-flop Dffr, and a clock refresh signal arithmetic unit; the input end of the crystal oscillator OSC is respectively connected with the drain electrode of a fifth PMOS (P-channel metal oxide semiconductor) transistor PMOS5, one end of a third capacitor C3, the drain electrode of a sixth PMOS transistor PMOS6 and the grid electrode of a second NMOS (N-channel metal oxide semiconductor) transistor NMOS2, and the output end of the crystal oscillator OSC is connected with the input end of a D trigger Dffr; the output end of the crystal oscillator OSC is connected with the grid electrode of the sixth PMOS transistor PMOS6 and the grid electrode of the second NMOS transistor NMOS2 at the same time and is used for feeding back a clock signal CLK to the sixth PMOS transistor PMOS6 and the second NMOS transistor NMOS2; the first output end and the second output end of the D trigger Dffr are respectively connected with the input end of the clock refreshing signal arithmetic unit; the clock refreshing signal operation unit outputs a clock refreshing signal as the input of the RS trigger in the logic trigger unit.

Preferably, the OSC down-conversion circuit generates an impulse signal Pulse based on a rising edge and a falling edge of the power supply voltage; and the RS trigger receives the clock refreshing signal and the impulse signal Pulse and generates a switch control signal based on RS trigger logic.

Preferably, when the RS flip-flop receives the clock Refresh signal in the Refresh state and simultaneously receives the impulse signal Pulse, the Switch control signal Switch switches the logic state to the high level output until the Refresh state of the clock Refresh signal Refresh is ended.

Preferably, when the switch control signal is output at a high level, the first input branch is turned off, and the second input branch charges the third capacitor C3; when the switch control signal is output at a low level, the first input branch is conducted, and the first input branch and the second input branch charge the third capacitor C3 at the same time.

Preferably, when the clock signal CLK is fed back to be output at a high level, the sixth PMOS transistor PMOS6 in the second input branch is turned off, the second NMOS transistor NMOS2 is turned on, and the third capacitor C3 is in a discharge state; when the clock signal CLK is fed back to be output at a low level, the sixth PMOS transistor PMOS6 in the second input branch is turned on, the second NMOS transistor NMOS2 is turned off, and the third capacitor C3 is in a charging state.

Preferably, the D flip-flop is configured to identify a clock signal output by the output terminal of the crystal oscillator OSC, and generate a periodic signal that is a set multiple of a clock period.

Preferably, the clock refresh signal operation unit is used for realizing the superposition of clock signals with different frequencies based on the first output and the second output of the D trigger, and generating the clock refresh signal based on the parameter requirement of the band-gap reference circuit.

Compared with the prior art, the band-gap reference stabilizing circuit for providing the refreshing logic based on the power supply fluctuation can accurately identify the rising edge and the falling edge of a power supply voltage Vdd signal, and control the input end of an OSC crystal oscillator according to the identification and a clock refreshing signal, so that the frequency reduction of a clock periodic signal is realized, namely, the time of the refreshing signal is prolonged, and the voltage of a band-gap reference source can be recovered to a normal value when the refreshing of one period is finished.

The beneficial effects of the invention also include:

1. the method can respectively and effectively identify the rising edge and the falling edge of the power supply voltage, and adaptively modify the logic of the clock refreshing signal based on the identified rising edge and the identified falling edge. The logic of the clock refreshing signal is modified, so that the oscillation process of the band gap voltage caused by the change of the power supply voltage cannot extend to a new period of the clock refreshing signal, and the band gap circuit is prevented from outputting inaccurate stable band gap voltage.

2. Because the invention adopts the mode of connecting the crystal oscillator, the D trigger and the clock refreshing signal arithmetic unit in series to realize the logic of the clock refreshing signal, and the logic can carry out adaptive updating and improvement based on the characteristics of the band gap circuit, and has a plurality of using scenes and wide application area.

Drawings

FIG. 1 is a schematic diagram of a bandgap reference source circuit with current pump refresh logic according to the prior art;

FIG. 2 is a schematic diagram of a bandgap reference signal based on current refresh logic according to the prior art;

FIG. 3 is a schematic diagram of a logic structure of a bandgap reference stabilization circuit for providing refresh logic based on power supply fluctuations according to the present invention;

FIG. 4 is a schematic circuit diagram of a bandgap reference stabilization circuit for providing refresh logic based on power supply fluctuations in accordance with the present invention;

fig. 5 is a schematic diagram of a switching control signal generated and controlled by a bandgap reference stabilization circuit for providing refresh logic based on power supply fluctuations according to the present invention.

Detailed Description

The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.

Fig. 1 is a schematic diagram of a bandgap reference source circuit with current pump refresh logic according to the prior art. As shown in fig. 1, for a low-voltage low-power consumption circuit, since the voltage value of the regulated voltage Vreg1 generated by the low-voltage low-power consumption circuit is usually small and is not enough to provide enough driving for normal operation of the back-end circuit, a Charge Pump (CP) is needed to multiply and amplify the regulated voltage Vreg1 so that the regulated voltage Vreg2 output by the low-voltage low-power consumption circuit is large enough.

In one embodiment of the present invention, when the power supply voltage VDD is below 2V, vreg1 output by the voltage regulator is approximately equal to the power supply voltage VDD and increases with the increase of VDD. With the rising of the power voltage VDD, when VDD is greater than 2V, the regulator clamps the regulated voltage Vreg1 within 2V or fluctuates slightly around 2V.

After the stable voltage Vreg1 is inputted to the charge pump, the charge pump in an embodiment of the invention may have a multiplication factor. Therefore, the regulated voltage Vreg2 of the charge pump output will fluctuate between 0 and 4V. With such an arrangement, vreg2 can still maintain a large output when the power supply voltage is small, for example, vreg2 is 2V when the power supply voltage is 1V. When the power supply voltage is larger, vreg2 can be limited within a smaller range, for example, when the power supply voltage is 5V, vreg2 is 4V. The method not only ensures that the back-end circuit can sensitively receive the input of the Vreg2 so as to start the working state, but also can ensure that the back-end circuit is not damaged under the condition of larger power supply voltage.

Generally, in the prior art, a bandgap circuit is built in a circuit for realizing the output voltage Vreg2 of the charge pump, so as to further ensure the stability of the output voltage Vreg 2. The bandgap voltage source receives an input of an output voltage Vreg2 on the one hand and also feeds back a bandgap voltage Vbg to a circuit implementing the charge pump output voltage Vreg2 on the other hand. Therefore, the stability of the band gap voltage Vbg can be fully ensured through a feedback loop constructed between the band gap circuit and the charge pump output circuit.

In this one loop, at least the elements that should be present are large capacitors and loop switches. Wherein the loop switch is turned on and off based on the refresh logic implementation of the loop. In fig. 1, the Refresh logic is implemented by a signal Refresh. In addition, the large capacitor can ensure that the voltage Vbg is relatively stable along with the charge and discharge of the large capacitor in the cyclic opening and closing processes of the switch. Therefore, a large capacitance and a loop switch are indispensable elements in a loop for realizing basic logic of a bandgap circuit. FIG. 2 is a schematic diagram of a bandgap reference signal based on current refresh logic in the prior art. As shown in fig. 2, the bandgap reference circuit generates a stable bandgap reference voltage signal as the power supply voltage increases and decreases. Due to the Refresh logic in the circuit, in each Refresh cycle, the loop switch will close when the Refresh signal Refresh is high, discharging Vbg via Vreg 2. Meanwhile, the loop switch is turned on when the Refresh signal refreshh is at a low level, and the Vbg voltage is maintained by discharging the large capacitor.

In such a circuit, as shown in fig. 2, a situation occurs in which the supply voltage Vdd abruptly changes. When Vdd suddenly rises or drops, it has a certain effect on the bandgap voltage signal, so that the bandgap voltage Vbg oscillates slightly in a very short time. When the oscillation happens to occur at the moment when one refresh cycle is completely finished and the next refresh cycle is started, the loop switch is closed, so that the next input is provided for the band gap circuit. Since the band gap voltage fluctuation caused by the power supply voltage variation is not finished yet, the band gap voltage Vbg' stabilized in the new period is not accurate enough. Since Vdd is just on the rising edge during the second cycle, the bandgap regulated voltage for the second cycle drops slightly compared to the first cycle, as shown in fig. 2. In the third period, vdd is just at the falling edge, the band gap stable voltage of the third period is more sharply reduced, and even a back-end circuit, such as a comparator, can be identified incorrectly, so that a malfunction occurs.

In view of the above problems, the present invention provides a new solution. Fig. 3 is a schematic diagram of a logic structure of a bandgap reference stabilization circuit for providing refresh logic based on power supply fluctuations according to the present invention. As shown in fig. 3, a bandgap reference stabilizing circuit 100 providing refresh logic based on power supply fluctuation in the present invention includes a rising edge identification unit 101, a falling edge identification unit 102, a logic trigger unit 103, and a clock generation unit 104. Specifically, the output ends of the rising edge identification unit 101 and the falling edge identification unit 102 are respectively connected to the input end of the logic trigger unit 103, the output end of the logic trigger unit 103 is used for being connected to the clock generation unit to control the clock signal to be down-converted, and the clock generation unit 104 can also feed back a clock refresh signal to the logic trigger unit 103.

Preferably, the rising edge identification unit 101 is configured to identify a rising edge of the power supply voltage and generate a first identification signal; a falling edge identifying unit 102 for identifying a falling edge of the power supply voltage and generating a second identification signal; a logic trigger unit 103 for receiving the first and second identification signals from the rising edge and falling edge identification units and the clock refresh signal fed back from the clock generation unit 104, and generating a switch control signal based on the first and second identification signals; and a clock generation unit 104 for controlling the crystal oscillator and the D flip-flop to generate a clock cycle refresh signal based on the switch control signal.

Fig. 4 is a circuit diagram of a bandgap reference stabilization circuit for providing refresh logic based on power supply fluctuations according to the present invention. As shown in fig. 4, the OSC down-conversion circuit of the present invention preferably includes a rising edge identification unit. The rising edge identification unit comprises a first detection capacitor C1, a first detection resistor R1, a first current source I1 and a first field NMOS tube NMOS1; the first detection capacitor C1 is connected in series with the first detection resistor R1, one end of the first detection capacitor C1 is connected with a power supply voltage Vdd, and one end of the first detection resistor R1 is grounded; the first current source I1 is connected with the NMOS1 of the first field effect transistor in series, one end of the first current source is connected with a power voltage Vdd, the other end of the first current source is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is grounded, and the grid electrode of the first current source is respectively connected with the other ends of the first detection capacitor C1 and the first detection resistor R1; and the connection part of the first current source I1 and the first field effect transistor NMOS1 is used as the output end of the rising edge identification unit, and outputs a first identification signal of the rising edge identification unit.

It is understood that the process of detecting, identifying and generating the corresponding signal for the rising edge of the power voltage Vdd by the rising edge identification unit in the present invention is specifically as follows.

When the power supply voltage Vdd is maintained at a high level, the rising edge identification unit has a branch circuit formed by serially connecting the first detection capacitor C1 and the first detection resistor R1, and the branch circuit has the function of passing ac and dc, so that the gate voltage of the first NMOS transistor NMOS1 is maintained at 0 v. Due to the grid voltage state of the first NMOS transistor NMOS1, the NMOS1 is in a cut-off state, and the voltage at the point A is only influenced by the first current source I1, so that the voltage is always kept in a high-voltage state.

When the power supply voltage Vdd is in the falling edge state, although the first detection capacitor C1 functions, since the power supply voltage Vdd is lower at this time, the gate voltage of the first NMOS transistor NMOS1 is still lower and is not enough to support the turn-on of the first NMOS transistor NMOS1, and therefore, the voltage at the point a is still influenced by the first current source I1, and is in the high voltage state.

When the power voltage Vdd is maintained at a low level, the gate voltage of the first NMOS transistor NMOS1 is still at 0 v due to the dc resistance when the first detection capacitor C1 and the first detection resistor R1 are connected in series. At this time, although the power supply voltage Vdd is low, the point a is still in a high voltage state by the first current source I1.

When the power supply voltage Vdd is at a rising edge, the power supply voltage Vdd rises rapidly at this time, and the response speed of the first detection capacitor C1 is slow. The grid voltage of the first NMOS tube NMOS1 is at a high potential under the action of the first detection capacitor C1, and the grid-source voltage difference of the first NMOS tube NMOS1 is increased so as to conduct the NMOS1. Under the action of the conduction of the NMOS1, the potential of the point A is pulled down instantaneously, so that an instantaneous impulse signal is provided for the logic trigger unit as an identification signal.

Preferably, the falling edge identification unit includes a first PMOS transistor PMOS1, a second PMOS transistor PMOS2, a second current source I2, and a second detection capacitor C2; the source electrode of the first PMOS tube PMOS1 is connected with a power supply voltage Vdd, the drain electrode of the first PMOS tube PMOS1 is respectively connected with the source electrode of the second PMOS tube PMOS2 and one end of the second detection capacitor C2, and the grid electrodes of the first PMOS tube and the second PMOS tube are both connected with a first band gap voltage Vbp1; the drain electrode of the second PMOS tube PMOS2 is connected with one end of a second current source I2, and the other end of the second current source I2 is grounded; the other end of the second detection capacitor C2 is grounded; and the drain electrode of the second PMOS pipe PMOS2 and one end of the second current source I2 are used as the output end of the falling edge identification unit, and a second identification signal of the falling edge identification unit is output.

It is understood that the process of detecting, identifying and generating the corresponding signal for the falling edge of the power supply voltage Vdd by the falling edge identification unit in the present invention is specifically as follows.

When the power supply voltage Vdd is maintained at a low level, the second detection capacitor C2 is continuously discharged, the source voltage of the PMOS2 gradually decreases, and the bandgap reference voltage Vbp1 connected to the gate thereof decreases according to the decrease of the power supply voltage Vdd, at this time, although the second PMOS transistor PMOS2 is in a conducting state, the point B is kept at a lower level position under the action of the power supply voltage Vdd and the second current source I2.

When the power supply voltage Vdd is at a rising edge, the bandgap reference voltage Vbp1 rises with the rapid rise of the power supply voltage Vdd, and the current flowing through the two transistors PMOS1 and PMOS2 is large. However, since the second sensing capacitor C2 starts to enter the charging state and the source voltage of the second PMOS transistor PMOS2 will be maintained substantially unchanged, the voltage at the point B will also continue to be at the low potential state.

When the power voltage Vdd is in a high state, the second detection capacitor C2 continues to be charged after the power voltage Vdd is in a rising state. At this time, due to the effect of the bandgap reference voltage, the branch at the point B is continuously turned on, but because the on-state current formed by the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 is small, the potential at the point B is pulled down by the relatively large second current source I2, and the voltage at the point B is continuously at the low potential.

When the power voltage Vdd is at the falling edge, due to the discharging effect of the second detection capacitor C2, the source of the second PMOS transistor PMOS2 is temporarily maintained in the original voltage state, however, the voltage Vbp1 connected to the gate of the PMOS transistor is rapidly reduced along with the reduction of the power voltage, and at this time, the gate-source voltage Vgs of the second PMOS transistor PMOS2 becomes very large, so that the conduction current of the PMOS2 increases, the potential at the point B is not in the low potential state due to the small conduction current, but is rapidly raised along with the rise of the potential at the point B, and thus an impulse signal corresponding to the falling edge of the power voltage is generated.

Preferably, the logic trigger unit comprises a first not gate, a nor gate, a second not gate and an RS flip-flop; the input end of the first NOT gate is connected with the output end of the rising edge identification unit, and the output end of the first NOT gate is connected with one input end of the NOR gate; the other input end of the NOR gate is connected with the output end of the falling edge identification unit, and the output end of the NOR gate is connected with the input end of the second NOR gate; the input end of the second NOT gate is connected with one input end of the RS trigger, and the other input end of the RS trigger inputs a clock refreshing signal fed back by the clock generating unit; the output end of the RS trigger outputs a switch control signal and is connected with the clock generation unit.

It is understood that the logic triggering unit in the present invention is composed of a logic circuit commonly used in the prior art, and can realize the down-conversion control of providing a good clock signal for the clock generation unit, i.e. the Switch control signal Switch referred to herein.

When the Vdd signal is in a rising edge state, the voltage at point a is low. On the other hand, when the power supply voltage signal is in the other state, the voltage at the point a is high. And the voltage at the point A is input to the first input end of the NOR gate after passing through the NOR gate. Therefore, for the first input terminal of the nor gate, the voltage at the first input terminal of the nor gate is in a high state when the power supply voltage is at a rising edge, and is in a low state when the power supply voltage is in other states.

On the other hand, when the power supply voltage Vdd signal is in the falling edge state, the voltage at the point B is high; when the supply voltage Vdd signal is in the other state, the voltage at point B is low. And the voltage at the point B is used as the voltage of a second input end of the NOR gate.

Fig. 5 is a schematic diagram of a switching control signal generated and controlled by a bandgap reference stabilization circuit for providing refresh logic based on power supply fluctuations according to the present invention. As shown in fig. 5, after passing through the internal logic of the nor gate, the generated signal varies according to the voltage states of the two points a and B. Then, the output signal of the NOR gate is inverted again after passing through the NOR gate. In summary, the generated impulse signal Pulse transitions following the switching state of the high and low levels of the power supply voltage Vdd signal. Specifically, the output of the short-time impulse signal Pulse is high when the power supply voltage Vdd is at a rising edge or a falling edge, and is low when the power supply voltage Vdd is at another state.

Preferably, the OSC down-conversion circuit generates an impulse signal Pulse based on a rising edge and a falling edge of the power supply voltage; the RS trigger receives the clock refresh signal and the impulse signal Pulse and generates a switch control signal based on the RS trigger logic.

The two input ends of the trigger are respectively connected with the impulse signal Pulse and the Refresh signal Refresh. In particular, the refresh signal may be based on a method in the prior art or a refresh signal generated by a method in the clock generation unit of the present invention. The signal is usually obtained by performing addition, subtraction and combination operations on periodic signals with different frequencies. The cycle length of the refresh signal, and the length of the refresh period, may be modified based on different operational parameters, as required by the bandgap reference circuit.

That is, when the Refresh signal Refresh is in a normal state, the bandgap reference circuit may generate the bandgap reference voltage according to a voltage provided by a high level signal. The Refresh logic is provided in order to prevent the bandgap reference voltage from gradually rising, and thus the bandgap reference voltage does not rise any more but is stable as a low level signal when the Refresh signal Refresh is in a Refresh state. After a period, the refresh signal repeats the above operations.

After the Refresh signal Refresh and the impulse signal Pulse pass through the RS flip-flop together, the output of the RS flip-flop is realized according to the logic of the RS flip-flop. Preferably, when the RS flip-flop receives the clock Refresh signal in the Refresh state and simultaneously receives the impulse signal Pulse, the Switch control signal Switch switches the logic state to the high level output until the Refresh state of the clock Refresh signal Refresh is ended.

Specifically, when the Refresh signal Refresh is in a high state, and the signal passes through the RS flip-flop, the Switch control signal Switch is in a low state no matter where the impulse signal Pulse is. When the Refresh signal Refresh is in a low level Refresh state, and the circuit does not detect the impulse signal Pulse, the output Switch signal maintains a low level; at this time, when the circuit detects the impulse signal Pulse, the output Switch signal inverts the Refresh signal Refresh to output a high-level signal. The signal output by the RS flip-flop is the Switch control signal Switch in the present invention.

Preferably, the clock generation unit comprises a first input branch, a second input branch and a crystal oscillator branch; the first input branch circuit is used for realizing the on-off of the branch circuit based on a switch control signal output by the logic trigger unit and providing a part of input current I4 for the crystal oscillator branch circuit when the first input branch circuit is on; the second input branch is used for receiving the clock signal CLK fed back by the crystal oscillator branch, controlling the size of the branch current I5 based on the feedback and providing partial input current I5 for the crystal oscillator branch; and the crystal oscillator branch is used for generating a clock signal CLK and a delayed clock refreshing signal.

It can be understood that the clock generation unit in the present invention can control the period length of the clock period signal generated by the Crystal Oscillator (OSC) in the Crystal Oscillator branch according to the sum of the currents generated in the first input branch and the second input branch.

Preferably, the first input branch comprises a third PMOS transistor PMOS3, a fifth PMOS transistor PMOS5 and a third capacitor C3; the source electrode of the third PMOS tube PMOS3 is connected to a power supply voltage Vdd, the gate electrode of the third PMOS tube PMOS3 is connected to a second band gap voltage Vbp2, and the drain electrode of the third PMOS tube PMOS is connected with the source electrode of the fifth PMOS tube PMOS 5; the grid electrode of the fifth PMOS tube PMOS5 is connected with the output end of the logic trigger unit, receives a switch control signal output by the logic trigger unit, and the drain electrode of the fifth PMOS tube PMOS5 is connected with one end of a third capacitor C3; the other end of the third capacitor is grounded.

It is understood that the two PMOS transistors PMOS3 and PMOS5 included in the first input branch of the present invention can be turned on or off according to the second bandgap voltage and the magnitude of the switch control signal. And the third capacitor C3 can realize the charging or discharging of the capacitor C3 according to whether the two PMOS transistors are in a conducting state.

Specifically, when PMOS5 is turned on with the Switch control signal Switch in the low voltage state, the first input branch will also be turned on, the capacitor C3 is in the charging state, and the current I4 generated by the first input branch is input into the OSC. When PMOS5 is turned off with the Switch control signal Switch in the high voltage state, the first input branch will also be turned off, while only the second input branch is still charging the capacitor C3 and simultaneously supplying current to the OSC branch.

Preferably, the second input branch comprises a fourth PMOS transistor PMOS4, a sixth PMOS transistor PMOS6 and a second NMOS transistor NMOS2; the source electrode of the fourth PMOS tube is connected with a power supply voltage Vdd, the grid electrode of the fourth PMOS tube is connected with a second band gap voltage Vbp2, and the drain electrode of the fourth PMOS tube is connected with the source electrode of a sixth PMOS tube PMOS 6; the drain electrode of a sixth PMOS (P-channel metal oxide semiconductor) transistor PMOS6 is connected with the drain electrode of the second NMOS transistor, and the grid electrode of the sixth PMOS transistor PMOS6 is connected with the grid electrode of the second NMOS transistor; the source electrode of the second NMOS tube is grounded.

It will be appreciated that the second input branch is also used to supply current to the oscillator branch OSC. The fourth PMOS transistor PMOS4 is turned on according to the second bandgap voltage, and the sixth PMOS transistor PMOS6 and the second NMOS transistor NMOS2 are alternately turned on or off according to the feedback of the clock signal generated by the crystal oscillator OSC.

Preferably, when the clock signal CLK is fed back to be the high level output, the sixth PMOS transistor PMOS6 in the second input branch is turned off, the second NMOS transistor NMOS2 is turned on, and the third capacitor C3 is in the discharge state; when the clock signal CLK is fed back to be output at a low level, the sixth PMOS transistor PMOS6 in the second input branch is turned on, the second NMOS transistor NMOS2 is turned off, and the third capacitor C3 is in a charging state.

The OSC oscillates with the repeated charging and discharging of the third capacitor, thereby generating a stable CLK clock signal.

It can be understood that when the Switch control signal Switch is turned on in the low voltage state, the first input branch and the second input branch charge the capacitor C3 together, the charging speed of the capacitor C3 is faster, and the current received by the OSC is also larger, and at this time, the period of the crystal oscillator generated by the OSC is shorter, so the period of the clock signal CLK is shorter. On the other hand, when the PMOS5 is turned off when the Switch control signal Switch is in the high voltage state, the first input branch is turned off and the current I4 is not generated. At this time, only the second input branch charges the capacitor C3 at a slow speed, so the period time of the crystal oscillator generated by the OSC is long, and the period of the CLK clock signal is also long.

Thus, the period of the clock signal is extended during the time that the refresh signal is received, i.e., when Vdd is on the falling edge.

Preferably, the crystal oscillator branch comprises a crystal oscillator OSC, a D flip-flop Dffr, and a clock refresh signal arithmetic unit; the input end of the crystal oscillator OSC is respectively connected with the drain electrode of a fifth PMOS (P-channel metal oxide semiconductor) transistor PMOS5, one end of a third capacitor C3, the drain electrode of a sixth PMOS transistor PMOS6 and the grid electrode of a second NMOS (N-channel metal oxide semiconductor) transistor NMOS2, and the output end of the crystal oscillator OSC is connected with the input end of a D trigger Dffr; the output end of the crystal oscillator OSC is simultaneously connected with the grid electrode of the sixth PMOS tube PMOS6 and the grid electrode of the second NMOS tube NMOS2 and is used for feeding back a clock signal CLK to the sixth PMOS tube PMOS6 and the second NMOS tube NMOS2; the first output end and the second output end of the D trigger Dffr are respectively connected with the input end of the clock refreshing signal arithmetic unit; the clock refreshing signal arithmetic unit outputs a clock refreshing signal as the input of the RS trigger in the logic trigger unit.

In summary, from the analysis of the first input branch and the second input branch, it can be known that the first input branch is turned on when the Switch signal is at a low level, i.e. the power supply voltage is in a stable high level state or a stable low level state. The OSC signal receives an input current of I4+ I5 at this time.

When the Switch signal is high, i.e. the power supply voltage is at a rising or falling edge, the first input branch is turned off, the input current received by the crystal oscillator OSC is I5, and a small part of the current is generated by the discharge of the third capacitor C3. At this time, it is known that the current generated by discharging the third capacitor C3 is smaller than the original current I4, and the discharging current is gradually reduced with the passage of time. Thus, as the input current decreases, the OSC signal gradually decreases, thereby generating a down-conversion of the clock signal within the current clock.

Preferably, the D flip-flop is configured to identify a clock signal output by the output terminal of the crystal oscillator OSC, and generate a periodic signal that is a set multiple of a clock period. The D flip-flop of the present invention functions the same as the D flip-flop of the prior art, recognizing the rising and falling edges of the clock cycle, and modifying the output level of the flip-flop based on this information.

Preferably, the clock refresh signal operation unit is used for realizing the superposition of clock signals with different frequencies based on the first output and the second output of the D flip-flop and generating the clock refresh signal based on the parameter requirement of the band-gap reference circuit.

As shown in fig. 5, the clock Refresh signal Refresh generates a waveform of one cycle in a low state for a longer time as the clock signal goes down.

The signal duration in the refreshing state in the period completely covers the BG oscillation waveform of the band-gap reference voltage signal. Therefore, after the bandgap voltage output signal BG is recovered through the refresh process, the bandgap voltage generated in the next period will not change too much. Therefore, the method in the invention further stabilizes the bandgap voltage of the bandgap reference source.

Compared with the prior art, the band-gap reference stabilizing circuit for providing the refreshing logic based on the power supply fluctuation can accurately identify the rising edge and the falling edge of a power supply voltage Vdd signal, and control the input end of an OSC crystal oscillator according to the identification and a clock refreshing signal, so that the frequency reduction of a clock periodic signal is realized, namely, the time of the refreshing signal is prolonged, and the voltage of a band-gap reference source can be recovered to a normal value when the refreshing of one period is finished. .

The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for the purpose of limiting the scope of the present invention, and on the contrary, any modifications or modifications based on the spirit of the present invention should fall within the scope of the present invention.

Claims

1. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple, comprising:

the circuit comprises a rising edge identification unit, a falling edge identification unit, a logic trigger unit and a clock generation unit; wherein,

the rising edge identification unit is used for identifying the rising edge of the power supply voltage and generating a first identification signal;

the falling edge identification unit is used for identifying the falling edge of the power supply voltage and generating a second identification signal;

the logic trigger unit is used for receiving the first and second identification signals from the rising edge and falling edge identification units and the clock refresh signal fed back from the clock generation unit and generating a switch control signal based on the first and second identification signals;

and the clock generation unit is used for controlling the crystal oscillator and the D trigger to generate clock period refreshing signals based on the switch control signals.

2. A bandgap reference stabilization circuit as recited in claim 1 for providing refresh logic based on power supply fluctuations, wherein:

the rising edge identification unit comprises a first detection capacitor C1, a first detection resistor R1, a first current source I1 and a first field NMOS transistor NMOS1; wherein,

the first detection capacitor C1 is connected in series with the first detection resistor R1, one end of the first detection capacitor C1 is connected with a power supply voltage Vdd, and one end of the first detection resistor R1 is grounded;

the first current source I1 is connected with the NMOS1 in series, one end of the first current source is connected with a power supply voltage Vdd, the other end of the first current source is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is grounded, and the grid electrode of the first current source is respectively connected with the other ends of the first detection capacitor C1 and the first detection resistor R1;

and the joint of the first current source I1 and the first field effect transistor NMOS1 is used as the output end of the rising edge identification unit, and outputs a first identification signal of the rising edge identification unit.

3. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 1, wherein:

the falling edge identification unit comprises a first PMOS (P-channel metal oxide semiconductor) transistor PMOS1, a second PMOS transistor PMOS2, a second current source I2 and a second detection capacitor C2; wherein,

the source electrode of the first PMOS tube PMOS1 is connected with a power supply voltage Vdd, the drain electrode of the first PMOS tube PMOS1 is respectively connected with the source electrode of the second PMOS tube PMOS2 and one end of a second detection capacitor C2, and the grid electrodes of the first PMOS tube and the second PMOS tube are both connected with a first band gap voltage Vbp1;

the drain electrode of the second PMOS tube PMOS2 is connected with one end of a second current source I2, and the other end of the second current source I2 is grounded;

the other end of the second detection capacitor C2 is grounded;

and the drain electrode of the second PMOS tube PMOS2 and one end of the second current source I2 are used as the output end of the falling edge identification unit to output a second identification signal of the falling edge identification unit.

4. A bandgap reference stabilization circuit as recited in claim 1 for providing refresh logic based on power supply fluctuations, wherein:

the logic trigger unit comprises a first NOT gate, a NOR gate, a second NOT gate and an RS trigger; wherein,

the input end of the first not gate is connected with the output end of the rising edge identification unit, and the output end of the first not gate is connected with one input end of the nor gate;

the other input end of the NOR gate is connected with the output end of the falling edge identification unit, and the output end of the NOR gate is connected with the input end of a second NOR gate;

the input end of the second NOT gate is connected with one input end of an RS trigger, and the other input end of the RS trigger inputs the clock refreshing signal fed back by the clock generating unit;

and the output end of the RS trigger outputs a switch control signal and is connected with the clock generation unit.

5. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 1, wherein:

the clock generation unit comprises a first input branch, a second input branch and a crystal oscillator branch; wherein,

the first input branch circuit is used for realizing the on-off of the branch circuit based on the switch control signal output by the logic trigger unit and providing a part of input current I4 for the crystal oscillator branch circuit when the first input branch circuit is on;

the second input branch is used for receiving the clock signal CLK fed back by the crystal oscillator branch, controlling the size of the branch current I5 based on the feedback, and providing a part of input current I5 for the crystal oscillator branch;

the crystal oscillator branch is used for generating a clock signal CLK and a delayed clock refreshing signal.

6. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 1, wherein:

the first input branch comprises a third PMOS (P-channel metal oxide semiconductor) transistor PMOS3, a fifth PMOS transistor PMOS5 and a third capacitor C3; wherein,

the source electrode of the third PMOS tube PMOS3 is connected with a power supply voltage Vdd, the grid electrode of the third PMOS tube PMOS3 is connected with a second band gap voltage Vbp2, and the drain electrode of the third PMOS tube PMOS is connected with the source electrode of the fifth PMOS tube PMOS 5;

the grid electrode of the fifth PMOS tube PMOS5 is connected with the output end of the logic trigger unit, receives a switch control signal output by the logic trigger unit, and the drain electrode of the fifth PMOS tube PMOS5 is connected with one end of the third capacitor C3;

the other end of the third capacitor is grounded.

7. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 5, wherein:

the second input branch comprises a fourth PMOS tube PMOS4, a sixth PMOS tube PMOS6 and a second NMOS tube NMOS2; wherein,

the source electrode of the fourth PMOS tube is connected with a power supply voltage Vdd, the grid electrode of the fourth PMOS tube is connected with a second band gap voltage Vbp2, and the drain electrode of the fourth PMOS tube is connected with the source electrode of a sixth PMOS tube PMOS 6;

the drain electrode of the sixth PMOS tube PMOS6 is connected with the drain electrode of the second NMOS tube, and the grid electrode of the sixth PMOS tube PMOS6 is connected with the grid electrode of the second NMOS tube;

and the source electrode of the second NMOS tube is grounded.

8. A bandgap reference stabilization circuit as recited in claim 6 for providing refresh logic based on power supply fluctuations, wherein:

the crystal oscillator branch comprises a crystal oscillator OSC, a D trigger Dffr and a clock refreshing signal arithmetic unit; wherein,

the input end of the crystal oscillator OSC is respectively connected with the drain electrode of a fifth PMOS (P-channel metal oxide semiconductor) transistor PMOS5, one end of a third capacitor C3, the drain electrode of a sixth PMOS transistor PMOS6 and the grid electrode of a second NMOS (N-channel metal oxide semiconductor) transistor NMOS2, and the output end of the crystal oscillator OSC is connected with the input end of a D trigger Dffr;

the output end of the crystal oscillator OSC is connected to the gate of the sixth PMOS transistor PMOS6 and the gate of the second NMOS transistor NMOS2 at the same time, and is configured to feed back a clock signal CLK to the sixth PMOS transistor PMOS6 and the second NMOS transistor NMOS2;

the first output end and the second output end of the D trigger Dffr are respectively connected with the input end of the clock refreshing signal operation unit;

and the clock refreshing signal operation unit outputs a clock refreshing signal which is used as the input of the RS trigger in the logic trigger unit.

9. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 4, wherein:

the OSC frequency reduction circuit generates impulse signals Pulse based on the rising edge and the falling edge of the power supply voltage;

and the RS trigger receives the clock refreshing signal and the impulse signal Pulse and generates the switch control signal based on RS trigger logic.

10. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 9, wherein:

when the RS flip-flop receives that the clock Refresh signal is in a Refresh state and receives the impulse signal Pulse at the same time, the Switch control signal Switch switches the logic state to a high level and outputs the high level until the Refresh state of the clock Refresh signal Refresh is finished.

11. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 6, wherein:

when the switch control signal is output in a high level, the first input branch is cut off, and the second input branch charges a third capacitor C3;

when the switch control signal is output at a low level, the first input branch is turned on, and the first input branch and the second input branch charge the third capacitor C3 at the same time.

12. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 7, wherein:

when the clock signal CLK is fed back to be output at a high level, a sixth PMOS tube PMOS6 in the second input branch circuit is cut off, a second NMOS tube NMOS2 is conducted, and the third capacitor C3 is in a discharging state;

when the clock signal CLK is fed back to be output at a low level, the sixth PMOS transistor PMOS6 in the second input branch is turned on, the second NMOS transistor NMOS2 is turned off, and the third capacitor C3 is in a charging state.

13. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 8, wherein:

the D flip-flop is used for identifying the clock signal output by the output end of the crystal oscillator OSC and generating a periodic signal which is in a set multiple of the clock period.

14. A bandgap reference stabilization circuit for providing refresh logic based on power supply ripple as recited in claim 8, wherein:

the clock refreshing signal operation unit realizes the superposition of clock signals with different frequencies based on the first output and the second output of the D trigger, and generates clock refreshing signals based on the parameter requirements of the band-gap reference circuit.