CN112688539A

CN112688539A - High-side switch driving circuit with short circuit detection function

Info

Publication number: CN112688539A
Application number: CN202011509233.6A
Authority: CN
Inventors: 王贵奇; 李俊宏; 张国俊
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2021-04-20

Abstract

Belongs to the technical field of electronic circuits. The switching tube NM3 is turned on under the control of the enable signal EN, the two pairs of MOS tubes connected with the cross coupling are connected with each other, the two externally input square waves have the same frequency and opposite phases, the high voltage is VIN square waves, the capacitor C3 is alternately charged, the grid voltage of the main switching tube LDMOS is raised, the main switching tube LDMOS is smoothly conducted, and the output voltage OUT is obtained. The grid voltage is stabilized through the serial connection of 8 diodes, and the situation that the LDMOS of the power tube is damaged due to overlarge grid voltage is avoided. The Zener tube Z1 ensures that the amplitude of the grid voltage is higher than the source output voltage by about 5V. When the voltage of the output end OUT is reduced to 8.3V lower than the Vbb voltage, the voltage drop of the branch circuit where the Z2 is located makes the branch circuit conduct reversely, the current is increased, the output SC is low level through the current mirror and the hysteresis comparator, and the indicating circuit is short-circuited at the moment. The design can quickly switch off the main switch tube and quickly detect the short circuit state of the circuit.

Description

High-side switch driving circuit with short circuit detection function

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a high-side switch driving circuit with a short-circuit detection function.

Background

The high-side power switch driving circuit integrates a power device, a grid driving circuit and a protection circuit in the same chip, and has the high-quality characteristics of small volume, light weight, high power density, high reliability and the like. The high-side gate driving circuit is an important circuit, can drive and control the on and off of a high-side power device, ensures the normal work of the power device, and determines whether the performance of the power device can be fully utilized or not.

According to the conduction characteristic of the MOS tube, the MOS tube can be conducted only when the grid-source voltage is larger than the threshold voltage. The conduction is divided into a linear region and a saturation region, under the condition of the same device and the same gate-source voltage, the resistance of the linear region is far smaller than that of the saturation region, the larger the gate-source voltage is, the smaller the on-resistance is, therefore, for a high-side N-type power device, the grid boosting is needed, and the charge pump is a circuit for realizing the function.

Short-circuit protection is used when the load is short-circuited. The transient fault current generated during short circuit generally far exceeds the maximum current multiple of a circuit system, and the huge short-circuit current can damage a power switch device, so that the short-circuit state of the circuit needs to be detected, and the short-circuit state is fed back in time to avoid the damage of a chip.

Disclosure of Invention

In view of the above-mentioned description of the high-side power switch circuit, the present invention provides a high-side switch driving circuit with a short-circuit detection function. The grid voltage raising circuit comprises a cross-coupled charge pump structure for realizing grid voltage raising, a grid driving and protecting structure and a short circuit detection structure.

Ibias is a bias current source, NM1 and NM2 form a basic current mirror, NM1 has its drain connected to Ibias and its source connected to ground. NM2 has gate connected to NM1, source connected to ground, and drain connected to NM 3.

PM1 and PM2 constitute a current mirror, NM3 is a switching tube, EN is an enable signal, and Vbb is an input voltage. The sources of PM1 and PM2 are connected with an input voltage Vbb, the drain of PM1 is connected with the drain of NM3, and the gates of PM1 and PM2 are connected.

B1 is a cross-coupled charge pump for boosting and transferring the supply voltage. The MOS transistor comprises MOS transistors NM4, NM5, PM3, PM4, capacitors C1, C2, C3 and a diode D1.

NM4 and NM5 are MOS transistors coupled and connected in a first pair. With NM4 and NM5 substrates both grounded. The drains of NM4 and NM5 are connected to the drain of PM2. The gate of NM4 is connected to the source of NM5 and to the top plate of C2 and the drain of PM 3. The lower plate of C2 is connected with square wave VN input from outside.

Similarly, the gate of NM5 is connected to the source of NM4 and to the top plate of C1 and the drain of PM 4. The lower plate of C1 is connected to the square wave VP input from outside. Drain electrode

And the PM3 and the PM4 are MOS transistors connected in a second pair coupling mode. The gate of PM3 interfaces with the gate of PM 4. The drain of PM4 is connected to the gate of PM 3. The sources of PM3 and PM4 are connected, and are connected to the anode of diode D1 and the top plate of C3. With the lower plate of C3 grounded.

B2 is a gate driving and protecting structure, including a main switching tube LDMOS, a mirror tube M _ LDMOS, 8 diodes D2, D3, D8, D9, a Zener diode Z1, resistors R1, R2, R3, R4, MOS tubes NM6 and NM 7.

The drain of NM6 is connected to the negative electrode of D1 and to the positive electrodes of R1 and R2. The gate of NM6 is connected to the output of inverter INV, the input of which is connected to enable signal EN. NM6 source is grounded.

The negative pole of R1 is connected with the negative pole of Z1, and the positive pole of Z1 is connected with the output end OUT. The cathode of the R2 is connected with the anode of the D2, 8 diodes D2, D3, D8 and D9 are connected in series, and finally the cathode of the D9 is connected with the ground voltage input end Vbb.

The drain of NM7 is connected to the cathode of R2, and the source is connected to the voltage output terminal OUT. The grid is connected with the cathode of the R3 and the anode of the R4. R4 is connected to the output OUT.

The grid electrode of the main switching tube LDMOS is connected with the negative electrode of the drain electrode R2 of the NM7, the drain electrode is connected with the input end Vbb, and the source electrode is connected with the output end OUT. The grid electrode of the mirror image tube M _ LDMOS is connected with the grid electrode of the LDMOS, and the drain electrode of the mirror image tube M _ LDMOS is also connected with the input end Vbb. The source is connected with the anode of the R3.

B3 is a short-circuit detection structure for detecting a short-circuit at the output terminal OUT. The device comprises MOS transistors PM5, PM6, PM7, PM8, NM8, NM9, NM10, NM11, NM12, NM13 and NM14, resistors R5, R6, R7, a diode D10, a Zener tube Z2 and a capacitor C4.

Wherein the gate of the PM5 is connected to the gate and drain of the PM1, the source is connected to the voltage input Vbb, the drain is connected to the drain and gate of NM8 and the gate of NM9, as described earlier. The source of NM8 is connected to the drain and gate of NM10 and the gate of NM11, and the drain is connected to the output terminal OUT. NM11 has its drain connected to NM9 source and source connected to OUT.

The positive electrode of Z2 is connected to the drain of NM9, the negative electrode of Z2 is connected to the negative electrode of diode D2, and the positive electrode of D2 is connected to the drain and gate of PM6 and the gate of PM 7.

The source of PM6 and the source of PM7 are all connected to input Vbb, the drain of PM7 is connected to the positive pole of R5, the negative pole of R5 is connected to the positive pole of R6, the negative pole of R6 is connected to the positive pole of R7, and the negative pole of R7 is grounded.

The upper polar plate of the C4 is connected with the anode of the R7, and the lower polar plate is grounded. The PM8 is connected with the grids of NM12 and NM13 and the upper plate of C4. The source of PM8 is connected to voltage source VDD, and the drain is connected to the drain of NM12 and the gate of NM 14. The source of NM12 is connected to the drain of NM13 and the drain of NM14, and the substrate is grounded. The drain of NM14 is connected to voltage source VDD, and the gate is connected to output port SC.

The invention can rapidly raise the grid voltage of the main power switch tube to a fixed value higher than a certain value of the power supply voltage under different voltages, and can well control the on-off of the switch tube. The short circuit detection can timely feed back whether the circuit is short or not.

Drawings

Fig. 1 is a circuit diagram of a gate driving circuit with short circuit detection function according to the present invention.

Fig. 2 is a simulation waveform of the cross-coupled pump gate voltage ramp and the resulting output voltage OUT.

Fig. 3 is a waveform diagram of a short circuit detection simulation.

Detailed Description

In order to make the aforementioned features and functions of the present invention more clear, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows an overall circuit diagram of the present invention, B1 is a cross-coupled charge pump structure for realizing gate voltage boosting, B2 is a gate driving and protecting structure, and B3 is a short circuit detection structure.

NM1 and NM2 constitute a current mirror, Ibias is a bias current source, and PM1 and PM2 also constitute a set of current mirrors. NM3 is a switch, when the enable signal EN is high, NM3 is turned on, and the branch where NM3 is located is turned on to provide gate voltage for PM2.

The operation of the cross-coupled pump of B1 is as follows: VP and VN are square waves with the same frequency and opposite phases generated by the outside, the high voltage is VIN, and the circuit starts to enable all capacitors to have no charge.

And (3) setting the voltage of the node A as Vx, and charging the C1 and the C2:

VP is high level, VN is low level, voltage at two ends of the capacitor C1 cannot suddenly change, at the moment, voltage of an upper plate of the capacitor C1 is VIN, the NM5 tube is opened, the voltage Vx charges the capacitor C2, and after a certain period, voltage on the capacitor C2 is Vx.

When VP is at a low level and VN is at a high level, the voltage at two ends of the capacitor C2 cannot suddenly change, the voltage of the upper plate of the capacitor C2 is VIN, the NM4 tube is opened, the capacitor C1 is charged by the voltage Vx, and after a plurality of cycles, the voltage on the capacitor C1 is Vx.

The discharging process of the capacitors C1 and C2 to the load is as follows:

when VP is high and VN is low, the voltage across the capacitor C1 cannot suddenly change, the upper plate voltage of C1 is 2VIN, the upper plate voltage of C2 is already charged to VIN, the PM3 tube is turned on, and C1 charges the load capacitor C3.

When VP is low and VN is high, the voltage across the capacitor C2 cannot change suddenly, the upper plate voltage of C2 is 2VIN, the upper plate voltage of C1 is already charged to VIN, at this time, the PM4 tube is turned on, and C2 charges the load capacitor C3.

The two branches alternately charge the capacitor C3, and the switch tube has no threshold loss, so the charging efficiency is very high.

The gate driving and protection process of B2 is as follows: after the charge pump raises the voltage, the charge is transferred to the gate of the main power tube through the diode D1 and the resistor R2. When the circuit is abnormal, the enable signal EN is low level, the gate of NM6 is high level through the inverter, NM6 is opened, the gate charge is released to the ground, and the power tube is turned off.

Under the BCD process, the breakdown voltage of a grid source is less than 10V, the amplitude of the grid voltage needs to be stabilized, and Z1 is a Zener diode and can ensure that the amplitude of the grid voltage is about 5V higher than the output voltage of the source electrode.

D2, D3, D8 and D9 are 8 diodes connected in series, the conduction voltage drop of a single diode is 0.7V, and the conduction voltage drop of 8 diodes is about 5V, so that the gate voltage is stabilized, and the condition that the gate voltage is not too large to cause damage to the LDMOS of the power tube is ensured.

The M _ LDMOS and the power tube LDMOS share a grid electrode and a drain electrode, and the source electrode area of the power tube is K times of that of the M _ LDMOS. In normal operation, the self-current limiting structure consisting of R3, R4 and NM7 does not work. When the load current suddenly increases, the current flowing through R3 and R4 also increases, so that the voltage drop of R3 and R4 increases, the resistance values of R3 and R4 are adjusted to open NM7, the gate charge is rapidly released, the gate voltage decreases, and the power transistor LDMOS exits the linear operating region. And the self-current-limiting protection of the grid is realized.

Fig. 2 is a simulation waveform of the cross-coupled pump gate voltage ramp and the resulting output voltage OUT. As can be seen, when the enable signal EN is high, the GATE voltage V _ GATE rapidly rises to a value higher than the power voltage and is stable. The power tube is turned on and the output voltage OUT rises to a stable value slightly lower than the supply voltage. Until EN is low, the gate charge is quickly released, turning off the power transistor, and OUT also becomes 0V.

The short circuit detection structure of B3 works as follows: PM5 and PM1 form a current mirror, and NM8, NM9, NM10 and NM11 form a cascode current mirror. PM6, PM7 constitute a pair of current mirrors. NM12, NM13, NM14, PM8 and voltage source VDD constitute a hysteresis comparator.

The reverse conduction voltage drop of the zener Z2 is about 5.7V. When the circuit normally works, when the OUT is not short-circuited, the voltage difference between the OUT voltage of the output end and the input voltage Vbb is small, the Z2 cannot be conducted reversely, the current of the branch where the Z2 is located is very small, the branches where the resistors R5, R6 and R7 are located are also small, and the voltage drop on the R7 is small. The output SC of the hysteresis comparator is high at 5V, indicating that the circuit is not short-circuited.

When the voltage of the output end OUT is reduced to be lower than the Vbb voltage by 8.3V, the branch circuit where the Z2 is located is subjected to voltage drop to conduct the branch circuit in the reverse direction, and the Zener diode current conducted in the reverse direction is increased according to the characteristics of the Zener diode. The branch current of the resistor R7 also increases, and the voltage drop across R7 increases, so that the hysteresis comparator output SC is low, indicating that a short circuit condition occurs in the circuit.

Fig. 3 is a waveform diagram of short circuit detection simulation, when the circuit normally works, the voltage of the output terminal OUT suddenly drops, and when the voltage of the OUT drops to a voltage difference with the input voltage Vbb larger than 8.3V, the detection signal SC becomes low level, that is, an output short circuit occurs.

The embodiments described herein are meant to aid the reader in understanding the principles of the invention and are not meant to be limiting. Any person skilled in the art can make various other specific modifications and combinations according to the teachings of the present invention without departing from the spirit thereof, and these modifications and combinations are still within the scope of the present invention.

Claims

1. A high-side switch driving circuit with a short-circuit detection function is characterized in that: the high-voltage power supply comprises a cross-coupled charge pump unit for realizing grid voltage lifting, a grid driving and protecting unit and a short circuit detection unit, wherein the short circuit detection unit comprises MOS (metal oxide semiconductor) tubes PM1, PM2...... An 8, NM1, NM2.. An 14, diodes D1, D2... An D10, zener tubes Z1 and Z2, resistors R1 and R2.. An R7, and capacitors C1, C2, C3 and C4.

2. The high-side switch drive circuit with short-circuit detection function according to claim 1, characterized in that: the control switch tube NM3 of the enable signal EN, the two pairs of MOS tubes NM4 and NM5 and PM3 and PM4 are connected in a cross-coupling mode, the two externally input frequencies are the same, the phases are opposite, the square waves VP and VN with high voltage VIN alternately charge the capacitor C3, and the grid voltage of the main switch tube LDMOS is raised.

3. The high-side switch drive circuit with short-circuit detection function according to claim 1, characterized in that: the grid voltage is stabilized through the serial connection of 8 diodes, the situation that the LDMOS of the power tube is damaged due to overlarge grid voltage is guaranteed, and the situation that the amplitude of the grid voltage is about 5V higher than the output voltage of the source electrode is guaranteed through the Zener tube Z1.

4. The high-side switch drive circuit with short-circuit detection function according to claim 1, characterized in that: when the voltage of the output end OUT is reduced to 8.3V lower than the Vbb voltage, the voltage drop of the branch circuit where the Z2 is located makes the branch circuit conduct reversely, the current is increased, the output SC is low level through the current mirror formed by the PM6 and the PM7 and the hysteresis comparator, and the short-circuit condition of the circuit is indicated at the moment.

5. The high-side switch drive circuit with short-circuit detection function according to claim 1, characterized in that:

the main switching tube LDMOS is an N-channel MOS tube, the mirror image tube M _ LDMOS is also an N-channel MOS tube, and the mirror image tube M _ LDMOS and the main switching tube are in a common-gate common-drain connection mode.