CN114978152A - Latch circuit and digital-to-analog converter comprising same - Google Patents
Latch circuit and digital-to-analog converter comprising same Download PDFInfo
- Publication number
- CN114978152A CN114978152A CN202210503095.3A CN202210503095A CN114978152A CN 114978152 A CN114978152 A CN 114978152A CN 202210503095 A CN202210503095 A CN 202210503095A CN 114978152 A CN114978152 A CN 114978152A
- Authority
- CN
- China
- Prior art keywords
- switching device
- level
- terminal
- turned
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 230000007704 transition Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The application relates to a latch circuit and a digital-to-analog converter including the same. The latch circuit receives a data signal, a clock signal, and the circuit includes an output portion that generates an output signal and first and second portions connected in series, wherein: the first part is coupled to a high level and includes a first switching device and a second switching device connected in series, wherein the first switching device is controlled to be turned on by a first level of a data signal and the second switching device is controlled to be turned on by a second level of a clock signal; the second portion is coupled to a low level and includes a third switching device and a fourth switching device connected in series, wherein the third switching device is turned on by being controlled by a second level of the clock signal and the fourth switching device is turned on by being controlled by an opposite level of the first level of the data signal; and an output section coupled between the first section and the second section to generate an output signal.
Description
Technical Field
The present application relates to the field of digital signal processing, and in particular, to a latch circuit and a digital-to-analog converter including the same.
Background
High speed latches are an important module in high speed analog to digital converters. A high speed latch will be able to convert a data bit into, for example, a differential signal for use by an analog to digital converter to generate an analog signal output. However, an adc generally includes a plurality of latches, and the skew (skew) between the latches determines the noise performance of the adc output.
Accordingly, there is a need for an improved latch circuit.
Disclosure of Invention
Embodiments of the present application provide a latch circuit and a digital-to-analog converter including the same for reducing a deviation between latch circuits.
According to an aspect of the present application, a latch circuit is provided. The circuit receives a data signal, a clock signal, and the circuit includes an output portion that generates an output signal and first and second portions connected in series, wherein: the first portion is coupled to a high level and includes a first switching device and a second switching device connected in series, wherein the first switching device is controlled to be turned on by a first level of the data signal and the second switching device is controlled to be turned on by a second level of the clock signal; the second portion is coupled to a low level and includes a third switching device and a fourth switching device connected in series, wherein the third switching device is turned on under control of the second level of the clock signal and the fourth switching device is turned on under control of an opposite level of the first level of the data signal; and the output section is coupled between the first section and the second section to generate the output signal.
In some embodiments of the present application, optionally, the low level is a system ground level.
In some embodiments of the present application, optionally, the first level is a low level or a high level, and an opposite level of the first level is a corresponding high level or a low level; and the second level is a low level or a high level.
In some embodiments of the present application, optionally, the first switch device has a first terminal and a second terminal controlled by the first level to be turned on, wherein the first terminal is switched to a high level; and the second switching device has a third terminal and a fourth terminal which are turned on by the second level control, wherein the third terminal is connected to the second terminal, and the fourth terminal is connected to the second section and the output section.
In some embodiments of the present application, optionally, the second switching device has a third terminal and a fourth terminal which are controlled by the second level to conduct, wherein the third terminal is switched in a high level; and the first switching device has a first terminal and a second terminal which are turned on by the first level control, wherein the first terminal is connected to the fourth terminal, and the second terminal is connected to the second section and the output section.
In some embodiments of the present application, optionally, the third switching device has a fifth terminal and a sixth terminal controlled by the second level to be turned on, wherein the fifth terminal is connected to the first part and the output part; and the fourth switching device has a seventh terminal and an eighth terminal turned on by an opposite level of the first level, wherein the seventh terminal is connected to the sixth terminal, and the eighth terminal is connected to the low level.
In some embodiments of the present application, optionally, the fourth switching device has a seventh terminal and an eighth terminal which are controlled to be turned on by an opposite level of the first level, wherein the seventh terminal is connected to the first portion and the output portion; and the third switching device has a fifth terminal and a sixth terminal controlled by the second level to be turned on, wherein the fifth terminal is connected to the eighth terminal, and the sixth terminal is connected to the low level.
In some embodiments of the present application, optionally, any one of the first switching device, the second switching device, the third switching device and the fourth switching device is a triode or a field effect transistor.
In some embodiments of the present application, optionally, one of the first switching device and the fourth switching device is an NPN-type transistor, and the other is a PNP-type transistor; and one of the second switching device and the third switching device is an NPN type triode, and the other one is a PNP type triode.
In some embodiments of the present application, optionally, one of the first switching device and the fourth switching device is a P-channel fet, and the other is an N-channel fet; and one of the second switching device and the third switching device is a P-channel field effect transistor, and the other is an N-channel field effect transistor.
According to another aspect of the present application, a digital-to-analog converter is provided. The digital-to-analog converter includes: a plurality of latch circuits as any one of the above; and a digital-to-analog conversion module configured to receive an output signal from each of the latch circuits via a common line.
Drawings
The above and other objects and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like or similar elements are designated by like reference numerals.
FIG. 1 shows a latch circuit according to the prior art;
FIG. 2 shows a digital-to-analog converter according to the prior art;
FIG. 3 illustrates a latch circuit according to one embodiment of the present application;
FIG. 4 shows a digital-to-analog converter according to an embodiment of the present application;
FIG. 5 illustrates a latch circuit operating waveform according to one embodiment of the present application;
FIG. 6 illustrates the principle of operation of a latch circuit according to one embodiment of the present application;
FIG. 7 illustrates the principle of operation of a latch circuit according to one embodiment of the present application;
fig. 8 illustrates the principle of operation of a latch circuit according to an embodiment of the present application.
Detailed Description
For the purposes of brevity and explanation, the principles of the present application are described herein with reference primarily to exemplary embodiments thereof. However, those skilled in the art will readily appreciate that the same principles are equally applicable to all types of latch circuits, digital-to-analog converters, and that these same or similar principles may be implemented therein, with any such variations not departing from the true spirit and scope of the present application.
Fig. 1 shows a latch circuit according to the prior art. As shown, the latch circuit 10 includes a plurality of components from left to right, and some of the switch components are turned on and off by the clock signal CLK and/or its inverted signal CLKB. The data D input from the left side of the latch circuit 10 is output as a signal O from the right side of the latch circuit 10 through the processing of the respective components shown in the figure.
Fig. 2 shows a digital-to-analog converter. As shown in the figure, the digital-to-analog converter 20 is provided with 4 latch circuits 10-1, 10-2, 10-3 and 10-4 in total, and is configured to receive 4 inputs respectively and integrate them into one signal to be sent to the digital-to-analog conversion module 202, so as to realize conversion from a 4-bit digital signal to an analog signal. Each of the latch circuits 10-1, 10-2, 10-3, and 10-4 may have the structure shown in fig. 1. Since each component of the latch circuit is deviated during the manufacturing process, it takes different time for one data to pass through different latch circuits, which is also called deviation between latch circuits. This deviation, which may be larger when more components are involved in the processing, will affect the discrimination of the digital-to-analog conversion module 202 for signals from different latch circuits, thereby reducing the accuracy of the operation of the digital-to-analog converter 20.
According to an aspect of the present application, a latch circuit is provided. Two latch circuits 30-1 and 30-2 are shown in fig. 3, and these two have the same configuration, specifically, the switching devices MP1, MP0, MN0, MN1 in the latch circuit 30-1 correspond to the switching devices MP3, MP2, MN2, MN3 in the latch circuit 30-2, respectively, and the difference is only in the signals received by the respective devices of the latch circuit 30-1 and the latch circuit 30-2. The latch circuits 30-1 and 30-2 receive the two signals DATA1 and DATA2 in parallel and output a signal OUT through a common line. The operation of the latch circuit of some embodiments of the present application will be described below in terms of latch circuit 30-1.
As shown in FIG. 3, the latch circuit 30-1 receives the DATA signal DATA1 and the clock signal CLK (including its inverse CKB) and generates an output signal to form a common output signal OUT for both latch circuits. The latch circuit 30-1 includes an output section that generates an output signal and a first section and a second section connected in series.
Wherein a first portion (shown by the uppermost dotted line box) of the latch circuit 30-1 is coupled to a high level (a level provided by the uppermost line in the drawing) and includes a first switching device MP1 and a second switching device MP0 connected in series. The first switching device MP1 is turned on by being controlled by a first level (e.g., a low level) of the DATA signal DATA1, and the second switching device MP0 is turned on by being controlled by a second level (e.g., a high level) of the clock signal CK. Shown in the drawing is that the inverted signal CKB of the clock signal CK is input to the second switching device MP0, at which time the second switching device MP0 is controlled to be turned on by the inverted level (e.g., low level) of the second level of the inverted signal CKB of the clock signal CK, but the basic control logic is identical.
The second portion (shown by the lowermost dotted line block) of the latch circuit 30-1 is coupled to a low level and includes a third switching device MN0 and a fourth switching device MN1 connected in series, wherein the third switching device MN0 is controlled to be turned on by a second level (e.g., a high level) of the clock signal CK, and the fourth switching device MN1 is controlled to be turned on by an opposite level (e.g., a high level) of the first level of the DATA signal DATA 1.
With the above arrangement, the clocks are simultaneously gated on or off by the second and third switching devices MP0 and MN0, thereby enabling or disabling the latch circuit 30-1.
In the present application, the high and low levels coupled to the first and second portions, respectively, are selected to enable downstream circuitry to distinguish between the two. For example, the downstream digital-to-analog conversion module recognizes a high level above the threshold as a signal "1" and recognizes a low level below the threshold as a signal "0" by deciding the threshold. In some embodiments of the present application, the low level is a system ground level. In other examples, the low level may also be other levels that are significantly lower than the high level.
In some embodiments of the present application, the first level may be a low level or a high level, and an opposite level of the first level is a corresponding high level or a low level. Further, the second level may be a low level or a high level. The high level and the low level of the first level and the second level are not necessarily equal in value, and may be equal to the high level (provided by the uppermost line in the figure) and the low level (system ground level) connected to the latch circuit 30-1 shown in fig. 3, as long as the switching devices are turned on/off. In some embodiments of the present application, DATA1, as a DATA signal, has only two levels, high and low, and CK, as a clock signal, has only two levels, high and low.
An output portion (shown in phantom in the middle) of latch circuit 30-1 is coupled between the first portion and the second portion to generate an output signal. The output signal will be sent to the common output line of latch circuits 30-1 and 30-2 to produce a common output signal OUT.
In some embodiments of the present application, as shown in fig. 3, the first switching device MP1 has a first terminal (upper terminal) and a second terminal (lower terminal) controlled by a first level (e.g., low level of DATA 1) to turn on, wherein the first terminal is turned on to a high level. The second switching device MP0 has a third terminal (upper terminal) and a fourth terminal (lower terminal) that are turned on under the control of a second level (e.g., a low level of CKB, in other words, a high level of CK), wherein the third terminal is also connected to the second terminal, and the fourth terminal is connected to the second section and the output section.
In some embodiments of the present application, since the first switching device MP1 and the second switching device MP0 are connected in series, they can also switch positions. For example, the second switching device has a third terminal and a fourth terminal controlled to be turned on by the second level, wherein the third terminal is connected to the high level. The first switching device has a first terminal and a second terminal which are controlled by the first level to turn on, wherein the first terminal is connected to the fourth terminal, and the second terminal is connected to the second section and the output section.
In some embodiments of the present application, as shown in fig. 3, the third switching device MN0 has a fifth terminal (upper terminal) and a sixth terminal (lower terminal) controlled by the second level (e.g., high level of CK) to turn on, wherein the fifth terminal is connected to the first part and the output part. The fourth switching device MN1 has a seventh terminal (upper terminal) turned on by the opposite level of the first level (e.g., high level of DATA 1) and an eighth terminal (lower terminal), wherein the seventh terminal is connected to the sixth terminal and the eighth terminal is connected to low level.
In some embodiments of the present application, since the third switching device MN0 and the fourth switching device MN1 are also connected in series, they can also switch positions. For example, the fourth switching device has a seventh terminal and an eighth terminal turned on by being controlled by an opposite level of the first level, wherein the seventh terminal is connected to the first section and the output section. The third switching device has a fifth terminal and a sixth terminal controlled by the second level to be turned on, wherein the fifth terminal is connected to the eighth terminal, and the sixth terminal is connected to the low level.
In some embodiments of the present application, the first switching device MP1, the second switching device MP0, the third switching device MN0, and the fourth switching device MN1 illustrated in fig. 3 may be transistors or field effect transistors.
In some embodiments of the present application, one of the first switching device and the fourth switching device is an NPN transistor, and the other is a PNP transistor. Therefore, the first switching device and the fourth switching device can be turned on for the same signal at different times. In other words, for a signal (whether appearing high or low), one of the first switching device and the fourth switching device is always off and the other is on. In addition, one of the second switching device and the third switching device is an NPN type triode, and the other is a PNP type triode. Therefore, the second switching device and the third switching device can be turned on simultaneously aiming at two opposite-phase signals. In other words, the second switching device and the third switching device are always turned off or on simultaneously for two inverted signals.
In some embodiments of the present application, one of the first switching device and the fourth switching device is a P-channel fet and the other is an N-channel fet. Therefore, the first switching device and the fourth switching device can be turned on for the same signal at different times. In other words, for a signal (whether appearing high or low), one of the first switching device and the fourth switching device is always off and the other is on. In addition, one of the second switching device and the third switching device is a P-channel field effect transistor, and the other one is an N-channel field effect transistor. Therefore, the second switching device and the third switching device can be turned on simultaneously aiming at two opposite-phase signals. In other words, the second switching device and the third switching device are always turned off or on simultaneously for two inverted signals.
To illustrate the operation of the latch circuit 30-1 shown in fig. 3, fig. 6 and 7 show different operating states, respectively. As shown, the first and second switching devices MP1 and MP0 are P-channel fets, and the third and fourth switching devices MN0 and MN1 are N-channel fets.
As shown in fig. 6, when CK is high level and CKB is the inverse (low level) of CK, the second switching device MP0 and the third switching device MN0 will be simultaneously turned on. In this state, the latch circuit 30-1 will be enabled to output a valid signal. Specifically, when the DATA1 is low (representing "0"), the first switching device MP1 will be turned on and the fourth switching device MN1 will be turned off. At this time, the path shown on the left side of the figure will be formed in the latch circuit 30-1, that is, the output portion of the latch circuit 30-1 will be coupled to the high level. When the DATA1 is high (representing "1"), the first switching device MP1 will be turned off and the fourth switching device MN1 will be turned on. At this time, the path shown on the right side of the figure will be formed in the latch circuit 30-1, that is, the output portion of the latch circuit 30-1 will be coupled to the low level. Thus, the output signal of the latch circuit 30-1 according to this design will be the inverse of the input signal DATA 1.
It can be seen that the delay of the output signal will depend at most on the characteristics of the two switching devices, i.e. the signal deviation is at most related to the characteristics of the two switching devices. The latch circuit shown in fig. 3 can greatly reduce the deviation between latch circuits in parallel as compared with the latch circuit shown in fig. 1.
Turning to fig. 7, when CK is low level and CKB is the inverse (high level) of CK, the second switching device MP0 and the third switching device MN0 will be turned off at the same time. Thus, the output portion of the latch circuit 30-1 will be completely isolated from the high and low levels. In this state, latch circuit 30-1 will be inhibited from outputting a valid signal, i.e., the output of latch circuit 30-1 will be empty.
Fig. 8 shows the operating principle of another latch circuit. As shown, the first switching device MP1, the second switching device MP0, the third switching device MN0, and the fourth switching device MN1 are an N-channel fet, a P-channel fet, an N-channel fet, and a P-channel fet, respectively. When CK is high level and CKB is the inverse (low level) of CK, the second switching device MP0 and the third switching device MN0 will be simultaneously turned on. In this state, the latch circuit will be enabled to output a valid signal. Specifically, when the DATA1 is low (representing "0"), the first switching device MP1 will be turned off and the fourth switching device MN1 will be turned on. At this time, the path shown on the left side of the figure will be formed in the latch circuit, that is, the output portion of the latch circuit will be coupled to a low level. When the DATA1 is high (representing "1"), the first switching device MP1 will be turned on and the fourth switching device MN1 will be turned off. At this time, the path shown on the right side of the figure will be formed in the latch circuit, that is, the output portion of the latch circuit will be coupled to a high level. Thus, the output signal of the latch circuit according to this design will be the in-phase signal of the input signal DATA 1.
According to another aspect of the present application, a digital-to-analog converter is provided. As shown in fig. 4, the digital-analog converter 40 includes: a plurality of latch circuits of any of the above (shown in fig. 4 as two latch circuits 30-1 and 30-2 in fig. 3), a digital to analog conversion module 402. The digital-to-analog conversion module 402 receives and processes the output signal from each of the latch circuits 30-1 and 30-2 via the common line, and outputs the processed output signal as an analog signal.
Returning to FIG. 3, since the switching devices MP0 and MP2 access opposite signals and the switching devices MN0 and MN2 also access opposite signals, the latch circuits 30-1 and 30-2 are always in a state that one enables the other to be disabled. Fig. 5 shows waveforms for the operation of the latch circuits 30-1 and 30-2. As shown, when time T1 is coming, CK transitions high (CKB transitions low). According to the above description of the operating principle of the latch circuit 30-1 in conjunction with FIG. 6, etc., during the period from time T1 to time T2, the latch circuit 30-1 is enabled and the latch circuit 30-2 is disabled, so the output signal OUT is related to (e.g., is an inverted or in-phase signal of) the input signal DATA 1. Similarly, when time T2 is up, CK transitions low (CKB transitions high). During the time period from time T2 to time T3, the latch circuit 30-1 is disabled and the latch circuit 30-2 is enabled, so the output signal OUT is related to (e.g., is an inverted or in-phase signal of) the input signal DATA 2. In the process, the upper edge and the lower edge of the clock signal CK can trigger the data transmission.
The conventional digital-to-analog converter 20 shown in fig. 2 can generally trigger the signal transmission of one latch circuit only at the rising edge or the falling edge of the clock. Thus, the digital-to-analog converter 40 shown in fig. 4 requires only half the number of latch circuits to input the digital signals of the same number of bits into the digital-to-analog conversion module in the case where the clock signal CK has the same frequency.
The above are merely specific embodiments of the present application, but the scope of the present application is not limited thereto. Other possible variations or substitutions may occur to those skilled in the art based on the teachings herein, and are intended to be covered by the present disclosure. The embodiments and features of the embodiments of the present application may be combined with each other without conflict. The scope of protection of the present application is subject to the description of the claims.
Claims (11)
1. A latch circuit, wherein the circuit receives a data signal, a clock signal, and the circuit comprises an output portion that generates an output signal and first and second portions connected in series, wherein:
the first portion is coupled to a high level and includes a first switching device and a second switching device connected in series, wherein the first switching device is controlled to be turned on by a first level of the data signal and the second switching device is controlled to be turned on by a second level of the clock signal;
the second portion is coupled to a low level and includes a third switching device and a fourth switching device connected in series, wherein the third switching device is turned on under control of the second level of the clock signal and the fourth switching device is turned on under control of an opposite level of the first level of the data signal; and
the output portion is coupled between the first portion and the second portion to generate the output signal.
2. The circuit of claim 1, wherein the low level is a system ground level.
3. The circuit of claim 1, wherein the first level is a low level or a high level and an opposite level of the first level is a respective high level or low level; and the second level is a low level or a high level.
4. The circuit of claim 1, wherein:
the first switch device is controlled by the first level to conduct a first end and a second end, wherein the first end is connected with a high level; and
the second switching device has a third terminal and a fourth terminal controlled to be turned on by the second level, wherein the third terminal is connected to the second terminal, and the fourth terminal is connected to the second section and the output section.
5. The circuit of claim 1, wherein:
the second switching device is provided with a third end and a fourth end which are controlled by the second level to be conducted, wherein the third end is connected with a high level; and
the first switching device has a first terminal and a second terminal turned on by the first level control, wherein the first terminal is connected to the fourth terminal, and the second terminal is connected to the second section and the output section.
6. The circuit of claim 1, wherein:
the third switching device has a fifth terminal and a sixth terminal controlled by the second level to be turned on, wherein the fifth terminal is connected to the first portion and the output portion; and
the fourth switching device has a seventh terminal and an eighth terminal turned on by an opposite level of the first level, wherein the seventh terminal is connected to the sixth terminal, and the eighth terminal is connected to the low level.
7. The circuit of claim 1, wherein:
the fourth switching device has a seventh terminal and an eighth terminal turned on by an opposite level of the first level, wherein the seventh terminal is connected to the first portion and the output portion; and
the third switching device has a fifth terminal and a sixth terminal controlled by the second level to be turned on, wherein the fifth terminal is connected to the eighth terminal, and the sixth terminal is connected to the low level.
8. The circuit of claim 1, wherein any of the first, second, third, and fourth switching devices is a triode or a field effect transistor.
9. The circuit of claim 8, wherein:
one of the first switching device and the fourth switching device is an NPN type triode, and the other one of the first switching device and the fourth switching device is a PNP type triode; and
one of the second switching device and the third switching device is an NPN type triode, and the other one of the second switching device and the third switching device is a PNP type triode.
10. The circuit of claim 8, wherein:
one of the first switching device and the fourth switching device is a P-channel field effect transistor, and the other one is an N-channel field effect transistor; and
one of the second switching device and the third switching device is a P-channel field effect transistor, and the other one is an N-channel field effect transistor.
11. A digital-to-analog converter, the digital-to-analog converter comprising:
a plurality of latch circuits according to any one of claims 1 to 10; and
a digital-to-analog conversion module configured to receive an output signal from each of the latch circuits via a common line.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210503095.3A CN114978152B (en) | 2022-05-10 | 2022-05-10 | Latch circuit and digital-to-analog converter including the same |
| PCT/CN2022/093572 WO2023216287A1 (en) | 2022-05-10 | 2022-05-18 | Latch circuit and digital-to-analog converter comprising same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210503095.3A CN114978152B (en) | 2022-05-10 | 2022-05-10 | Latch circuit and digital-to-analog converter including the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114978152A true CN114978152A (en) | 2022-08-30 |
| CN114978152B CN114978152B (en) | 2024-06-21 |
Family
ID=82981570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210503095.3A Active CN114978152B (en) | 2022-05-10 | 2022-05-10 | Latch circuit and digital-to-analog converter including the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114978152B (en) |
| WO (1) | WO2023216287A1 (en) |
Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5181034A (en) * | 1991-04-30 | 1993-01-19 | Kabushiki Kaisha Toshiba | Digital to analog converter |
| US5231314A (en) * | 1992-03-02 | 1993-07-27 | National Semiconductor Corporation | Programmable timing circuit for integrated circuit device with test access port |
| JPH066186A (en) * | 1992-06-18 | 1994-01-14 | Nec Corp | Latch circuit |
| US6023179A (en) * | 1997-06-04 | 2000-02-08 | Sun Microsystems, Inc. | Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop |
| US20020140484A1 (en) * | 2001-03-28 | 2002-10-03 | Fujitsu Limited | Delay circuit, semiconductor integrated circuit device containing a delay circuit and delay method |
| US20030076149A1 (en) * | 2001-10-03 | 2003-04-24 | Nec Corporation | Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device |
| CN1702963A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Synchronous enabled type condition presetting CMOS trigger |
| US20070132496A1 (en) * | 2005-12-12 | 2007-06-14 | Satoshi Kuboyama | Single-event effect tolerant latch circuit and flip-flop circuit |
| JP2011055224A (en) * | 2009-09-01 | 2011-03-17 | Nec Corp | Flip-flop circuit |
| CN102456316A (en) * | 2011-12-15 | 2012-05-16 | 北京大学深圳研究生院 | Data driving circuit and display device thereof |
| CN102739257A (en) * | 2012-07-25 | 2012-10-17 | 北京昆腾微电子有限公司 | Digital-to-analog converter |
| US20130015993A1 (en) * | 2011-07-14 | 2013-01-17 | Synopsys, Inc. | Synchronous switching in high-speed digital-to-analog converter using quad synchronizing latch |
| US20140125392A1 (en) * | 2012-11-05 | 2014-05-08 | Arm Limited | Low power latching circuits |
| CN104796132A (en) * | 2014-01-22 | 2015-07-22 | 陈祺琦 | Flip-flop circuit |
| CN106160748A (en) * | 2015-05-14 | 2016-11-23 | 联发科技股份有限公司 | A kind of latch circuit |
| CN106205664A (en) * | 2016-06-28 | 2016-12-07 | 醴陵恒茂电子科技有限公司 | Memory read/write transmission gate management and control circuit |
| CN106656108A (en) * | 2015-10-29 | 2017-05-10 | 智原科技股份有限公司 | Flip-flop circuit |
| CN107733421A (en) * | 2016-11-18 | 2018-02-23 | 上海兆芯集成电路有限公司 | For the data synchronizing unit for being latched the asynchronous data signal relevant with clock signal |
| CN108347234A (en) * | 2017-12-29 | 2018-07-31 | 成都华微电子科技有限公司 | high-speed comparator circuit based on inverter design |
| CN110784191A (en) * | 2018-07-31 | 2020-02-11 | 瑞昱半导体股份有限公司 | Latch circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09270677A (en) * | 1995-09-05 | 1997-10-14 | Mitsubishi Electric Corp | Flip-flop circuit, scanning path and storage circuit |
| CN101977036A (en) * | 2010-09-21 | 2011-02-16 | 四川和芯微电子股份有限公司 | High-speed latch circuit |
| CN102637059B (en) * | 2011-02-14 | 2014-12-10 | 珠海全志科技股份有限公司 | Time deviation processing device and processing method thereof |
| CN106936410B (en) * | 2017-01-24 | 2020-07-17 | 合肥工业大学 | High-speed low-power-consumption reinforced latch |
| CN108832910A (en) * | 2018-06-27 | 2018-11-16 | 重庆湃芯入微科技有限公司 | A kind of data sampler that threshold voltage is configurable |
-
2022
- 2022-05-10 CN CN202210503095.3A patent/CN114978152B/en active Active
- 2022-05-18 WO PCT/CN2022/093572 patent/WO2023216287A1/en unknown
Patent Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5181034A (en) * | 1991-04-30 | 1993-01-19 | Kabushiki Kaisha Toshiba | Digital to analog converter |
| US5231314A (en) * | 1992-03-02 | 1993-07-27 | National Semiconductor Corporation | Programmable timing circuit for integrated circuit device with test access port |
| JPH066186A (en) * | 1992-06-18 | 1994-01-14 | Nec Corp | Latch circuit |
| US6023179A (en) * | 1997-06-04 | 2000-02-08 | Sun Microsystems, Inc. | Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop |
| US20020140484A1 (en) * | 2001-03-28 | 2002-10-03 | Fujitsu Limited | Delay circuit, semiconductor integrated circuit device containing a delay circuit and delay method |
| US20030076149A1 (en) * | 2001-10-03 | 2003-04-24 | Nec Corporation | Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device |
| CN1702963A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Synchronous enabled type condition presetting CMOS trigger |
| US20070132496A1 (en) * | 2005-12-12 | 2007-06-14 | Satoshi Kuboyama | Single-event effect tolerant latch circuit and flip-flop circuit |
| JP2011055224A (en) * | 2009-09-01 | 2011-03-17 | Nec Corp | Flip-flop circuit |
| US20130015993A1 (en) * | 2011-07-14 | 2013-01-17 | Synopsys, Inc. | Synchronous switching in high-speed digital-to-analog converter using quad synchronizing latch |
| CN102456316A (en) * | 2011-12-15 | 2012-05-16 | 北京大学深圳研究生院 | Data driving circuit and display device thereof |
| CN102739257A (en) * | 2012-07-25 | 2012-10-17 | 北京昆腾微电子有限公司 | Digital-to-analog converter |
| US20140125392A1 (en) * | 2012-11-05 | 2014-05-08 | Arm Limited | Low power latching circuits |
| CN104796132A (en) * | 2014-01-22 | 2015-07-22 | 陈祺琦 | Flip-flop circuit |
| CN106160748A (en) * | 2015-05-14 | 2016-11-23 | 联发科技股份有限公司 | A kind of latch circuit |
| CN106656108A (en) * | 2015-10-29 | 2017-05-10 | 智原科技股份有限公司 | Flip-flop circuit |
| CN106205664A (en) * | 2016-06-28 | 2016-12-07 | 醴陵恒茂电子科技有限公司 | Memory read/write transmission gate management and control circuit |
| CN107733421A (en) * | 2016-11-18 | 2018-02-23 | 上海兆芯集成电路有限公司 | For the data synchronizing unit for being latched the asynchronous data signal relevant with clock signal |
| CN108347234A (en) * | 2017-12-29 | 2018-07-31 | 成都华微电子科技有限公司 | high-speed comparator circuit based on inverter design |
| CN110784191A (en) * | 2018-07-31 | 2020-02-11 | 瑞昱半导体股份有限公司 | Latch circuit |
Non-Patent Citations (2)
| Title |
|---|
| SANTANU SARKAR: "500 MHz differential latched current comparator for calibration of current steering DAC", 《PROCEEDINGS OF THE 2014 IEEE STUDENTS\' TECHNOLOGY SYMPOSIUM》, 31 December 2014 (2014-12-31), pages 1 - 4 * |
| 汪正锋: "一种基于电压窗口技术的超低功耗SAR ADC", 《电子学报》, 31 December 2016 (2016-12-31), pages 211 - 215 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023216287A1 (en) | 2023-11-16 |
| CN114978152B (en) | 2024-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8373444B2 (en) | Time-domain voltage comparator for analog-to-digital converter | |
| KR100801055B1 (en) | Data receiver and semiconductor including the receiver | |
| CN1918795B (en) | Latch circuit | |
| US8487802B2 (en) | Comparator and analog-to-digital converter | |
| CN107800412B (en) | Built-in threshold comparator | |
| US6486719B2 (en) | Flip-flop circuits having digital-to-time conversion latches therein | |
| US6085033A (en) | Method for determining bit element values for driver impedance control | |
| US6617881B2 (en) | Semiconductor integrated circuit | |
| US7271703B2 (en) | 2-bit binary comparator and binary comparing device using the same | |
| CN114978152B (en) | Latch circuit and digital-to-analog converter including the same | |
| JP2007067819A (en) | Delay adjusting circuit and synchronous type semiconductor device equipped with the circuit | |
| US7847591B2 (en) | Low jitter CMOS to CML converter | |
| US11611362B2 (en) | Duobinary receiver for receiving a duobinary signal | |
| US8963575B2 (en) | Analog majority vote circuit | |
| US20130002350A1 (en) | Differential Comparator | |
| EP1130780B1 (en) | Semiconductor integrated circuit having logical operation function | |
| US20070290724A1 (en) | Comparator circuit | |
| US9602085B2 (en) | Data storage element and signal processing method | |
| US9000964B2 (en) | Circuit and method for signal conversion | |
| US8891717B1 (en) | Method and system for comparing digital values | |
| García et al. | High performance single supply CMOS inverter level up shifter for multi-supply voltages domains | |
| KR100261865B1 (en) | A comparator | |
| KR100964791B1 (en) | Voltage level shifter | |
| KR100611315B1 (en) | High speed analog logical multipler and phase detector having the same | |
| KR0183752B1 (en) | Output port having a delay circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |