CN102739257A - Digital-to-analog converter - Google Patents
Digital-to-analog converter Download PDFInfo
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- CN102739257A CN102739257A CN2012102595671A CN201210259567A CN102739257A CN 102739257 A CN102739257 A CN 102739257A CN 2012102595671 A CN2012102595671 A CN 2012102595671A CN 201210259567 A CN201210259567 A CN 201210259567A CN 102739257 A CN102739257 A CN 102739257A
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Abstract
The invention relates to a digital-to-analog converter which comprises an input register for latching an input digital signal and outputting the digital signal at an effective edge of a clock signal, a first digital-to-analog conversion module for performing digital-to-analog conversion on the digital signal output by the input register and outputting an analog voltage signal, a first switch of which one end is connected with the output end of the first digital-to-analog conversion module and the other end is used as the output end of the digital-to-analog converter, and a pulse generator for generating a pulse signal with a preset time width at the effective edge of the clock signal, wherein the pulse signal is used for controlling the turn-on and turn-off of the first switch; and the moment that the pulse generator outputs the pulse signal relative to the time delay of the effective edge of the clock signal is smaller than or equal to the moment that the digital-to-analog conversion module outputs the analog voltage signal relative to the time delay of the effective edge of the clock signal. By using the digital-to-analog converter, burrs in the analog voltage signal output by the digital-to-analog converter can be easily and effectively reduced.
Description
Technical field
The present invention relates to microelectronic, relate in particular to a kind of digital to analog converter.
Background technology
Digital to analog converter converts digital input signals to analog signal output.As shown in Figure 1, be the structural representation of digital to analog converter in the prior art, digital to analog converter comprises input register 11 and D/A converter module 12, wherein, input register 11 can be realized through d type flip flop usually.The operation principle of digital to analog converter is following: n bit digital input signal at first is transfused to register 11 and latchs, and the n position digital signal after the sampling carries out digital-to-analogue conversion together in D/A converter module 12.
In digital to analog converter, a lot of situation can cause in analog output signal, existing burr (Glitch).For example: the time-delay difference of the n position digital signal after the sampling can cause in analog output signal, existing bigger burr; Have parasitic capacitance in the analog circuit, produce burr when causing importing data variation, especially when input signal when 01111111 changes to 1000000; Clock feedthrough can cause total harmonic distortion, and being reflected on the output waveform of circuit is the existence that causes burr equally.Burr can cause output signal harmonic performance decrease usually; In some control loops; The existence of burr may cause the concussion of loop, and burr is the main restricting factor that influences the digital to analog converter operating accuracy, therefore in circuit design, need reduce burr as far as possible.Weighing the good and bad leading indicator of burr is the energy of burr, and the energy of burr is not only relevant with the size of burr, and is also relevant with the duration, the area that the energy of burr can be regarded burr as intuitively and surrounded.As shown in Figure 2, be two types burr sketch map common in the prior art, burr is represented in the shadow region; A1, A2, A3 are the area in shadow region; The burr energy of type (a) is A2-A1, and the burr energy of type (b) is A3, although the burr energy is that the shadow region area subtracts each other up and down in the type (a); Yet still can worsen the harmonic performance of output signal, therefore still need reduce A1 and A2 area separately.
In the prior art, the reason that produces to burr usually reduces burr through the performance that improves circuit.For example: carry out Circuit Matching, reduce the time-delay distinguishment between the Digital Signal Processing as far as possible; Reduce the parasitic capacitance in the analog circuit; Reduce the feedthrough of clock circuit for output.But these methods can't tackle the problem at its root effectively.
Summary of the invention
The present invention provides a kind of digital to analog converter, in order to the burr in the analog voltage signal of realizing reducing simply and effectively digital to analog converter output.
The present invention provides a kind of digital to analog converter, comprising:
Input register is used for the digital signal of input is latched, and on the effective edge edge of clock signal, exports said digital signal;
First D/A converter module is used for the digital signal of said input register output is carried out analog-to-digital conversion the output analog voltage signal;
Also comprise:
First switch, an end is connected with the output of said first D/A converter module, and the other end is as the output of said digital to analog converter;
Pulse generator is used for the effective edge edge in said clock signal, generates the pulse signal of a scheduled time width, and said pulse signal is used to control the switch and the closure of said first switch; Wherein, said pulse generator moment of exporting said pulse signal is less than or equal to the time-delay with respect to the effective edge edge of said clock signal of moment that said D/A converter module exports said analog voltage signal with respect to the time-delay on the effective edge edge of said clock signal.
The present invention also provides a kind of digital to analog converter, comprising:
Input register is used for the digital signal of input is latched, and on the effective edge edge of clock signal, exports said digital signal;
Second D/A converter module is used for the digital signal of said input register output is carried out analog-to-digital conversion the output analog current signal;
Also comprise:
First switch, an end is connected with the output of said second D/A converter module, and the other end is as the output of said digital to analog converter;
First resistance, an end is connected with the output of said digital to analog converter, and the other end is connected with common;
Second switch, an end is connected with the output of said second D/A converter module;
Second resistance, an end is connected with the other end of said second switch, and the other end is connected with said common;
Pulse generator is used for the effective edge edge in said clock signal, generates the pulse signal of a scheduled time width; Wherein, said pulse generator moment of exporting said pulse signal is less than or equal to the time-delay with respect to the effective edge edge of said clock signal of moment that said D/A converter module exports said analog current signal with respect to the time-delay on the effective edge edge of said clock signal;
Inverter is connected with the output of said pulse generator, is used for said pulse signal negate;
Wherein, said pulse signal is used to control the switch and the closure of said first switch, and the pulse signal after the negate is used to control the switch and the closure of said second switch.
In the present invention; When the analog signal of first simulation D/A converter module or second D/A converter module output is in when initially setting up process, have bigger burr in this analog signal, thereby first switch breaks off the output that this burr of resistance outputs to digital to analog converter; After waiting for pulse width time; First simulation D/A converter module or second D/A converter module output analog signal set up gradually, at this moment, the burr in this analog signal is very little or disappear; First K switch, 1 closure then; This analog signal is exported to the output of digital to analog converter, so the burr in the analog signal of the output of digital to analog converter is also very little or disappear, thereby has reduced the burr in the analog signal of digital to analog converter output greatly.
Description of drawings
Fig. 1 is the structural representation of digital to analog converter in the prior art;
Fig. 2 is two a types burr sketch map common in the prior art;
Fig. 3 is the structural representation of digital to analog converter first embodiment of the present invention;
Fig. 4 is the waveform sketch map of each node voltage in the structural representation shown in Figure 3 among digital to analog converter first embodiment of the present invention;
Fig. 5 is the structural representation of digital to analog converter second embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description and embodiment the present invention is done further description.
As shown in Figure 3, be the structural representation of digital to analog converter first embodiment of the present invention, this digital to analog converter can comprise input register 11, first D/A converter module 121, first K switch 1 and pulse generator 13.First D/A converter module 121 is connected with input register 11; One end of first K switch 1 is connected with the output of first D/A converter module 121, and the other end is as the output out of digital to analog converter; Pulse generator 13 is connected with first K switch 1.
Alternatively, input register 11, first D/A converter module 121, first K switch 1 and pulse generator 13 are integrated in the single integrated circuit.This integrated circuit can adopt complementary metal oxide semiconductors (CMOS), and (Complementary Metal-Oxide-Semiconductor Transistor, be called for short: CMOS) technology, BiCMOS technology or any other technology wanting to adopt or the combination of technology are made.
Wherein, input register 11 is used for the digital signal of input is latched, on the effective edge edge of clock signal, and the output digital signal; Preferably, input register 11 adopts d type flip flops to realize, need to prove that input register 11 is not limited to d type flip flop, anyly can realize that the device of latch function can.First D/A converter module 121 is used for the digital signal of input register output is carried out digital-to-analogue conversion, the output analog voltage signal.Pulse generator 13 is used for the effective edge edge in clock signal, generates the pulse signal swctrl of a scheduled time width, and pulse signal swctrl is used to control the switch and the closure of first K switch 1; Wherein, the moment of pulse generator 13 output pulse signals is less than or equal to the time-delay of the moment of first D/A converter module, 121 output analog voltage signals with respect to the effective edge edge of clock signal with respect to the time-delay on the effective edge edge of clock signal; Particularly, pulse signal swctrl is used to control first K switch 1 and when pulse signal swctrl takes place, breaks off, and is closed when pulse signal swctrl finishes.
In the present embodiment, the time width of pulse signal swctrl is less than the cycle of clock signal, can be in side circuit according to the burr duration of reality and the burr index decision of circuit, thus can be from reducing the energy of burr to the full extent.
Introduce the course of work of present embodiment below in detail, the effective edge of supposing clock signal is along being rising edge, and pulse signal swctrl is a low level pulse.The digital signal of 11 pairs of inputs of input register latchs, in rising edge of clock signal, and the output digital signal; The digital signal of 121 pairs of input register outputs of first D/A converter module is carried out digital-to-analogue conversion, the output analog voltage signal; Pulse generator 13 generates the pulse signal swctrl of a scheduled time width in rising edge of clock signal, and in other words, pulse generator 13 converts each rising edge of clock signal to a low level pulse, the burst length fixed width.Need to prove; The time-delay of the moment of pulse generator 13 output pulse signals with respect to the effective edge edge of clock signal is less than or equal to the time-delay of the moment of first D/A converter module, 121 output analog voltage signals with respect to the effective edge edge of clock signal; Preferably, the moment of pulse generator 13 output pulse signals equals the time-delay of the moment of first D/A converter module, 121 output analog voltage signals with respect to the effective edge edge of clock signal with respect to the time-delay on the effective edge edge of clock signal.The output of first D/A converter module 121 connects first K switch 1; The disconnection of first K switch 1 and closure are controlled by pulse signal swctrl: when pulse signal swctrl is low level; First K switch 1 is broken off, when pulse signal swctrl is high level, and first K switch, 1 closure.The output N1 node of first D/A converter module 121 is exported new analog voltage signal in rising edge of clock signal, like this, and when rising edge clock signal arrives; The N1 node begins to export new analog voltage signal, at this moment, and the pulse of pulse signal swctrl output low level; First K switch 1 is broken off; The output out of digital to analog converter temporarily separates with the N1 node, first K switch, 1 closure behind the wait pulse width time, and the analog voltage signal of N1 node is just finally exported to output out.
As shown in Figure 4; Be the waveform sketch map of each node voltage in the structural representation shown in Figure 3 among digital to analog converter first embodiment of the present invention, wherein Ts is the time width of pulse signal swctrl, in sketch map shown in Figure 4; The time-delay of the moment of pulse generator 13 output pulse signals with respect to the effective edge edge of clock signal equals the time-delay of the moment of first D/A converter module, 121 output analog voltage signals with respect to the effective edge edge of clock signal; First K switch 1 break off during this period of time in, the analog voltage signal of N1 node is in the process of initially setting up, and has bigger burr in this analog voltage signal; But because first K switch 1 is broken off; Therefore this burr can not output to the output out of digital to analog converter, and behind the wait pulse width time, the analog voltage signal of N1 node is set up gradually; At this moment; Burr in the analog voltage signal of N1 node is very little or disappear, first K switch, 1 closure then, and the analog voltage signal of N1 node is exported to output out; Therefore the burr in the analog voltage signal of the output out of digital to analog converter is also very little or disappear, thereby has reduced the burr in the analog voltage signal of digital to analog converter output greatly.First K switch 1 break off during this period of time in because there is parasitic capacitance in output out, big variation can't take place in the analog voltage signal of output out, remains unchanged basically.
As shown in Figure 5; Be the structural representation of digital to analog converter second embodiment of the present invention, this digital to analog converter can comprise input register 11, second D/A converter module 122, first K switch 1, first resistance R 1, second switch K2, second resistance R 2, pulse generator 13 and inverter 14.First D/A converter module 121 is connected with input register 11; One end of first K switch 1 is connected with the output of second D/A converter module 12, and the other end is as the output out of digital to analog converter; One end of first resistance R 1 is connected with the other end of first K switch 1, and the other end is connected with common; The end of second switch K2 is connected with the output of second D/A converter module 122; One end of second resistance R 2 is connected with the output of second D/A converter module 122, and the other end is connected with common; Inverter 14 is connected with the output of pulse generator 13.
In the present embodiment, the time width of pulse signal swctrl is less than the cycle of clock signal, can be in side circuit according to the burr duration decision of reality, thus can be from reducing the energy of burr to the full extent.
Alternatively, input register 11, second D/A converter module 122, first K switch 1, second switch K2, first resistance R 1, second resistance R 2, pulse generator 13 and inverter 14 are integrated in the single integrated circuit.This integrated circuit can adopt the technology that CMOS technology, BiCMOS technology or any other want to adopt or the combination of technology to make.
Introduce the course of work of present embodiment below in detail, the effective edge of supposing clock signal is along being rising edge, and pulse signal swctrl is a low level pulse.The digital signal of 11 pairs of inputs of input register latchs, in rising edge of clock signal, and the output digital signal; The digital signal of 122 pairs of input register outputs of second D/A converter module is carried out digital-to-analogue conversion, the output analog current signal; Pulse generator 13 generates the pulse signal swctrl of a scheduled time width in rising edge of clock signal, and in other words, pulse generator 13 converts each rising edge of clock signal to a low level pulse, the burst length fixed width.Need to prove; The time-delay of the moment of pulse generator 13 output pulse signals with respect to the effective edge edge of clock signal is less than or equal to the time-delay of the moment of second D/A converter module, 122 output analog current signals with respect to the effective edge edge of clock signal; Preferably, the moment of pulse generator 13 output pulse signals equals the time-delay of the moment of second D/A converter module, 122 output analog current signals with respect to the effective edge edge of clock signal with respect to the time-delay on the effective edge edge of clock signal.The output of second D/A converter module 122 connects first K switch 1 and second switch K2; Disconnection and the closure of first K switch 1 and second switch K2 are controlled by pulse signal swctrl: when pulse signal swctrl is low level; First K switch 1 is broken off, and second switch K2 is closed, when pulse signal swctrl is high level; First K switch, 1 closure, second switch K2 breaks off.The output N2 node of second D/A converter module 122 is exported new analog current signal in rising edge of clock signal, like this, and when rising edge clock signal arrives; The N1 node begins to export new analog current signal, at this moment, and the pulse of pulse signal swctrl output low level; First K switch 1 is broken off, and second switch K2 is closed, and the analog current signal of N1 node output flows to common through the second switch K2 and second resistance R 2; The output out of digital to analog converter temporarily separates with the N2 node; First K switch, 1 closure behind the wait pulse width time, second switch K2 breaks off, and the analog current signal of N2 node flows to common through first K switch 1 and first resistance R 1; At this moment, the aanalogvoltage of N2 node is just finally exported to output out.
In structural representation shown in Figure 5, first K switch 1 break off during this period of time in, the analog current signal of N2 node is in the process of foundation; There is big burr in meeting in the analog current signal of N2 node, and second switch K2 is closed when being disconnection owing to first K switch 1, so this burr can flow to common through the second switch K2 and second resistance R 2; And can not output to the output out of digital to analog converter, wait for the set time after, first K switch, 1 closed second switch K2 simultaneously breaks off; The analog current signal of N2 node is set up gradually; At this moment, the burr in the analog current signal of N2 node is very little or disappear, because first K switch 1 is closed and second switch K2 breaks off; Therefore; This analog current signal flows to common through first K switch 1 and first resistance R 1, cause burr in the analog voltage signal of output out output of digital to analog converter also very little or disappear, thereby has reduced the burr in the analog voltage signal that digital to analog converter exports greatly.First K switch 1 break off during this period of time in because there is parasitic capacitance in output out, big variation can't take place in the analog voltage signal of output out, remains unchanged basically.
What should explain at last is: above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is specified with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that; Can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and the scope of technical scheme of the present invention.
Claims (10)
1. digital to analog converter comprises:
Input register is used for the digital signal of input is latched, and on the effective edge edge of clock signal, exports said digital signal;
First D/A converter module is used for the digital signal of said input register output is carried out analog-to-digital conversion the output analog voltage signal;
It is characterized in that, also comprise:
First switch, an end is connected with the output of said first D/A converter module, and the other end is as the output of said digital to analog converter;
Pulse generator is used for the effective edge edge in said clock signal, generates the pulse signal of a scheduled time width, and said pulse signal is used to control the switch and the closure of said first switch; Wherein, said pulse generator moment of exporting said pulse signal is less than or equal to the time-delay with respect to the effective edge edge of said clock signal of moment that said D/A converter module exports said analog voltage signal with respect to the time-delay on the effective edge edge of said clock signal.
2. digital to analog converter according to claim 1 is characterized in that, said input register, said first D/A converter module, said first switch and said pulse generator are integrated in the single integrated circuit.
3. digital to analog converter according to claim 2 is characterized in that, said integrated circuit adopts the CMOS technology manufacturing.
4. digital to analog converter according to claim 1 is characterized in that, said first switch breaks off when said pulse signal takes place, and is closed when said pulse signal ends.
5. digital to analog converter according to claim 1 is characterized in that, said input register is a d type flip flop.
6. digital to analog converter comprises:
Input register is used for the digital signal of input is latched, and on the effective edge edge of clock signal, exports said digital signal;
Second D/A converter module is used for the digital signal of said input register output is carried out analog-to-digital conversion the output analog current signal;
It is characterized in that, also comprise:
First switch, an end is connected with the output of said second D/A converter module, and the other end is as the output of said digital to analog converter;
First resistance, an end is connected with the output of said digital to analog converter, and the other end is connected with common;
Second switch, an end is connected with the output of said second D/A converter module;
Second resistance, an end is connected with the other end of said second switch, and the other end is connected with said common;
Pulse generator is used for the effective edge edge in said clock signal, generates the pulse signal of a scheduled time width; Wherein, said pulse generator moment of exporting said pulse signal is less than or equal to the time-delay with respect to the effective edge edge of said clock signal of moment that said D/A converter module exports said analog current signal with respect to the time-delay on the effective edge edge of said clock signal;
Inverter is connected with the output of said pulse generator, is used for said pulse signal negate;
Wherein, said pulse signal is used to control the switch and the closure of said first switch, and the pulse signal after the negate is used to control the switch and the closure of said second switch.
7. digital to analog converter according to claim 6; It is characterized in that said input register, said second D/A converter module, said first switch, said second switch, said first resistance, said second resistance, the said inverter of said pulse generator are integrated in the single integrated circuit.
8. digital to analog converter according to claim 7 is characterized in that, said integrated circuit adopts the CMOS technology manufacturing.
9. digital to analog converter according to claim 6 is characterized in that, said first switch breaks off when said pulse signal takes place, and is closed when said pulse signal ends;
Said second switch is closed when said pulse signal takes place, and when said pulse signal ends, breaks off.
10. digital to analog converter according to claim 6 is characterized in that, said input register is a d type flip flop.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114978152A (en) * | 2022-05-10 | 2022-08-30 | 上海韬润半导体有限公司 | Latch circuit and digital-to-analog converter comprising same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109756823B (en) * | 2017-11-03 | 2021-07-06 | 炬芯科技股份有限公司 | Audio digital-to-analog conversion device, switch device and audio output equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05347562A (en) * | 1992-06-16 | 1993-12-27 | Matsushita Electric Ind Co Ltd | Variable gain d/a converter |
| US5646620A (en) * | 1995-06-02 | 1997-07-08 | National Instruments Corporation | Method and apparatus for deglitching DAC signals |
| JP2000078013A (en) * | 1998-08-31 | 2000-03-14 | Toyo Electric Mfg Co Ltd | Digital-to-analog conversion method |
| CN102571087A (en) * | 2012-02-23 | 2012-07-11 | 诸荩锋 | Circuit for eliminating short-term pulse interference of digital-to-analog converter, and using method for circuit |
| CN202713276U (en) * | 2012-07-25 | 2013-01-30 | 北京昆腾微电子有限公司 | Digital-analog converter |
-
2012
- 2012-07-25 CN CN201210259567.1A patent/CN102739257B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05347562A (en) * | 1992-06-16 | 1993-12-27 | Matsushita Electric Ind Co Ltd | Variable gain d/a converter |
| US5646620A (en) * | 1995-06-02 | 1997-07-08 | National Instruments Corporation | Method and apparatus for deglitching DAC signals |
| JP2000078013A (en) * | 1998-08-31 | 2000-03-14 | Toyo Electric Mfg Co Ltd | Digital-to-analog conversion method |
| CN102571087A (en) * | 2012-02-23 | 2012-07-11 | 诸荩锋 | Circuit for eliminating short-term pulse interference of digital-to-analog converter, and using method for circuit |
| CN202713276U (en) * | 2012-07-25 | 2013-01-30 | 北京昆腾微电子有限公司 | Digital-analog converter |
Non-Patent Citations (1)
| Title |
|---|
| 朱其祥: "《一种高速、高精度数/模转换器厚膜混合集成电路设计》", 《中国优秀硕士学位论文全文数据库（电子期刊）信息科技辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114978152A (en) * | 2022-05-10 | 2022-08-30 | 上海韬润半导体有限公司 | Latch circuit and digital-to-analog converter comprising same |
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