CN101079613A - Low power consumption and low clock swing range D trigger based on C2MOS and sensitive amplifier structure - Google Patents
Low power consumption and low clock swing range D trigger based on C2MOS and sensitive amplifier structure Download PDFInfo
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Abstract
The invention discloses a low-power low-clock oscillation range D trigger based on C2MOS and sensitive amplifier structure in the D trigger technical domain, which is characterized by the following: the first grade is latcher with two clock control CMOS inverters and one inverter; the output MX of two clock control CMOS inverters connects; the second grade is sensitive amplifier with two inverters connecting from front to tail; the trigger adopts single power supplying, which is fit for all-purpose CMOS technique; the clock input driving adopts inverter of the overlapped PMOS transistor with input driving the master-to-slave grade of the trigger, which affirms the correction of D trigger; the D trigger adopts individual power supplying for clock under low clock oscillation range; all substrates of the PMOS transistors of the trigger connect power; all substrates of NMOS transistor connect ground. The invention has low power consumption and little delay with simple structure, which reinforces the anti-noise property through difference input second grade.
Description
Technical field
The invention belongs to the d type flip flop design field, particularly a kind of based on C
2The low power consumption and low clock swing range D trigger of MOS and sensitive amplifier structure.Specifically, " low power consumption and low clock swing range D trigger " is the low-power consumption high speed flip flop circuit design that adopts low-clock signal excursion to drive, and is a kind of low-power consumption d type flip flop circuit unit that is applicable to low amplitude of oscillation clock signal networks technology.
Background technology
Along with the development of microelectronics CMOS technology, the scale and the complexity of integrated circuit are increasing, and power consumption and heat dissipation problem on the unit are come into one's own day by day.In large-scale digital ic design, it is increasing that the power consumption of clock network accounts for the ratio of total power consumption.Studies show that in 2003, in current high-performance processor, the dynamic power consumption of clock distributing network subsystem accounts for 40% of entire system dynamic power consumption and (sees document David E.Duarte, N.Vijaykrishnan, and Mary Jane Irwin, ' A Clock Power Modelto Evaluate Impact of Architectural and Technology Optimizations-A Summary ' IEEE CIRCUITS AND SYSTEMS MAGAZINE, THIRD QUARTER, p.36 THIRDQUARTER 2003).The power consumption of clock network mainly consumes on buffer, clock interconnection line and the sequential logic unit in clock trees.Therefore, by reducing the voltage signal amplitude of oscillation on the clock network, can reduce the energy that consumes on the clock network.
Be illustrated in figure 1 as the flip-flop element schematic diagram, D is a signal input part among the figure, and CK is a clock signal input terminal, and Q and QN are the complementary signal output.Shown in Figure 2 is traditional flip-flop circuit structure, and it is widely used in the digital circuit standard cell design library.Here the flip-flop element DFFX1 that triggers with rising edge in the UMC 0.18 μ m technology digital standard cell library is that an example explanation (is seen document UMC 180nm L180GIIProcess 1.8-Volt SAGE-X
TMV1.0 Standard Cell Library Databook).Sort circuit is simple in structure, but is not suitable for low amplitude of oscillation clock network system, and power consumption and time-delay are all big simultaneously.
Figure 3 shows that the trigger LS_IP_DCO of another example.This circuit adopts dual power supply, and wherein clock partly adopts the power supply of VDD/2 power supply.When reducing power consumption, adopt the transistor of MTCMOS technology (to see document Saihua Lin to guarantee that time-delay does not increase, et al., " Vdd/2 clock swing D flip-flop byusing output feedback and MTCMOS; " Electronic Letters, 20th July 2006 Vol.42 No.15).But it adopts duplicate supply and uses MTCMOS technology to improve cost, though transistor size is less, the area of its physical layout but can increase.
Summary of the invention
The objective of the invention is to propose a kind of based on C
2The low power consumption and low clock swing range D trigger of MOS and sensitive amplifier structure, this trigger can be applicable to low amplitude of oscillation clock network Circuits System; Be applicable to general CMOS technology simultaneously, do not increase cost; And use the single power supply power supply.
One of feature of the present invention is that this d type flip flop contains:
1) inverter of being made up of stacked PMOS transistor, NMOS pipe is used for carrying out anti-phasely to hanging down amplitude of oscillation clock signal C K, and this inverter comprises:
PMOS manages MPV, and the source electrode of this pipe and substrate meet power vd D, and grid and drain electrode are connected together;
PMOS manages MP1, and the grid of the source electrode of this pipe and described MPV pipe, drain electrode are connected together, and the substrate of this pipe meets power vd D, and the grid of this pipe meets clock signal C K, and drain labeled is designated as CKN;
PMOS manages MP2, and the grid of the source electrode of this pipe and described MPV pipe, drain electrode are connected together, and the substrate of this pipe meets power vd D, and the grid of this pipe meets CKN, and drain labeled is designated as CKD;
PMOS manages MPE, and the grid of the source electrode of this pipe and described MPV pipe, drain electrode are connected together, and the substrate of this pipe meets power vd D, and the grid of this pipe meets CKD, and drain labeled is designated as CKE;
NMOS manages (MN1), and the drain electrode of the drain electrode of this pipe and described (MP1) pipe is connected to node CKN, and the grid of this pipe meets clock signal C K, and the source electrode of this pipe and substrate be ground connection all;
NMOS manages MN2, and the drain electrode of the drain electrode of this pipe and described MP2 pipe is connected to node CKD, and the grid of this pipe meets CKN, and the source electrode of this pipe and substrate be ground connection all;
NMOS manages MNE, and the drain electrode of the drain electrode of this pipe and described MPE pipe is connected to node CKE, and the grid of this pipe meets CKD, and the source electrode of this pipe and substrate be ground connection all;
2) comprise the trigger primary circuit of clock controlled reversed-phase circuit and negative circuit, wherein:
Clock controlled reversed-phase circuit comprises:
PMOS manages MP4, and the source electrode of this pipe and substrate all meet power vd D, and grid meets data input signal D;
PMOS manages MP3, and the drain electrode of the source electrode of this pipe and described MP4 pipe is joined, and the grid of this pipe meets CKD, and drain labeled is designated as node M X, and substrate meets power vd D;
NMOS manages MN4, and the drain electrode of this pipe is connected to node M X, and the grid of this pipe meets CKE, substrate ground connection;
NMOS manages MN3, and the drain electrode of this pipe connects the source electrode of described MN4 pipe, and grid meets data input signal D, source electrode and substrate ground connection;
PMOS manages MP6, and the source electrode of this pipe and substrate all meet power vd D;
PMOS manages MP5, and the drain electrode of the source electrode of this pipe and described MP6 pipe is joined, and the grid of this pipe meets CKE, and drain electrode is connected to node M X, and substrate meets power vd D;
NMOS manages MN6, and the drain electrode of this pipe is connected to node M X, and the grid of this pipe meets CKD, substrate ground connection;
NMOS manages MN5, and the drain electrode of this pipe connects the source electrode of described MN6 pipe, source electrode and substrate ground connection;
Negative circuit, XI1 constitutes by inverter, and this inverter XI1 is input as node M X, and output token is node M Y, and MY and described MP6 pipe, MN5 pipe join;
3) trigger comprises from the level circuit:
Two end to end inverter XI2 and XI3, the input marking of inverter XI2 is SY, output token is SX, promptly inverter XI3 be input as SX, be output as SY;
NMOS manages MN7, and the drain electrode of this MN7 pipe meets SY, and the grid of this pipe meets node M X, substrate ground connection;
NMOS manages MN8, and the drain electrode of this MN8 pipe meets SX, and the grid of this pipe meets node M Y, and the source electrode of source electrode and described MN7 pipe joins, substrate ground connection;
NMOS manages MN9, and the source electrode of the drain electrode of this MN9 pipe and described MN7 pipe, MN8 pipe joins, and the grid of this pipe meets clock signal C K, the source electrode of this pipe and substrate ground connection;
Inverter XI4, the input of this inverter is SX, output is Q signal;
Inverter XI5, the input of this inverter is SY, output is the QN signal.
Two of feature of the present invention is: the described inverter of being made up of stacked PMOS transistor, NMOS pipe, remove transistor MPE and MNE in this inverter, and the main input signal CKE of described trigger primary circuit replaced with CKN, thereby reduced transistor size, so its total power consumption compares LST_C
2MOS_SA is little.
Beneficial effect of the present invention is: compare with low clock swing range trigger LS_IP_DCO with traditional digital standard cells D FFX1, the present invention has following performance advantage: whole trigger adopts the single power supply power supply, be applicable to universal CMOS technology, can adopt low amplitude of oscillation clock signal to drive the power consumption that reduces clock network.The trigger power consumed is less, and under identical test condition, the time-delay power consumption is long-pending to reduce by 9.94%, and the time-delay of trigger is less, has reduced by 78.73% than the average electricity leakage power dissipation of LS_IP_DCO, and the delay performance that drives than conventional trigger device full swing clock signal is good.Trigger proposed by the invention is suitable as the digital circuit standard cell very much, and is applied in the low power consumption integrated circuit design.
Description of drawings
Fig. 1 is the flip-flop element schematic diagram, and D is a signal input part, and CK is a clock signal input terminal, and Q and QN are the complementary signal output.
Fig. 2 is the circuit structure diagram of the trigger DFFX1 that triggers of the rising edge of complementary output in the UMC 0.18 μ m technological standards cell library.
Fig. 3 is the circuit structure diagram of trigger LS_IP_DCO.
Fig. 4 is trigger LST_C of the present invention
2The circuit structure diagram of MOS_SA.
Fig. 5 is the analogous circuit structure chart of Fig. 4.
Embodiment
The present invention proposes a kind of based on C
2The low power consumption and low clock swing range D trigger of MOS and sensitive amplifier structure, this d type flip flop comprises 1) inverter formed by stacked PMOS transistor, NMOS pipe, 2) comprise the trigger primary circuit and 3 of clock controlled reversed-phase circuit and negative circuit) trigger constitutes from the level circuit.This trigger can be applicable to low amplitude of oscillation clock network Circuits System; Be applicable to general CMOS technology simultaneously, do not increase cost; And use the single power supply power supply.
Figure 4 shows that the high-performance low-clock signal excursion master-slave D type flip-flop LST_C that the present invention proposes
2The circuit structure of MOS_SA.The clock input drives to adopt and stacks the transistorized inverter of PMOS, and its output drives principal and subordinate's level of trigger, and the correctness of the d type flip flop of assurance makes LST_C simultaneously again
2The MOS_SA trigger can be worked under low clock swing range, has avoided adopting another VDD/2 power supply power supply.Than conventional trigger device and LS_IP_DCO, this structure has less time-delay and lower power consumption, is more suitable for the design in low power consumption integrated circuit.
Among Fig. 4, MPV, MP1, MP2, MPE, MN1, MN2, MNE form one can carry out anti-phase inverter to the low amplitude of oscillation, and MPV has the dividing potential drop effect as active load, makes that the voltage of node LV is VDD-V
DS(MPV), being equivalent to MP1, MP2, MPE, MN1, MN2, MNE so, to form power supply be the inverter of LV.Can so that its to the CK of the low amplitude of oscillation when anti-phase, leakage power is less.Therefore circuit has been realized only realizing that with a power supply power supply low amplitude of oscillation clock signal drives, and has avoided circuit is provided the difficulty of two power supplys and the physics realization of flip-flop element circuit.
The operation principle of circuit: at power vd D is under the situation of 1.8V, and when CK was low level, CKD was a low level, the highest 1.5V that can be of the voltage of CKE, and there is the inclined to one side effect of lining in the MP5 pipe simultaneously, manages correct the shutoff so can guarantee MP5; If data input signal D is a high level, this moment, node M X was a low level, and MY is a high level.When the clock rising edge arrived, according to the state of MX and MY, MN7 ended, and the MN8 conducting makes SX and SY be changed to low level and high level respectively, so Q upset is high level, and QN is a low level.D be low level situation similarly.When CK was high level, the highest 1.36V that can be of the voltage of CKD, CKE were low level, and there is the inclined to one side effect of lining in the MP3 pipe simultaneously, managed correct the shutoff so can guarantee MP3; Circuit has been realized the function of the d type flip flop that rising edge triggers thus.
Analogous circuit structure: remove MPV, MP1 among Fig. 4, MP2, MPE, MN1, MN2, the transistor MPE and MNE that can carry out anti-phase inverter of MNE composition to the low amplitude of oscillation; And the main input signal CKE of trigger shown in Figure 4 replaced with CKN.Circuit structure as shown in Figure 5.The title of this structure is designated as LS_C
2MOS_SA-1 is characterized in having reduced transistor size.Therefore its total power consumption compares LST_C
2MOS_SA is little, but because CKN voltage when high level is up to 1.36V, so the quiescent dissipation of structure is bigger under partial mode.
Essential features of the present invention is: at first, circuit can adopt in the situation of single power supply power supply Low amplitude of oscillation clock signal drives, and has effectively reduced the power consumption of clock network system. Secondly, in the flip-flop circuit Discharging and recharging of section's node is less, compares with the conventional trigger device and can reduce by 25.44% time-delay and 5.79% power consumption. At last, circuit adopts the master-slave type structure to be easy to be modified as the trailing edge trigger.
For LST_C more proposed by the invention2MOS_SA and LS_C2The MOS_SA-1 trigger is relative In the characteristic of property of other two routine triggers, we adopt UMC 0.18 μ m technology, use circuit simulation tools HSPICE has carried out emulation relatively to several circuit structures.
Transistor size, transistor width summation and dynamic power consumption that table 1 is depicted as four kinds of triggers compare. Its The data of middle LS_IP_DCO are drawn from document. Power supply VDD is 1.8V, in the emulation of circuit dynamic power consumption Clock signal input CK is 100MHz (amplitude of oscillation of DFFX1: 0V-1.8V, the amplitude of oscillation of remaining circuit: 0V-0.9V), 50% dutycycle is rise time and fall time 100ps. Data-signal input D is 50MHz, 50% dutycycle is rise time and fall time 100ps. Output termination 20fF capacitive load.
Table 1
| DFF | Number of transistors | Transistor width summation [μ] | Time-delay (D-Q) [ps] | Internal power consumption [μ W] | Clock power consumption [μ W] | The power consumption of data D [μ W] | Total power consumption [μ W] | Power consumption time-delay long-pending [fJ] |
| DFFX1 | 28 | 14.16 | 355.8 | 7.110 | 0.09704 | 0.01093 | 7.218 | 2.568 |
| LS_IP_DCO | 21 | N/A | 268.8 | N/A | N/A | N/A | 7.451 | 2.003 |
| LST_C 2MOS_SA | 27 | 18.05 | 265.3 | 6.681 | 0.06610 | 0.05271 | 6.800 | 1.804 |
| LS_C 2MOS_SA-1 | 25 | 18.09 | 260.0 | 6.317 | 0.06895 | 0.05702 | 6.443 | 1.675 |
As can be drawn from Table 1, compare LST_C with DFFX12The delay powerproduct of MOS_SA has reduced 29.75%; LS_C2The delay powerproduct of MOS_SA-1 has reduced by 34.77%. Compare with LS_IP_DCO, LST_C2The delay powerproduct of MOS_SA has reduced by 9.94%; LS_C2The delay powerproduct of MOS_SA-1 Reduced by 16.38%.
Table 2 is LST_C2The comparison of the static leakage power consumption of MOS_SA and LS_IP_DCO. LST_C2The average electricity leakage power dissipation of MOS_SA has reduced by 78.73% than LS_IP_DCO.
Table 2
| Trigger | CK | D | LS_IP_DCO[nW] | LST_C 2MOS_SA[nW] | |
| Electricity leakage power dissipation | Low level | Low level | 148.2931 | 0.3443 | |
| Low level | High level | 148.2920 | 0.4266 | ||
| High level | Low level | 38.1104 | 39.25 | ||
| High level | High level | 38.1094 | 39.28 | ||
| The percentage that average electricity leakage power dissipation reduces | 78.73％ | ||||
By relatively can finding out of above-mentioned data, trigger structure of the present invention and traditional trigger phase Ratio, it can drive with low amplitude of oscillation clock, except the power consumption that can reduce clock network, this trigger structure This all has bigger advantage on time-delay and power consumption. Compare with LS_IP_DCO, structure of the present invention is suitable for In universal CMOS technology, and only need the single power supply power supply, and preferably delay powerproduct is arranged. And by Feed back in MTCMOS and output that LS_IP_DCO uses, so LST_C2The area of MOS_SA can be not big In LS_IP_DCO. Therefore, these performance advantages of having of trigger structure of the present invention make it very suitable Close in the digital VLSI Design that is applied to low-power consumption.
Claims (2)
1. one kind based on C
2The low power consumption and low clock swing range D trigger of MOS and sensitive amplifier structure is characterized in that, this d type flip flop comprises:
1) inverter of being made up of stacked PMOS transistor, NMOS pipe is used for carrying out anti-phasely to hanging down amplitude of oscillation clock signal C K, and this inverter comprises:
PMOS manages (MPV), and the source electrode of this pipe and substrate meet power vd D, and grid and drain electrode are connected together;
PMOS manages (MP1), and the grid of the source electrode of this pipe and described (MPV) pipe, drain electrode are connected together, and the substrate of this pipe meets power vd D, and the grid of this pipe meets clock signal C K, and drain labeled is designated as CKN;
PMOS manages (MP2), and the grid of the source electrode of this pipe and described (MPV) pipe, drain electrode are connected together, and the substrate of this pipe meets power vd D, and the grid of this pipe meets CKN, and drain labeled is designated as CKD;
PMOS manages (MPE), and the grid of the source electrode of this pipe and described (MPV) pipe, drain electrode are connected together, and the substrate of this pipe meets power vd D, and the grid of this pipe meets CKD, and drain labeled is designated as CKE;
NMOS manages (MN1), and the drain electrode of the drain electrode of this pipe and described (MP1) pipe is connected to node CKN, and the grid of this pipe meets clock signal C K, and the source electrode of this pipe and substrate be ground connection all;
NMOS manages (MN2), and the drain electrode of the drain electrode of this pipe and described (MP2) pipe is connected to node CKD, and the grid of this pipe meets CKN, and the source electrode of this pipe and substrate be ground connection all;
NMOS manages (MNE), and the drain electrode of the drain electrode of this pipe and described (MPE) pipe is connected to node CKE, and the grid of this pipe meets CKD, and the source electrode of this pipe and substrate be ground connection all;
2) comprise the trigger primary circuit of clock controlled reversed-phase circuit and negative circuit, wherein:
Clock controlled reversed-phase circuit comprises:
PMOS manages (MP4), and the source electrode of this pipe and substrate all meet power vd D, and grid meets data input signal D;
PMOS manages (MP3), and the drain electrode of the source electrode of this pipe and described (MP4) pipe is joined, and the grid of this pipe meets CKD, and drain labeled is designated as node M X, and substrate meets power vd D;
NMOS manages (MN4), and the drain electrode of this pipe is connected to node M X, and the grid of this pipe meets CKE, substrate ground connection;
NMOS manages (MN3), and the drain electrode of this pipe connects the source electrode of described (MN4) pipe, and grid meets data input signal D, source electrode and substrate ground connection;
PMOS manages (MP6), and the source electrode of this pipe and substrate all meet power vd D;
PMOS manages (MP5), and the drain electrode of the source electrode of this pipe and described (MP6) pipe is joined, and the grid of this pipe meets CKE, and drain electrode is connected to node M X, and substrate meets power vd D;
NMOS manages (MN6), and the drain electrode of this pipe is connected to node M X, and the grid of this pipe meets CKD, substrate ground connection;
NMOS manages (MN5), and the drain electrode of this pipe connects the source electrode of described (MN6) pipe, source electrode and substrate ground connection;
Negative circuit is made of inverter (XI1), this inverter (XI1) be input as node M X, output token is node M Y, MY and described (MP6) manage, (MN5) pipe joins;
3) trigger comprises from the level circuit:
Two end to end inverters (XI2) and (XI3), the input marking of inverter (XI2) is SY, output token is SX, promptly inverter (XI3) be input as SX, be output as SY;
NMOS manages (MN7), and the drain electrode of being somebody's turn to do (MN7) pipe meets SY, and the grid of this pipe meets node M X, substrate ground connection;
NMOS manages (MN8), and the drain electrode of being somebody's turn to do (MN8) pipe meets SX, and the grid of this pipe meets node M Y, and the source electrode of source electrode and described (MN7) pipe joins substrate ground connection;
NMOS manages (MN9), and drain electrode and described (MN7) that is somebody's turn to do (MN9) pipe manages, the source electrode of (MN8) pipe joins, and the grid of this pipe meets clock signal C K, the source electrode of this pipe and substrate ground connection;
Inverter (XI4), the input of this inverter is SX, output is Q signal;
Inverter (XI5), the input of this inverter is SY, output is the QN signal.
2. described based on C according to claim 1
2The low clock swing range master-slave D flip-flop of MOS and sensitive amplifier structure, it is characterized in that, the transistor MPE and the MNE that are made up of in the inverter stacked PMOS transistor, NMOS pipe of described d type flip flop are removed, and the main input signal CKE of described trigger primary circuit replaced with CKN, and become the analogous circuit structure of this d type flip flop, thereby reduced transistor size, therefore further reduced total power consumption.
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| CN 200710119008 CN101079613A (en) | 2007-06-18 | 2007-06-18 | Low power consumption and low clock swing range D trigger based on C2MOS and sensitive amplifier structure |
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| CN 200710119008 CN101079613A (en) | 2007-06-18 | 2007-06-18 | Low power consumption and low clock swing range D trigger based on C2MOS and sensitive amplifier structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102426846A (en) * | 2011-12-07 | 2012-04-25 | 北京大学 | Sensitive-amplifier-based trigger |
| CN102592662A (en) * | 2011-01-11 | 2012-07-18 | 中国科学院声学研究所 | Storage unit and single-end low-swing bit line writing circuit |
| CN103580650A (en) * | 2012-07-20 | 2014-02-12 | 台湾积体电路制造股份有限公司 | D flip-flop with high-swing output |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN113595531A (en) * | 2021-08-06 | 2021-11-02 | 东南大学 | Low-delay semi-dynamic trigger based on tunneling field effect transistor hybrid integration |
| CN114826163A (en) * | 2022-05-16 | 2022-07-29 | 合肥工业大学 | Low-power-consumption high-performance trigger based on sensitive amplifier and working method thereof |
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2007
- 2007-06-18 CN CN 200710119008 patent/CN101079613A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102592662A (en) * | 2011-01-11 | 2012-07-18 | 中国科学院声学研究所 | Storage unit and single-end low-swing bit line writing circuit |
| CN102592662B (en) * | 2011-01-11 | 2014-11-12 | 中国科学院声学研究所 | Storage unit and single-end low-swing bit line writing circuit |
| CN102426846A (en) * | 2011-12-07 | 2012-04-25 | 北京大学 | Sensitive-amplifier-based trigger |
| CN103580650A (en) * | 2012-07-20 | 2014-02-12 | 台湾积体电路制造股份有限公司 | D flip-flop with high-swing output |
| CN103580650B (en) * | 2012-07-20 | 2016-08-17 | 台湾积体电路制造股份有限公司 | There is the d type flip flop of wide amplitude of oscillation outfan |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN113595531A (en) * | 2021-08-06 | 2021-11-02 | 东南大学 | Low-delay semi-dynamic trigger based on tunneling field effect transistor hybrid integration |
| CN114826163A (en) * | 2022-05-16 | 2022-07-29 | 合肥工业大学 | Low-power-consumption high-performance trigger based on sensitive amplifier and working method thereof |
| CN114826163B (en) * | 2022-05-16 | 2024-03-01 | 合肥工业大学 | Low-power-consumption high-performance trigger based on sense amplifier and working method thereof |
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