CN114826163B

CN114826163B - Low-power-consumption high-performance trigger based on sense amplifier and working method thereof

Info

Publication number: CN114826163B
Application number: CN202210527991.3A
Authority: CN
Inventors: 杜高明; 王超; 王�琦; 贾忱皓; 陈卓然; 陶斯博; 刘洋; 周睿彬; 杜嘉程; 崔丰麒
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2024-03-01
Anticipated expiration: 2042-05-16
Also published as: CN114826163A

Abstract

The invention discloses a low-power-consumption high-performance trigger based on a sense amplifier and a working method thereof, wherein the trigger comprises a trigger main stage and a trigger slave stage; wherein, the trigger main stage comprises: a precharge section, a RAM-like structure, a data input section, a switching tube, and a shorting tube; the flip-flop slave stage comprises two inverters inv3, inv4 and one C-cell. The invention can greatly reduce the possibility of burrs generated in the trigger so as to reduce the power consumption; the dependence of Q and QB can be eliminated, so that the running speed is improved; meanwhile, the influence of external load on the performance of the trigger can be greatly reduced.

Description

Low-power-consumption high-performance trigger based on sense amplifier and working method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a low-power-consumption high-performance trigger based on a sense amplifier and an implementation method thereof.

Background

In recent years, with the continuous development of semiconductor technology, the feature size of an integrated circuit is continuously reduced, the power consumption of a chip is also increased, the power consumption of the chip becomes a main factor for restricting the development of the integrated circuit, the increased power consumption is unfavorable for the use of portable equipment, and meanwhile, the problem of insufficient heat dissipation caused by the increased power consumption possibly causes that the chip cannot work normally, so that the reduction of the power consumption of the integrated circuit is particularly important. The trigger is a basic component unit of the digital circuit, the power consumption of the trigger accounts for about 30% -50% of the total power consumption of the digital circuit, the frequent overturn or the burr generation inside the trigger can greatly increase the power consumption of the chip, and the chip function can not be normally realized under serious conditions; meanwhile, the trigger is used as a basic component of the digital circuit, and the speed of the trigger greatly restricts the speed of the whole chip. Therefore, the invention provides a low-power-consumption and high-performance flip-flop which is a current problem to be solved in the field of integrated circuits.

Disclosure of Invention

The invention aims to solve the defects of the prior art, and provides a low-power-consumption high-performance trigger based on a sense amplifier and a working method thereof, so that the power consumption and the possibility of burrs generated in the trigger can be greatly reduced while the speed requirement of the trigger is ensured, and meanwhile, the dependence of Q and QB can be eliminated, so that the running speed is improved; and the external capacitive load and the inside of the trigger can be isolated, so that the anti-interference capability of the trigger is improved.

In order to achieve the aim of the invention, the invention adopts the following technical scheme:

the invention relates to a low-power-consumption high-performance trigger based on a sense amplifier, which is characterized by comprising the following components: a trigger master stage and a trigger slave stage;

the trigger master stage includes: the data input part, the pre-charging part, the RAM-like structure, the short circuit tube and the switch tube;

the data input section includes: a second NMOS tube N2 and a fourth NMOS tube N4;

the precharge section includes: the first PMOS tube P1 and the second PMOS tube P2;

the RAM-like structure is composed of two cross-coupled inverters and includes: the third PMOS tube P3, the fourth PMOS tube P4, the third NMOS tube N3 and the fifth NMOS tube N5; the third PMOS tube P3 and the third NMOS tube N3 form a first inverter inv1; a second inverter inv2 is formed by the fourth PMOS tube P4 and the fifth NMOS tube N5;

the short-circuit tube is a sixth NMOS tube N6;

the switching tube is a first NMOS tube N1;

the flip-flop slave stage comprises: a third inverter inv3 and a fourth inverter inv4 and 1C cell;

the third inverter inv3 is composed of a seventh PMOS tube P7 and a ninth NMOS tube N9;

the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;

the C unit comprises: a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8;

when the clock signal clk=0, the first PMOS transistor P1 and the second PMOS transistor P2 of the precharge portion place the full swing signals SB and RB output by the main stage of the flip-flop at a high level; meanwhile, when clk=0, the switching tube is turned off, so that a pull-down path between the third NMOS tube N3, the second NMOS tube N2, and the first NMOS tube N1 cannot be formed or a pull-down path formed between the fifth NMOS tube N5, the fourth NMOS tube N4, and the first NMOS tube N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the main stage of the trigger to be in a high level state;

the first PMOS tube P1 and the second PMOS tube P2 of the precharge part are turned off when the clock signal CLK=1, so that the full-swing signals SB and RB output by the main stage of the trigger are in a non-set state, and meanwhile, the switch tube is turned on when the clock signal CLK=1, so that the second NMOS tube N2 and the fourth NMOS tube N4 can selectively form a pull-down path between the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 or a pull-down path formed between the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 according to the values of the differential input signals D and DB, and the level of the full-swing signals SB or RB output by the main stage of the trigger is placed at a low level;

the second NMOS tube N2 and the fourth NMOS tube N4 respectively read external differential input signals D and DB and serve as inputs of a main stage of the trigger;

when the clock signal clk=1, the first inverter inv1 and the second inverter inv2 selectively pull down the full-swing signal SB or RB output by the main stage of the flip-flop through the first inverter inv1 or the second inverter inv2 according to the signal with higher level in the differential input signals D and DB, pull up the other full-swing signal RB or SB output by the main stage of the Gao Chufa device through the second inverter inv2 or the first inverter inv1, and output the full-swing signals SB and RB to the slave stage of the flip-flop;

the short circuit tube is always in a conducting state, and the error overturning of full-swing signal SB and RB output by the main stage of the trigger is caused by the leakage of the third PMOS tube P3 or the fourth PMOS tube P4 is released;

the third inverter inv3 inverts the full swing signal SB output by the main stage of the trigger and generates an input signal S of the C unit;

the C unit receives the input signal S and a full swing signal RB output by a trigger main stage and generates an output signal QB;

when the clock signal clk=0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS tube P5 or the sixth PMOS tube P6 is conducted, and the output signal QB of the C unit keeps a high resistance state;

when the clock signal clk=1, the C unit generates an output signal QB of the C unit according to the received output signals RB and S;

the fourth inverter inv4 inverts the output signal QB of the C cell and generates the output signal Q of the flip-flop.

The low-power-consumption high-performance trigger based on the sensitive amplifier is also characterized in that:

the first input end of the trigger main stage is the grid electrode of the second NMOS tube N2 and is connected with an external input signal D;

the second input end of the trigger main stage is the grid electrode of the fourth NMOS tube N4 and is connected to an external input signal DB;

the first output end of the main stage of the trigger is the drains of the first PMOS tube P1 and the third PMOS tube P3 and outputs a full swing signal SB;

the second output end of the main stage of the trigger is the drains of a second PMOS tube P2 and a fourth PMOS tube P4 and outputs a full swing signal RB;

the sources of the first PMOS tube P1 and the second PMOS tube P2 are connected with a power supply VDD, the gates of the first PMOS tube P1 and the second PMOS tube P2 are connected with a clock signal CLK, the drain electrode of the first PMOS tube P1 generates a full-swing signal SB output by the main stage of the trigger, and the drain electrode of the second PMOS tube P2 generates a full-swing signal RB output by the main stage of the trigger;

the third PMOS tube P3 is connected with the first PMOS tube P1 in parallel, the source electrode of the third PMOS tube P3 is connected with the source electrode of the first PMOS tube P1, the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, and the grid electrode of the third PMOS tube P3 is connected with the drain electrode of the fourth PMOS tube P4; the fourth PMOS tube P4 is connected in parallel with the second PMOS tube P2, the source electrode of the fourth PMOS tube P4 is connected to the source electrode of the second PMOS tube P2, the drain electrode of the fourth PMOS tube P4 is connected to the drain electrode of the second PMOS tube P2, and the grid electrode of the fourth PMOS tube P4 is connected to the drain electrode of the third PMOS tube P3;

the source electrode of the third NMOS tube N3 is connected to the drain electrode of the second NMOS tube N2, the drain electrode of the third NMOS tube N3 is connected to the drain electrode of the third PMOS tube P3, and the grid electrode of the third NMOS tube N3 is connected to the grid electrode of the third PMOS tube P3; the source electrode of the fifth NMOS tube N5 is connected to the drain electrode of the fourth NMOS tube N4, the drain electrode of the fifth NMOS tube N5 is connected to the drain electrode of the fourth PMOS tube P4, and the grid electrode of the fifth NMOS tube N5 is connected to the grid electrode of the fourth PMOS tube P4;

in the data input part, the source electrode of the second NMOS tube N2 and the source electrode of the fourth NMOS tube N4 are connected to the drain electrode of the first NMOS tube N1 together, the drain electrode of the second NMOS tube N2 is connected to the source electrode of the third NMOS tube N3, the grid electrode of the second NMOS tube N2 is used as a primary output end of the trigger and is connected with an external input signal D, the drain electrode of the fourth NMOS tube N4 is connected to the source electrode of the fifth NMOS tube N5, and the grid electrode of the fourth NMOS tube N4 is used as a secondary output end of the trigger and is connected with an external input signal DB;

the source electrode or the drain electrode of the sixth NMOS tube N6 is connected to the source electrode of the third NMOS tube N3; the drain electrode or the source electrode of the sixth NMOS tube N6 is connected to the source electrode of the fifth NMOS tube N5; the source electrode and the grid electrode of the fifth NMOS tube N5 are connected with a power supply VDD and keep an on state;

the source electrode of the first NMOS tube N1 is grounded GND, the drain electrode of the first NMOS tube N1 is connected with the source electrodes of the second NMOS tube N2 and the fourth NMOS tube N4, and the grid electrode of the first NMOS tube N1 is connected with a clock signal CLK.

The first input end of the secondary stage of the trigger is the grid electrode of the eighth NMOS tube N8 and the fifth PMOS tube P5 and is connected with a full-swing signal RB output by the primary stage of the trigger;

the second input end of the slave stage of the trigger is the grid electrode of a ninth NMOS tube N9 and is connected to a full-swing signal SB output by the master stage of the trigger;

the output end of the secondary trigger stage is the drain electrodes of the eighth PMOS tube P8 and the tenth NMOS tube N10, and an output signal Q of the secondary trigger stage is generated;

in the third inverter inv3, a seventh PMOS transistor P7 and a ninth NMOS transistor N9 are connected in series, a gate of the seventh PMOS transistor P7 is connected to drains of the first PMOS transistor P1 and the third PMOS transistor P3, a source of the seventh PMOS transistor P7 is connected to a power supply VDD, a source of the ninth NMOS transistor N9 is connected to ground GND, and after drains of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are shorted, a signal S generated by the drain is connected to gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7;

in the unit C, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8 are sequentially connected in series, the source electrode of the fifth PMOS tube P5 is connected to a power supply VDD, the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the sixth PMOS tube P6, the drain electrode of the sixth PMOS tube P6 is connected with the drain electrode of the seventh NMOS tube N7, the source electrode of the seventh NMOS tube N7 is connected to the drain electrode of the eighth NMOS tube N8, the drain electrode of the eighth NMOS tube N8 is connected to the ground GND, and the grid electrodes of the fifth PMOS tube P5 and the eighth NMOS tube N8 are connected to the drain electrodes of the second PMOS tube P2 and the fourth PMOS tube P4 after being in short circuit;

in the inverter inv4, an eighth PMOS transistor P8 and a tenth NMOS transistor N10 are connected in series, a source of the eighth PMOS transistor P8 is connected to the power supply VDD, and a source of the tenth NMOS transistor N10 is connected to the ground GND; after the gates of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted, the gates are connected to the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted.

The invention relates to a working method of a low-power-consumption high-performance trigger of a sense amplifier, which is characterized by being applied to a trigger consisting of a trigger main stage and a trigger slave stage; wherein the trigger master stage comprises: the data input part, the pre-charging part, the RAM-like structure, the short circuit tube and the switch tube;

the short-circuit tube is a sixth NMOS tube N6;

the switching tube is a first NMOS tube N1;

the C unit comprises: a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8; the working method comprises the following steps:

in the step 1, when the trigger is in the precharge phase, the clock signal clk=0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the first NMOS transistor N1 is turned off, so that the full swing signals SB and RB output by the main stage of the trigger are both 1, the full swing signal SB output by the main stage of the trigger passes through the third inverter inv3 and then outputs the signal s=0, meanwhile, the input signal rb=1, s=0 of the C unit, so that the sixth PMOS transistor P6 and the eighth NMOS transistor N8 are turned on, and the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed, at this time, the C unit is in a high impedance state, the output signal QB of the C unit remains unchanged, and the output signal Q of the slave stage of the trigger remains unchanged;

step 2, when the trigger is in a data sampling stage, a clock signal clk=1, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor N1 is turned on, after a precharge process, full swing signals SB and RB output by a main stage of the trigger are both in a high level, the third NMOS transistor N3 and the fifth NMOS transistor N5 are both in a conducting state, the second NMOS transistor N2 and the fourth NMOS transistor N4 sample input differential signals D and DB, and the second NMOS transistor N2 or the fourth NMOS transistor N4 is turned on according to a higher level signal in the input differential signals D and DB to form a discharge path on one side, so that the full swing signal SB or RB output by the main stage of the trigger is pulled down, the fourth PMOS transistor P4 or the third PMOS transistor P3 is turned on, and the full swing signal RB or SB output by the main stage of the trigger is charged to a high level; one signal of full swing signals SB and RB output by the main stage of the trigger is in high level, and the other signal is in low level;

when sb=0 and rb=1, the input signal s=1 and rb=1 of the C unit, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, and the output signal qb=0 of the C unit generates the output signal q=1 of the flip-flop slave stage after passing through the fourth inverter inv 4;

when sb=1 and rb=0, the input signal s=0 and rb=0 of the C unit, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, and the output signal qb=1 of the C unit generates the output signal q=0 of the flip-flop slave stage after passing through the fourth inverter inv 4.

Compared with the prior art, the invention has the beneficial effects that:

1. the conventional sense amplifier-based flip-flop Con SAFF of the prior art is composed of a cross-coupled inverter with Q and QB as inputs and 2 inverters with SB and RB as inputs, and there is a correlation between the Q and QB signals, and the Q and QB settling times differ by one nand gate delay, so that the rising delay and the falling delay of the output signal are not equal, thereby affecting the operation speed of the flip-flop. The low-power-consumption high-performance trigger based on the sensitive amplifier isolates QB and Q through the inverter, the slave stage does not adopt a symmetrical structure to generate Q and QB at the same time, and the rising delay and the falling delay are equal, so that the operation speed of the trigger is improved.

2. The conventional sense amplifier based flip-flop Con SAFF of the prior art, consisting of a cross-coupled inverter with Q and QB inputs and 2 inverters with SB and RB inputs, introduces a comparative logic: the pull-up network and the pull-down network compete, thereby affecting the stability of the flip-flop and possibly causing logic errors of the flip-flop. The low-power-consumption high-performance trigger based on the sense amplifier adopts the C unit at the slave stage, ensures that the polarities of the input signals S and RB of the C unit are the same, avoids the competition problem of the logic with the ratio, and improves the stability of the trigger.

3. In the prior art, the slave stage can effectively avoid the competition phenomenon by inserting the gate tube controlled by the clock, reduce the generation of burrs, but introduce additional devices and increase the power consumption. The low-power-consumption high-performance trigger based on the sensitive amplifier only needs 10 MOS tubes at the slave stage, which is less than 12 MOS tubes of the Strollo SAFF, so that the power consumption is reduced.

Drawings

FIG. 1 is a schematic diagram of a low power consumption high performance flip-flop primary structure based on a sense amplifier of the present invention;

FIG. 2 is a graph showing waveforms of signals CLK, SB, RB, D, DB according to the present invention;

FIG. 3 is a schematic diagram of a low power consumption high performance flip-flop slave stage structure based on a sense amplifier of the present invention;

fig. 4 is a schematic diagram of the overall structure of the low-power-consumption high-performance trigger based on the sense amplifier.

Detailed Description

In this embodiment, a low-power-consumption high-performance flip-flop based on a sense amplifier is mainly applied to a digital circuit with power consumption challenges as the process is advanced, and specifically includes: a trigger master stage and a trigger slave stage.

In this embodiment, as shown in fig. 1, the flip-flop main stage includes a data input section, a precharge section, a RAM-like structure, a shorting tube, and a switching tube. Wherein, the precharge part is used for setting the output signals SB and RB of the main stage of the trigger to 1 when the clock signal CLK is 0; the RAM-like structure is used for amplifying the difference value of the differential inputs D and DB of the main stage of the trigger so as to drive the main stage output signals SB and RB to become full-swing signals; the data input part is used for reading the trigger differential input signals D and DB; the switching tube is used for turning off a discharge path when the clock signal CLK=0, so that the primary output signals SB and RB are 1 no matter what values the input signals D and DB are, and simultaneously, when the clock signal CLK=1, the values of the primary output signals SB and RB of the trigger are controlled according to the values of the trigger input signals D and DB; the short circuit pipe is used for communicating the internal nodes A and B, so that a pull-down path exists between the main stage output signals SB and RB, the internal nodes A and B are prevented from floating at a low level, and the flip-flop output signal Q is prevented from being overturned by mistake;

specifically, the data input part includes a second NMOS transistor N2 and a fourth NMOS transistor N4;

the switching tube is a first NMOS tube N1;

in this embodiment, as shown in fig. 2, when the clock signal clk=0, the first PMOS transistor P1 and the second PMOS transistor P2 of the precharge portion place the full swing signals SB and RB output by the main stage of the flip-flop at a high level; meanwhile, when clk=0, the switching tube is turned off, so that a pull-down path between the third NMOS tube N3, the second NMOS tube N2, and the first NMOS tube N1 cannot be formed or a pull-down path formed between the fifth NMOS tube N5, the fourth NMOS tube N4, and the first NMOS tube N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the main stage of the trigger to be in a high level state;

the first PMOS tube P1 and the second PMOS tube P2 of the precharge part are turned off when the clock signal CLK=1, so that the full swing signals SB and RB output by the main stage of the trigger are in a non-setting state, and meanwhile, the switch tube is turned on when the clock signal CLK=1, so that a pull-down passage formed by the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 or a pull-down passage formed by the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 is selectively formed according to the values of the differential input signals D and DB, and the level of the main stage output signal SB or RB of the trigger is set at a low level;

specifically, when CLK is at high level, when d=0 and db=1 are input, the fourth NMOS transistor N4 and the fifth NMOS transistor N5, the first NMOS transistor N1 is turned on to form a discharge path, the RB node is connected to ground to become low level, and the signal RB is charged to high level through the first inverter inv1 and the SB node; when the input d=1 and db=0, the second NMOS transistor N2, the third NMOS transistor N3 and the first NMOS transistor N1 are turned on to form a discharge path, the SB node is connected with the ground and pulled to be at a low level, and the signal SB passes through the first inverter inv2 and the charging value of the RB node is at a high level;

the RAM-like structure is composed of two inverters inv1 and inv2 cross-coupled and comprises: the third PMOS tube P3, the fourth PMOS tube P4, the third NMOS tube N3 and the fifth NMOS tube N5, and the third PMOS tube P3 and the third NMOS tube N3 form a first inverter inv1; a second inverter inv2 is formed by the fourth PMOS tube P4 and the fifth NMOS tube N5; in this embodiment, as shown in table 1, when the clock signal clk=1, the output signal SB or RB of the primary stage of the flip-flop is selectively pulled down according to the higher level signal of the differential input signals D and DB, and the other output signal RB or SB of the flip-flop is pulled up by inv2 or inv1 and output to the secondary stage of the flip-flop;

table 1: the RAM-like structure clock inputs the signal CLK, inputs D and DB, outputs the truth table of SB and RB;

the short-circuit tube is a sixth NMOS tube N6 which is always conducted, and the false overturn of the main stage output signals SB and RB of the trigger caused by the leakage of the third PMOS tube P3 or the fourth PMOS tube P4 is released;

the flip-flop slave stage includes a third inverter inv3 and a fourth inverter inv4 and 1C cell. inv3 is used for reversing the output signal SB of the main stage of the trigger to generate a C unit input signal S; the C unit is used for ensuring that when the clock signal CLK=0, the trigger output signal Q is kept unchanged, and when the clock signal CLK=1, the trigger works normally, and the trigger output signal Q changes according to the values of the signals S and RB; inv4 is used for inverting the C unit output signal QB to generate a trigger output signal Q;

specifically, the inverter inv3 includes a seventh PMOS transistor P7 and a ninth NMOS transistor N9, configured to invert the full swing signal SB output by the main stage of the flip-flop, and generate an input signal S of the C unit;

the inverter inv4 includes: and the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are configured to invert the output signal QB of the C unit and generate the output signal Q of the flip-flop.

The C unit comprises a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8, receives the input signal S and a full swing signal RB output by the main stage of the trigger, and generates an output signal QB. In this example, as shown in table 2:

table 2: a truth table for inputting the signal CLK, inputting S, RB and outputting QB;

specifically, when clk=0 and the two inputs S and RB of the C unit are unequal (s=0, rb=1 or s=1, rb=0), the pull-up path and the pull-down path of the C unit cannot be turned on, the C unit is in a high-impedance state, the output QB remains unchanged, and the C unit can effectively filter single-node inversion; when clk=1 and the two inputs S and RB of the c unit are equal, s=rb=0, the pull-up path (fifth PMOS transistor P5, sixth PMOS transistor P6) is turned on, qb=1. When s=rb=1, the pull-down path (seventh NMOS transistor N7, eighth NMOS transistor N8) is turned on, and qb=0.

the second output end of the main stage of the trigger is the drains of the second PMOS tube P2 and the fourth PMOS tube P4 and outputs a full swing signal RB;

in the data input part, the source electrode of the second NMOS tube N2 and the source electrode of the fourth NMOS tube N4 are connected to the drain electrode of the first NMOS tube N1 together, the drain electrode of the second NMOS tube N2 is connected to the source electrode of the third NMOS tube N3, the grid electrode of the second NMOS tube N2 is used as a trigger main stage first output end and is connected with an external input signal D, the drain electrode of the fourth NMOS tube N4 is connected to the source electrode of the fifth NMOS tube N5, and the grid electrode of the fourth NMOS tube N4 is used as a trigger main stage second output end and is connected with an external input signal DB.

In this embodiment, as shown in fig. 3, the first input end of the slave stage of the trigger is the gates of the eighth NMOS transistor N8 and the fifth PMOS transistor P5, and is connected to the full swing signal RB output by the master stage of the trigger;

the second input end of the slave stage of the trigger is the grid electrode of the ninth NMOS tube N9 and is connected to the full swing signal SB output by the master stage of the trigger;

the output end of the slave stage of the trigger is the drain electrodes of the eighth PMOS tube P8 and the tenth NMOS tube N10, and an output signal Q of the slave stage of the trigger is generated;

in the fourth inverter inv4, an eighth PMOS transistor P8 and a tenth NMOS transistor N10 are connected in series, a source of the eighth PMOS transistor P8 is connected to the power supply VDD, and a source of the tenth NMOS transistor N10 is connected to the ground GND; after the gates of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted, the gates are connected to the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted.

In this embodiment, as shown in fig. 4, a low-power-consumption high-performance trigger based on a sense amplifier works as follows:

step 2, in this embodiment, as shown in table 3:

TABLE 3 trigger truth table

When the trigger is in a data sampling stage, a clock signal CLK=1, a first PMOS tube P1 and a second PMOS tube P2 are turned off, a first NMOS tube N1 is turned on, after a precharge process, full-swing signals SB and RB output by a main stage of the trigger are all in high level, a third NMOS tube N3 and a fifth NMOS tube N5 are in a conducting state, the second NMOS tube N2 and the fourth NMOS tube N4 sample input differential signals D and DB, and according to higher level signals in the input differential signals D and DB, the second NMOS tube N2 or the fourth NMOS tube N4 is started to form a discharge channel at one side, so that the full-swing signals SB or RB output by the main stage of the trigger are pulled down, the fourth PMOS tube P4 or the third PMOS tube P3 is started, and the full-swing signals RB or SB output by the main stage of the trigger are charged to the high level; one signal of full swing signals SB and RB output by the main stage of the trigger is in high level, and the other signal is in low level;

Claims

1. A low power consumption high performance trigger based on a sense amplifier, comprising: a trigger master stage and a trigger slave stage;

the short-circuit tube is a sixth NMOS tube N6;

the switching tube is a first NMOS tube N1;

2. The sense amplifier-based low power consumption high performance flip-flop of claim 1, wherein:

3. The sense amplifier-based low power consumption high performance flip-flop of claim 1, wherein:

4. A working method of a low-power-consumption high-performance trigger of a sense amplifier is characterized by being applied to a trigger consisting of a trigger main stage and a trigger slave stage; wherein the trigger master stage comprises: the data input part, the pre-charging part, the RAM-like structure, the short circuit tube and the switch tube;

the short-circuit tube is a sixth NMOS tube N6;

the switching tube is a first NMOS tube N1;