CN111105827B - SRAM sensitive amplifier circuit and storage unit - Google Patents

SRAM sensitive amplifier circuit and storage unit Download PDF

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Publication number
CN111105827B
CN111105827B CN201811251479.0A CN201811251479A CN111105827B CN 111105827 B CN111105827 B CN 111105827B CN 201811251479 A CN201811251479 A CN 201811251479A CN 111105827 B CN111105827 B CN 111105827B
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signal
tube
bit line
nmos
circuit
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CN111105827A (en
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柯蕾
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

An SRAM sense amplifier circuit and a storage unit, the SRAM sense amplifier circuit includes a control signal generating unit, a signal amplifying unit and a signal outputting unit, wherein: the control signal generating unit is connected with the clock signal generating unit and the signal amplifying unit, the signal amplifying unit is connected with the control signal generating unit and the signal output unit, and the signal amplifying unit includes: the circuit comprises a bit line signal latch circuit, a bit line signal amplifying circuit and a positive feedback circuit; the bit line signal latch circuit is connected with the signal amplification unit; the bit line signal amplifying circuit is connected with the bit line signal latching circuit and the positive feedback circuit; the positive feedback circuit is connected with the signal amplification circuit and the signal output circuit; and the signal output unit is connected with the signal amplification unit. The scheme of the invention can improve the reading margin and improve the stability of the reading operation.

Description

SRAM sensitive amplifier circuit and storage unit
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an SRAM (static random access memory) sensitive amplifier circuit and a storage unit.
Background
A Sense Amplifier (SA) is an important component of a peripheral circuit of a Static Random Access Memory (SRAM). In the memory cell of the SRAM, a sense amplifier samples and amplifies a slight signal change on a bit line, so that the memory cell of the SRAM can determine the storage information of the corresponding memory cell in a read operation.
With the development of integrated circuit technology, the feature size of transistors is gradually reduced, and the operating voltage of the circuit is gradually reduced. In the prior art, a sense amplifier is used for amplifying a differential voltage on a bit line, but as a power supply voltage is continuously reduced, a read margin of the sense amplifier is also continuously reduced. The reduction of the read margin not only limits the speed of the read operation, but also causes the stability and the anti-interference capability of the read operation to be reduced.
Disclosure of Invention
The embodiment of the invention solves the problem of improving the read margin to improve the stability of the read operation.
To solve the above technical problem, an embodiment of the present invention provides an SRAM sense amplifier circuit, where the SRAM sense amplifier circuit includes: control signal generation unit, signal amplification unit and signal output unit, wherein: the control signal generating unit is connected with the clock signal generating unit and the signal amplifying unit and is used for receiving the internal clock signal generated by the clock signal generating unit and controlling the switching and the pre-charging of the sensitive amplifier by adopting the internal clock signal; the signal amplifying unit is connected with the control signal generating unit and the signal output unit and is used for amplifying the received bit line signal and outputting the amplified bit line signal to the signal output unit; the signal amplification unit includes: the circuit comprises a bit line signal latch circuit, a bit line signal amplifying circuit and a positive feedback circuit; the bit line signal latch circuit is connected with the signal amplification unit and is used for latching and amplifying a bit line signal; the bit line signal amplifying circuit is connected with the bit line signal latching circuit and the positive feedback circuit and is used for differentially amplifying the bit line signals; the positive feedback circuit is connected with the signal amplifying circuit and the signal output circuit and is used for positively feeding back the bit line signal and the amplified bit line signal; and the signal output unit is connected with the signal amplification unit and used for processing and outputting the amplified bit line signal.
Optionally, the bit line signal latch circuit further includes a precharge circuit; the pre-charging circuit is connected with the bit line signal latch circuit and is used for pre-charging the bit line signal latch circuit.
Optionally, the bit line signal latch circuit includes a pre-charge circuit, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the pre-charging circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; wherein: the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor and the internal clock signal, the source of the first PMOS transistor is connected to the source of the third PMOS transistor, the source of the fifth PMOS transistor and the source of the sixth PMOS transistor, and the drain of the first PMOS transistor is connected to the source of the first NMOS transistor, the drain of the fifth PMOS transistor, the gate of the second NMOS transistor, the gate of the sixth PMOS transistor, the bit line signal amplifying circuit, the amplified bit line signal and the signal output unit; the source electrode of the second PMOS tube is connected with the power supply, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube and the bit line signal amplifying circuit; the drain of the third PMOS tube is connected with the drain of the sixth PMOS tube, the source of the second NMOS tube, the gate of the fifth PMOS tube, the gate of the first NMOS tube, the bit line signal amplifying unit, the inverse signal of the amplified bit line signal and the signal output unit; and the source electrode of the fourth PMOS tube is connected with the power supply, and the drain electrode of the fourth PMOS tube is connected with the bit line signal amplifying circuit and the drain electrode of the second NMOS tube.
Optionally, the substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor are connected to a power supply, and the substrates of the first NMOS transistor and the second NMOS transistor are grounded.
Optionally, the bit line signal amplifying circuit includes a third NMOS transistor and a fourth NMOS transistor, where: the grid electrode of the third NMOS tube is connected with a counter signal of the bit line signal, the source electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the first NMOS tube, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube and the positive feedback circuit; and the grid electrode of the fourth NMOS tube is connected with the bit line signal, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube and the drain electrode of the fourth PMOS tube.
Optionally, the third NMOS transistor and the fourth NMOS transistor are grounded.
Optionally, the positive feedback circuit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, wherein: the grid electrode of the fifth NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the sixth PMOS tube and the signal output unit, the source electrode of the fifth NMOS tube is connected with the bit line signal and control signal generation unit, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the sixth PMOS tube, the source electrode of the second NMOS tube, the grid electrode of the fifth PMOS tube, the grid electrode of the first NMOS tube, the amplified bit line signal inverse signal and the signal output unit, and the source electrode of the sixth NMOS tube is connected with the bit line signal inverse signal and the control signal generation unit; the grid electrode of the seventh NMOS tube is connected with the internal clock signal, the source electrode of the seventh NMOS tube is connected with the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube, the drain electrode of the seventh NMOS tube is connected with the source electrode of the eighth NMOS tube, the substrate of the seventh NMOS tube is connected with the substrate of the eighth NMOS tube and the drain electrode of the eighth NMOS tube, and the seventh NMOS tube is connected with the signal output unit; and the grid electrode of the eighth NMOS tube is connected with the control signal generating unit.
Optionally, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are grounded.
In order to solve the above technical problem, an embodiment of the present invention further discloses a memory cell, including any one of the above SRAM sense amplifier circuits.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the sense amplifier is controlled by an external signal and is changed into an internal clock, a bit line signal latch circuit, a bit line signal amplification circuit and a positive feedback circuit are added, two pairs of NMOS tubes are added and are respectively used for differentially amplifying the input of a bit line signal and a positive feedback circuit of the bit line signal, and therefore the read margin of the SRAM is improved.
Furthermore, a pre-charge circuit is added in the bit line signal latch circuit, and comprises four additional PMOS tubes as pre-charge tubes of the pre-charge circuit, and the pre-charge tubes are used for pre-charging the bit line signal latch circuit so as to improve the latching and amplifying effects of the bit line signal latch circuit on bit line signals, and further improve the read margin of the SRAM.
Drawings
FIG. 1 is a circuit diagram of a prior art SRAM sense amplifier circuit;
FIG. 2 is a circuit diagram of an SRAM sense amplifier circuit according to an embodiment of the present invention;
fig. 3 is a comparison diagram of read margins of an SRAM sense amplifier circuit in the prior art and an SRAM sense amplifier circuit in the embodiment of the present invention.
Detailed Description
In the prior art, a sense amplifier samples and amplifies a differential voltage on a bit line. As the supply voltage continues to decrease, the read margin of the sense amplifier also continues to decrease. The reduction of the read margin not only limits the speed of the read operation, but also causes the stability and the anti-interference capability of the read operation to be reduced.
In the embodiment of the invention, the sense amplifier is changed from external signal control to internal clock control, and the bit line signal latch circuit, the bit line signal amplification circuit and the positive feedback circuit are added, wherein the sense amplifier comprises two pairs of NMOS tubes which are respectively used for differentially amplifying the input of the bit line signal and the positive feedback circuit of the bit line signal, so that the read margin of the SRAM is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The SRAM sensitive amplifier circuit provided by the embodiment of the invention can be applied to a storage unit of an integrated circuit.
Fig. 1 is a circuit configuration diagram of a conventional SRAM sense amplifier circuit.
The conventional SRAM sense amplifier circuit includes a control signal generating unit 101, a signal amplifying unit 102, and a signal outputting unit 103.
The control signal generating unit 101, connected to the clock signal generating unit and the signal amplifying unit, may be configured to receive the internal clock signals CK1 and CK4 generated by the clock signal generating unit, and may be configured to control the switching and precharging of the sense amplifier.
In a specific implementation, the internal clock signal CK1 is processed and repaired by two stages of inverters to output the internal clock signal CK 3. When the internal clock signal CK3 is high, the sense amplifier is turned on.
In a specific implementation, the internal clock signal CK4 is processed and repaired by two stages of inverters to output the internal clock signal CK 6. When the internal clock signal CK6 is low, the sense amplifier starts precharging, precharging the bit line signals DB, DBX and the D, DX signal of the signal amplifying unit 102 to a high level.
The signal amplifying unit 102 is connected to the control signal generating unit 101 and the signal output unit 103, and is configured to amplify the received bit line signals DB and DBX and output the amplified bit line signals to the signal output unit 103.
In a specific implementation, the internal clock signals CK1 and CK4 output a shutdown signal close through circuits formed by connecting nand gates and inverters in series, respectively. When the signal output by the off signal close is high, the signal amplifying unit 102 is isolated from the bit line signals DB, DBX. At this time, the internal clock signals CK3 and CK6 of the control signal generating unit are simultaneously high level, and the bit line signals DB, DBX are amplified and output to the signal output unit 103.
In a specific implementation, the shutdown signal close controls the isolation and amplification of the bit line signals DB, DBX. Therefore, the delay time of the off signal close and the internal clock signal CK3 in the signal amplification unit may cause the voltage of the bit line signals DB, DBX to drop, resulting in a drop in the read margin.
The signal output unit 103 is connected to the signal amplification unit 102, and is configured to process and output the amplified bit line signal D, DX.
In a specific implementation, the amplified bit line signal D, DX is processed by a latch formed by two nand gates and an inverter and then output to the output terminal, thereby completing the amplification process of the bit line signals DB and DBX.
In the specific implementation, the substrates of all PMOS tubes are connected with a power supply, and the substrates of all NMOS tubes are grounded.
In the prior art, a sense amplifier is used for amplifying a differential voltage on a bit line, but as a power supply voltage is continuously reduced, a read margin of the sense amplifier is also continuously reduced. The reduction of the read margin not only limits the speed of the read operation, but also causes the stability and the anti-interference capability of the read operation to be reduced.
Fig. 2 is a circuit structure diagram of an SRAM sense amplifier circuit in an embodiment of the present invention.
The SRAM sense amplifier circuit in the embodiment of the present invention includes a control signal generating unit 201, a signal amplifying unit 202, and a signal outputting unit 203.
The control signal generating unit 201 is connected to the clock signal generating unit and the signal amplifying unit 102, and is configured to receive the internal clock signal CK3 generated by the clock signal generating unit, and control the switching and precharging of the sense amplifier by using the internal clock signal CK 3.
In a specific implementation, the internal clock signal CK1 is processed and repaired by two stages of inverters to output the internal clock signal CK 3. When the internal clock signal CK3 is high, the sense amplifier is turned on.
In a specific implementation, the internal clock signal CK4 is processed and repaired by two stages of inverters to output the internal clock signal CK 6. When the internal clock signal CK6 is low, the sense amplifier starts precharging.
The signal amplifying unit 202 is connected to the control signal generating unit 201 and the signal output unit 203, and is configured to amplify the received bit line signals DB and DBX and output the amplified bit line signals to the signal output unit 203. The signal amplification unit 202 further includes: a bit line signal latch circuit, a bit line signal amplification circuit and a positive feedback circuit. The bit line signal latch circuit is connected with the signal amplification unit 201 and is used for latching and amplifying bit line signals DB and DBX; the bit line signal amplifying circuit is connected with the bit line signal latching circuit and the positive feedback circuit and is used for differentially amplifying the bit line signals DB and DBX; the positive feedback circuit is connected to the signal amplifying circuit and the signal output circuit 203, and is configured to positively feedback the bit line signals DB and DBX and the amplified bit line signal D, DX.
In a specific implementation, the bit line signal latch circuit may further include a precharge circuit; the pre-charging circuit is connected with the bit line signal latch circuit and is used for pre-charging the bit line signal latch circuit.
In a specific implementation, the internal clock signal CK3 replaces the shutdown signal close in the prior art to control the amplification process of the bit line signals DB, DBX. When a signal output with respect to the internal clock signal CK3 is at a high level, the signal amplifying unit 202 is isolated from the bit line signals DB, DBX. At this time, the internal clock signals CK3 and CK6 of the control signal generating unit are simultaneously high level, and the bit line signals DB, DBX are amplified and output to the signal output unit 203.
In a specific implementation, the bit line signal latch circuit may include a precharge circuit, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the pre-charging circuit can comprise a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor.
In an embodiment of the present invention, the adding of the precharge circuit to the bit line signal latch circuit includes adding four PMOS transistors as the precharge transistors of the precharge circuit for precharging the bit line signal latch circuit to improve the latch and amplification effects of the bit line signal latch circuit on the bit line signal, thereby improving the read margin of the SRAM.
In a specific implementation, the bit line signal amplifying circuit may include a third NMOS transistor and a fourth NMOS transistor.
In a specific implementation, the positive feedback circuit may include a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor.
In an embodiment of the present invention, a positive feedback circuit is added to the signal amplifying unit 202, which includes two pairs of NMOS transistors respectively used for differentially amplifying the input of the bit line signal and a positive feedback loop for the bit line signal, so as to improve the read margin of the SRAM.
In a specific implementation, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor and the internal clock signal CK3, the source of the first PMOS transistor is connected to the source of the third PMOS transistor, the source of the fifth PMOS transistor and the source of the sixth PMOS transistor, the drain of the first PMOS transistor is connected to the source of the first NMOS transistor, the drain of the fifth PMOS transistor, the gate of the second NMOS transistor, the gate of the sixth PMOS transistor, the bit line signal amplifying circuit, the amplified bit line signal D, DX and the signal output unit 203;
the source electrode of the second PMOS tube is connected with a power supply VDD, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube and the bit line signal amplifying circuit;
the drain of the third PMOS transistor is connected to the drain of the sixth PMOS transistor, the source of the second NMOS transistor, the gate of the fifth PMOS transistor, the gate of the first NMOS transistor, the bit line signal amplifying circuit, the inverse signal DX of the amplified bit line signal, and the signal output unit 203;
and the source electrode of the fourth PMOS tube is connected with a power supply VDD, and the drain electrode of the fourth PMOS tube is connected with the bit line signal amplifying circuit and the drain electrode of the second NMOS tube.
In a specific implementation, a gate of the third NMOS transistor is connected to a counter signal DBX of the bit line signal, a source of the third NMOS transistor is connected to a drain of the second PMOS transistor and a drain of the first NMOS transistor, and a drain of the third NMOS transistor is connected to a drain of the fourth NMOS transistor and the positive feedback circuit;
and the grid electrode of the fourth NMOS tube is connected with the bit line signal DB, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube and the drain electrode of the fourth PMOS tube.
In a specific implementation, a gate of the fifth NMOS transistor is connected to the source of the first NMOS transistor, the drain of the first PMOS transistor, the drain of the fifth PMOS transistor, the gate of the second NMOS transistor, the gate of the sixth PMOS transistor, and the signal output unit 203, a source is connected to the bit line signal DB and the control signal generating unit 201, and a drain is connected to the drain of the sixth NMOS transistor;
the gate of the sixth NMOS transistor is connected to the drain of the third PMOS transistor, the drain of the sixth PMOS transistor, the source of the second NMOS transistor, the gate of the fifth PMOS transistor, the gate of the first NMOS transistor, the inverse signal DX of the amplified bit line signal, and the signal output unit 203, and the source is connected to the inverse signal DBX of the bit line signal and the control signal generation unit 201;
the gate of the seventh NMOS transistor is connected to the internal clock signal CK3, the source of the seventh NMOS transistor is connected to the drain of the third NMOS transistor and the drain of the fourth NMOS transistor, the drain of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, the substrate of the seventh NMOS transistor is connected to the substrate of the eighth NMOS transistor and the drain of the eighth NMOS transistor, and the seventh NMOS transistor is connected to the signal output unit 203; and the gate of the eighth NMOS transistor is connected to the control signal generating unit 201.
The signal output unit 203 is connected to the signal amplifying unit 202, and is configured to process and output the amplified bit line signal D, DX.
In a specific implementation, the amplified bit line signal D, DX is processed by a latch formed by two nand gates and an inverter and then output to the output terminal, thereby completing the amplification process of the bit line signals DB and DBX.
In the specific implementation, the substrates of all PMOS tubes are connected with a power supply, and the substrates of all NMOS tubes are grounded.
Compared with the prior art, the scheme of the invention changes the control of the sense amplifier from the close signal to the CK3 controlled by the internal clock, and adds the bit line signal latch circuit, the bit line signal amplification circuit and the positive feedback circuit, including adding two pairs of NMOS tubes which are respectively used for differentially amplifying the input of the bit line signal and the positive feedback circuit of the bit line signal, thereby improving the read margin of the SRAM.
Furthermore, a pre-charge circuit is added in the bit line signal latch circuit, and comprises four additional PMOS tubes as pre-charge tubes of the pre-charge circuit, and the pre-charge tubes are used for pre-charging the bit line signal latch circuit so as to improve the latching and amplifying effects of the bit line signal latch circuit on bit line signals, and further improve the read margin of the SRAM.
Fig. 3 is a comparison diagram of read margins of an SRAM sense amplifier circuit in the prior art and an SRAM sense amplifier circuit in the embodiment of the present invention.
Referring to fig. 3, it can be seen that, compared with the read margin of the SRAM sense amplifier circuit in the prior art, the read margin of the SRAM sense amplifier circuit in the embodiment of the present invention is larger, thereby ensuring the stability of the read operation.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (6)

1. An SRAM sense amplifier circuit, comprising: control signal generation unit, signal amplification unit and signal output unit, wherein:
the control signal generating unit is connected with the clock signal generating unit and the signal amplifying unit and is used for receiving the internal clock signal generated by the clock signal generating unit and controlling the switching and the pre-charging of the sensitive amplifier by adopting the internal clock signal;
the signal amplifying unit is connected with the control signal generating unit and the signal output unit and is used for amplifying the received bit line signal and outputting the amplified bit line signal to the signal output unit; the signal amplification unit includes: the circuit comprises a bit line signal latch circuit, a bit line signal amplifying circuit and a positive feedback circuit;
the bit line signal latch circuit is connected with the signal amplification unit and is used for latching and amplifying bit line signals;
the bit line signal amplifying circuit is connected with the bit line signal latching circuit and the positive feedback circuit and is used for differentially amplifying the bit line signals;
the positive feedback circuit is connected with the signal amplifying circuit and the signal output circuit and is used for positively feeding back the bit line signal and the amplified bit line signal;
the signal output unit is connected with the signal amplification unit and used for processing and outputting the amplified bit line signal;
the bit line signal latch circuit comprises a pre-charge circuit, a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube; the pre-charging circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; wherein:
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the internal clock signal, the source electrode of the first PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube, and the drain electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, the source electrode of the fifth PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the sixth PMOS tube, the positive feedback circuit, the amplified bit line signal and the signal output unit;
the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube and the bit line signal amplifying circuit;
the source electrode of the third PMOS tube is connected with the drain electrode of the sixth PMOS tube, the drain electrode of the second NMOS tube, the grid electrode of the fifth PMOS tube, the grid electrode of the first NMOS tube, the positive feedback circuit, the amplified bit line signal inverse signal and the signal output unit;
the drain electrode of the fourth PMOS tube is connected with a power supply, and the source electrode of the fourth PMOS tube is connected with the bit line signal amplifying circuit and the source electrode of the second NMOS tube;
the bit line signal amplifying circuit comprises a third NMOS tube and a fourth NMOS tube, wherein:
the grid electrode of the third NMOS tube is connected with a counter signal of the bit line signal, the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the first NMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube and the positive feedback circuit;
and the grid electrode of the fourth NMOS tube is connected with the bit line signal, and the source electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube and the source electrode of the fourth PMOS tube.
2. The SRAM sense amplifier circuit of claim 1, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor are connected to a power supply, and the first NMOS transistor and the second NMOS transistor are grounded.
3. The SRAM sense amplifier circuit of claim 1 wherein the third NMOS transistor and fourth NMOS transistor substrate are grounded.
4. The SRAM sense amplifier circuit of claim 1, wherein the positive feedback circuit comprises a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, wherein:
the grid electrode of the fifth NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the sixth PMOS tube and the signal output unit, the source electrode of the fifth NMOS tube is connected with the bit line signal and control signal generation unit, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the sixth PMOS tube, the source electrode of the second NMOS tube, the grid electrode of the fifth PMOS tube, the grid electrode of the first NMOS tube, the amplified bit line signal inverse signal and the signal output unit, and the source electrode of the sixth NMOS tube is connected with the bit line signal inverse signal and the control signal generation unit;
the grid electrode of the seventh NMOS tube is connected with the internal clock signal, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, the substrate of the seventh NMOS tube is connected with the substrate of the eighth NMOS tube and the source electrode of the eighth NMOS tube, and the seventh NMOS tube is connected with the signal output unit;
and the grid electrode of the eighth NMOS tube is connected with the control signal generating unit.
5. The SRAM sense amplifier circuit of claim 4, wherein the fifth, sixth, seventh and eighth NMOS transistors substrates are grounded.
6. A memory cell comprising the SRAM sense amplifier circuit of any one of claims 1 to 5.
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CN112259135B (en) * 2020-10-23 2021-08-13 海光信息技术股份有限公司 Read data control device and method of static random access memory and electronic equipment
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CN107464584A (en) * 2016-06-02 2017-12-12 中芯国际集成电路制造(上海)有限公司 It is a kind of to increase the sense amplifier and electronic installation for reading data surplus
CN107818801A (en) * 2016-09-14 2018-03-20 中芯国际集成电路制造(上海)有限公司 Sensitive amplifier circuit and memory

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KR100394573B1 (en) * 2001-05-31 2003-08-14 삼성전자주식회사 Sense amplifier in semiconductor memory device

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CN1909108A (en) * 2005-08-01 2007-02-07 旺宏电子股份有限公司 Sense amplifier with input offset compensation
CN107464584A (en) * 2016-06-02 2017-12-12 中芯国际集成电路制造(上海)有限公司 It is a kind of to increase the sense amplifier and electronic installation for reading data surplus
CN107818801A (en) * 2016-09-14 2018-03-20 中芯国际集成电路制造(上海)有限公司 Sensitive amplifier circuit and memory

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