CN108346442B - Sensitive amplifier - Google Patents
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- CN108346442B CN108346442B CN201710060981.2A CN201710060981A CN108346442B CN 108346442 B CN108346442 B CN 108346442B CN 201710060981 A CN201710060981 A CN 201710060981A CN 108346442 B CN108346442 B CN 108346442B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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Abstract
The invention provides a sensitive amplifier which comprises a reference current branch and a storage unit current branch, wherein the reference current branch is provided with a first input end and a first output end, the storage unit current branch is provided with a second input end and a second output end, the first input end is directly connected with the first output end through a first feedback amplifying circuit, and the second input end is directly connected with the second output end through a second feedback amplifying circuit; differential signals input at the first input end and the second input end generate output signals through the sensitive amplifier, the output signals pass through the first feedback amplifying circuit or the second feedback amplifying circuit, and the voltage signal of one input end of the first input end and the second input end is pulled down, so that the differential voltage of the two input ends is increased, the anti-interference capacity of the sensitive amplifier is improved, the speed performance of the sensitive amplifier is improved, and the design of the high-sensitivity amplifier is realized.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a sensitive amplifier.
Background
A Sense Amplifier (SA) is an important component of an NVM (non-volatile memory) circuit for reading data in a memory array. Sense amplifiers are widely used in various memory designs to convert differential small signals into large signals to resolve "1" or "0" data stored in a memory (Bit Cell).
Sense amplifiers typically include a reference current branch and a memory cell current branch, with either a "0" or "1" signal being output by comparing the reference current branch to the memory cell current branch.
With the development of advanced technology, the power supply voltage is further reduced, and the anti-interference capability of the sense amplifier to noise is required to be further improved, and especially when a high-speed reading circuit is designed, how to increase the differential input voltage of the sense amplifier is beneficial to anti-interference and speed performance improvement.
Therefore, how to increase the differential input voltage of the sense amplifier, improve the anti-interference capability and improve the speed performance is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a sense amplifier, which increases differential input voltage, enhances the anti-interference capability of the sense amplifier and improves the speed performance.
In order to achieve the above object, the present invention provides a sense amplifier, including a reference current branch and a memory cell current branch connected to each other, where the reference current branch has a first input terminal and a first output terminal, and the memory cell current branch has a second input terminal and a second output terminal, and the first input terminal is directly connected to the first output terminal through a first feedback amplifier circuit, the second input terminal is directly connected to the second output terminal through a second feedback amplifier circuit, the first feedback amplifier circuit is configured to amplify an output signal of the first output terminal, and the second feedback amplifier circuit is configured to amplify an output signal of the second output terminal.
Optionally, the first feedback amplifying circuit includes a first inverter and a twelfth transistor; the second feedback amplifying circuit comprises a second inverter and a thirteenth transistor.
Optionally, an input end of the first inverter is connected to the first output end, and an output end of the first inverter is connected to a gate of the twelfth transistor; the drain of the twelfth transistor is connected to the first input end, and the source of the twelfth transistor is connected to a ground terminal; an input end of the second inverter is connected to the second output end, and an output end of the second inverter is connected to a gate of the thirteenth transistor; the drain of the thirteenth transistor is connected to the second input terminal, and the source of the thirteenth transistor is connected to ground.
Optionally, the twelfth transistor and the thirteenth transistor are both NMOS transistors.
Optionally, the reference current branch and the memory cell current branch are designed in a mirror symmetry manner.
Optionally, the reference current branch comprises four transistors; a first electrode of the first transistor is connected with a first electrode of the second transistor, a second electrode of the first transistor, a second electrode of the second transistor and a second electrode of the third transistor are connected to a second output end, and a grid electrode of the first transistor is connected to an enable signal; the grid electrode of the second transistor and the grid electrode of the third transistor are connected to a first output end; the first electrode of the third transistor is connected with the second electrode of the fourth transistor; the gate of the fourth transistor is connected to the first input terminal.
Optionally, the memory cell current branch comprises four transistors; a first electrode of a fifth transistor is connected with a first electrode of a sixth transistor, a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of a seventh transistor are connected to a first output end, and a grid electrode of the fifth transistor is connected to an enable signal; the grid electrode of the sixth transistor and the grid electrode of the seventh transistor are connected to the second output end; a first electrode of the seventh transistor is connected with a second electrode of the eighth transistor; a gate of the eighth transistor is connected to the second input terminal, and a first electrode of the eighth transistor is connected to a first electrode of the fourth transistor.
Optionally, the first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the fifth transistor, and the first electrode of the sixth transistor are connected.
Optionally, the sense amplifier further includes a ninth transistor, a gate of the ninth transistor is connected to an enable signal, a first electrode of the ninth transistor is grounded, and a second electrode of the ninth transistor is connected to the first electrode of the fourth transistor and the first electrode of the eighth transistor.
Optionally, the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode.
Optionally, the operation timing sequence of the sense amplifier includes three stages:
a pre-charging stage: charging a first input end and a second input end of the sensitive amplifier;
the voltage difference is staged: forming a differential voltage difference between a first input terminal and a second input terminal of the sense amplifier;
the working stage is as follows: and the sensitive amplifier is started, and the output signal is amplified through the first feedback amplifying circuit or the second feedback amplifying circuit, so that the voltage difference between the two input ends is enhanced.
Optionally, in the precharge phase, the voltages of the first input terminal and the second input terminal are equal and maintained at a predetermined level.
Optionally, in the operating phase, the sense amplifier is turned on by using an enable signal.
Compared with the prior art, the sense amplifier provided by the invention has the advantages that the first feedback amplifying circuit is arranged between the first input end and the first output end, the second feedback amplifying circuit is arranged between the second input end and the second output end, the first feedback amplifying circuit is used for amplifying the output signal of the first output end, and the second feedback amplifying circuit is used for amplifying the output signal of the second output end; differential signals input at the first input end and the second input end generate output signals through the sensitive amplifier, the output signals pass through the first feedback amplifying circuit or the second feedback amplifying circuit, and the voltage signal of one input end of the first input end and the second input end is pulled down, so that the differential voltage of the two input ends is increased, the anti-interference capacity of the sensitive amplifier is improved, the speed performance of the sensitive amplifier is improved, and the design of the high-sensitivity amplifier is realized.
Drawings
FIG. 1 is a schematic diagram of a sense amplifier.
Fig. 2 is a schematic diagram of a sense amplifier according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a preferred circuit of a sense amplifier according to an embodiment of the invention.
Fig. 4 and 5 are simulated waveforms of a sense amplifier according to an embodiment of the invention.
Detailed Description
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
FIG. 1 is a schematic diagram of a sense amplifier, as shown in FIG. 1, including a reference current branch and a memory cell current branch, which output a "0" or "1" signal by comparing the reference current branch with the memory cell current branch.
In fig. 1, the reference current branch includes four transistors M1, M2, M3 and M4, the memory cell current branch includes four transistors M5, M6, M7 and M8, IO-TOP and IO-BOT are two input terminals, Dob and Do are two output terminals, VSS is a ground terminal, and the inverted signal SAENb of the enable signal outputs the enable signal SEN through the inverter C to be provided to different transistors. In addition, the inverter further comprises a transistor M9 which is connected with the output end of the inverter C and the transistors M4 and M8. Differential signals are output at two input ends IO-TOP and IO-BOT, and signals of '0' or '1' are output by comparing a reference current branch and a memory cell current branch.
However, with the development of advanced technology, the power supply voltage is further reduced, and the anti-interference capability of the sense amplifier to noise is required to be further improved, and especially when a high-speed reading circuit is designed, how to increase the differential input voltage of the sense amplifier is beneficial to anti-interference and speed performance improvement.
The inventor provides a sense amplifier through further research, wherein a first feedback amplifying circuit is arranged between a first input end and a first output end, and a second feedback amplifying circuit is arranged between a second input end and a second output end, the first feedback amplifying circuit is used for amplifying an output signal of the first output end, and the second feedback amplifying circuit is used for amplifying an output signal of the second output end; differential signals input at the first input end and the second input end generate output signals through the sensitive amplifier, the output signals pass through the first feedback amplifying circuit or the second feedback amplifying circuit, and the voltage signal of one input end of the first input end and the second input end is pulled down, so that the differential voltage of the two input ends is increased, the anti-interference capacity of the sensitive amplifier is improved, the speed performance of the sensitive amplifier is improved, and the design of the high-sensitivity amplifier is realized.
Please refer to fig. 2, which is a diagram illustrating a sense amplifier according to an embodiment of the present invention. As shown in fig. 2, the sense amplifier includes a reference current branch 10 and a memory cell current branch 20 connected to each other, the reference current branch 10 has a first input IO-TOP and a first output DOb, the memory cell current branch 20 has a second input IO-BOT and a second output DO, the first input IO-TOP is directly connected to the first output DOb through a first feedback amplifier circuit 11, the second input IO-BOT is directly connected to the second output DO through a second feedback amplifier circuit 21, the first feedback amplifier circuit 11 is configured to amplify the output signal of the first output DOb, and the second feedback amplifier circuit 21 is configured to amplify the output signal of the second output DO.
The reference current branch 10 and the memory cell current branch 20 are designed in a mirror symmetry. The reference current branch comprises four transistors; a first electrode of the first transistor T1 is connected to a first electrode of the second transistor T2, a second electrode of the first transistor T1, a second electrode of the second transistor T2 and a second electrode of the third transistor T3 are connected to the second output terminal DO, and a gate of the first transistor T1 is connected to the enable signal SEN; the gates of the second transistor T2 and the third transistor T3 are connected to the first output terminal DOb; a first electrode of the third transistor T3 is connected to a second electrode of the fourth transistor T4; the gate of the fourth transistor T4 is connected to the first input IO-TOP.
The memory cell current branch 20 comprises four transistors; a first electrode of the fifth transistor T5 is connected to a first electrode of the sixth transistor T6, a second electrode of the fifth transistor T5, a second electrode of the sixth transistor T6 and a second electrode of the seventh transistor T7 are connected to the first output terminal DOb, and a gate of the fifth transistor T5 is connected to the enable signal SEN; the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are connected to the second output terminal DO; a first electrode of the seventh transistor T7 is connected to a second electrode of the eighth transistor T8; a gate of the eighth transistor T8 is connected to the second input IO-BOT, and a first electrode of the eighth transistor T8 is connected to a first electrode of the fourth transistor T4.
A first electrode of the first transistor T1, a first electrode of the second transistor T2, a first electrode of the fifth transistor T5, and a first electrode of the sixth transistor T6 are connected.
The sense amplifier further includes a ninth transistor T9, a gate of the ninth transistor T9 is connected to the enable signal SEN, a first electrode of the ninth transistor T9 is grounded, and a second electrode of the ninth transistor T9 is connected to the first electrode of the fourth transistor T4 and the first electrode of the eighth transistor T8. Wherein the first electrode is one of a source or a drain, and the second electrode is the other of the source or the drain, for example, if the first electrode is the source, the second electrode is the drain; and if the first electrode is a drain electrode, the second electrode is a source electrode.
In the sense amplifier provided by the invention, the first feedback amplifying circuit 11 is arranged between the first input end IO-TOP and the first output end DOb, the second feedback amplifying circuit 21 is arranged between the second input end IO-BOT and the second output end DO, a differential signal between the first input end IO-TOP and the second input end IO-BOT passes through the sense amplifier to generate a small-signal output signal, the output signal passes through the first feedback amplifying circuit 11 or the second feedback amplifying circuit 21, and a voltage signal of one input end of the first input end IO-TOP and the second input end IO-BOT is pulled down, so that the differential voltage of the two input ends is increased, the anti-interference is facilitated, the speed performance of the sense amplifier is improved, and the design of the high-sensitivity amplifier is realized.
The first feedback amplifying circuit 11 and the second feedback amplifying circuit 21 are used for amplifying an output signal and pulling down a voltage signal of one of the two input ends, so that a differential signal of the two input ends is increased, and the anti-interference performance and the speed performance of the sense amplifier are improved. The actual circuit of the first feedback amplifier circuit 11 or the second feedback amplifier circuit 21 is not particularly limited in the present invention, so as to achieve the above object. The present invention provides a preferred specific circuit of the first feedback amplifying circuit and the second feedback amplifying circuit, and the following description is made by a specific embodiment.
Please refer to fig. 3, which is a preferred circuit diagram of a sense amplifier according to an embodiment of the present invention. As shown in fig. 3, the sense amplifier includes a reference current branch 100 and a memory cell current branch 200 connected to each other, the reference current branch 100 has a first input IO-TOP and a first output DOb, the memory cell current branch 200 has a second input IO-BOT and a second output DO, the first input IO-TOP is directly connected to the first output DOb through a first feedback amplifier circuit 110, the second input IO-BOT is directly connected to the second output DO through a second feedback amplifier circuit 210, the first feedback amplifier circuit 110 is configured to amplify the output signal of the first output DOb, and the second feedback amplifier circuit 210 is configured to amplify the output signal of the second output DO.
The first feedback amplifying circuit 110 or the second feedback amplifying circuit 210 includes an inverter and a transistor, the first feedback amplifying circuit 110 includes a first inverter C1 and a twelfth transistor P1, and the second feedback amplifying circuit 21 includes a second inverter C2 and a thirteenth transistor P2. An input terminal of the first inverter C1 is connected to the first output terminal DOb, an output terminal of the first inverter C1 is connected to a gate of the twelfth transistor P1, a drain of the twelfth transistor P1 is connected to the first input terminal IO-TOP, and a source of the twelfth transistor P1 is connected to a ground terminal VSS. An input terminal of the second inverter C2 is connected to the second output terminal DO, an output terminal of the second inverter C2 is connected to a gate of the thirteenth transistor P2, a drain of the thirteenth transistor P2 is connected to the second input terminal IO-BOT, and a source of the thirteenth transistor P2 is connected to a ground terminal VSS. Preferably, the twelfth transistor P1 and the thirteenth transistor P2 are both NMOS transistors.
The reference current branch 100 and the memory cell current branch 200 are designed in a mirror symmetry. The reference current branch 100 includes five transistors; a first electrode of the first transistor T1 is connected to a first electrode of the second transistor T2, a second electrode of the first transistor T1, a second electrode of the second transistor T2 and a second electrode of the third transistor T3 are connected to the second output terminal DO, and a gate of the first transistor T1 and a gate of the fifth transistor T5 are connected to the enable signal SEN; the gates of the second transistor T2 and the third transistor T3 are connected to the first output terminal DOb; a first electrode of the third transistor T3, a second electrode of the fourth transistor T4, and a second electrode of the fifth transistor T5 are connected; the gate of the fourth transistor T4 is connected to the first input IO-TOP; a first electrode of the fifth transistor T5 is connected to a power supply voltage VDD.
The memory cell current branch 200 includes five transistors; a first electrode of the sixth transistor T6 is connected to a first electrode of the seventh transistor T7, a second electrode of the sixth transistor T6, a second electrode of the seventh transistor T7, and a second electrode of the eighth transistor T8 are connected to the first output terminal DOb, and a gate of the sixth transistor T6 and a gate of the tenth transistor T10 are connected to the enable signal SEN; the gate of the seventh transistor T7 and the gate of the eighth transistor T8 are connected to the second output terminal DO; a first electrode of the eighth transistor T8 and a second electrode of the ninth transistor T9 are connected to the second electrode of the tenth transistor T10; a gate of the ninth transistor T9 is connected to the second input IO-BOT, and a first electrode of the ninth transistor T9 is connected to a first electrode of the fourth transistor T4; a first electrode of the tenth transistor T10 is connected to the power supply voltage VDD.
The first electrode of the first transistor T1, the first electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the first electrode of the seventh transistor T7 are connected to a power source VDD.
The sense amplifier further includes an eleventh transistor T11, a gate of the eleventh transistor T11 is connected to the enable signal SEN, a first electrode of the eleventh transistor T11 is connected to a ground terminal VSS, and a second electrode of the eleventh transistor T11 is connected to a first electrode of the fourth transistor T4 and a first electrode of the ninth transistor T9. In addition, in this embodiment, the sense amplifier further includes a third inverter C3, an inverted signal SAENb of an enable signal is input to an input terminal of the third inverter C3, and an enable signal SEN is output to an output terminal of the third inverter C3, so that the enable signal SEN is provided to the gate of the first transistor T1, the gate of the fifth transistor T5, the gate of the sixth transistor T6, the gate of the tenth transistor T10, and the gate of the eleventh transistor T11. Wherein the first electrode is one of a source or a drain, and the second electrode is the other of the source or the drain, for example, if the first electrode is the source, the second electrode is the drain; and if the first electrode is a drain electrode, the second electrode is a source electrode.
The working sequence of the sensitive amplifier comprises three stages:
precharge phase D1: charging a first input end and a second input end of the sensitive amplifier;
voltage difference phasing D2: forming a differential voltage difference between a first input terminal and a second input terminal of the sense amplifier;
working phase D3: and the sensitive amplifier is started, and the output signal is amplified through the first feedback amplifying circuit or the second feedback amplifying circuit, so that the voltage difference between the two input ends is enhanced.
Specifically, in the precharge phase D1, for two input terminals of the sense amplifier: the first input terminal IO-TOP and the second input terminal IO-BOT are charged to make the voltages of the two input terminals equal and maintain a predetermined level, for example, the predetermined level is 0.8 times the voltage VDD.
When the voltage difference stage D2, the memory (BitCell) is turned on and the Reference Current (Reference Current) works normally, a differential voltage difference is gradually formed between the two input ends of the sense amplifier, and when the differential voltage reaches a pre-designed value after a certain time, the sense amplifier is turned on immediately. The pre-designed value is a differential voltage value for turning on the sense amplifier.
In the operation phase D3, the enable signal turns on the sense amplifier, and the sense amplifier starts to operate. The magnitude of the differential voltage (IO _ BOT-IO _ TOP) will determine the speed performance of the sense amplifier. Given the differential voltage, the interior of the sense amplifier is amplified, causing a change in the output signal (DO/Dob). And the change is amplified again (amplified to PD _ BOT/PD _ TOP) through the first feedback amplifying circuit or the second feedback amplifying circuit, and the voltage of one input end of the two input ends of the sensitive amplifier is pulled down, so that the voltage difference of the two input ends is amplified in an enhanced way, and the speed performance of the sensitive amplifier is further improved.
Fig. 4 and 5 are simulated waveforms of a sense amplifier according to an embodiment of the invention. As shown in fig. 4, the memory (BitCell) has a large current, the IO _ BOT port of the second input terminal is a selected cell path, the net current is pulled down, and the IO _ TOP port of the first input terminal is a reference voltage. The voltage of the IO _ BOT port of the second input end is pulled down to accelerate amplification, when the DO is amplified to a certain degree, the differential voltage of the IO _ BOT/the IO _ TOP port of the second input end/the first input end is amplified in an enhanced mode to form positive feedback, and the speed performance is improved.
As shown in fig. 5, the memory (BitCell) is a small current, the IO _ BOT port of the second input terminal is a selected cell path, and the net current is pulled up; the first input terminal IO _ TOP port is a reference voltage. The voltage of the first input end IO _ TOP port is pulled down to accelerate amplification, and when the output signal DOb is amplified to a certain degree, the differential voltage of the second input end IO _ BOT/the first input end IO _ TOP is amplified in an enhanced mode to form positive feedback, so that the speed performance is improved.
In summary, in the sense amplifier provided by the present invention, a first feedback amplifier circuit is disposed between a first input end and a first output end, and a second feedback amplifier circuit is disposed between a second input end and a second output end, where the first feedback amplifier circuit is configured to amplify an output signal of the first output end, and the second feedback amplifier circuit is configured to amplify an output signal of the second output end; differential signals input at the first input end and the second input end generate output signals through the sensitive amplifier, the output signals pass through the first feedback amplifying circuit or the second feedback amplifying circuit, and the voltage signal of one input end of the first input end and the second input end is pulled down, so that the differential voltage of the two input ends is increased, the anti-interference capacity of the sensitive amplifier is improved, the speed performance of the sensitive amplifier is improved, and the design of the high-sensitivity amplifier is realized.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (13)
1. A sense amplifier is characterized by comprising a reference current branch and a storage unit current branch which are connected with each other, wherein the reference current branch is provided with a first input end and a first output end, the storage unit current branch is provided with a second input end and a second output end, the first input end is directly connected with the first output end through a first feedback amplification circuit, the second input end is directly connected with the second output end through a second feedback amplification circuit, the first feedback amplification circuit is used for amplifying an output signal of the first output end, and the second feedback amplification circuit is used for amplifying an output signal of the second output end;
the output signal of the first output end or the output signal of the second output end passes through the first feedback amplifying circuit or the second feedback amplifying circuit, and the voltage signal of one input end of the first input end and the second input end is pulled down, so that the differential voltage of the two input ends is increased.
2. The sense amplifier of claim 1, wherein the first feedback amplification circuit comprises a first inverter and a twelfth transistor; the second feedback amplifying circuit comprises a second inverter and a thirteenth transistor.
3. The sense amplifier of claim 2, wherein an input of the first inverter is connected to the first output, and an output of the first inverter is connected to a gate of the twelfth transistor; the drain of the twelfth transistor is connected to the first input end, and the source of the twelfth transistor is connected to a ground terminal; an input end of the second inverter is connected to the second output end, and an output end of the second inverter is connected to a gate of the thirteenth transistor; the drain of the thirteenth transistor is connected to the second input terminal, and the source of the thirteenth transistor is connected to ground.
4. The sense amplifier of claim 3 wherein the twelfth transistor and the thirteenth transistor are both NMOS transistors.
5. The sense amplifier of claim 1 wherein the reference current branch is mirror symmetric in design with the memory cell current branch.
6. The sense amplifier of claim 5 wherein the reference current branch comprises four transistors; a first electrode of the first transistor is connected with a first electrode of the second transistor, a second electrode of the first transistor, a second electrode of the second transistor and a second electrode of the third transistor are connected to a second output end, and a grid electrode of the first transistor is connected to an enable signal; the grid electrode of the second transistor and the grid electrode of the third transistor are connected to a first output end; the first electrode of the third transistor is connected with the second electrode of the fourth transistor; the gate of the fourth transistor is connected to the first input terminal.
7. The sense amplifier of claim 6 wherein the memory cell current branch comprises four transistors; a first electrode of a fifth transistor is connected with a first electrode of a sixth transistor, a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of a seventh transistor are connected to a first output end, and a grid electrode of the fifth transistor is connected to an enable signal; the grid electrode of the sixth transistor and the grid electrode of the seventh transistor are connected to the second output end; a first electrode of the seventh transistor is connected with a second electrode of the eighth transistor; a gate of the eighth transistor is connected to the second input terminal, and a first electrode of the eighth transistor is connected to a first electrode of the fourth transistor.
8. The sense amplifier of claim 7 wherein the first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the fifth transistor, and the first electrode of the sixth transistor are coupled.
9. The sense amplifier of claim 8, further comprising a ninth transistor, a gate of the ninth transistor being connected to an enable signal, a first electrode of the ninth transistor being connected to ground, a second electrode of the ninth transistor being connected to a first electrode of the fourth transistor and a first electrode of the eighth transistor.
10. The sense amplifier of claim 9 wherein the first electrode is one of a source or a drain and the second electrode is the other of the source or the drain.
11. The sense amplifier of any of claims 1-10, wherein the timing of the operation of the sense amplifier comprises three phases:
a pre-charging stage: charging a first input end and a second input end of the sensitive amplifier;
the voltage difference is staged: forming a differential voltage difference between a first input terminal and a second input terminal of the sense amplifier;
the working stage is as follows: and the sensitive amplifier is started, and the output signal is amplified through the first feedback amplifying circuit or the second feedback amplifying circuit, so that the voltage difference between the two input ends is enhanced.
12. The sense amplifier of claim 11 wherein the voltages at the first input terminal and the second input terminal are equal and maintained at a predetermined level during the precharge phase.
13. The sense amplifier of claim 11 wherein an enable signal is used to turn on the sense amplifier during the operational phase.
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| CN109559767B (en) * | 2018-11-28 | 2021-11-16 | 安徽大学 | Circuit structure for resisting bit line leakage current by adopting two sensitive amplifier technologies |
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| CN1505045A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���������Ƽ� | Semiconductor memory device and semiconductor integrated circuit |
| US7279939B2 (en) * | 2004-04-26 | 2007-10-09 | University Of Massachusetts | Circuit for differential current sensing with reduced static power |
| CN1971755A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Differential sense amplifier circuit and method triggered by a clock signal through a switch circuit |
| CN102543146A (en) * | 2012-01-19 | 2012-07-04 | 北京大学 | Flash sense amplifier |
| CN103973273A (en) * | 2013-01-24 | 2014-08-06 | 西安电子科技大学 | High-speed high-precision low-detuning fully differential dynamic comparator |
| CN105322946A (en) * | 2014-07-28 | 2016-02-10 | 株式会社索思未来 | Receiving circuit |
| CN105719680A (en) * | 2016-01-11 | 2016-06-29 | 安徽大学 | Novel high-speed self-starting sense amplifier circuit |
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| CN108346442A (en) | 2018-07-31 |
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