TWI387974B - Bit line precharge circuit - Google Patents

Description

Bit line precharge circuit

This invention relates to a memory component, and more particularly to a bit line precharge circuit in a memory component.

Flash memory components are gradually moving toward miniaturization, and their feature sizes are currently sub-micron (0.25 μm, 0.18 μm, 0.13 μm). However, shrinking the feature size not only counters the need to reduce power supply and reduce power loss, it can even increase the clock frequency of the system. Since maintaining the high stability of the sense amplifier while maintaining high read speed and low current consumption and the sense amplifier is also very important, the sense amplifier becomes a very important memory component in non-volatile memory.

In today's sense amplifiers, a compromise must be made between current loss and access time. That is to say, when access is performed in a short time, high current loss is usually caused, and conversely, if current loss is reduced, access may not be possible in a short time. However, some applications often have to meet the requirements of low current consumption, so in order to achieve this, the read action is usually divided into two phases (precharge phase and induction phase).

In order to complete the read operation of the flash memory, a plurality of selected bit lines must be charged to the expected voltage level before sensing. Therefore, if the selected bit line can be quickly and accurately stabilized to the standard level, the sensing capability is improved.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional bit line precharge circuit 10. As shown in FIG. 1, the bit line precharge circuit 10 is composed of a plurality of precharge sub-circuits PC[1]~PC[n]. The precharge sub-circuit PC[i] includes a controllable current-to-voltage converter L[i], a sense amplifier Amp[i], a memory cell Cell[i], and a drain bias controller DBC[i], where i is 1 An integer to n. The coupling relationship of the controllable current-to-voltage converter L[i], the sense amplifier Amp[i], and the gate bias controller DBC[i] can be seen from FIG. 1 and will not be discussed here.

In the above, the drain bias controller DBC[i] is coupled to the memory cell Cell[i], wherein the memory cell Cell[i] has an effective effect on the N-type MOS transistor N3 and the bit line BL[i] Capacitor C _BL . The controllable current-to-voltage converter L[i] includes an N-type MOS transistor N1 and a P-type MOS transistor P1, P2, and an N-type MOS transistor N1 and a P-type MOS transistor P1. The coupling relationship of P2 can be seen from Figure 1, and will not be discussed here.

It is worth noting that the drain bias controller DBC[i] includes an inverter Inv and a clamped N-type MOS transistor N2, wherein the inverter Inv and the clamped N-type MOS transistor N2 are formed. A negative feedback loop controls the gate bias of the clamped N-type MOS transistor N2. With this negative feedback loop, the voltage level on the bit line BL[i] can be quickly precharged to the target standard level, and the voltage level of the bit line BL[i] does not change much. Stable.

The above conventional bit line precharge circuit uses a feedback loop formed by an inverter and a clamped N-type MOS transistor as a gate bias controller, and the bit line is enabled according to the concept of negative feedback. Precharge in a fast and stable situation. However, due to flash memory once A large number of bits are read, so the design of the conventional bit line pre-charging circuit wastes a large layout space and causes a large power loss. For example, when performing the paging mode read operation, since 128 bits must be read at the same time, the bit line precharge circuit needs 128 (n=128 in FIG. 1) precharger. The circuit is enabled.

Reference is made to the U.S. Patent No. 7,082,069 issued to Chou et al., which discloses a bit line pre-charging circuit that can be operated quickly without the use of a large number of gate bias controllers. However, this bit line precharge circuit requires an additional column memory cell as the dummy bit line and requires an additional level detector to detect in advance whether the selected bit line is precharged. However, in general, it is not easy to design a balanced load on the reference path or the path of the memory cell, and may even derive the layout principle of setting up additional dummy bit lines and their well-to-well (well-to-well). Layout rule) causes the layout space to expand.

In short, in the above conventional bit line precharge circuit, one of the designs will have a large layout space and will generate a large energy loss, and another design may require additional dummy bit lines to make it The layout space has expanded.

In view of this, the present invention provides a bit line precharge circuit for use in a memory device, such as a flash memory.

To specifically describe the content of the present invention, a bit line pre-preparation is proposed herein. A charging circuit includes a reference pre-charge sub-circuit and at least one pre-charge sub-circuit. The reference precharge subcircuit includes a first current mirror, a first drain bias controller, and a first current to voltage converter. The first current mirror receives the reference current and provides a first current to the first drain bias controller in accordance with the reference current. The first drain bias controller is coupled to the first current mirror. The first drain bias controller includes a first inverter and a first clamped N-type oxynitride. The source terminal of the first clamp N-type MOS transistor is coupled to the input end of the first inverter and configured to receive the first current. The output of the first inverter is coupled to the gate terminal of the first clamped N-type MOS transistor. The first current-to-voltage converter is coupled to the 汲 terminal of the first clamp N-type MOS transistor of the first 偏压-bias bias controller, and is pre-charged P-type MOS half grounded as a gate terminal according to the pre-charge signal Transistor or diode load. The pre-charge sub-circuit includes a second current-to-voltage converter, a second clamped N-type MOS transistor, an equalization switch, and a memory cell. The second current-to-voltage converter is also loaded with a pre-charged P-type MOS transistor or diode that is grounded as a gate terminal based on the pre-charge signal. The gate of the second clamp N-type MOS transistor is coupled to the output of the first inverter, and the drain thereof is coupled to the second current-voltage converter and the sense amplifier, and the source is coupled to the equalization switch One end. The other end of the equalization switch is coupled to the source terminal of the first clamped N-type MOS transistor, and the equalization switch is controlled by the pre-charge signal to equalize both ends thereof. The memory cell is controlled by the word line signal and has a bit line, wherein the bit line is coupled to the source terminal of the second clamp N-type MOS transistor.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 2. FIG. 2 is a circuit diagram of a bit line precharge circuit 20 according to an embodiment of the present invention. The bit line precharge circuit 20 includes a reference precharge sub circuit 22, a plurality of precharge sub-circuits 23[1] to 23[n], and a reference current generator 21. The reference current generator 21 is coupled to the reference pre-charge sub-circuit 22, and the reference pre-charge sub-circuit 22 is coupled to a plurality of pre-charge sub-circuits 23[1]~23[n], where n is a natural number.

The reference current generator 21 includes a drain bias controller DBC2, an N-type MOS transistor N1, and a current mirror CM2. The drain bias controller DBC2 is coupled to the current mirror CM2, and includes an inverter INV2 and a clamped N-type MOS transistor. Wherein, the source terminal of the clamp N-type MOS transistor CN3 is coupled to the input terminal of the inverter INV2 and the 汲 terminal of the N-type MOS transistor N1, and the output terminal of the inverter INV2 is coupled to the clamp N The gate terminal of the type of gold oxide semi-transistor CN3. The gate terminal of the N-type MOS transistor N1 is coupled to the reference word line signal RWL, and the source terminal of the N-type MOS transistor N1 is coupled to the ground GND. In the present embodiment, the N-type oxynitride semiconductor N1 is a flash memory cell as a reference memory cell, such as a flash N-type MOS transistor. The current mirror CM2 receives the current I2 flowing through the clamped N-type MOS transistor III, and outputs a reference current IREF according to the current I2.

The current mirror CM2 includes P-type MOS transistors P5 and P3, wherein the source terminal of the P-type MOS transistor P5 is coupled to the power supply voltage VDD, and the 汲 terminal of the P-type MOS transistor P5 is coupled to the gate terminal thereof. And clamping the 汲 terminal of the N-type MOS transistor to the current I2. The gate terminal of P-type MOS transistor P6 is coupled to the gate terminal of P-type MOS transistor 5, and its source is extremely coupled. The power supply voltage VDD is connected, and the 汲 terminal is coupled to the current mirror CM1 of the pre-charge sub-circuit 22 to output a reference current IREF.

In addition, the reference current generator 21 can be triggered by the trigger signal ATD (not shown in FIG. 2, please refer to FIG. 4) to provide the reference current IREF to the bit line precharge circuit 20 at the correct time. In addition, the flash N-type MOS transistor N1 has a high threshold voltage. However, in this embodiment, the implementations of the reference current generator 21, the current mirror CM2, and the N-type MOS transistor N1 described above are not intended to limit the present invention, and any one of ordinary skill in the art may use other Method to realize.

The reference precharge subcircuit 22 includes a current mirror CM1, a drain bias controller DBC1, and a current to voltage converter CVC1. The current mirror CM1 receives the reference current IREF and supplies the current I1 to the drain bias controller DBC1 in accordance with the reference current IREF. The current mirror CM1 includes N-type gold oxide semi-transistors N5, N6. The source terminal of the N-type MOS transistor N5 is coupled to the ground GND, and the 汲 terminal is coupled to its gate terminal to receive the reference current IREF. The gate terminal of the N-type MOS transistor N6 is coupled to the gate terminal of the N-type MOS transistor N5, and the source terminal is coupled to the ground GND, and the 汲 terminal is coupled to the clamp N-type MOS The source terminal of the crystal CN1 outputs a first current I1.

It should be noted that the implementation of the current mirror CM1 described above is not intended to limit the scope of the present invention, and those skilled in the art may also implement the current mirror CM1 by other implementations.

The drain bias controller DBC1 is coupled to the first current mirror CM1, wherein the drain bias controller DBC1 includes an inverter INV1 and a clamp N-type MOS transistor CN1. The source of the clamped N-type MOS transistor CN1 is coupled to the input of the inverter INV1 and is used to receive the current I1. In addition, anti The output end of the phase INV1 is coupled to the gate terminal of the clamped N-type MOS transistor.

The current-to-voltage converter CVC1 is coupled to the 汲 terminal of the clamp N-type MOS transistor CN1 of the 偏压-bias controller DBC1, and can be pre-charged P-type MOS half which is grounded as a gate terminal according to the pre-charge signal PRE The transistor (shown in Figure 3A) or as a diode load (shown in Figure 3B).

The current-to-voltage converter CVC1 includes an N-type MOS transistor N2, a P-type MOS transistor P1, and a P-type MOS transistor P2. The gate terminal of the N-type MOS transistor N2 is coupled to the pre-charge signal PRE, and its source terminal is coupled to the ground GND. The gate terminal of the P-type MOS transistor P1 is coupled to the pre-charge signal PRE, and the 汲 terminal is coupled to the 汲 terminal of the N-type MOS transistor N2, and the source terminal is coupled to the drain bias controller DBC1. Clamp the N-type MOS semi-transistor CN1's 汲 extreme. The gate terminal of the P-type MOS transistor P2 is coupled to the 汲 terminal of the N-type MOS transistor N2, and the source terminal is coupled to the power supply voltage VDD, and the 汲 terminal is coupled to the P-type MOS transistor P1. The source is extreme.

Based on the above structure and configuration relationship, the current-to-voltage converter CVC1 can be used as a pre-charged P-type MOS transistor (shown in FIG. 3A) or as a diode load (grounded as a gate terminal) according to the pre-charge signal PRE. Figure 3B). It should be noted that the implementation of the above-mentioned current-to-voltage converter CVC1 is not intended to limit the present invention. Those skilled in the art may also modify the structure of the current-to-voltage converter CVC1 or implement current and voltage by other implementations. The converter CVC1 is made to achieve the same function as described above.

The precharge sub-circuit 23[i] (i is, for example, an integer from 1 to n) includes electricity The current-to-voltage converter CVC2, the clamp N-type MOS transistor CN2, the equalization switch ES, the sense amplifier SA, and the memory cell MCELL, wherein the current-voltage converter CVC2 can be pre-charged as a gate terminal ground according to the pre-charge signal PRE P-type oxy-halide transistors (shown in Figure 3A) or as diode loads (shown in Figure 3B).

The current-to-voltage converter CVC2 includes an N-type MOS transistor N3 and P-type MOS transistors P3 and P4. The gate terminal of the N-type MOS transistor N3 is coupled to the precharge signal PRE, and the source terminal thereof is coupled to the ground GND. The gate terminal of the P-type MOS transistor P3 is coupled to the pre-charge signal PRE, and the 汲 terminal is coupled to the 汲 terminal of the N-type MOS transistor N3, and the source terminal is coupled to the clamp N-type MOS The 汲 extreme of the crystal CN2. The gate terminal of the P-type MOS transistor P4 is coupled to the 汲 terminal of the N-type MOS transistor N3, the source terminal is coupled to the power supply voltage VDD, and the 汲 terminal is coupled to the source of the P-type MOS transistor P3. extreme.

Based on the above structure and configuration relationship, the current-to-voltage converter CVC2 can be used as a pre-charged P-type MOS transistor (shown in FIG. 3A) or as a diode load (grounded as a gate terminal) according to the pre-charge signal PRE. Figure 3B). It should be noted that the above manner of implementing the current-to-voltage converter CVC2 is not intended to limit the present invention. Those skilled in the art may also modify the structure of the current-to-voltage converter CVC2 or implement current-to-voltage conversion using other implementations. CVC2 is made to achieve the same function as described above.

The gate terminal of the clamp N-type MOS transistor CN2 is coupled to the output terminal of the inverter INV1, and the 汲 terminal is coupled to the current-voltage converter CVC2 and the sense amplifier SA, and the source terminal thereof is coupled to the equalization switch ES. One end. The other end of the equalization switch ES is coupled to the source terminal of the clamped N-type MOS transistor, and the equalization switch ES is controlled by the pre-charge signal PRE to equalize the voltage levels of the two terminals thereof (shown Figure 3A).

In the present embodiment, the equalization switch ES can be realized by the N-type MOS transistor N4. Wherein, the gate terminal of the N-type MOS transistor N4 is coupled to the pre-charge signal PRE, and the 汲 terminal is coupled to the source terminal of the clamp N-type MOS transistor CN2, and the source terminal is coupled to the clamp N-type The source terminal of the gold-oxide semi-transistor CN1. It should be noted that the implementation of the above-described equalization switch ES is not intended to limit the present invention, and any one of ordinary skill in the art may use other implementations to implement the equalization switch ES.

In this embodiment, the sense amplifier SA is a differential amplifier having a negative input coupled to the reference voltage VREF and a positive input coupled to the clamp terminal of the clamped N-type MOS transistor CN2. It is worth mentioning that the sense amplifier SA can have an output latch. When the latch signal LAT (not shown in FIG. 2, please refer to FIG. 4) triggers the output latch, the sense amplifier SA is triggered to output the amplified sensing value OUT[i].

The memory cell MCELL is controlled by the word line signal WL and has a bit line BL[i], wherein the bit line BL[i] is coupled to the source terminal of the clamped N-type MOS transistor. The memory cell MCELL includes a flash N-type gold oxide semi-transistor N7. The gate terminal of the flash N-type MOS transistor N7 is coupled to the word line signal WL, and the source terminal is coupled to the ground GND, and the 汲 terminal is coupled to the bit line BL[i]. It should be noted that the memory cell MCELL has a payload capacitance C _BL coupled between the bit line BL[i] and the ground GND. Further, the N-type MOS transistor N7 has a high threshold voltage.

As can be seen from the above, in the bit line precharge circuit 20 provided in this embodiment, the precharge sub-circuits 23[1] to 23[n] included therein share a drain bias controller DBC2. Next, the operation method of the bit line precharge circuit 20 will be explained in detail.

Please refer to FIG. 3A , FIG. 3B and FIG. 4 , wherein FIG. 3A is an equivalent circuit diagram of the bit line pre-charging circuit 20 during operation during pre-charging according to an embodiment of the present invention, and FIG. 3B is an The equivalent circuit diagram of the bit line precharge circuit 20 provided in the embodiment during operation is performed, and FIG. 4 is a waveform diagram when the bit line precharge circuit 20 performs reading.

As shown in FIG. 4, the reading action can be divided into two stages of a pre-charging period and an inductive period. During pre-charging, the pre-charge signal PRE is at a high level. The trigger signal ATD changes from the low level to the high level and starts to trigger the reference current generator 21. The reference word line signal RWL is changed from a low level to a high level to turn on the N-type MOS transistor N1 and generate a current I2. Further, the drain bias generator DBC2 forms a negative feedback loop, and thus, the current I2 is a steady current. That is to say, by using the negative feedback principle, the gate voltage of the clamped N-type MOS transistor can be quickly reached to a specified voltage value to generate a stable current I2. The current mirror CM2 outputs a reference current IREF to the current mirror CM1. Therefore, the reference current IREF can be generated.

Next, the word line signal WL changes from a low level to a high level, and the trigger signal ATD is at a low level. The voltage of the bit line BL[i] is precharged. During pre-charging, N-type MOS transistors N2 and N3 will be turned on, P-type MOS transistors P2 and P4 will be turned on, and P-type MOS will be turned on. The crystals P1, P3 will be turned off. Therefore, the current-to-voltage converters CVC2 and CVC1 are precharged P-type MOS transistors (shown in FIG. 3A) that are grounded as gate terminals. In addition, each equalization switch ES will equalize the voltage level of its two ends (shown in Figure 3A), so that all bit lines BL[1]~BL[i] will be precharged to the same Voltage level. That is, the equalization voltage DFLB is input to the input terminal of the drain bias controller DBC1, and the negative feedback loop adjusts the output voltage of the inverter INV1 so that the bit lines BL[1]~BL[i] can be It is quickly pre-charged.

During sensing, the precharge signal PRE is at a low level. The P-type MOS transistors P1 to P4 are turned on, and the N-type MOS transistors N1 and N3 are turned off. Therefore, the current-to-voltage converters CVC1 and CVC2 act as a diode load (shown in FIG. 3B). Both ends of the equalization switch ES are open and separated during sensing (shown in Figure 3B). Then, the latch signal LAT changes from the low level to the high level to trigger the output latch of the sense amplifier SA, and then the sense amplifier SA outputs the amplified sense value OUT[i].

In summary, the bit line precharge circuit provided in this embodiment includes a plurality of precharge sub-circuits sharing a gate bias controller. The buckling bias controller has an inverter and an N-type gold-oxygen half-clamp N-type MOS transistor to form a negative feedback loop and thereby speed up the precharge word line. When the bit line precharge circuit operates in the read mode, the bit line precharge circuit only needs to use a gate bias controller. As such, the bit line pre-charging circuit provided by the embodiments of the present invention can greatly save layout space and power consumption during operation without relying on additional dummy bit lines or expanding the layout.

Although the present invention has been disclosed above by way of example, it is not intended to be limiting. The invention may be modified and modified by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. Prevail.

10, 20‧‧‧ bit line precharge circuit

21‧‧‧Reference current generator

22‧‧‧Reference precharge subcircuit

Amp[i], SA‧‧‧ sense amplifier

ATD‧‧‧ trigger signal

BL[i]‧‧‧ bit line

C _BL ‧‧‧ payload capacitance

Cell[i], MCELL‧‧‧ memory cells

CM1, CM2‧‧‧ current mirror

CN1, CN2, CN3‧‧‧Clamp N-type gold oxide semi-transistor

CVC1, CVC2‧‧‧ current and voltage converter

DBC[i], DBC1, DBC2‧‧‧汲polar bias controller

DFLB‧‧‧ equalization voltage

ES‧‧‧ Equalization switch

GND‧‧‧ ground terminal

I1, I2‧‧‧ current

Inv, INV1, INV2‧‧‧ inverter

IREF‧‧‧reference current

LAT‧‧‧Latch signal

L[i]‧‧‧Controllable current-to-voltage converter

N1~N7‧‧‧N type MOS semi-transistor

OUT[i]‧‧‧Amplified inductance

P1~P6‧‧‧P type MOS semi-transistor

PC[1]~PC[n], 23[1]~23[n]‧‧‧ Precharge subcircuit

PRE‧‧‧Precharge signal

RWL‧‧‧ reference word line signal

VDD‧‧‧Power supply voltage

VREF‧‧‧reference voltage

WL‧‧‧ character line signal

FIG. 1 is a circuit diagram of a conventional bit line precharge circuit 10.

2 is a circuit diagram of a bit line precharge circuit according to an embodiment of the present invention.

FIG. 3A is an equivalent circuit diagram of the bit line precharge circuit 20 provided during the precharge period according to an embodiment of the present invention.

FIG. 3B is an equivalent circuit diagram of the bit line precharge circuit 20 provided during operation during sensing in accordance with an embodiment of the present invention.

FIG. 4 is a waveform diagram when the bit line precharge circuit 20 performs reading.

20‧‧‧ bit line precharge circuit

21‧‧‧Reference current generator

22‧‧‧Reference precharge subcircuit

SA‧‧‧Sense Amplifier

BL[i]‧‧‧ bit line

C _BL ‧‧‧ payload capacitance

MCELL‧‧‧ memory cell

CM1, CM2‧‧‧ current mirror

CN1, CN2, CN3‧‧‧Clamp N-type gold oxide semi-transistor

CVC1, CVC2‧‧‧ current and voltage converter

DBC1, DBC2‧‧‧汲polar bias controller

DFLB‧‧‧ equalization voltage

ES‧‧‧ Equalization switch

GND‧‧‧ ground terminal

I1, I2‧‧‧ current

INV1, INV2‧‧‧ inverter

IREF‧‧‧reference current

N1~N7‧‧‧N type MOS semi-transistor

OUT[i]‧‧‧Amplified inductance

P1~P6‧‧‧P type MOS semi-transistor

23[1]~23[n]‧‧‧Precharge subcircuit

PRE‧‧‧Precharge signal

RWL‧‧‧ reference word line signal

VDD‧‧‧Power supply voltage

VREF‧‧‧reference voltage

WL‧‧‧ character line signal

Claims (12)

A bit line precharge circuit includes: a reference precharge sub-circuit, comprising: a first current mirror, receiving a reference current and providing a first current to a first drain bias controller according to the reference current; The first drain bias controller is coupled to the first current mirror, the first drain bias controller includes a first inverter and a first clamp N-type MOS transistor, wherein the first A source terminal of the first clamp N-type MOS transistor is coupled to an input end of the first inverter and configured to receive the first current, and an output end of the first inverter is coupled to the first a gate terminal of a clamped N-type MOS transistor; and a first current-to-voltage converter coupled to the first clamp N-type MOS transistor汲 extreme, and the first current-to-voltage converter is a pre-charged P-type MOS transistor or a diode load that is grounded as a gate terminal according to a pre-charge signal; and at least one pre-charge sub-circuit, including: a second a current-to-voltage converter, based on the pre-charge signal as a pre-charge of the gate terminal ground a P-type MOS transistor or as a diode load; a second clamp N-type MOS transistor, the gate terminal of which is coupled to the output end of the first inverter, and the 汲 terminal is coupled to the first a current-to-voltage converter and a sense amplifier, wherein a source terminal is coupled to one end of the equalization switch; the other end of the switch is coupled to the source terminal of the first clamp N-type MOS transistor, And controlled by the precharge signal to equalize And a memory cell controlled by a word line signal having a bit line, wherein the bit line is coupled to the source terminal of the second clamp N-type MOS transistor. The bit line pre-charging circuit of claim 1, further comprising: a reference current generator, comprising: a second drain bias controller coupled to a second current mirror, the second The pole bias controller includes a second inverter and a third clamp N-type MOS transistor, wherein a source terminal of the third clamp N-type MOS transistor is coupled to the second inverter An input terminal of the first N-type MOS transistor and an output terminal of the second inverter are coupled to a gate terminal of the third clamp N-type MOS transistor The first N-type MOS transistor has a gate terminal coupled to a column of word line signals and a source terminal grounded thereto; and the second current mirror receives the third clamp N-type MOS half-electricity a second current of the crystal, and the reference current is output according to the second current. The bit line precharge circuit of claim 1, wherein the first current voltage converter comprises: a second N-type MOS transistor, the gate terminal of which is coupled to the precharge signal, and The source is extremely grounded; a first P-type MOS transistor, the gate terminal of which is coupled to the precharge signal, and the 汲 terminal is coupled to a terminal of the second N-type MOS transistor, and the source is extremely coupled Connecting the first clamp of the first drain bias controller The 汲 terminal of the N-type MOS transistor; and a second P-type MOS transistor having a gate terminal coupled to the 汲 terminal of the second N-type MOS transistor, the source terminal coupling a supply voltage, and the drain is coupled to the source terminal of the first P-type MOS transistor. The bit line pre-charging circuit of claim 1, wherein the pre-charging sub-circuit further comprises: the inductive amplifier, wherein the negative input end is coupled to a reference voltage, and the positive input end is coupled to the second The 汲 extreme of the clamped N-type MOS transistor. The bit line pre-charging circuit of claim 1, wherein the second current-voltage converter comprises: a third N-type MOS transistor, the gate terminal of which is coupled to the pre-charge signal, and The source is extremely grounded; a third P-type MOS transistor has a gate terminal coupled to the precharge signal, the 汲 terminal is coupled to a terminal of the third N-type MOS transistor, and the source is extremely coupled Connected to the 汲 terminal of the second clamp N-type MOS transistor; and a fourth P-type MOS transistor, the gate terminal of which is coupled to the 汲 terminal of the third N-type MOS transistor, The source terminal is coupled to a power supply voltage, and the drain terminal is coupled to the source terminal of the third P-type MOS transistor. The bit line pre-charging circuit according to claim 1, wherein the equalizing switch is a fourth N-type MOS transistor, the gate terminal is coupled to the pre-charging signal, and the 汲 terminal is coupled to the terminal. Second clamp type N The source terminal of the MOS transistor, and the source terminal thereof is coupled to the source terminal of the first clamp N-type MOS transistor. The bit line precharge circuit according to claim 1, wherein the first current mirror comprises: a fifth N-type MOS transistor, the source terminal is grounded, and the 汲 terminal is coupled to the gate terminal thereof. And receiving a reference current; and a sixth N-type MOS transistor, the gate terminal of which is coupled to the gate terminal of the fifth N-type MOS transistor, the source terminal is grounded, and the 汲 is extremely coupled The source terminal of the first clamped N-type MOS transistor outputs the first current. The bit line pre-charging circuit according to claim 2, wherein the second current mirror comprises: a fifth P-type MOS transistor, the source terminal is coupled to a power supply voltage, and the 汲 extreme coupling a gate terminal and a third terminal of the N-type MOS transistor to receive the second current; and a sixth P-type MOS transistor, the gate terminal of which is coupled to the fifth P-type The gate terminal of the MOS transistor has a source terminal coupled to the power supply voltage and a 汲 terminal coupled to the first current mirror to output the reference current. The bit line pre-charging circuit of claim 1, wherein the memory cell comprises: a seventh N-type MOS transistor, the gate terminal of which is coupled to the word line signal, and the source terminal is grounded. And the 汲 is extremely coupled to the bit line. The bit line precharge circuit of claim 2, wherein the first N-type MOS transistor is a flash N-type MOS transistor. The bit line precharge circuit according to claim 9, wherein the seventh N-type MOS transistor is a flash N-type MOS transistor. The bit line precharge circuit of claim 1, wherein the precharge signal is at a high level during a precharge period and the word line signal changes from a low level to a high level. The bit line is precharged to a standard level; and during a sensing period, the precharge signal is at a low level, and when a latch signal changes from a low level to a high level, the sense amplifier is Trigger and output an amplified sense value.