CN114826163A - Low-power-consumption high-performance trigger based on sensitive amplifier and working method thereof - Google Patents

Low-power-consumption high-performance trigger based on sensitive amplifier and working method thereof Download PDF

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CN114826163A
CN114826163A CN202210527991.3A CN202210527991A CN114826163A CN 114826163 A CN114826163 A CN 114826163A CN 202210527991 A CN202210527991 A CN 202210527991A CN 114826163 A CN114826163 A CN 114826163A
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tube
pmos
transistor
nmos transistor
nmos
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CN114826163B (en
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杜高明
王超
王�琦
贾忱皓
陈卓然
陶斯博
刘洋
周睿彬
杜嘉程
崔丰麒
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Hefei University of Technology
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Hefei University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45032—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are multiple paralleled transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled

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  • Logic Circuits (AREA)

Abstract

The invention discloses a low-power-consumption high-performance trigger based on a sensitive amplifier and a working method thereof, wherein the trigger comprises a trigger main stage and a trigger slave stage; wherein, the flip-flop primary includes: the device comprises a pre-charging part, an RAM-like structure, a data input part, a switch tube and a short-circuit tube; the flip-flop slave stage comprises two inverters inv3, inv4 and one C-cell. The invention can greatly reduce the possibility of generating burrs inside the trigger so as to reduce the power consumption; the dependence of Q and QB can be eliminated, so that the running speed is improved; meanwhile, the influence of an external load on the performance of the trigger can be greatly reduced.

Description

Low-power-consumption high-performance trigger based on sensitive amplifier and working method thereof
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a low-power-consumption high-performance trigger based on a sensitive amplifier and an implementation method thereof.
Background
In recent years, with the continuous development of semiconductor technology, the feature size of an integrated circuit is continuously reduced, the power consumption of a chip is increased, the power consumption of the chip becomes a main factor restricting the development of the integrated circuit, the power consumption is increased, the portable device is not favorable for use, and meanwhile, the problem of insufficient heat dissipation caused by the increased power consumption may cause the chip to be incapable of working normally, so that the reduction of the power consumption of the integrated circuit becomes important. The trigger is a basic composition unit of the digital circuit, the power consumption of the trigger accounts for about 30% -50% of the total power consumption of the digital circuit, the power consumption of the chip can be greatly increased due to frequent turnover of the trigger or internal burr generation of the trigger, and the chip function cannot be normally realized under severe conditions; meanwhile, the trigger is used as a basic component of a digital circuit, and the speed of the trigger greatly restricts the speed of the whole chip. Therefore, the invention of a flip-flop with low power consumption and high performance is a problem to be solved in the field of integrated circuits.
Disclosure of Invention
The invention aims to solve the defects of the prior art and provides a low-power-consumption high-performance trigger based on a sensitive amplifier and a working method thereof, so that the power consumption of the trigger and the possibility of generating burrs inside the trigger can be greatly reduced while the speed requirement of the trigger is ensured, and meanwhile, the dependence of Q and QB can be eliminated, and the running speed is improved; and the external capacitive load can be isolated from the interior of the trigger so as to improve the anti-interference capability of the trigger.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention relates to a trigger with low power consumption and high performance based on a sensitive amplifier, which is characterized by comprising the following components: a master flip-flop stage, a slave flip-flop stage;
the flip-flop primary includes: the device comprises a data input part, a pre-charging part, a RAM-like structure, a short-circuit tube and a switching tube;
the data input section includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;
the precharge section includes: a first PMOS transistor P1 and a second PMOS transistor P2;
the RAM-like structure is composed of two cross-coupled inverters and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fifth NMOS transistor N5; a first inverter inv1 is formed by the third PMOS transistor P3 and a third NMOS transistor N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and a fifth NMOS transistor N5;
the short-circuit tube is a sixth NMOS tube N6;
the switch tube is a first NMOS tube N1;
the flip-flop slave stage includes: a third inverter inv3 and a fourth inverter inv4 and 1C cell;
the third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;
the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;
the C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8;
when a clock signal CLK is equal to 0, a first PMOS tube P1 and a second PMOS tube P2 of the pre-charging part place full swing signals SB and RB output by the main stage of the trigger at a high level; meanwhile, the switch tube is turned off when the CLK is equal to 0, so that a pull-down path between the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 cannot be formed, or a pull-down path between the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the master stage of the flip-flop in a high level state;
the first PMOS tube P1 and the second PMOS tube P2 of the pre-charging part are turned off when a clock signal CLK is 1, so that full swing signals SB and RB output by the main stage of the trigger are in a non-setting state, and meanwhile, the switch tube is turned on when the clock signal CLK is 1, so that the second NMOS tube N2 and the fourth NMOS tube N4 can selectively form a pull-down path among the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 or a pull-down path composed among the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 according to the values of the differential input signals D and DB, thereby placing the level of the full swing signal SB or RB output by the main stage of the trigger at a low level;
the second NMOS transistor N2 and the fourth NMOS transistor N4 respectively read external differential input signals D and DB and serve as the input of the main stage of the trigger;
when the clock signal CLK is equal to 1, the first inverter inv1 and the second inverter inv2 selectively pull down the full-swing signal SB or RB output by the master of the flip-flop through the first inverter inv1 or the second inverter inv2, pull up the other full-swing signal RB or SB output by the master of the flip-flop through the second inverter inv2 or the first inverter inv1, and output the full-swing signals SB and RB to the slave of the flip-flop, according to the higher signal level in the differential input signals D and DB;
the short-circuit tube is always in a conducting state and discharges the error upset of full swing signal signals SB and RB output by the main stage of the trigger caused by the leakage of a third PMOS tube P3 or a fourth PMOS tube P4;
the third inverter inv3 inverts the full swing signal SB output by the main stage of the flip-flop and generates the input signal S of the C unit;
the C unit receives the input signal S and a full swing signal RB output by a trigger main stage and generates an output signal QB;
when the clock signal CLK is equal to 0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS tube P5 or the sixth PMOS tube P6 is conducted, and the output signal QB of the C unit keeps a high-impedance state;
when the clock signal CLK is 1, the C unit generates an output signal QB of the C unit according to the received output signals RB and S;
the fourth inverter inv4 inverts the output signal QB of the C-cell and generates the output signal Q of the flip-flop.
The low-power consumption high-performance trigger based on the sensitive amplifier is also characterized in that:
the first input end of the main stage of the trigger is the grid electrode of a second NMOS (N-channel metal oxide semiconductor) tube N2 and is connected with an external input signal D;
the second input end of the main stage of the trigger is the grid electrode of a fourth NMOS tube N4 and is connected to an external input signal DB;
the first output end of the main stage of the trigger is the drains of a first PMOS tube P1 and a third PMOS tube P3, and outputs a full swing signal SB;
the second output end of the main stage of the trigger is the drains of a second PMOS tube P2 and a fourth PMOS tube P4, and outputs a full swing signal RB;
the source electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a power supply VDD, the grid electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a clock signal CLK, the drain electrode of the first PMOS tube P1 generates a full swing signal SB output by the master stage of the trigger, and the drain electrode of the second PMOS tube P2 generates a full swing signal RB output by the master stage of the trigger;
a third PMOS tube P3 and a first PMOS tube P1 are connected in parallel, the source electrode of the third PMOS tube P3 is connected with the source electrode of the first PMOS tube P1, the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, and the grid electrode of the third PMOS tube P3 is connected with the drain electrode of the fourth PMOS tube P4; a fourth PMOS transistor P4 and a second PMOS transistor P2 are connected in parallel, the source electrode of the fourth PMOS transistor P4 is connected to the source electrode of the second PMOS transistor P2, the drain electrode of the fourth PMOS transistor P4 is connected to the drain electrode of the second PMOS transistor P2, and the gate electrode of the fourth PMOS transistor P4 is connected to the drain electrode of the third PMOS transistor P3;
the source electrode of the third NMOS transistor N3 is connected to the drain electrode of the second NMOS transistor N2, the drain electrode of the third NMOS transistor N3 is connected to the drain electrode of the third PMOS transistor P3, and the gate electrode of the third NMOS transistor N3 is connected to the gate electrode of the third PMOS transistor P3; the source electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth NMOS transistor N4, the drain electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth PMOS transistor P4, and the gate electrode of a fifth NMOS transistor N5 is connected to the gate electrode of a fourth PMOS transistor P4;
in the data input part, the source electrode of a second NMOS transistor N2 and the source electrode of a fourth NMOS transistor N4 are connected to the drain electrode of a first NMOS transistor N1 together, the drain electrode of the second NMOS transistor N2 is connected to the source electrode of a third NMOS transistor N3, the grid electrode of a second NMOS transistor N2 is used as a first output end of a main stage of the trigger and is connected with an external input signal D, the drain electrode of the fourth NMOS transistor N4 is connected to the source electrode of a fifth NMOS transistor N5, and the grid electrode of the fourth NMOS transistor N4 is used as a second output end of the main stage of the trigger and is connected with an external input signal DB;
the source or the drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3; the drain or source of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; the source electrode and the grid electrode of the fifth NMOS tube N5 are connected with a power supply VDD and are kept in an on state;
the source of the first NMOS transistor N1 is grounded GND, the drain is connected to the sources of the second NMOS transistor N2 and the fourth NMOS transistor N4, and the gate of the first NMOS transistor N1 is connected to the clock signal CLK.
The first input end of the slave stage of the trigger is the grids of an eighth NMOS transistor N8 and a fifth PMOS transistor P5, and is connected with a full swing signal RB output by the master stage of the trigger;
the second input end of the slave stage of the trigger is the grid of a ninth NMOS (N-channel metal oxide semiconductor) tube N9 and is connected to a full swing signal SB output by the master stage of the trigger;
the output end of the flip-flop slave stage is the drains of an eighth PMOS transistor P8 and a tenth NMOS transistor N10, and generates an output signal Q of the flip-flop slave stage;
in the third inverter inv3, a seventh PMOS transistor P7 and a ninth NMOS transistor N9 are connected in series, the gate of the seventh PMOS transistor P7 is connected to the drains of the first PMOS transistor P1 and the third PMOS transistor P3, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, the source of the ninth NMOS transistor N9 is connected to the GND, and after the drains of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are shorted, a signal S generated by the drain is connected to the gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7;
in the unit C, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8 are sequentially connected in series, the source of the fifth PMOS tube P5 is connected to a power supply VDD, the drain of the fifth PMOS tube P5 is connected with the source of the sixth PMOS tube P6, the drain of the sixth PMOS tube P6 is connected with the drain of the seventh NMOS tube N7, the source of the seventh NMOS tube N7 is connected with the drain of the eighth NMOS tube N8, the drain of the eighth NMOS tube N8 is connected to the ground GND, and the gate of the fifth PMOS tube P5 and the gate of the eighth NMOS tube N8 are connected to the drains of the second PMOS tube P2 and the fourth PMOS tube P4 after being short-circuited;
in the inverter inv4, an eighth PMOS transistor P8 and a tenth NMOS transistor N10 are connected in series, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the source of the tenth NMOS transistor N10 is connected to the ground GND; after the gates of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted, the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 are connected, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted.
The working method of the low-power-consumption high-performance trigger of the sense amplifier is characterized by being applied to a trigger consisting of a trigger main stage and a trigger slave stage; wherein the flip-flop primary comprises: the device comprises a data input part, a pre-charging part, a RAM-like structure, a short-circuit tube and a switching tube;
the data input section includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;
the precharge section includes: a first PMOS transistor P1 and a second PMOS transistor P2;
the RAM-like structure is composed of two cross-coupled inverters and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fifth NMOS transistor N5; a first inverter inv1 is formed by the third PMOS transistor P3 and a third NMOS transistor N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and a fifth NMOS transistor N5;
the short-circuit tube is a sixth NMOS tube N6;
the switch tube is a first NMOS tube N1;
the flip-flop slave stage includes: a third inverter inv3 and a fourth inverter inv4 and 1C cell;
the third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;
the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;
the C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8; the working method comprises the following steps:
step 1, when the flip-flop is in a precharge stage, a clock signal CLK is 0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the first NMOS transistor N1 is turned off, so that the full swing signals SB and RB output by the master stage of the flip-flop are both 1, the full swing signal SB output by the master stage of the flip-flop passes through the third inverter inv3 and then outputs a signal S of 0, meanwhile, the input signal RB of the C unit is 1, S is 0, so that the sixth PMOS transistor P6 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed, at this time, the C unit is in a high impedance state, the output signal QB of the C unit remains unchanged, and the output signal Q of the slave stage of the flip-flop remains unchanged;
step 2, when the flip-flop is in a data sampling stage, a clock signal CLK is 1, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor N1 is turned on, and after a precharge process, full swing signals SB and RB output by a master stage of the flip-flop are both at a high level, the third NMOS transistor N3 and the fifth NMOS transistor N5 are both in a conductive state, the second NMOS transistor N2 and the fourth NMOS transistor N4 sample input differential signals D and DB, and according to a higher level signal in the input differential signals D and DB, the second NMOS transistor N2 or the fourth NMOS transistor N4 is turned on to form a discharge path on one side, so that the full swing signal SB or RB output by the master stage of the flip-flop is pulled down, the fourth PMOS transistor P4 or the third PMOS transistor P3 is turned on, and the full swing signal RB or SB output by the master stage of the flip-flop is charged to a high level; one signal of full swing signals SB and RB output by the main stage of the trigger is high level, and the other signal is low level;
when SB is 0 and RB is 1, the input signal S of the unit C is 1, RB is 1, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, and the output signal QB of the unit C is 0 and generates the output signal Q of the slave stage of the flip-flop by the fourth inverter inv4, which is 1;
when SB is 1 and RB is 0, the input signal S of the C unit is 0, RB is 0, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, and the output signal QB of the C unit is 1, which is output signal Q of the slave stage of the flip-flop is 0 through the fourth inverter inv 4.
Compared with the prior art, the invention has the beneficial effects that:
1. in a traditional sense amplifier-based flip-flop Con SAFF in the prior art, a slave stage consists of cross-coupled inverters taking Q and QB as inputs and 2 inverters taking SB and RB as inputs, signals Q and QB are correlated, and the stabilizing time of Q and QB is different by the gate delay of a NAND gate, so that the rising delay and the falling delay of an output signal are unequal, and the operating speed of the flip-flop is influenced. The low-power-consumption high-performance trigger based on the sense amplifier isolates QB and Q through the phase inverter, the slave stage does not adopt a symmetrical structure to simultaneously generate Q and QB, and the rising delay and the falling delay are equal, so that the running speed of the trigger is improved.
2. The conventional sense amplifier based flip-flop Con SAFF of the prior art, which is composed of a cross-coupled inverter with Q and QB as input and 2 inverters with SB and RB as input, introduces a logic: the pull-up network and the pull-down network compete with each other, thereby affecting the stability of the flip-flop and possibly causing logic errors of the flip-flop. The low-power-consumption high-performance trigger based on the sensitive amplifier adopts the C unit at the slave stage, simultaneously ensures that the polarities of input signals S and RB of the C unit are the same, avoids the problem of logic competition, and improves the stability of the trigger.
3. In the Strollo SAFF in the prior art, the slave stage can effectively avoid the competition phenomenon by inserting a clock-controlled gate tube, and reduce the generation of glitches, but introduces an additional device and increases the power consumption. The low-power-consumption high-performance trigger based on the sense amplifier only needs 10 MOS tubes in the slave stage, and the number of the MOS tubes is less than 12 MOS tubes of Strollo SAFF, so that the power consumption is reduced.
Drawings
FIG. 1 is a schematic diagram of a main-stage structure of a low-power-consumption high-performance flip-flop based on a sense amplifier according to the present invention;
FIG. 2 is a waveform diagram illustrating the relationship between signals CLK, SB, RB, D, DB according to the present invention;
FIG. 3 is a diagram of a slave-stage structure of a low-power-consumption high-performance flip-flop based on a sense amplifier according to the present invention;
fig. 4 is a schematic diagram of the overall structure of the low-power-consumption high-performance flip-flop based on the sense amplifier of the present invention.
Detailed Description
In this embodiment, a low-power-consumption high-performance flip-flop based on a sense amplifier is mainly applied to a digital circuit which faces power consumption challenges with continuous progress of a process, and specifically includes: a flip-flop master stage, a flip-flop slave stage.
In this embodiment, as shown in fig. 1, the main stage of the flip-flop includes a data input portion, a precharge portion, a RAM-like structure, a short-circuit tube, and a switch tube. The pre-charging part is used for setting the output signals SB and RB of the main stage of the trigger to be 1 when the clock signal CLK is 0; the RAM-like structure is used for amplifying the difference value of differential inputs D and DB of the main stage of the trigger, so as to drive main stage output signals SB and RB to become full-swing signals; the data input part is used for reading the differential input signals D and DB of the trigger; the switching tube is used for cutting off a discharge path when the clock signal CLK is equal to 0, so that the main-stage output signals SB and RB are both 1 no matter what the values of the input signals D and DB are, and simultaneously, when the clock signal CLK is equal to 1, the values of the main-stage output signals SB and RB of the trigger are controlled according to the values of the input signals D and DB of the trigger; the short-circuit tube is used for communicating the internal nodes A and B, so that pull-down paths exist in the main-stage output signals SB and RB, the internal nodes A and B are prevented from floating at a low level, and the output signal Q of the trigger is prevented from being turned over by mistake;
specifically, the data input part comprises a second NMOS transistor N2 and a fourth NMOS transistor N4;
the switch tube is a first NMOS tube N1;
in this embodiment, as shown in fig. 2, when the clock signal CLK is equal to 0, the first PMOS transistor P1 and the second PMOS transistor P2 of the precharge portion place the full swing signals SB and RB output by the master stage of the flip-flop at a high level; meanwhile, the switch tube is turned off when the CLK is equal to 0, so that a pull-down path between the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 cannot be formed, or a pull-down path between the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the master stage of the flip-flop in a high level state;
the first PMOS tube P1 and the second PMOS tube P2 of the pre-charging part are turned off when a clock signal CLK is 1, so that full swing signals SB and RB output by the main stage of the trigger are in a non-setting state, and meanwhile, the switch tubes are turned on when CLK is 1, so that a pull-down path among a third NMOS tube N3, a second NMOS tube N2 and a first NMOS tube N1 or a pull-down path among a fifth NMOS tube N5, a fourth NMOS tube N4 and a first NMOS tube N1 is selectively formed according to the values of differential input signals D and DB, and the level of the output signal SB or RB of the main stage of the trigger is placed at a low level;
specifically, when CLK is at a high level, when the input D is 0 and DB is 1, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the first NMOS transistor N1 are turned on to form a discharge path, the RB node is connected to ground and becomes a low level, the signal RB passes through the first inverter inv1, and the SB node is charged to a high level; when the input D is 1 and DB is 0, the second NMOS transistor N2, the third NMOS transistor N3, and the first NMOS transistor N1 are turned on to form a discharge path, the SB node is connected to ground and pulled to a low level, the signal SB passes through the first inverter inv2, and the RB node is charged to a high level;
the RAM-like structure is composed of two cross-coupled inverters inv1 and inv2, and includes: a third PMOS tube P3, a fourth PMOS tube P4, a third NMOS tube N3 and a fifth NMOS tube N5, wherein a first phase inverter inv1 is formed by the third PMOS tube P3 and the third NMOS tube N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and the fifth NMOS transistor N5; in the present embodiment, as shown in table 1, when the clock signal CLK is 1, the output signal SB or RB of the master stage of the flip-flop is selectively pulled down according to the higher level signal of the differential input signals D and DB, and the output signal RB or SB of the other flip-flop is pulled up by inv2 or inv1 and output to the slave stage of the flip-flop;
table 1: inputting a clock input signal CLK, inputting D and DB and outputting truth tables of SB and RB by a RAM-like structure;
Figure BDA0003645114270000071
the short-circuit tube is a sixth NMOS tube N6 which is always conducted, and the wrong inversion of the main-stage output signals SB and RB of the trigger caused by the leakage of the third PMOS tube P3 or the fourth PMOS tube P4 is released;
the flip-flop slave stage includes a third inverter inv3 and a fourth inverter inv4 and 1C cell. inv3 is used for inverting the flip-flop main stage output signal SB to generate the C unit input signal S; the unit C is used for ensuring that when the clock signal CLK is equal to 0, the output signal Q of the trigger keeps unchanged, and when the clock signal CLK is equal to 1, the trigger works normally, and the output signal Q of the trigger changes according to the values of the signals S and RB; inv4 is used to invert the C cell output signal QB, generating the flip-flop output signal Q;
specifically, the inverter inv3 includes a seventh PMOS transistor P7 and a ninth NMOS transistor N9, and is configured to invert the full swing signal SB output by the main stage of the flip-flop and generate the input signal S of the C unit;
the inverter inv4 includes: an eighth PMOS transistor P8 and a tenth NMOS transistor N10 for inverting the output signal QB of the C-unit and generating the output signal Q of the flip-flop.
The unit C comprises a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8, and receives the input signal S and the full swing signal RB output by the flip-flop main stage, and generates an output signal QB. In this example, as shown in table 2:
table 2: c unit clock input signal CLK, input S, RB, output QB truth table;
Figure BDA0003645114270000081
when the clock signal CLK is equal to 0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS tube P5 or the sixth PMOS tube P6 is conducted, and the output signal QB of the C unit keeps a high-impedance state;
when the clock signal CLK is 1, the C unit generates an output signal QB of the C unit according to the received output signals RB and S;
specifically, when CLK is 0 and the two inputs S and RB of the C unit are not equal (S is 0, RB is 1 or S is 1, RB is 0), neither the pull-up nor the pull-down path of the C unit can conduct, the C unit is in a high impedance state, the output QB remains unchanged, and the C unit can effectively filter single node flips; when CLK is 1, and two inputs S and RB of the C unit are equal, and S is 0, the pull-up path (the fifth PMOS transistor P5 and the sixth PMOS transistor P6) is turned on, and QB is 1. When S equals RB equals 1, the pull-down path (the seventh NMOS transistor N7, the eighth NMOS transistor N8) is turned on, and QB equals 0.
The first input end of the main stage of the trigger is the grid electrode of a second NMOS tube N2 and is connected with an external input signal D;
the second input end of the main stage of the trigger is the grid of a fourth NMOS tube N4 and is connected to an external input signal DB;
the first output end of the main stage of the trigger is the drains of a first PMOS tube P1 and a third PMOS tube P3, and outputs a full swing signal SB;
the second output end of the main stage of the trigger is the drains of a second PMOS tube P2 and a fourth PMOS tube P4, and outputs a full swing signal RB;
the source electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a power supply VDD, the grid electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a clock signal CLK, the drain electrode of the first PMOS tube P1 generates a full swing signal SB output by the master stage of the trigger, and the drain electrode of the second PMOS tube P2 generates a full swing signal RB output by the master stage of the trigger;
a third PMOS tube P3 and a first PMOS tube P1 are connected in parallel, the source electrode of the third PMOS tube P3 is connected with the source electrode of the first PMOS tube P1, the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, and the grid electrode of the third PMOS tube P3 is connected with the drain electrode of the fourth PMOS tube P4; a fourth PMOS tube P4 and a second PMOS tube P2 are connected in parallel, the source electrode of the fourth PMOS tube P4 is connected to the source electrode of the second PMOS tube P2, the drain electrode of the fourth PMOS tube P4 is connected to the drain electrode of the second PMOS tube P2, and the gate electrode of the fourth PMOS tube P4 is connected to the drain electrode of the third PMOS tube P3;
the source electrode of the third NMOS transistor N3 is connected to the drain electrode of the second NMOS transistor N2, the drain electrode of the third NMOS transistor N3 is connected to the drain electrode of the third PMOS transistor P3, and the gate electrode of the third NMOS transistor N3 is connected to the gate electrode of the third PMOS transistor P3; the source electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth NMOS transistor N4, the drain electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth PMOS transistor P4, and the gate electrode of a fifth NMOS transistor N5 is connected to the gate electrode of a fourth PMOS transistor P4;
in the data input part, the source electrode of the second NMOS transistor N2 and the source electrode of the fourth NMOS transistor N4 are connected together to the drain electrode of the first NMOS transistor N1, the drain electrode of the second NMOS transistor N2 is connected to the source electrode of the third NMOS transistor N3, the grid electrode of the second NMOS transistor N2 is used as the first output end of the main stage of the trigger and is connected with an external input signal D, the drain electrode of the fourth NMOS transistor N4 is connected to the source electrode of the fifth NMOS transistor N5, and the grid electrode of the fourth NMOS transistor N4 is used as the second output end of the main stage of the trigger and is connected with an external input signal DB.
The source or the drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3; the drain or source of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; the source electrode and the grid electrode of the fifth NMOS tube N5 are connected with a power supply VDD and are kept in an on state;
the source of the first NMOS transistor N1 is grounded GND, the drain is connected to the sources of the second NMOS transistor N2 and the fourth NMOS transistor N4, and the gate of the first NMOS transistor N1 is connected to the clock signal CLK.
In this embodiment, as shown in fig. 3, the first input terminal of the slave stage of the flip-flop is the gates of an eighth NMOS transistor N8 and a fifth PMOS transistor P5, and is connected to the full swing signal RB output by the master stage of the flip-flop;
the second input end of the slave stage of the trigger is the grid of a ninth NMOS tube N9 and is connected to a full swing signal SB output by the master stage of the trigger;
the output end of the flip-flop slave stage is the drains of an eighth PMOS transistor P8 and a tenth NMOS transistor N10, and generates an output signal Q of the flip-flop slave stage;
in the third inverter inv3, a seventh PMOS transistor P7 and a ninth NMOS transistor N9 are connected in series, the gate of the seventh PMOS transistor P7 is connected to the drains of the first PMOS transistor P1 and the third PMOS transistor P3, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, the source of the ninth NMOS transistor N9 is connected to the GND, and after the drains of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are shorted, a signal S generated by the drain is connected to the gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7;
in the unit C, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8 are sequentially connected in series, the source of the fifth PMOS tube P5 is connected to a power supply VDD, the drain of the fifth PMOS tube P5 is connected with the source of the sixth PMOS tube P6, the drain of the sixth PMOS tube P6 is connected with the drain of the seventh NMOS tube N7, the source of the seventh NMOS tube N7 is connected with the drain of the eighth NMOS tube N8, the drain of the eighth NMOS tube N8 is connected to the ground GND, and the gate of the fifth PMOS tube P5 and the gate of the eighth NMOS tube N8 are connected to the drains of the second PMOS tube P2 and the fourth PMOS tube P4 after being short-circuited;
in the fourth inverter inv4, an eighth PMOS transistor P8 and a tenth NMOS transistor N10 are connected in series, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the source of the tenth NMOS transistor N10 is connected to the ground GND; after the gates of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted, the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 are connected, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted.
In this embodiment, as shown in fig. 4, a working method of a low-power-consumption high-performance flip-flop based on a sense amplifier is performed according to the following steps:
step 1, when the flip-flop is in a precharge stage, a clock signal CLK is 0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the first NMOS transistor N1 is turned off, so that the full swing signals SB and RB output by the master stage of the flip-flop are both 1, the full swing signal SB output by the master stage of the flip-flop passes through the third inverter inv3 and then outputs a signal S of 0, meanwhile, the input signal RB of the C unit is 1, S is 0, so that the sixth PMOS transistor P6 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed, at this time, the C unit is in a high impedance state, the output signal QB of the C unit remains unchanged, and the output signal Q of the slave stage of the flip-flop remains unchanged;
step 2, in this embodiment, as shown in table 3:
TABLE 3 trigger truth table
Figure BDA0003645114270000101
When the trigger is in a data sampling stage, a clock signal CLK is 1, a first PMOS tube P1 and a second PMOS tube P2 are turned off, a first NMOS tube N1 is turned on, full swing signals SB and RB output by a master stage of the trigger are both high level after a pre-charging process, a third NMOS tube N3 and a fifth NMOS tube N5 are both in a conducting state, a second NMOS tube N2 and a fourth NMOS tube N4 sample input differential signals D and DB, and according to higher level signals in the input differential signals D and DB, the second NMOS tube N2 or the fourth NMOS tube N4 are turned on to form a discharging path on one side, so that the full swing signal SB or RB output by the master stage of the trigger is pulled down, the fourth PMOS tube P4 or the third PMOS tube P3 is turned on, and the full swing signal RB or SB output by the master stage of the trigger is charged to high level; one signal of full swing signals SB and RB output by the main stage of the trigger is high level, and the other signal is low level;
when SB is 0 and RB is 1, the input signal S of the unit C is 1, RB is 1, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, and the output signal QB of the unit C is 0 and generates the output signal Q of the slave stage of the flip-flop by the fourth inverter inv4, which is 1;
when SB is 1 and RB is 0, the input signal S of the unit C is 0, RB is 0, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, and the output signal QB of the unit C is 1, which is passed through the fourth inverter inv4, to generate the output signal Q of the slave stage of the flip-flop, which is 0.

Claims (4)

1. A low-power consumption high-performance trigger based on a sensitive amplifier is characterized by comprising: a master flip-flop stage, a slave flip-flop stage;
the flip-flop primary includes: the device comprises a data input part, a pre-charging part, a RAM-like structure, a short-circuit tube and a switching tube;
the data input section includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;
the precharge section includes: a first PMOS transistor P1 and a second PMOS transistor P2;
the RAM-like structure is composed of two cross-coupled inverters and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fifth NMOS transistor N5; a first inverter inv1 is formed by the third PMOS transistor P3 and a third NMOS transistor N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and a fifth NMOS transistor N5;
the short-circuit tube is a sixth NMOS tube N6;
the switch tube is a first NMOS tube N1;
the flip-flop slave stage includes: a third inverter inv3 and a fourth inverter inv4 and 1C cell;
the third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;
the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;
the C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8;
when a clock signal CLK is equal to 0, a first PMOS tube P1 and a second PMOS tube P2 of the pre-charging part place full swing signals SB and RB output by the main stage of the trigger at a high level; meanwhile, the switch tube is turned off when the CLK is equal to 0, so that a pull-down path between the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 cannot be formed, or a pull-down path between the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the master stage of the flip-flop in a high level state;
the first PMOS tube P1 and the second PMOS tube P2 of the pre-charging part are turned off when a clock signal CLK is 1, so that full swing signals SB and RB output by the main stage of the trigger are in a non-setting state, and meanwhile, the switch tube is turned on when the clock signal CLK is 1, so that the second NMOS tube N2 and the fourth NMOS tube N4 can selectively form a pull-down path among the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 or a pull-down path composed among the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 according to the values of the differential input signals D and DB, thereby placing the level of the full swing signal SB or RB output by the main stage of the trigger at a low level;
the second NMOS transistor N2 and the fourth NMOS transistor N4 respectively read external differential input signals D and DB and serve as the input of the main stage of the trigger;
when the clock signal CLK is equal to 1, the first inverter inv1 and the second inverter inv2 selectively pull down the full-swing signal SB or RB output by the master of the flip-flop through the first inverter inv1 or the second inverter inv2, pull up the other full-swing signal RB or SB output by the master of the flip-flop through the second inverter inv2 or the first inverter inv1, and output the full-swing signals SB and RB to the slave of the flip-flop, according to the higher signal level in the differential input signals D and DB;
the short-circuit tube is always in a conducting state and discharges the false overturning of full swing signal signals SB and RB output by the main stage of the trigger caused by the leakage of a third PMOS tube P3 or a fourth PMOS tube P4;
the third inverter inv3 inverts the full swing signal SB output by the main stage of the flip-flop and generates the input signal S of the C unit;
the C unit receives the input signal S and a full swing signal RB output by a trigger main stage and generates an output signal QB;
when the clock signal CLK is equal to 0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS tube P5 or the sixth PMOS tube P6 is conducted, and the output signal QB of the C unit keeps a high-impedance state;
when the clock signal CLK is 1, the C unit generates an output signal QB of the C unit according to the received output signals RB and S;
the fourth inverter inv4 inverts the output signal QB of the C-cell and generates the output signal Q of the flip-flop.
2. The sense amplifier based low power consumption high performance flip-flop of claim 1, wherein:
the first input end of the main stage of the trigger is the grid electrode of a second NMOS tube N2 and is connected with an external input signal D;
the second input end of the main stage of the trigger is the grid electrode of a fourth NMOS tube N4 and is connected to an external input signal DB;
the first output end of the main stage of the trigger is the drains of a first PMOS tube P1 and a third PMOS tube P3, and outputs a full swing signal SB;
the second output end of the main stage of the trigger is the drains of a second PMOS tube P2 and a fourth PMOS tube P4, and outputs a full swing signal RB;
the source electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a power supply VDD, the grid electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a clock signal CLK, the drain electrode of the first PMOS tube P1 generates a full swing signal SB output by the master stage of the trigger, and the drain electrode of the second PMOS tube P2 generates a full swing signal RB output by the master stage of the trigger;
a third PMOS tube P3 and a first PMOS tube P1 are connected in parallel, the source electrode of the third PMOS tube P3 is connected with the source electrode of the first PMOS tube P1, the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, and the grid electrode of the third PMOS tube P3 is connected with the drain electrode of the fourth PMOS tube P4; a fourth PMOS transistor P4 and the second PMOS transistor P2 are connected in parallel, the source of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2, the drain of the fourth PMOS transistor P4 is connected to the drain of the second PMOS transistor P2, and the gate of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3;
the source electrode of the third NMOS transistor N3 is connected to the drain electrode of the second NMOS transistor N2, the drain electrode of the third NMOS transistor N3 is connected to the drain electrode of the third PMOS transistor P3, and the gate electrode of the third NMOS transistor N3 is connected to the gate electrode of the third PMOS transistor P3; the source electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth NMOS transistor N4, the drain electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth PMOS transistor P4, and the gate electrode of a fifth NMOS transistor N5 is connected to the gate electrode of a fourth PMOS transistor P4;
in the data input part, the source electrode of a second NMOS transistor N2 and the source electrode of a fourth NMOS transistor N4 are connected to the drain electrode of a first NMOS transistor N1 together, the drain electrode of the second NMOS transistor N2 is connected to the source electrode of a third NMOS transistor N3, the grid electrode of a second NMOS transistor N2 is used as a first output end of a main stage of the trigger and is connected with an external input signal D, the drain electrode of the fourth NMOS transistor N4 is connected to the source electrode of a fifth NMOS transistor N5, and the grid electrode of the fourth NMOS transistor N4 is used as a second output end of the main stage of the trigger and is connected with an external input signal DB;
the source or the drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3; the drain or source of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; the source electrode and the grid electrode of the fifth NMOS tube N5 are connected with a power supply VDD and are kept in an on state;
the source of the first NMOS transistor N1 is grounded GND, the drain is connected to the sources of the second NMOS transistor N2 and the fourth NMOS transistor N4, and the gate of the first NMOS transistor N1 is connected to the clock signal CLK.
3. The sense amplifier based low power consumption high performance flip-flop of claim 1, wherein:
the first input end of the slave stage of the trigger is the grids of an eighth NMOS transistor N8 and a fifth PMOS transistor P5, and is connected with a full swing signal RB output by the master stage of the trigger;
the second input end of the slave stage of the trigger is the grid of a ninth NMOS (N-channel metal oxide semiconductor) tube N9 and is connected to a full swing signal SB output by the master stage of the trigger;
the output end of the flip-flop slave stage is the drains of an eighth PMOS transistor P8 and a tenth NMOS transistor N10, and generates an output signal Q of the flip-flop slave stage;
in the third inverter inv3, a seventh PMOS transistor P7 and a ninth NMOS transistor N9 are connected in series, the gate of the seventh PMOS transistor P7 is connected to the drains of the first PMOS transistor P1 and the third PMOS transistor P3, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, the source of the ninth NMOS transistor N9 is connected to the GND, and after the drains of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are shorted, a signal S generated by the drain is connected to the gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7;
in the unit C, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8 are sequentially connected in series, the source of the fifth PMOS tube P5 is connected to a power supply VDD, the drain of the fifth PMOS tube P5 is connected with the source of the sixth PMOS tube P6, the drain of the sixth PMOS tube P6 is connected with the drain of the seventh NMOS tube N7, the source of the seventh NMOS tube N7 is connected with the drain of the eighth NMOS tube N8, the drain of the eighth NMOS tube N8 is connected to the ground GND, and the gate of the fifth PMOS tube P5 and the gate of the eighth NMOS tube N8 are connected to the drains of the second PMOS tube P2 and the fourth PMOS tube P4 after being short-circuited;
in the inverter inv4, an eighth PMOS transistor P8 and a tenth NMOS transistor N10 are connected in series, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the source of the tenth NMOS transistor N10 is connected to the ground GND; after the gates of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted, the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 are connected, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted.
4. A working method of a trigger with low power consumption and high performance of a sensitive amplifier is characterized in that the trigger is applied to a trigger consisting of a trigger main stage and a trigger slave stage; wherein the flip-flop primary comprises: the device comprises a data input part, a pre-charging part, a RAM-like structure, a short-circuit tube and a switching tube;
the data input section includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;
the precharge section includes: a first PMOS transistor P1 and a second PMOS transistor P2;
the RAM-like structure is composed of two cross-coupled inverters and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fifth NMOS transistor N5; a first inverter inv1 is formed by the third PMOS transistor P3 and a third NMOS transistor N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and a fifth NMOS transistor N5;
the short-circuit tube is a sixth NMOS tube N6;
the switch tube is a first NMOS tube N1;
the flip-flop slave stage includes: a third inverter inv3 and a fourth inverter inv4 and 1C cell;
the third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;
the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;
the C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8; the working method comprises the following steps:
step 1, when the flip-flop is in a precharge stage, a clock signal CLK is 0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the first NMOS transistor N1 is turned off, so that the full swing signals SB and RB output by the master stage of the flip-flop are both 1, the full swing signal SB output by the master stage of the flip-flop passes through the third inverter inv3 and then outputs a signal S of 0, meanwhile, the input signal RB of the C unit is 1, S is 0, so that the sixth PMOS transistor P6 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed, at this time, the C unit is in a high impedance state, the output signal QB of the C unit remains unchanged, and the output signal Q of the slave stage of the flip-flop remains unchanged;
step 2, when the flip-flop is in a data sampling stage, a clock signal CLK is 1, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor N1 is turned on, and after a precharge process, full swing signals SB and RB output by a master stage of the flip-flop are both at a high level, the third NMOS transistor N3 and the fifth NMOS transistor N5 are both in a conductive state, the second NMOS transistor N2 and the fourth NMOS transistor N4 sample input differential signals D and DB, and according to a higher level signal in the input differential signals D and DB, the second NMOS transistor N2 or the fourth NMOS transistor N4 is turned on to form a discharge path on one side, so that the full swing signal SB or RB output by the master stage of the flip-flop is pulled down, the fourth PMOS transistor P4 or the third PMOS transistor P3 is turned on, and the full swing signal RB or SB output by the master stage of the flip-flop is charged to a high level; one signal of full swing signals SB and RB output by the main stage of the trigger is high level, and the other signal is low level;
when SB is 0 and RB is 1, the input signal S of the unit C is 1, RB is 1, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, and the output signal QB of the unit C is 0 and generates the output signal Q of the slave stage of the flip-flop by the fourth inverter inv4, which is 1;
when SB is 1 and RB is 0, the input signal S of the unit C is 0, RB is 0, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, and the output signal QB of the unit C is 1, which is passed through the fourth inverter inv4, to generate the output signal Q of the slave stage of the flip-flop, which is 0.
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