CN117789779B - Self-control SRAM sensitive amplifier circuit and module based on latch cross coupling - Google Patents

Abstract

The invention relates to the technical field of sense amplifier design, in particular to a self-control SRAM sense amplifier circuit and a self-control SRAM sense amplifier module based on latch cross coupling. The invention comprises the following steps: an enable control section, a latch coupling section, a self-control input section, and a precharge circuit section. The self-control input part is adopted, the signal input of the target bit line and the signal turn-off of the non-target bit line are controlled in a self-adaptive mode according to the voltage change of Q, QB, the influence of the non-target bit line on the output node Q, QB is avoided, and therefore offset voltage and amplification delay are reduced. The invention adopts the latch coupling part to amplify the voltage signal, avoids the control mode of cascading the inverters, and thereby avoids the oscillation risk of the prior patent. The invention solves the problems of large offset voltage of the existing latch type sensitive amplifier and oscillation risk of the existing patent.

Description

Self-control SRAM sensitive amplifier circuit and module based on latch cross coupling

Technical Field

The invention relates to the technical field of sensitive amplifier design, in particular to a self-control SRAM sensitive amplifier circuit based on latch cross coupling and a sensitive amplifier module based on the circuit design.

Background

With the popularization of wearable devices and the continuous shrinking of critical dimensions of CMOS processes, the integration level of chips is continuously improved, and the demands of high-capacity and high-density memory chips are increasingly raised. But the large capacity high density memory array will mount more memory cells on one bit line, which increases the bit line capacitance continuously and greatly increases the delay of the bit line full swing discharge and its dynamic power consumption.

In order to avoid the problem of excessive delay in reading of stored information due to slow discharge of bit lines, in a Static Random Access Memory (SRAM), a sense amplifier is generally used to sense a voltage difference across the bit lines and perform fast amplification and reading operations of stored data. Meanwhile, the design mode of reading, writing and separating the independent read bit line is more common because the data overturning risk caused by the reading half-selection problem in the memory array can be avoided, so that the sense amplifier capable of identifying the voltage information change of the single-ended read bit line is more favored.

At present, the latch type sensitive amplifier is widely applied to an SRAM circuit by virtue of the advantages of simple structure and capability of rapidly amplifying bit line differential pressure information through cross coupling positive feedback. The latching sense amplifier is composed of a core structure of data amplification by two pairs of cross-coupled inverters: the input of bit line information is controlled by a pair of voltage-controlled transmission transistors, and an NMOS transistor is used as an enabling control end of the circuit and a power supply current source. However, since the latch-type sense amplifier has a differential structure, offset voltage is introduced, that is, when the differential voltage signal of the bit line is smaller than a certain voltage, the latch-type sense amplifier cannot recognize or recognize errors; and as the process size decreases, the offset voltage becomes larger, and the interference thereof becomes more serious.

In addition, the inventor searches the prior patent CN202310410709.8 to disclose an adaptive turn-off type SRAM sensitive amplifier circuit based on lower cross coupling, and the patent can reduce the offset voltage of the sensitive amplifier, but the offset voltage is in cascade coupling of control signals of an internal inverter and an external inverter, so that the risk of oscillation of the circuit exists under the condition that the voltage difference of a bit line is close.

Disclosure of Invention

Based on this, it is necessary to provide a self-controlled SRAM sense amplifier circuit and module based on latch cross coupling, aiming at the problems of large offset voltage of the existing latch-type sense amplifier and oscillation risk of the existing patent.

The invention is realized by adopting the following technical scheme:

In a first aspect, the present invention provides a self-controlled SRAM sense amplifier circuit based on latch cross-coupling, comprising: an enable control section, a latch coupling section, a self-control input section, and a precharge circuit section.

The enable control part is used for controlling whether the sense amplifier circuit works or not.

The latch coupling portion is used for rapidly amplifying the voltage difference of the output node Q, QB through positive feedback coupling according to the bit lines BL, BLB. The latch coupling part comprises 2 NMOS tubes and 2 PMOS tubes, which are marked as N4, N5, P7 and P8. The grid electrode of N4 is connected with QB, and the drain electrode of N4 is connected with Q; the grid electrode of N5 is connected with Q, the drain electrode of N5 is connected with QB, the source electrode of N5 is connected with the source electrode of N4, and is commonly connected to the enabling control part; the gate of P7 is connected to QB, the source of P7 is connected to BL, and the drain of P7 is connected to Q; the gate of P8 is connected to Q, the source of P8 is connected to BLB, and the drain of P8 is connected to QB.

The self-control input is used to adaptively cut off the effect of BLB or BL on the latch coupling according to the voltage change of Q, QB. The self-control input part comprises 6 PMOS transistors and 4 NMOS transistors, which are denoted as P1, P2, P3, P4, P5, P6, N2, N3, N6 and N7. The grid of P1 is connected with Q, the source of P1 is connected with a reference voltage BL_ref, and the drain of P1 is connected with a control node H; the grid of P2 is connected with H, and the source of P2 is connected with BLB; the grid electrode of P3 is connected with the control node K, the source electrode of P3 is connected with the drain electrode of P2, and the drain electrode of P3 is connected with the input node B; the grid electrode of P4 is connected with H, and the drain electrode of P4 is connected with the input node A; the grid of P5 is connected with K, the source electrode of P5 is connected with BL, and the drain electrode of P5 is connected with the source electrode of P4; the gate of P6 is connected to QB, the source of P6 is connected to BL_ref, and the drain of P6 is connected to K; the grid electrode of N2 is connected with K, the source electrode of N2 is connected with VSS, and the drain electrode of N2 is connected with B; a gate of N3 is connected with B, a drain of N3 is connected with Q, and a source of N3 is connected with an enabling control part; a gate of N6 is connected with A, a drain of N6 is connected with QB, and a source of N6 is connected with an enabling control part; the gate of N7 is connected to H, the source of N7 is connected to VSS, and the drain of N7 is connected to A.

The precharge circuit section is configured to precharge H, K to a low level through VSS and to precharge Q, QB to a high level through VDD when the sense amplifier circuit is not operating.

Implementation of such a latch cross-coupled based self-controlled SRAM sense amplifier circuit is in accordance with a method or process of an embodiment of the present disclosure.

In a second aspect, the present invention discloses a sense amplifier module, which adopts the circuit layout of the self-control SRAM sense amplifier circuit based on latch cross coupling as in the first aspect.

Implementation of such sense amplifier modules is in accordance with methods or processes of embodiments of the present disclosure.

Compared with the prior art, the invention has the following beneficial effects:

The self-control SRAM sensitive amplifier circuit based on latch cross coupling is a direct improvement on a circuit structure level, and has a simple and clear structure and is convenient to realize.

2, The invention adopts the mode of connecting the self-control input part and the latch coupling part in parallel, reduces the serial connection of excessive transistors from VDD to VSS, saves the voltage redundancy, avoids the problem of smaller voltage redundancy caused by the serial connection of excessive MOS transistors, and can adapt to the working environment of 0.9V voltage; the self-control input part is adopted, and according to the voltage change of Q, QB, the signal input of the target bit line and the signal turn-off of the non-target bit line are controlled in a self-adaptive manner, so that the influence of the non-target bit line on Q, QB is avoided, and the offset voltage and the amplifying delay are reduced; the invention adopts the latch coupling part to amplify the voltage signal, avoids the control mode of cascading the inverters, and thereby avoids the oscillation risk of the prior patent.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a circuit diagram of a self-controlled SRAM sense amplifier circuit based on latch cross-coupling provided in embodiment 1 of the present invention;

FIG. 2 is a pin layout diagram of a sense amplifier module according to embodiment 1 of the present invention;

FIG. 3 is a waveform diagram showing the operation of the sense amplifier circuit of embodiment 2 of the present invention;

fig. 4 is a circuit configuration diagram of a conventional CLSA sense amplifier circuit in embodiment 3 of the present invention;

FIG. 5 is a graph showing the offset voltage versus the differential amplification of the circuit of FIG. 1 and the circuit of FIG. 4 at different process angles for a 65nm CMOS process in accordance with example 3 of the present invention;

FIG. 6 is a graph showing the comparison of amplification delays when differential amplification is performed at different process angles using the circuit of FIG. 1 and the circuit of FIG. 4 in a 65nm CMOS process in accordance with example 3 of the present invention;

FIG. 7 is a graph showing the dynamic power consumption of the differential amplification at different process angles using the circuit of FIG. 1 and the circuit of FIG. 4 in a 65nm CMOS process according to example 3 of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that when an element is referred to as being "mounted to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or/and" as used herein includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to fig. 1, a circuit configuration diagram of a self-controlled SRAM sense amplifier circuit based on latch cross-coupling provided in this embodiment 1 is shown.

The sense amplifier circuit includes: 9 NMOS transistors and 10 PMOS transistors. The 9 NMOS transistors are marked as N0-N8; the 10 PMOS transistors are denoted P1 to P10.

As shown in fig. 1:

the source of N0 is connected to VSS, the drain of N0 is connected to the sources of N3, N4, N5, N6, and the gate of N0 is connected to enable signal SAE. The gate of N1 is connected with the precharge inverse signal NPRE, the source of N1 is connected with VSS, and the drain of N1 is connected with the control node H. The gate of N2 is connected to control node K, the source of N2 is connected to VSS, and the drain of N2 is connected to input node B. The grid electrode of N3 is connected with the input node B, the drain electrode of N3 is connected with the output node Q, and the source electrode of N3 is connected with the drain electrode of the N0 pipe. The grid electrode of N4 is connected with the drain electrode of the output node QB, the drain electrode of N4 is connected with the drain electrode of the N0 pipe, and the source electrode of N4 is connected with the output node Q. The grid electrode of the N5 is connected with the output node Q, the drain electrode of the N5 is connected with the output node QB, and the source electrode of the N5 is connected with the drain electrode of the N0 pipe. The grid electrode of N6 is connected with the drain electrode of the input node A, N6 and the drain electrode of the output node QB, and the source electrode of N6 is connected with the drain electrode of the N0 pipe. The gate of N7 is connected to control node H, the source of N7 is connected to VSS, and the drain of N7 is connected to input node a. The gate of N8 is connected to the precharge inverse signal NPRE, the source of N8 is connected to VSS, and the drain of N8 is connected to the control node K.

The gate of P1 is connected to the output node Q, the source of P1 is connected to the reference voltage bl_ref, and the drain of P1 is connected to the control node H. The gate of P2 is connected to the control node H, the source of P2 is connected to the bit line BLB, and the drain of P2 is connected to the source of P3. The source of P3 is connected to the drain of P2, the gate of P3 is connected to control node K, and the drain of P3 is connected to input node B. The gate of P4 is connected to control node H, the drain of P4 is connected to input node a, and the source of P4 is connected to the drain of P5. The gate of P5 is connected to control node K, the source of P5 is connected to bit line BL, and the drain of P5 is connected to the source of P4. The gate of P6 is connected to the output node QB, the source of P6 is connected to the reference voltage bl_ref, and the drain of P6 is connected to the control node K. The gate of P7 is connected to output node QB, the source of P7 is connected to bit line BL, and the drain of P7 is connected to output node Q. The gate of P8 is connected to output node Q, the source of P8 is connected to BLB, and the drain of P8 is connected to output node QB. The gate of P9 is connected to the precharge signal PRE, the source of P9 is connected to VDD, and the drain of P9 is connected to the output node Q. The gate of P10 is connected to the precharge signal PRE, the source of P10 is connected to VDD, and the drain of P10 is connected to the output node QB.

Functionally, the sense amplifier circuit includes: an enable control section, a latch coupling section, a self-control input section, and a precharge circuit section.

The following describes each functional unit one by one:

① The enable control part is used for controlling whether the sense amplifier circuit works or not. Referring to fig. 1, the enable control section includes 1 NMOS transistor, denoted as N0.

The source of N0 is connected to VSS, the drain of N0 is connected to the source of N3, the source of N4, the source of N5, the source of N6, and the gate of N0 is connected to enable control signal SAE.

When SAE is at a low level, N0 is turned off, and the sense amplifier circuit does not work; when SAE is high, N0 is on, and the sense amplifier circuit works.

② The latch coupling portion is used for rapidly amplifying the voltage difference of the output node Q, QB through positive feedback coupling according to the bit lines BL, BLB. Referring to fig. 1, the latch coupling portion includes 2 NMOS transistors and 2 PMOS transistors, denoted as N4, N5, P7, P8.

The grid electrode of N4 is connected with QB, and the drain electrode of N4 is connected with Q; the grid electrode of N5 is connected with Q, the drain electrode of N5 is connected with QB, the source electrode of N5 is connected with the source electrode of N4, and is commonly connected to the enabling control part; the gate of P7 is connected to QB, the source of P7 is connected to BL, and the drain of P7 is connected to Q; the gate of P8 is connected to Q, the source of P8 is connected to BLB, and the drain of P8 is connected to QB.

The above connection of N4, N5, P7, P8 forms a latch cross-coupling that can rapidly amplify the voltage difference at the output node Q, QB through positive feedback coupling when the sense amplifier circuit is in operation.

③ The self-control input is used to adaptively cut off the effect of BLB or BL on the latch coupling according to the voltage change of Q, QB. Referring to fig. 1, the self-control input section includes 6 PMOS transistors and 4 NMOS transistors, denoted as P1, P2, P3, P4, P5, P6, N2, N3, N6, N7.

The grid of P1 is connected with Q, the source of P1 is connected with a reference voltage BL_ref, and the drain of P1 is connected with a control node H; the grid of P2 is connected with H, and the source of P2 is connected with BLB; the grid electrode of P3 is connected with the control node K, the source electrode of P3 is connected with the drain electrode of P2, and the drain electrode of P3 is connected with the input node B; the grid electrode of P4 is connected with H, and the drain electrode of P4 is connected with the input node A; the grid of P5 is connected with K, the source electrode of P5 is connected with BL, and the drain electrode of P5 is connected with the source electrode of P4; the gate of P6 is connected to QB, the source of P6 is connected to BL_ref, and the drain of P6 is connected to K; the grid electrode of N2 is connected with K, the source electrode of N2 is connected with VSS, and the drain electrode of N2 is connected with B; a gate of N3 is connected with B, a drain of N3 is connected with Q, and a source of N3 is connected with an enabling control part; a gate of N6 is connected with A, a drain of N6 is connected with QB, and a source of N6 is connected with an enabling control part; the gate of N7 is connected to H, the source of N7 is connected to VSS, and the drain of N7 is connected to A.

The self-control input part is a control core of the invention, and can adaptively control the signal input of the target bit line and the signal turn-off of the non-target bit line, thereby avoiding the influence of the non-target bit line on Q, QB, and further reducing the offset voltage and the amplifying delay.

④ The precharge circuit section is configured to precharge H, K to a low level through VSS and to precharge Q, QB to a high level through VDD when the sense amplifier circuit is not operating. Referring to fig. 1, the precharge circuit section includes 2 PMOS transistors and 2 NMOS transistors, denoted as P9, P10, N1, N8.

The gate of P9 is connected to the precharge signal PRE, the source of P9 is connected to VDD, and the drain of P9 is connected to Q. The gate of P10 is connected to the precharge signal PRE, the source of P10 is connected to VDD, and the drain of P10 is connected to QB. The gate of N1 is connected to the precharge inverse signal NPRE, the source of N1 is connected to VSS, and the drain of N1 is connected to H. The gate of N8 is connected to the precharge inverse signal NPRE, the source of N8 is connected to VSS, and the drain of N8 is connected to K.

The precharge signal PRE and the precharge counter signal NPRE are opposite signals. In general, the precharge signal PRE is connected to the precharge counter signal NPRE through an inverter so that both are always opposite.

Based on the circuit structure of the sense amplifier circuit, the single-read bit line SRAM memory cell and the double-read bit line SRAM memory cell can be adapted:

When the sense amplifier circuit is matched with a single-read bit line SRAM memory cell, the sense amplifier circuit performs data amplification in a mode of identifying a single-end read bit line. Specifically, one of BL and BLB is connected with a single-ended read bit line of a single-read bit line SRAM memory cell, and the other is connected with BL_ref and used as a reference bit line; BL_ref is connected with VDD-3σ; σ represents the variance of the offset voltage (i.e., offset).

When the sense amplifier circuit is matched with a double-read bit line SRAM memory cell, the sense amplifier circuit performs data amplification by identifying the difference of double-read bit lines. Specifically, BL, BLB respectively correspond to two read bit lines connected to the dual read bit line SRAM memory cell, BL_ref is connected to VDD.

Embodiment 1 also discloses a sense amplifier module synchronously, which adopts the circuit layout of the self-control SRAM sense amplifier circuit based on latch cross coupling. The mode of packaging into a module is easier to popularize and apply.

Referring to fig. 3, the pins of the sense amplifier module include 10 pins. The first pin is used for connecting the sources of P9 and P10 with VDD, and the second pin is used for connecting the sources of N0, N1, N2, N7 and N8 with VSS. The third pin is used to connect the gate of N0 to SAE. The fourth pin is used to connect the gates of P9, P10 to PRE. The fifth pin is used for connecting the gates of N1 and N8 with NPRE. The sixth pin is used for connecting the sources of P5 and P7 to BL. The seventh pin is used for connecting the sources of P2 and P8 to BLB. The eighth pin is used to connect the sources of P1, P6 to BL_ref. The ninth pin is used to connect to the output node Q. The tenth pin is used for connecting the output node QB.

Example 2

This embodiment 2 discloses the operation of the sense amplifier circuit of embodiment 1. The sense amplifier circuit of embodiment 1 is controlled in the same manner as the sense amplifier circuit, whether it is in a single-ended read bit line or differential amplification:

When the sensitive amplifier circuit does not work, SAE is low level, and N0 is turned off; PRE is low and NPRE is high; p9, P10 are turned on, Q is precharged to high (i.e., Q is charged high by VDD through P9), QB is precharged to high (i.e., QB is charged high by VDD through P10); n1, N8 are turned on, H is precharged to a low level (i.e., H is discharged by VSS through N1) and K is precharged to a low level (i.e., K is discharged by VSS through N8).

Under the condition that H, K is precharged to a low level, P2 and P3 are turned on, N2 is turned off, and BLB voltage is transmitted to B through P2 and P3; p4, P5 are on, N7 is off, BL voltage is transmitted to A through P4, P5.

When the sense amplifier circuit works, SAE is high level, and N0 is conducted; PRE is high, NPRE is low, and P9, P10, N1, N8 are off.

Since A, B was charged by BL and BLB, respectively, when the previous sense amplifier circuit was not operating, the voltage at A, B is then BL and BLB, respectively. And the output node Q, QB is charged high by VDD, avoiding the effect of the last amplification result before that on the output node Q, QB, and eliminating the charge residues.

If the voltage of A is greater than the voltage of B (i.e., the bit line voltage of BL is greater than the bit line voltage of BLB), N6 and N3 are both on, but the on-current of N6 is greater than the on-current of N3. Therefore Q, QB discharges (i.e., Q discharges to VSS through N3, N0, QB discharges to VSS through N6, N0), and the discharge rate of Q is less than that of QB, so that the voltage of Q is greater than that of QB.

Because the latch coupling part forms positive feedback coupling (namely P7 and N5 are conducted, and P8 and N4 are disconnected), Q is promoted to be charged to a high level, QB is discharged to a low level, and the pressure difference of Q, QB is rapidly amplified; p6 is on, and P1 is off; k is charged high (i.e., K is charged high by BL_ref through P6), H continues to remain low; p5 is turned off to cut off the connection between A and BL, P3 is turned off to cut off the connection between B and BLB, and influence of Q, QB charge and discharge on BL and BLB voltages is avoided; n7 is turned off, P2 and P4 are turned on, and N2 is turned on; a continues to maintain high level, QB continues to discharge (i.e., a continues to discharge to VSS through N6, N0); b discharges low (i.e., B is discharged low by VSS through N2), N3 turns off, shutting off the effect of BLB (i.e., the non-target bit line in this case) on the latch coupling.

In summary, in this case, the above structure can achieve the effect of self-controlling and maintaining or cutting off the input bit line information, and simultaneously reduce the potential risk that the bit line voltage signal may be discharged in the metastable state and the potential risk that oscillation may occur when the bit line potential approaches in the lower cross-coupling structure, and complete the rapid amplification of the bit line voltage difference information.

Similarly, if the voltage of A is less than the voltage of B (i.e., the bit line voltage of BL is less than the bit line voltage of BLB), N6 and N3 are both on, but the on-current of N3 is greater than the on-current of N6. Therefore Q, QB discharges (i.e., Q discharges to VSS through N3, N0, QB discharges to VSS through N6, N0), and the discharge rate of Q is greater than that of QB, so that the voltage of QB is greater than that of Q.

Because the latch coupling part forms positive feedback coupling (namely P7 and N5 are conducted, and P8 and N4 are disconnected), QB is promoted to be charged to a high level, Q is discharged to a low level, and the pressure difference of QB and Q is rapidly amplified; p6 is on, and P1 is off; h charges to high level (i.e., H is charged to high level by bl_ref through P1), K continues to maintain low level; p4 is turned off to cut off the connection between A and BL, P2 is turned off to cut off the connection between B and BLB, and influence of Q, QB charge and discharge on BL and BLB voltages is avoided; n7 is conducted, P5 and P3 are conducted, and N2 is turned off; b continues to maintain high level, Q continues to discharge (i.e., Q continues to discharge to VSS through N3, N0); a discharges low (i.e., a is discharged low by VSS through N7), N6 turns off, shutting off the effect of BL (i.e., the non-target bit line in this case) on the latch coupling.

In this case, the same effect can be achieved by the above structure, and repetition is not performed.

In addition, the operational waveform diagram of fig. 2 may be combined, wherein SAE denotes an enable signal and Q, QB denotes an output signal. 500ps ago, SAE was placed low, i.e., the sense amplifier circuit was not operating, Q, QB was precharged high by VDD. When 500ps, SAE is set to high level, and the voltage of Q drops to 0 rapidly because the discharging speed of Q is larger than QB, and QB drops and rises first and outputs 1 in a short time, so that an output signal is generated, and the amplification output of the bit line voltage difference information is completed.

Example 3

In order to more clearly demonstrate the technical solution provided in embodiment 1 and the technical effects produced in this embodiment 3, a conventional voltage-controlled current-type SRAM sense amplifier circuit (abbreviated as CLSA) shown in fig. 4 is introduced, and performance simulation is performed with the sense amplifier circuit (abbreviated as The proposed SA) of embodiment 1, so that performance differences in differential amplification are examined.

Referring to fig. 5, a graph of offset voltage versus differential amplification of The proposed SA and CLSA at different process angles for a 65nm CMOS process is shown. The simulation conditions were vdd=0.9V and temperature=27℃.

One of the main sources of offset voltage in the sense amplifier is the mismatch of the sizes of pull-down transistors in the pull-down path, that is, the mismatch of the sizes of pull-down transistors N1 and N2 and input transistors N3 and N4 in the cross coupling structure in the CLSA circuit, and because two pairs of pull-down transistors in the CLSA circuit are in series connection, the two mismatches have the risk of mutual overlapping influence. The pull-down tube in The proposed SA circuit is composed of N4 and N5 in the latch coupling part and N3 and N4 of the self-control input part, the two pairs of pull-down tubes are in parallel connection, the size mismatch of the pull-down tubes does not affect the superposition, meanwhile, in the The proposed SA working process, the voltage signal of the input node at one side can be turned off through the self-control input part, the pull-down is accelerated at the other side, the output node is promoted to be rapidly pulled to be at a high-low level, the risk of error identification of a small bit line voltage difference is avoided, and the offset voltage is further reduced. As can be seen from FIG. 5, the proposed SA has a lower offset voltage than the CLSA offset voltage at each process corner, and is reduced by at least 33%.

Referring to fig. 6, there is a graph comparing amplification delays of CLSA and The proposed SA at different process angles for differential amplification operation under a 65nm CMOS process. The simulation conditions were vdd=0.9V, temperature=27 ℃, bit line capacitance=30ff.

In the amplifying process, the proposed SA controls the N3 and N4 auxiliary latch coupling parts to discharge the output nodes Q and QB through the corresponding input node voltages, so that the discharging speed is accelerated, and the amplifying delay is reduced. As can be seen from fig. 6, at different process angles, the amplification delay of The proposed SA is reduced from CLSA by a maximum of 28.2%.

Referring to fig. 7, for comparison of dynamic power consumption during amplification when CLSA and The proposed SA are differentially amplified at different process angles under 65nm CMOS process, the simulation conditions are vdd=0.9V, temperature=27 ℃, bit line capacitance=30 fF.

Since the sources of P7, P8 are connected to bit lines BL, BLB, respectively, and the operation processes N1, N2 are turned off, there is no DC path from power supply VDD to VSS during the The proposed SA amplification, and the dynamic power consumption is reduced compared with CLSA. As can be seen from fig. 7, the dynamic power consumption during the amplification of The proposed SA is reduced compared to CLSA at different process corners, and at least reduced by 21.6%.

Overall The proposed SA has a significant improvement over the above performance metrics.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A self-controlled SRAM sense amplifier circuit based on latch cross-coupling comprising:

An enable control section for controlling whether or not the sense amplifier circuit is operated;

A latch coupling part for rapidly amplifying a voltage difference of the output node Q, QB through positive feedback coupling according to the bit lines BL, BLB; the latch coupling part comprises 2 NMOS tubes and 2 PMOS tubes, which are marked as N4, N5, P7 and P8; the grid electrode of N4 is connected with QB, and the drain electrode of N4 is connected with Q; the grid electrode of N5 is connected with Q, the drain electrode of N5 is connected with QB, the source electrode of N5 is connected with the source electrode of N4, and is commonly connected to the enabling control part; the gate of P7 is connected to QB, the source of P7 is connected to BL, and the drain of P7 is connected to Q; the gate of P8 is connected to Q, the source of P8 is connected to BLB, and the drain of P8 is connected to QB;

A self-control input section for adaptively shutting off an influence of the BLB or BL on the latch coupling section according to a voltage change of Q, QB; the self-control input part comprises 6 PMOS transistors and 4 NMOS transistors, which are marked as P1, P2, P3, P4, P5, P6, N2, N3, N6 and N7; the grid of P1 is connected with Q, the source of P1 is connected with a reference voltage BL_ref, and the drain of P1 is connected with a control node H; the grid of P2 is connected with H, and the source of P2 is connected with BLB; the grid electrode of P3 is connected with the control node K, the source electrode of P3 is connected with the drain electrode of P2, and the drain electrode of P3 is connected with the input node B; the grid electrode of P4 is connected with H, and the drain electrode of P4 is connected with the input node A; the grid of P5 is connected with K, the source electrode of P5 is connected with BL, and the drain electrode of P5 is connected with the source electrode of P4; the gate of P6 is connected to QB, the source of P6 is connected to BL_ref, and the drain of P6 is connected to K; the grid electrode of N2 is connected with K, the source electrode of N2 is connected with VSS, and the drain electrode of N2 is connected with B; a gate of N3 is connected with B, a drain of N3 is connected with Q, and a source of N3 is connected with an enabling control part; a gate of N6 is connected with A, a drain of N6 is connected with QB, and a source of N6 is connected with an enabling control part; the grid electrode of N7 is connected with H, the source electrode of N7 is connected with VSS, and the drain electrode of N7 is connected with A; and

And a precharge circuit section for precharging H, K to a low level through VSS and precharging Q, QB to a high level through VDD when the sense amplifier circuit is not operating.

2. The self-controlled SRAM sense amplifier circuit based on latch cross-coupling of claim 1, wherein said enable control comprises 1 NMOS transistor, denoted N0;

The source of N0 is connected to VSS, the drain of N0 is connected to the source of N3, the source of N4, the source of N5, the source of N6, and the gate of N0 is connected to enable control signal SAE.

3. The self-controlled SRAM sense amplifier circuit based on latch cross-coupling of claim 2, wherein said sense amplifier circuit is inactive when SAE is low; the sense amplifier circuit operates at a high level for SAE.

4. The self-controlled SRAM sense amplifier circuit based on latch cross-coupling of claim 2, wherein said precharge circuit section comprises 2 PMOS transistors and 2 NMOS transistors, denoted P9, P10, N1, N8;

The grid electrode of P9 is connected with the PRE-charge signal PRE, the source electrode of P9 is connected with VDD, and the drain electrode of P9 is connected with Q;

the gate of P10 is connected with the PRE-charge signal PRE, the source of P10 is connected with VDD, and the drain of P10 is connected with QB;

The grid electrode of N1 is connected with a pre-charge inverse signal NPRE, the source electrode of N1 is connected with VSS, and the drain electrode of N1 is connected with H;

the grid electrode of N8 is connected with a pre-charge inverse signal NPRE, the source electrode of N8 is connected with VSS, and the drain electrode of N8 is connected with K;

the precharge signal PRE and the precharge counter signal NPRE are opposite signals.

5. The self-controlled SRAM sense amplifier circuit of claim 4, wherein when said sense amplifier circuit is used in combination with a single read bitline SRAM memory cell, one of BL, BLB is connected to a single read bitline of the single read bitline SRAM memory cell and the other is connected to bl_ref and used as a reference bitline; BL_ref is connected with VDD-3σ; sigma represents the variance of the offset voltage;

when the sense amplifier circuit is matched with the double-read bit line SRAM memory cell for use, BL and BLB are correspondingly connected with two read bit lines of the double-read bit line SRAM memory cell respectively, and BL_ref is connected with VDD.

6. The self-controlled SRAM sense amplifier circuit based on latch cross-coupling of claim 4 wherein SAE is low and N0 is off when said sense amplifier circuit is not operating; PRE is low and NPRE is high; p9 and P10 are conducted, Q is precharged to a high level, and QB is precharged to a high level; n1 and N8 are conducted, H is precharged to a low level, and K is precharged to a low level;

p2 and P3 are on, N2 is off, and BLB voltage is transmitted to B through P2 and P3; p4, P5 are on, N7 is off, BL voltage is transmitted to A through P4, P5.

7. The self-controlled SRAM sense amplifier circuit based on latch cross-coupling of claim 4 wherein, when said sense amplifier circuit is in operation, SAE is high and N0 is on; PRE is high level, NPRE is low level, and P9, P10, N1 and N8 are turned off;

If the voltage of A is greater than the voltage of B, the on current of N6 is greater than the on current of N3; q, QB discharging to enable the voltage of Q to be larger than that of QB; because the latch coupling part forms positive feedback coupling, Q is promoted to be charged to a high level, QB is discharged to a low level, and the pressure difference of Q, QB is rapidly amplified; p6 is on, and P1 is off; k is charged to a high level, and H is continuously maintained to a low level; p5 turns off to cut off the connection of a to BL; p3 turns off to cut off the connection of B to BLB; n7 is turned off, P2 and P4 are turned on, and N2 is turned on; a keeps on maintaining high level, QB keeps on discharging; b discharges to low level, N3 turns off, cutting off the influence of BLB on the latch coupling part.

8. The self-controlled SRAM sense amplifier circuit based on latch cross-coupling of claim 5, wherein, when said sense amplifier circuit is in operation, SAE is high and N0 is on; PRE is high level, NPRE is low level, and P9, P10, N1 and N8 are turned off;

If the voltage of A is smaller than the voltage of B, the conduction current of N3 is larger than the conduction current of N6; q is discharged to VSS through N3 and N0, QB is discharged to VSS through N6 and N0, and the discharging speed of Q is larger than that of QB, so that the voltage of QB is larger than that of Q; because the latch coupling part forms positive feedback coupling, QB is promoted to be charged to a high level, Q is discharged to a low level, and the voltage difference between QB and Q is rapidly amplified; p1 is turned on, and P6 is turned off; h is charged to a high level, and K is continuously maintained at a low level; p4 turns off to cut off the connection of A and BL; p2 turns off to disconnect B from BLB; n7 is conducted, P5 and P3 are conducted, and N2 is turned off; b keeps on maintaining high level, Q keeps discharging; a discharges to low level, N6 is turned off, and BL's influence on the latch coupling is cut off.

9. A sense amplifier module employing a circuit layout of a latch cross-coupled self-controlled SRAM sense amplifier circuit as defined in any one of claims 1-8.

10. The sense amplifier module of claim 9 wherein the pins of the sense amplifier module comprise:

a first pin for connecting the sources of P9 and P10 to VDD;

A second pin for connecting sources of N0, N1, N2, N7, N8 to VSS;

a third pin for connecting the gate of N0 to SAE;

A fourth pin for connecting the gates of P9, P10 to PRE;

a fifth pin for connecting the gates of N1, N8 to NPRE;

A sixth pin for connecting the sources of P5 and P7 to BL;

A seventh pin for connecting the sources of P2 and P8 to BLB;

an eighth pin for connecting the sources of P1, P6 to bl_ref;

a ninth pin for connecting Q; and

Tenth pin, it is used for connecting QB.