CN115035931A - Circuit structure, chip and module based on 8T-SRAM unit - Google Patents

Circuit structure, chip and module based on 8T-SRAM unit Download PDF

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CN115035931A
CN115035931A CN202210564062.XA CN202210564062A CN115035931A CN 115035931 A CN115035931 A CN 115035931A CN 202210564062 A CN202210564062 A CN 202210564062A CN 115035931 A CN115035931 A CN 115035931A
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electrically connected
transistors
slb
bit line
drain
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戴成虎
刘海涛
彭春雨
赵强
卢文娟
郝礼才
刘立
蔺智挺
吴秀龙
黎轩
高珊
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Anhui University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention relates to a circuit structure, a chip and a module based on an 8T-SRAM unit. The 8T-SRAM cell includes: NMOS transistors N1-6; PMOS transistors P1-2. P1, P2 are cross coupled with N1, N2 to latch the data on storage node Q, QB, the source of P1 and P2 are electrically connected to VDD, the storage node Q, QB node is turned on for power path, the source of N1 and the source of N2 are connected to VSS, and the storage node Q, QB node is turned on for ground path. Storage nodes Q and QB are connected to bit lines BL and BLB through transistors N4 and N3, respectively, transistors N3 and N4 are controlled by word line WL, word lines LCM and RCM are connected to bit lines SLB and SL through transistors N5 and N6, respectively, and transistors N5 and N6 are controlled by storage nodes Q and QB, respectively. The invention can realize the comparison operation in the memory and improve the search efficiency.

Description

Circuit structure, chip and module based on 8T-SRAM unit
Technical Field
The invention relates to the technical field of static random access memories, in particular to a circuit structure, a chip and a module based on 8T-SRAM units.
Background
As the artificial intelligence technology is expanded to be applied to more types of equipment, the requirements on the computing efficiency and the energy consumption are higher and higher. The arithmetic module and the memory in the traditional von neumann architecture are separated, when data needs to be used in the calculation process, the data needs to be read from the memory to the arithmetic module, however, the calculation power development process of the current arithmetic module is far beyond the development process of the memory access speed, so a large amount of operation time and power consumption are used for waiting for the data, and the operation time is increased while the operation time is wasted.
Disclosure of Invention
In order to reduce the time of calculation process used for data movement, a circuit structure, a chip and a module based on 8T-SRAM unit are provided.
The invention is realized by adopting the following technical scheme:
an 8T-SRAM cell, comprising:
an NMOS transistor N1;
the gate of the N2 of the NMOS transistor N2 is electrically connected with the gate of N1, the source of N2 is electrically connected with the source of N1, and the drain of N2 is electrically connected with the gate of N1;
the drain of the N3 of the NMOS transistor N3 is electrically connected with the drain of N1 and the gate of N2, the gate of N3 is electrically connected with a word line WL, and the source of N3 is electrically connected with a bit line BLB;
the drain of the NMOS transistor N4, N4 is electrically connected with the drain of N2 and the gate of N1, the gate of N4 is electrically connected with a word line WL, and the source of N4 is electrically connected with a bit line BL;
a gate of the NMOS transistor N5, N5 is electrically connected to a drain of N4, a drain of N2, and a gate of N1, a source of N5 is electrically connected to the bit line SLB, and a drain of N5 is electrically connected to the word line LCM;
a gate of the NMOS transistor N6, N6 is electrically connected to the drain of N3, the drain of N1, and the gate of N2, a source of N6 is electrically connected to a bit line SL, and a drain of N6 is electrically connected to a word line RCM;
a PMOS transistor P1, wherein the gate of P1 is electrically connected with the gate of N1, the drain of N4 and the gate of N5, the drain of P1 is electrically connected with the drain of N1, the drain of N3, the gate of N6 and the gate of N2, and the source of P1 is electrically connected with the source of P2;
a PMOS transistor P2, wherein the gate of P2 is electrically connected with the gate of N2, the drain of N3 and the gate of N6, the drain of P2 is electrically connected with the drain of N2, the drain of N4, the gate of N5 and the gate of N1, and the source of P2 is electrically connected with the source of P1;
transistors P1, P2 and transistors N1, N2 are cross-coupled to latch data at storage node Q, QN, the source of transistor P1 and P2 are electrically connected to VDD to turn on storage node Q, QB for the power path, the source of transistor N1 and N2 are connected to VSS, and storage node Q, QB is turned on for the ground path;
storage nodes Q and QB are connected to bit lines BL and BLB through transistors N4 and N3, respectively, transistors N3 and N4 are controlled by word line WL, word lines LCM and RCM are connected to bit lines SLB and SL through transistors N5 and N6, respectively, and transistors N5 and N6 are controlled by storage nodes Q and QB, respectively.
Further, the cell is maintained in a high state by the word lines LCM and RCM during the precharge phase, the bit lines SL and SLB are also precharged to a high level, the internal storage nodes Q and QB act on the transistors N5 and N6 to control the transistors to be turned on and off, assuming that the cell stores data of '1', i.e., "Q ═ 1 and QB ═ 0", during the search phase, the search data is loaded on the bit lines SL and SLB, assuming "SL ═ 0 and SLB ═ 1", the transistor N5 is turned on, the N6 is turned off, and the LCM and RCM are output at a high level of '1', i.e., data matching, after being acted by the SA sense amplifier and the and gate; conversely, the search data is "SL ═ 1, SLB ═ 0", the word line LCM is high, the bit line SLB is low, output through SA is '0', and logical and with the word line RCM is output as '0', i.e., data mismatch.
The invention also comprises a circuit structure based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit, which is characterized in that the 8T-SRAM unit is adopted, and the circuit structure comprises N × N8T-SRAM units;
in the 8T-SRAM unit positioned in the same row, the grid word lines WL of all the transistors N3 and N4 are electrically connected; the drains of all the transistors N5 are electrically connected to the word line LCM; the drains of all transistors N6 are electrically connected to the word line RCM;
8T-SRAM cells located in the same column, the sources of all transistors N3 being electrically connected to bit line BLB; the sources of all the transistors N4 are electrically connected to the bit line BL; the sources of all the transistors N5 are electrically connected to the bit line SLB, and the sources of all the transistors N6 are electrically connected to the bit line SL.
In one embodiment, it comprises 2 x 2 8T-SRAM cells; the gates of all the transistors N3 and N4 of two 8T-SRAM units in the same row are electrically connected with a word line WL; the drains of all the transistors N5 are electrically connected to the word line LCM; the drains of all transistors N6 are electrically connected to the word line RCM;
two 8T-SRAM cells in the same column, all the sources of transistors N3 being electrically connected to bit line BLB; the sources of all the transistors N4 are electrically connected to the bit line BL; the sources of all the transistors N5 are electrically connected to the bit line SLB; the sources of all the transistors N6 are electrically connected to the bit line SL.
Further, in the precharge stage, the word lines LCM and RCM are precharged to a high level, the bit lines SL and SLB are precharged to a high level, and two rows of cells turned on are respectively denoted as a and B, and it is assumed that data "Q ═ 1 and QB ═ 0" are stored in a, and data "Q ═ 0 and QB ═ 1" are stored in B;
in the calculation stage, all the word lines LCM AND RCM in a AND B are grounded AND discharged to a low level, the LCM AND RCM of the word lines in the rest rows are kept at VDD, SLB is output as '0' through SA, that is, 'NOR (a, B) ═ 0', the output of the other end of SA is '1', that is, 'OR (a, B) ═ 1', the output of SL is '0' through SA, that is, 'AND (a, B) ═ 0', the output of the other end of SA is '1', that is, 'NAND (a, B) ═ 1', as long as one of the data stored in a, B is '0', both SL AND SLB are discharged to ground, AND the output result is the same as above; when the data stored in a and B are both '1', i.e., "Q ═ 1 and QB ═ 0" in a and B, SLB is output as '0' through SA, i.e., SLB is output as
Figure BDA0003657090460000031
The output of the other end of the SA is '1', i.e., "a + B is 1", the output of the SL is '1', i.e., "AB is 1", via the SA, the output of the other end of the SA is '0', i.e., "AB is 1"
Figure BDA0003657090460000032
When the data stored in a and B are both '0', i.e., "Q is 0 and QB is 1" in a and B, SLB is output as '1' through SA, i.e., SLB is output as
Figure BDA0003657090460000033
The output of the other end of the SA is '0', that is, "a + B is 0", the output of SL is '0' through the SA, that is, "AB is 0", and the output of the other end of the SA is '0', that is, the output of SA is 0
Figure BDA0003657090460000041
In one embodiment, it comprises 4 x 4 8T-SRAM cells; the 8T-SRAM unit is positioned in four 8T-SRAM units in the same row, the gates of all the transistors N3 and N4 are electrically connected with a word line WL, the drains of all the transistors N5 are electrically connected with a word line LCM, and the drains of all the transistors N6 are electrically connected with a word line RCM;
in the four 8T-SRAM cells in the same column, the sources of all the transistors N3 are electrically connected to the bit line BLB, the sources of all the transistors N4 are electrically connected to the bit line BL, the sources of all the transistors N5 are electrically connected to the bit line SLB, and the sources of all the transistors N6 are electrically connected to the bit line SL.
Further, the circuit configuration is configured to precharge the word lines LCM and RCM to a high level in the precharge phase, precharge the search bit lines SL and SLB to a high level, and load data onto the SL and SLB in the search phase, assuming that the search data is "1010", that is, "SL <0> -1, SL <1> -0, SL <2> -1, SL <3> -0, SLB <0> -0, SLB <1> -1, SLB <2> -0, and SLB <3> -1", which are obtained from the stored data in the array, and when the 0 th row matches the search data, that is, the stored data in the QB matches the search data on SL, both are "1010", the output is "1", and the output of the remaining rows is "0", indicating a mismatch.
The invention also comprises an 8T-SRAM chip which is formed by packaging the 8T-SRAM unit; the pins of the 8T-SRAM chip comprise:
a first pin electrically connected to the gates of transistors N3, N4 through a word line WL;
a second pin electrically connected to the drain of transistor N5 through word line LCM;
a third pin electrically connected to the drain of transistor N6 through word line RCM;
a fourth pin electrically connected to the source of transistor N3 through bit line BLB;
a fifth pin electrically connected to the source of transistor N4 through bit line BL;
a sixth pin electrically connected to the source of transistor N5 through bit line SLB;
and a seventh pin electrically connected to the source of transistor N6 through bit line SL.
The invention also comprises a circuit chip based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit, which is characterized in that the circuit chip is formed by adopting the memory Boolean logic operation and the unidirectional BCAM circuit structure based on the 8T-SRAM unit for packaging; the pins of the circuit chip based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit comprise:
8T-SRAM cells located in the same row, wherein the gates of all transistors N3 and N4 are electrically connected with a word line WL, so that a first pin is led out; the drains of all the transistors N5 are electrically connected to the word line LCM, from which a second pin is led out; the drains of all the transistors N6 are electrically connected to the word line RCM, thereby drawing a third pin; one first pin, one second pin and one third pin are arranged in each row;
8T-SRAM cells located in the same column, the sources of all transistors N3 being electrically connected to bit line BLB, thereby drawing a fourth pin; the sources of all the transistors N4 are electrically connected to the bit line BL, and a fifth pin is led out therefrom; the sources of all the transistors N5 are electrically connected to the bit line SLB, whereby a sixth pin is drawn; the sources of all the transistors N6 are electrically connected to a bit line SL, from which a seventh pin is drawn, and one of the fourth pin, the fifth pin, the sixth pin, and the seventh pin exists for each column.
The invention also includes a circuit module based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell, which is characterized in that the circuit module adopts a circuit in the circuit structure based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell, and the circuit module based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell includes:
the 8T-SRAM units are positioned in the same row, and the grids of all the transistors N3 and N4 are electrically connected with WL, so that a first connection end is led out; the drains of all the transistors N5 are electrically connected to the word line LCM, thereby leading to a second connection terminal; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to a third connection; there is one of the first link, the second link, the third link per row;
8T-SRAM cells located in the same column, the sources of all transistors N3 being electrically connected to bit line BLB, thereby leading to a fourth connection; the sources of all the transistors N4 are electrically connected to the bit line BL, thereby leading to a fifth connection terminal; the sources of all the transistors N5 are electrically connected to the bit line SLB, thereby drawing a sixth pin; the sources of all transistors N6 are electrically connected to a bit line SL, from which a seventh connection leads, one for each column being the fourth, fifth, sixth and seventh connection.
The technical scheme provided by the invention has the following beneficial effects:
the circuit structure based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit is adopted, the column-direction Boolean logic operation and the row-direction addressing function can be realized, the circuit can be used for the memory Boolean logic operation and the unidirectional BCAM operation, the independence of stored data is ensured, the stability of the unit is improved, the operation efficiency is greatly improved, and the structure has the characteristic of good symmetry.
Drawings
FIG. 1 is a schematic diagram of an 8T-SRAM cell according to the present invention;
FIG. 2 is a schematic diagram of a 2 x 2 array of 8T-SRAM cells based on the 8T-SRAM cell of FIG. 1;
FIG. 3 is a simulation of the Boolean logic operation of FIG. 2;
FIG. 4 is a schematic diagram of the structure of 8T-SRAM cells distributed in a 4 x 4 array based on the 8T-SRAM cells of FIG. 1;
FIG. 5 is a simulation diagram of the row-wise BCAM search of FIG. 4;
FIG. 6 is a schematic diagram of an 8T-SRAM chip based on the 8T-SRAM cell of FIG. 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in FIG. 1, the present embodiment provides an 8T-SRAM cell, which includes NMOS transistor N1, MOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, PMOS transistor P1, and PMOS transistor P2.
The gate of N2 is electrically connected with the gate of N1, the source of N2 is electrically connected with the source of N1, and the drain of N2 is electrically connected with the gate of N1. The drain of N3 is electrically connected to the drain of N1 and the gate of N2, the gate of N3 is electrically connected to the word line WL, and the source of N3 is electrically connected to the bit line BLB. The drain of N4 is electrically connected to the drain of N2 and the gate of N1, the gate of N4 is electrically connected to the word line WL, and the source of N4 is electrically connected to the bit line BL. The gate of N5 is electrically connected to the drain of N4, the drain of N2, and the gate of N1, the source of N5 is electrically connected to the bit line SLB, and the drain of N5 is electrically connected to the word line LCM. The gate of N6 is electrically connected to the drain of N3, the drain of N1, and the gate of N2, the source of N6 is electrically connected to the bit line SL, and the drain of N6 is electrically connected to the word line RCM. The gate of P1 is electrically connected with the gate of N1, the drain of N4, the gate of N5, the drain of P1 is electrically connected with the drain of N1, the drain of N3, the gate of N6 and the gate of N2, and the source of P1 is electrically connected with the source of P2. The gate of P2 is electrically connected with the gate of N2, the drain of N3, the gate of N6 and the drain of P1, the drain of P2 is electrically connected with the drain of N2, the drain of N4, the gate of N5 and the gate of N1. Transistors P1, P2 and transistors N1, N2 are cross-coupled to latch data at storage node Q, QN, the source of transistor P1 and the source of P2 are electrically connected to VDD to turn on the storage node Q, QB node to power path, the source of transistor N1 and the source of N2 are connected to VSS to turn on the storage node Q, QB node to ground path.
Storage nodes Q and QB are connected to bit lines BL and BLB through transistors N4 and N3, respectively, transistors N3 and N4 are controlled by word line WL, word lines LCM and RCM are connected to bit lines SLB and SL through transistors N5 and N6, respectively, and transistors N5 and N6 are controlled by storage nodes Q and QB, respectively.
For the cross-coupled connection, specific description is made thereon, that is, the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1, the drain of the PMOS transistor P1 is electrically connected to the drain of the NMOS transistor N1, the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2, the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N2, the gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P2, and the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P1, so that data of the storage node Q, QN is latched.
For an 8T-SRAM cell, the implementation principle is roughly as follows: during the precharge phase, the word lines LCM and RCM are maintained at a high state, the bit lines SL and SLB are also precharged to a high state, and the internal storage nodes Q and QB act on the transistors N5 and N6, controlling the transistors to be turned on and off. Assuming that the cell stores data of '1', that is, "Q ═ 1, QB ═ 0", in the search phase, search data is loaded on bit lines SL and SLB, assuming "SL ═ 0, SLB ═ 1", then transistor N5 is turned on, N6 is turned off, and since bit line SLB and word line LCM are both high, no charge sharing occurs, and therefore, LCM and RCM output a high level of '1', that is, data matching, through the SA sense amplifier and the and gate. Conversely, if the search data is "SL ═ 1, SLB ═ 0", since the transistor N5 is turned on, N6 is turned off, the word line LCM is high, the bit line SLB is low, charge sharing occurs between the two, causing the voltage on the word line LCM to drop, and the word line LCM is output as '0' via SA, and the word line RCM is logically anded with the word line RCM to output as '0', i.e., data mismatch, so as long as the data on the bit line SLB and the Q stored data are different, or the data on the bit line SL and the QB stored data are different, a mismatch is indicated, i.e., the output is '0', and conversely, a match output is indicated as '1'.
The 8T-SRAM unit can be adopted to establish various circuit structures of memory Boolean logic operation and unidirectional BCAM, and a circuit structure based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit is formed, and the circuit structure can comprise N x N8T-SRAM units.
For N x N8T-SRAM cells, the 8T-SRAM cells in the same row, the gates of all transistors N3, N4 are electrically connected with a word line WL; the drains of all the transistors N5 are electrically connected to the word line LCM; the drains of all transistors N6 are electrically connected to word line RCM. 8T-SRAM cells in the same column, all sources of transistors N3 being electrically connected to bit line BLB; the sources of all the transistors N4 are electrically connected to the bit line BL; the sources of all the transistors N5 are electrically connected to the bit line SLB; the sources of all transistors N6 are electrically connected to the bit line SL.
For the N × N8T-SRAM units building the array structure, the circuit structure is symmetrically arranged, so that N is an even number.
Taking the SRAM mode as an example, the SRAM mode is performed based on the N × N8T-SRAM cells, and the steps are as follows:
s1, holding operation
During the period that the memory cell keeps data, the word line WL keeps low level, which causes the NMOS transistors N3 and N4 to be turned off, the bit lines BL and BLB are precharged to high level, the internal part of the circuit keeps initial state, and the circuit does not work;
s2, write operation
In the write data phase, word line WL is high, and if bit line BL is high and bit line BLB is low, '1' is written to storage node Q through transistor N4; if bit line BL is low and bit line BLB is high, '1' is written to storage node QB through transistor N3;
s3, read operation
In the read data phase, the bit lines BL and BLB are precharged to high level, the word line WL is high level, and N3 and N4 as pass transistors are turned on; if the circuit stores data as '0', then "Q is 0 and QB is 1", the bit line BL is discharged to ground through the transistors N4 and N2, so that the bit lines BLB and BL generate a voltage difference, and then the data is read out through the sense amplifier; if the circuit stores data as '1', Q is 1 and QB is 0, the bit line BLB is discharged to ground through the transistors N3 and N1, so that a voltage difference is generated between the bit lines BLB and BL, and then the data is read out through the sense amplifier.
As shown in fig. 2, taking 2 × 2 8T-SRAM cells as an example, memory calculation is performed by boolean logic, wherein, in two 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL; the drains of all the transistors N5 are electrically connected to the word line LCM; the drains of all transistors N6 are electrically connected to the word line RCM;
two 8T-SRAM cells in the same column, the sources of all transistors N3 being electrically connected to bit line BLB; the sources of all the transistors N4 are electrically connected to the bit line BL; the sources of all the transistors N5 are electrically connected to the bit line SLB; the sources of all the transistors N6 are electrically connected to the bit line SL.
For 2 x 2 8T-SRAM cells, the implementation principle is roughly as follows: between the same columnAnd the word lines LCM and RCM are controlled to be switched on and off, and two rows of logic AND, NAND, OR and NOR operations are realized through SL and SLB. In the precharge phase, word lines LCM and RCM are precharged to a high level, bit lines SL and SLB are precharged to a high level, two rows of cells turned on are respectively denoted as a and B, and it is assumed that data "Q ═ 1 and QB ═ 0" are stored in a, and data "Q ═ 0 and QB ═ 1" are stored in B; in the calculation phase, all the word lines LCM AND RCM in a AND B are grounded AND discharged to a low level, the LCM AND RCM in the word lines in the rest rows are kept at VDD, so that the N5 transistor in a is turned on, the N6 transistor in B is turned on, so that SL AND SLB are discharged to ground through the transistor N6 in B AND the transistor N5 in a, respectively, the SLB output through SA is '0', that is, "NOR (a, B) ═ 0", the output at the other end of S A is '1', that is, "OR (a, B) ═ 1", the SL output through SA is '0', that is, "AND (a, B) ═ 0", AND the output at the other end of SA is '1', that is, "NAND (a, B) ═ 1". If one of the data stored in A and B is '0', both SL and SLB will discharge to ground, and the output result is the same as above. When the data stored in a and B are all '1', that is, "Q is 1 and QB is 0" in a and B, this will turn on N5 transistor in a and N5 transistor in B, causing SLB to discharge to ground through N5 transistors in a and B, while SL remains high. SLB goes out of '0' over SA, i.e
Figure BDA0003657090460000091
The output of the other end of SA is '1', i.e., "a + B ═ 1", the output of SL is '1', i.e., "AB ═ 1" through SA, the output of the other end of SA is '0', i.e., "AB ═ 1", the output of the other end of SA is
Figure BDA0003657090460000092
When the data stored in a and B are both '0', i.e., "Q is 0 and QB is 1" in a and B, this will turn on the N6 transistor in a and the N6 transistor in B, causing SL to discharge to ground through the N6 transistors in a and B, while SLB remains high. SLB goes out of '1' over SA, i.e.
Figure BDA0003657090460000101
Then SA anotherOne end output is ' 0 ', that is, "a + B ═ 0", SL output is ' 0 ' through SA, that is, "AB ═ 0", then the other end output of SA is ' 0 ', that is, "AB ═ 0", then SA output is ' 0
Figure BDA0003657090460000102
The truth table is as follows:
boolean logic operation truth table
A B NOR OR NAND AND
0 0 1 0 1 0
0 1 0 1 1 0
1 0 0 1 1 0
1 1 0 1 0 1
As shown in fig. 3, the storage nodes are '1 ″ 0', that is, the boolean logic operation simulation result obtained when the data "Q" is 1, QB "is 0" is stored in a, AND the data "Q" is 0, QB "is 1" is stored in B, AND the output is consistent with the boolean logic calculation, NOR (a, B) is 0, OR (a, B) is 1, NAND (a, B) is 1, AND (a, B) is 0, so as to implement the vertical memory boolean logic operation.
As shown in fig. 4, taking 4 × 4 8T-SRAM cells as an example, a horizontal BCAM data search operation is performed, in which the gates of all transistors N3 and N4 are electrically connected to the word line WL, the drains of all transistors N5 are electrically connected to the word line LCM, and the drains of all transistors N6 are electrically connected to the word line RCM in four 8T-SRAM cells located in the same row. In the four 8T-SRAM cells in the same column, the sources of all the transistors N3 are electrically connected to the bit line BLB, the sources of all the transistors N4 are electrically connected to the bit line BL, the sources of all the transistors N5 are electrically connected to the bit line SLB, and the sources of all the transistors N6 are electrically connected to the bit line SL.
In the 4 × 4 8T-SRAM cells of the present embodiment, the implementation principle is roughly as follows: before data searching, the storage unit writes data into a Q point for storage through an SRAM writing mode. The precharge phase word lines LCM and RCM are both precharged to high, and the search bit lines SL and SLB are precharged to high. The search phase loads the data onto SL and SLB, which in this example is "1010", i.e., "SL <0> -1, SL <1> -0, SL <2> -1, SL <3> -0, SLB <0> -0, SLB <1> -1, SLB <2> -0, and SLB <3> -1". According to the stored data in the array, only the 0 th row is consistent with the search data, that is, the stored data in QB is consistent with the search data on SL and is 1010, the output is 1 ', and the rest rows are 0', which indicates a mismatch.
Referring to fig. 4, the search data is "1010", and the QB stored data are "1010, 0101, 0111, 0100" from the first row to the fourth row, respectively.
Referring to fig. 5, the search data is "1010", the QB storage data is "1010, 0101, 0111, 0100" from the first row to the fourth row, respectively, and as can be seen from the output result, only the 0 th row is consistent with the search data, so the 0 th row output result is "1", i.e. indicating a match, and the remaining rows are inconsistent with the search data, and the output is "0", indicating a mismatch.
In conclusion, the vertical memory logical operation and the horizontal BCAM data search operation can be performed, the data independence during the operation is ensured, and the anti-interference capability of the unit is improved.
On the basis of the 8T-SRAM unit, an 8T-SRAM chip is further provided, and the chip is formed by packaging the 8T-SRAM unit; the 8T-SRAM unit is easier to popularize and apply due to the mode of packaging into a chip.
As shown in fig. 6, the pins of the 8T-SRAM chip include:
a first pin electrically connected to the gates of transistors N3, N4 through a word line WL;
a second pin electrically connected to the drain of transistor N5 through word line LCM;
a third pin electrically connected to the drain of transistor N6 through word line RCM;
a fourth pin electrically connected to the source of transistor N3 through bit line BLB;
a fifth pin electrically connected to the source of transistor N4 through bit line BL;
a sixth pin electrically connected to the source of transistor N5 through bit line SLB;
and a seventh pin electrically connected to the source of transistor N6 through bit line SL.
On the basis of the above, a circuit chip based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit is further provided, and the chip is formed by packaging the N x N8T-SRAM units; the 8T-SRAM unit circuit is packaged into a chip mode, and is easier to popularize and apply.
The pins of the circuit chip based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit comprise:
8T-SRAM cells located in the same row, wherein the gates of all transistors N3 and N4 are electrically connected with a word line WL, so that a first pin is led out; the drains of all the transistors N5 are electrically connected to the word line LCM, from which a second pin is led out; the drains of all the transistors N6 are electrically connected to the word line RCM, thereby drawing a third pin; each row has a first pin, a second pin and a third pin;
8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to bit line BLB, thereby leading out a fourth pin; the sources of all the transistors N4 are electrically connected to the bit line BL, and a fifth pin is led out therefrom; the sources of all the transistors N5 are electrically connected to the bit line SLB, and a sixth pin is led out therefrom; the sources of all the transistors N6 are electrically connected to the bit line SL, so that a seventh pin is led out, and one fourth pin, one fifth pin, one sixth pin, and one seventh pin are present in each column.
On the basis of the foregoing, the present embodiment further includes a circuit module based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell, which employs a circuit in the circuit structure based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell, where the circuit module based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell includes:
the 8T-SRAM units are positioned in the same row, and the grids of all the transistors N3 and N4 are electrically connected with WL, so that a first connection end is led out; the drains of all the transistors N5 are electrically connected to the word line LCM, thereby leading to a second connection terminal; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to a third connection; each row has a first connecting end, a second connecting end and a third connecting end;
8T-SRAM cells located in the same column, the sources of all transistors N3 being electrically connected to bit line BLB, thereby leading to a fourth connection; the sources of all the transistors N4 are electrically connected to the bit line BL, thereby leading to a fifth connection terminal; the sources of all the transistors N5 are electrically connected to the bit line SLB, whereby a sixth pin is drawn; the sources of all transistors N6 are electrically connected to the bit line SL, from which the seventh connection leads, one for each column, fourth, fifth, sixth and seventh connection.
All possible combinations of the technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all the possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present description as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. An 8T-SRAM cell, comprising:
an NMOS transistor N1;
the gate of the NMOS transistor N2, N2 and the drain of N1 are electrically connected, the source of N2 and the source of N1 are electrically connected, and the drain of N2 and the gate of N1 are electrically connected;
an NMOS transistor N3, wherein the drain of N3 is electrically connected with the drain of N1 and the gate of N2, the gate of N3 is electrically connected with a word line WL, and the source of N3 is electrically connected with a bit line BLB;
the drain of the N4 of the NMOS transistor N4 is electrically connected with the drain of N2 and the gate of N1, the gate of N4 is electrically connected with a word line WL, and the source of N4 is electrically connected with a bit line BL;
a gate of the NMOS transistor N5, a gate of the N5 is electrically connected with a drain of the N4, a drain of the N2 and a gate of the N1, a source of the N5 is electrically connected with the bit line SLB, and a drain of the N5 is electrically connected with the word line LCM;
a gate of the NMOS transistor N6, N6 is electrically connected to a drain of N3, a drain of N1, and a gate of N2, a source of N6 is electrically connected to a bit line SL, and a drain of N6 is electrically connected to a word line RCM;
a PMOS transistor P1, the gate of P1 is electrically connected with the gate of N1, the drain of N4 and the gate of N5, the drain of P1 is electrically connected with the drain of N1, the drain of N3, the gate of N6 and the gate of N2, and the source of P1 is electrically connected with the source of P2;
a PMOS transistor P2, wherein the gate of P2 is electrically connected with the gate of N2, the drain of N3 and the gate of N6, the drain of P2 is electrically connected with the drain of N2, the drain of N4, the gate of N5 and the gate of N1, and the source of P2 is electrically connected with the source of P1;
transistors P1, P2 and transistors N1, N2 are cross-coupled to latch data at storage node Q, QB, the source of transistor P1 and P2 are electrically connected to VDD to turn on storage node Q, QB for the power path, the source of transistor N1 and N2 are connected to VSS, and storage node Q, QB is turned on for the ground path;
storage nodes Q and QB are connected to bit lines BL and BLB through transistors N4 and N3, respectively, transistors N3 and N4 are controlled by word line WL, word lines LCM and RCM are connected to bit lines SLB and SL through transistors N5 and N6, respectively, and transistors N5 and N6 are controlled by storage nodes Q and QB, respectively.
2. The 8T-SRAM cell of claim 1, wherein the cells are maintained in a high state by the word lines LCM and RCM during the precharge phase, the bit lines SL and SLB are also precharged to a high state, the internal storage nodes Q and QB act on the transistors N5 and N6, the transistors are controlled to be turned on and off, assuming that the cells store data of '1', that is, "Q ═ 1 and QB ═ 0", during the search phase, search data is loaded on the bit lines SL and SLB, assuming "SL ═ 0 and SLB ═ 1", the transistor N5 is turned on, N6 is turned off, and the LCM and RCM are output at a high '1' after SA sense amplifier and gate action, that is, data matching; conversely, the search data is "SL ═ 1, SLB ═ 0", the word line LCM is high, the bit line SLB is low, and output through SA is '0', and logical and is output with the word line RCM as '0', that is, data mismatch.
3. An in-memory boolean logic operation and unidirectional bcam (binary Content Addressable memory) circuit structure based on 8T-SRAM cells, characterized in that it employs the 8T-SRAM cells of claim 1 or 2, said circuit structure comprising N x N8T-SRAM cells;
wherein, the circuit structure is symmetrically arranged, so N is an even number; 8T-SRAM cells located in the same row, the gates of all transistors N3, N4 being electrically connected to word line WL; the drains of all the transistors N5 are electrically connected to the word line LCM; the drains of all transistors N6 are electrically connected to word line RCM;
8T-SRAM cells located in the same column, the sources of all transistors N3 being electrically connected to bit line BLB; the sources of all the transistors N4 are electrically connected to the bit line BL; the sources of all the transistors N5 are electrically connected to the bit line SLB; the sources of all transistors N6 are electrically connected to the bit line SL.
4. The circuit structure based on in-memory boolean logic operation of 8T-SRAM cells and unidirectional BCAM of claim 3, characterized in that it comprises 2 x 2 8T-SRAM cells; the gates of all the transistors N3 and N4 of two 8T-SRAM units in the same row are electrically connected with a word line WL; the drains of all the transistors N5 are electrically connected to the word line LCM; the drains of all transistors N6 are electrically connected to word line RCM;
two 8T-SRAM cells in the same column, the sources of all transistors N3 being electrically connected to bit line BLB; the sources of all the transistors N4 are electrically connected to the bit line BL; the sources of all the transistors N5 are electrically connected to the bit line SLB; the sources of all the transistors N6 are electrically connected to the bit line SL.
5. The 8T-SRAM cell based in-memory Boolean logic operation and unidirectional BCAM circuit structure of claim 4, wherein during the precharge phase, word lines LCM and RCM are precharged to high level, bit lines SL and SLB are precharged to high level, two rows of cells turned on are respectively denoted as A and B, and it is assumed that data stored in A is Q-1 and QB-0, and data stored in B is Q-0 and QB-1;
in the calculation phase, all the word lines LCM AND RCM in a AND B are grounded AND discharged to a low level, the LCM AND RCM of the word lines in the rest rows are kept at VDD, SLB is output as '0' through SA, that is, 'NOR (a, B) ═ 0', the output of the other end of SA is '1', that is, 'OR (a, B) ═ 1', SL is output as '0' through SA, that is, 'AND (a, B) ═ 0', the output of the other end of SA is '1', that is, 'NAND (a, B) ═ 1', as long as one of the data stored in a, B is '0', both SL AND SLB are discharged to the ground, AND the output result is the same; when the data stored in a and B are both '1', i.e., "Q ═ 1 and QB ═ 0" in a and B, SLB is output as '0' through SA, i.e., SLB is output as
Figure FDA0003657090450000031
The output of the other end of the SA is '1', i.e., "a + B is 1", the output of the SL is '1', i.e., "AB is 1", via the SA, the output of the other end of the SA is '0', i.e., "AB is 1"
Figure FDA0003657090450000032
When the data stored in a and B are all '0', that is, "Q is 0 and QB is 1" in a and B, SLB is output as '1' through SA, that is
Figure FDA0003657090450000033
The output of the other end of SA is '0', i.e. "a + B ═ 0", the output of SL is '0' through SA, i.e. "AB ═ 0", the output of the other end of SA is '0', i.e. "0
Figure FDA0003657090450000034
6. The circuit structure based on in-memory boolean logic operation of 8T-SRAM cells and unidirectional BCAM of claim 3, characterized in that it comprises 4 x 4 8T-SRAM cells; the gates of all the transistors N3 and N4 are electrically connected with a word line WL, the drains of all the transistors N5 are electrically connected with a word line LCM, and the drains of all the transistors N6 are electrically connected with a word line RCM;
in the four 8T-SRAM cells in the same column, the sources of all the transistors N3 are electrically connected to the bit line BLB, the sources of all the transistors N4 are electrically connected to the bit line BL, the sources of all the transistors N5 are electrically connected to the bit line SLB, and the sources of all the transistors N6 are electrically connected to the bit line SL.
7. The 8T-SRAM cell based in-memory boolean logic operation and unidirectional BCAM circuit configuration of claim 6, characterized in that the circuit configuration precharges word lines LCM and RCM to a high level in a precharge phase, precharges search bit lines SL and SLB to a high level, the search phase loads data onto SL and SLB, assuming that the search data is "1010", i.e., "SL <0> -1, SL <1> -0, SL <2> -1, SL <3> -0, SLB <0> -0, SLB <1> -1, SLB <2> -0, and SLB <3> -1", which are available from the stored data in the array, when the 0 th row is identical to the search data, i.e., the stored data in the QB is identical to the search data on SL, both are "1010", the output is "1", and the remaining row outputs are "0", which indicate a mismatch.
8. An 8T-SRAM chip packaged using the 8T-SRAM cell of claim 1; the pins of the 8T-SRAM chip comprise:
a first pin electrically connected to the gates of transistors N3, N4 through a word line WL;
a second pin electrically connected to the drain of transistor N5 through word line LCM;
a third pin electrically connected to the drain of transistor N6 through word line RCM;
a fourth pin electrically connected to the source of transistor N3 through bit line BLB;
a fifth pin electrically connected to the source of transistor N4 through bit line BL;
a sixth pin electrically connected to the source of transistor N5 through bit line SLB;
a seventh pin electrically connected to the source of transistor N6 through bit line SL.
9. A circuit chip based on the memory Boolean logic operation and the unidirectional BCAM of an 8T-SRAM unit is characterized by being packaged by adopting the circuit structure based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit according to any one of claims 3 to 7; the pins of the circuit chip based on the memory Boolean logic operation and the unidirectional BCAM of the 8T-SRAM unit comprise:
8T-SRAM cells located in the same row, wherein the gates of all transistors N3 and N4 are electrically connected with a word line WL, so that a first pin is led out; the drains of all the transistors N5 are electrically connected to the word line LCM, from which a second pin is led out; the drains of all the transistors N6 are electrically connected to the word line RCM, thereby drawing a third pin; one of the first pin, the second pin and the third pin exists in each row;
8T-SRAM cells in the same column, the sources of all transistors N3 are electrically connected to bit line BLB, thus leading out a fourth pin; the sources of all the transistors N4 are electrically connected to the bit line BL, and a fifth pin is led out therefrom; the sources of all the transistors N5 are electrically connected to the bit line SLB, and a sixth pin is led out therefrom; the sources of all the transistors N6 are electrically connected to a bit line SL, from which a seventh pin is drawn, and one of the fourth pin, the fifth pin, the sixth pin, and the seventh pin exists for each column.
10. A circuit block based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell, characterized in that it adopts a circuit in the circuit structure based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell according to any of the claims 1 to 7, and the circuit block based on the memory boolean logic operation and the unidirectional BCAM of the 8T-SRAM cell comprises:
the 8T-SRAM units are positioned in the same row, and the gates of all the transistors N3 and N4 are electrically connected with WL, so that a first connection end is led out; the drains of all the transistors N5 are electrically connected to the word line LCM, thereby leading to a second connection terminal; the drains of all the transistors N6 are electrically connected to the word line RCM, thereby leading to a third connection terminal; each row has one of the first connection end, the second connection end, and the third connection end;
8T-SRAM cells located in the same column, the sources of all transistors N3 being electrically connected to bit line BLB, thereby drawing a fourth connection; the sources of all the transistors N4 are electrically connected to the bit line BL, thereby leading to a fifth connection terminal; the sources of all the transistors N5 are electrically connected to the bit line SLB, and a sixth pin is led out therefrom; the sources of all transistors N6 are electrically connected to a bit line SL, from which a seventh connection leads, one for each column being the fourth, fifth, sixth and seventh connection.
CN202210564062.XA 2022-05-23 2022-05-23 Circuit structure, chip and module based on 8T-SRAM unit Pending CN115035931A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116206650A (en) * 2023-01-17 2023-06-02 安徽大学 8T-SRAM unit and operation circuit and chip based on 8T-SRAM unit
CN116206650B (en) * 2023-01-17 2024-02-13 安徽大学 8T-SRAM unit and operation circuit and chip based on 8T-SRAM unit

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