CN116204490A - 7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology - Google Patents

7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology Download PDF

Info

Publication number
CN116204490A
CN116204490A CN202310216702.2A CN202310216702A CN116204490A CN 116204490 A CN116204490 A CN 116204490A CN 202310216702 A CN202310216702 A CN 202310216702A CN 116204490 A CN116204490 A CN 116204490A
Authority
CN
China
Prior art keywords
circuit
operand
wlb
data
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310216702.2A
Other languages
Chinese (zh)
Inventor
蔺智挺
黄震
吴秀龙
彭春雨
戴成虎
卢文娟
赵强
周永亮
郝礼才
刘玉
李鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui University
Original Assignee
Anhui University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anhui University filed Critical Anhui University
Priority to CN202310216702.2A priority Critical patent/CN116204490A/en
Publication of CN116204490A publication Critical patent/CN116204490A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a 7T memory circuit, a multiply-accumulate operation circuit and a CIM chip based on a low-voltage technology. The 7T memory circuit is composed of 3 PMOS tubes P1-P3 and 4 NMOS tubes N1-N4, wherein the sources of P1 and P2 are connected with a power supply VDD. The gates of P2 and N2 are connected with the source of N3, the drain of P3 and the drain of N1, and serve as a storage node Q. The gates of P1, N1 are connected to the drains of P2, N2 and act as the inverted storage node QB. The drain electrode of the P1 is connected with the source electrode of the P3; the source of N1 is connected with the drain of N4. The source electrode of N2 and the source electrode of N4 are connected with VSS; the grid electrode of N3 is connected with a signal line WL; the drain electrode of N3 is connected with the signal line BL; the grid electrode of P3 is connected with a signal line WLA; the gate of N4 is connected to the signal line WLB. The multiply-accumulate circuit and CIM chip include a core array constructed from 7T memory circuits and the necessary peripheral functions. The invention solves the problems that the existing low-voltage CIM has high design difficulty, and the indexes such as power consumption, operation performance and the like of the circuit are difficult to meet expectations.

Description

7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a 7T memory circuit based on a low-voltage technology, a multiply-accumulate operation circuit and a CIM chip based on the 7T memory circuit.
Background
In a conventional von neumann computer architecture, the computation module is separate from the memory module, so the data processing operation needs to undergo data input and output. At present, with the demands of various emerging neural networks and other applications on huge data processing tasks, von neumann bottleneck problems are more and more prominent. Therefore, the academia and industry are constantly researching viable coping strategies. On this basis, the in-memory computing (CIM, computing In Memory) concept has developed.
Different from the traditional von neumann architecture, in-memory computing is a novel computing architecture for performing data computation in a memory, and a computing module and a storage unit are combined into a whole, so that data movement between the computing module and the storage unit caused by large-scale data processing is fundamentally avoided, storage and processing of initial data, intermediate data and final data are realized in the same area, and computational integration is directly realized in a hardware level, thereby effectively reducing access power consumption and time delay caused by von neumann bottleneck. In addition, the in-memory calculation has a remarkable advantage, namely the multi-row reading characteristic, and the parallel processing of the data can be realized through the simultaneous activation of a plurality of rows, so that the throughput of the data is greatly increased, and the calculation speed is further improved.
On the other hand, with the deep development of scale technology in integrated circuits, the operating voltage of chips becomes lower and lower, and the process variation thereof increases. The increase in process variations severely affects the performance of the system, which makes the requirements of the circuit for power consumption become more stringent. For a high-throughput SRAM array, the power consumption problem is particularly obvious, and the direct reduction of the working voltage of an SRAM storage unit is a more direct method except for low-power consumption technologies such as a gate power supply, a body bias, a source bias, a dynamic voltage, a bit line floating circuit and the like. However, with the continuous progress of the process technology, the threshold voltage of the MOS transistor is continuously reduced, and the device parameter fluctuation caused by the process fluctuation is also larger and larger. Because memory cell circuits in memory arrays that employ minimum size designs are more susceptible to device parameter variations, the design of memory cells in low voltage environments requires better anti-ripple capability and better data stability.
Based on the background, developing an in-memory operation circuit based on low-voltage technology is a current research direction in the field of integrated circuit design. However, because of the high difficulty in designing the low-voltage and high-performance in-memory operation circuit, there is no low-voltage in-memory operation chip scheme capable of meeting various performance requirements.
Disclosure of Invention
In order to solve the problems that the existing low-voltage in-memory operation circuit is high in design difficulty, and indexes such as power consumption and operation performance of the circuit are difficult to meet expectations, the invention provides a 7T memory circuit based on a low-voltage technology, a multiply-accumulate operation circuit and a CIM chip based on the 7T memory circuit.
The invention is realized by adopting the following technical scheme:
A7T memory circuit based on low voltage technology has a data read-write holding function and a multiplication function. The 7T memory circuit consists of 3 PMOS tubes P1-P3 and 4 NMOS tubes N1-N4, and the circuit connection relation is as follows:
the sources of P1 and P2 are connected with the power supply VDD. The gates of P2 and N2 are connected with the source of N3, the drain of P3 and the drain of N1, and serve as a storage node Q. The gates of P1, N1 are connected to the drains of P2, N2 and act as the inverted storage node QB. The drain electrode of the P1 is connected with the source electrode of the P3; the source of N1 is connected with the drain of N4. The source electrode of N2 and the source electrode of N4 are connected with VSS; the grid electrode of N3 is connected with a signal line WL; the drain electrode of N3 is connected with the signal line BL; the grid electrode of P3 is connected with a signal line WLA; the gate of N4 is connected to the signal line WLB.
In the 7T memory circuit provided by the invention, P1 and N1 form one inverter, and P2 and N2 form the other inverter; the two inverters constitute a cross-coupled latch structure and form two storage nodes Q and QB for storing and holding data. The signal line BL is connected to the latch structure through N3 as an input port for performing a data write operation by the 7T memory circuit and an output port for performing a multiplication operation. The signal line WLA is connected to the latch structure through P3 to control the on and off of the latch structure, the signal line WL is connected to the latch structure through N3 and used for inputting a high level signal with a specific pulse length to represent the weight of one operand in multiplication operation, and the signal line WLB is connected to the latch structure through N4 and used for inputting a high level signal with a specific level amplitude to represent the weight of the other operand in multiplication operation.
As a further improvement of the present invention, in a 7T memory circuit, the operating logic to implement the data retention state is as follows:
setting the signal line WL to a low level, setting WLA to a low level, and setting WLB to a high level; at this time, the latch structure in the 7T register circuit is in a conductive state, so that the storage nodes Q and QB can form positive feedback, thereby achieving the purpose of data retention.
As a further improvement of the present invention, in a 7T memory circuit, the operating logic for implementing data reading is as follows:
pre-charging the signal line BL to a high level; then, the WL is set to a high level, WLA is set to a low level, and WLB is set to a high level; the latch structure in the 7T register circuit is in an on state, enabling the originally stored Q, QB to form positive feedback. At this time, the signal line BL is equivalent to a capacitor due to the parasitic capacitance effect of the connection line; the bit line voltage of BL varies according to the data stored in the storage node Q as follows:
(1) When Q is high, i.e., the stored data is 1; BL is the same as Q potential, the gate voltage of N1 is 0, N1 is in an off state; BL cannot form a path from N3, N1, N4 to power ground VSS, BL remains high; i.e. the read data is 1.
(2) When Q is low, i.e., the stored data is 0; the grid voltage of N1 is high level, BL discharges power ground VSS through N3, N1 and N4, so that BL is converted from high level to low level; i.e. the read data is 0.
As a further improvement of the present invention, in a 7T memory circuit, the operating logic for implementing data writing is as follows:
first, the signal line WL is set to high level, WLA is set to high level, and WLB is set to high level; at this time, the latch structure in the 7T memory circuit is broken; meanwhile, the signal line BL is set to a high level or a low level according to whether data to be written is "1" or "0".
After the data writing to the storage node is completed, WLA and WL are set to low level, so that the 7T storage circuit is restored to the data holding state.
As a further improvement of the present invention, in a 7T memory circuit, the operation logic for implementing the multiplication operation is as follows:
a signal having a specific pulse width is generated based on the first operand and input to the signal line WL. Wherein the high-low state of WL represents the reference value "1" or "0" of the first operand, and the pulse width T of WL WL And representing the weight corresponding to the reference value of the first operand. Namely: in the multiplication operation of the 7T memory circuit of the present invention, the first operand is actually (T WL ·WL)。
At 7T memory circuitThe QB storage node of (c) is pre-written with a reference value of "1" or "0" of the second operand. Meanwhile, a signal with a specific level amplitude is generated and input to the signal line WLB; level amplitude V using WLB WLB And representing the weight corresponding to the reference value of the second operand. Namely: in the multiplication operation of the 7T memory circuit of the present invention, the second operand is actually (V WLB ·QB)。
In the operation process, the level state of the signal line BL is sampled according to the current voltage V of the signal line BL BL The voltage drop is calculated, and the product operation result P is quantized according to the amplitude of the voltage drop of the bit line of BL:
Figure BDA0004115197620000031
in the above equation, Δv represents the voltage drop of the corresponding BL when the result is unit 1 in the current multiplication operation.
As a further improvement of the present invention, the multiplication operation supported by the 7T memory circuit includes three kinds of single-bit number by single-bit number, single-bit number by multiple-bit number, and multiple-bit number by multiple-bit number; when any operand is a single-bit number, only the weight T of the corresponding operand is needed WL Or V WLB The value is set to 1.
The invention also comprises a multiply-accumulate circuit which adopts the 7T memory circuit as a basic unit for executing multiplication operation and accumulates the result of each multiplication operation through a shared bit line technology. The multiply-accumulate operation circuit includes: the memory device comprises an operation array, a bit line group, a word line group, a first input unit, a second input unit and an output unit.
The operation array comprises at least 1 calculation column, wherein the calculation column is formed by arranging N7T memory circuits according to columns. The bit line group comprises at least 1 bit line BL, and all 7T memory circuits in the calculation column are connected to the same bit line. The word line group includes three types of word lines WL, WLA, and WLB, and the number of each type of word line is N. Each 7T memory circuit of the same row in the operation array is connected to the same set of word lines WL, WLA, and WLB.
The first input unit is used for generating electric signals with specific levels and pulse widths according to a first operand in multiply-accumulate operation, and inputting the electric signals into the 7T storage circuits through word lines WL of each row. The first input unit is used for generating electric signals with specific level amplitude according to the second operand in the multiply-accumulate operation, and inputting the electric signals into the 7T storage circuits through word lines WLB of the rows. The output unit is connected to the bit line BL and is used for quantizing and outputting a corresponding multiply-accumulate operation result according to the voltage drop of the operation phase bit line BL.
In the multiply-accumulate operation circuit provided by the invention, the execution process of the multiply-accumulate operation is as follows:
(1) A pre-charging stage:
and writing a corresponding reference value of 1 or 0 in the storage node QB of each row of the operation array according to each second operand of the multiplication operation. The signal line BL is then precharged to a high level, and the latch structure is adjusted to a data hold state.
(2) An input stage:
WLA for each row of the operational array is set high. Then, a signal having a specific pulse width is generated based on the first operand of each row, and is input to the signal line WL. Wherein the high-low state of WL represents the reference value "1" or "0" of the first operand, and the pulse width T of WL WL The weight corresponding to the reference value representing the first operand is: the first operand is (T WL ·WL)。
At the same time, a signal having a specific level amplitude is generated from the second operand of each row and input to the signal line WLB. Wherein the data pre-stored in the storage node QB characterizes a reference value of the second operand, the level amplitude V of WLB WLB And representing the weight corresponding to the reference value of the second operand, namely: the second operand is (V WLB ·QB)。
(3) Product output stage:
the level state of the signal line BL is sampled according to the current voltage V of the signal line BL BL Calculating voltage drop and quantizing product according to amplitude of BL bit line voltage dropCalculation result MAC:
Figure BDA0004115197620000041
in the above equation, Δv represents the voltage drop of the corresponding BL when the result is unit 1 in the current multiply-accumulate operation.
The invention also comprises a CIM chip based on the 7T memory circuit, which is formed by packaging a core circuit with a data storage function and a multiply-accumulate operation function and an integrated circuit of other peripheral functional modules. The functional modules in the CIM chip based on the 7T memory circuit comprise: the device comprises a memory array, a word line group, a bit line group, a word line driver, a decoder, a pulse width modulation circuit, a pulse amplitude modulation circuit, a pre-charge circuit, a time sequence control module, a mode switching module and a quantization output module.
The memory array is formed by arranging N multiplied by M7T memory circuits in an array mode of N rows and M columns. The word line group includes three types of word lines WL, WLA, and WLB, and the number of each type of word line is N. Each 7T memory circuit of the same row in the memory array is connected to the same set of word lines WL, WLA, and WLB. The bit line group comprises M bit lines BL; all 7T memory circuits in the same column in the memory array are connected to the same bit line BL. The word line drivers are used to control the turning on of the respective word lines WL, WLA and WLB. The decoder is connected with the word line driver, and the decoder is used for decoding the address signals and transmitting the decoded address signals to the word line driver.
The pulse width modulation circuit is used for generating an electric signal with a specific level and pulse width according to a first operand in a multiplication operation or multiplication accumulation operation stage and inputting the electric signal into a corresponding 7T storage circuit through word lines WL of each row. The pulse amplitude modulation circuit is used for generating an electric signal with a specific level amplitude according to a second operand in multiplication operation or multiply-accumulate operation, and inputting the electric signal into a corresponding 7T storage circuit through word lines WLB of each row.
The precharge circuit is used for performing a precharge operation on the bit line BL in a data read-write stage or an operation stage. The timing control module is used for generating various clock signals required in the process of executing data storage tasks or multiplying operation and multiply-accumulate operation. The mode switching circuit is used for switching the working mode of the in-memory operation circuit, and the working mode of the in-memory operation circuit comprises a data storage mode and a logic operation mode.
The quantization output circuit is connected to the bit line BL; the quantization output circuit includes a data reading section and an operation output section. The data reading part is used for outputting the storage data of each storage node according to the level state of the bit line BL; the operation output section is used for monitoring the voltage of the bit line BL and outputting the voltage drop of the bit line BL as a multiplication operation result or an operation result of a multiply-accumulate operation through analog-to-digital conversion.
The technical scheme provided by the invention has the following beneficial effects:
the 7T memory circuit provided by the embodiment is a single-ended input type SRAM device with a simple structure, and can solve the problem that single ends are difficult to write in by utilizing a low-voltage technology. Meanwhile, the use of the interrupt pipe P3 in the 7T memory circuit in the invention enables the feedback unit in the original standard SRAM unit to be interrupted, and simultaneously increases the driving capability of single-ended writing operation, so that the writing of data can be completed under the condition of lower voltage; at the same time, the use of single-ended bit lines results in a half less number of bit lines in the array cells. Therefore, the 7T memory circuit provided by the invention has the advantages of lower power consumption and more stable data storage performance compared with corresponding devices,
The 7T memory circuit provided by the invention is based on three different input signals WL, WLA and WLB and one output signal BL, and can also realize the full-function multiplication performance, including the multiplication between single-bit numbers, the multiplication between single-bit numbers and multi-bit numbers and the multiplication between multi-bit numbers.
The invention further obtains a multiplication and accumulation operation circuit and a CIM chip based on the designed 7T memory circuit, and the two circuits can be applied to a high-throughput SRAM array, and the complex in-memory logic operation tasks such as multiplication, multiplication and accumulation and the like are completed by utilizing the layout of the memory array of the existing circuit. The circuit designed by the invention has simple structure, and can further reduce the circuit power consumption in large-scale logic operation and static non-operation state on the basis of effectively improving the operation efficiency and speed.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
fig. 1 is a circuit diagram of a 7T memory circuit based on a low voltage technology provided in embodiment 1 of the present invention.
Fig. 2 is a circuit state diagram of the 7T memory circuit in embodiment 1 of the present invention under a data retention operation.
Fig. 3 is a circuit state diagram of the 7T memory circuit in embodiment 1 of the present invention when reading the data "1" stored in the storage node.
Fig. 4 is a circuit state diagram of the 7T memory circuit in embodiment 1 of the present invention when reading data "0" stored in the storage node.
Fig. 5 is a circuit state diagram of the 7T memory circuit in embodiment 1 of the present invention when data writing is performed in the read storage node.
Fig. 6 is a schematic circuit diagram of the 7T memory circuit in embodiment 1 of the present invention when performing multiplication.
Fig. 7 is a circuit diagram of a multiply-accumulate operation circuit according to embodiment 2 of the present invention.
Fig. 8 is a circuit diagram of a CIM chip based on a 7T memory circuit according to embodiment 3 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a 7T memory circuit based on a low voltage technology, which has a data read-write holding function and a multiplication function. As shown in fig. 1, the 7T register circuit is composed of 3 PMOS transistors P1 to P3 and 4 NMOS transistors N1 to N4, and the circuit connection relationship is as follows:
The sources of P1 and P2 are connected with the power supply VDD. The gates of P2 and N2 are connected with the source of N3, the drain of P3 and the drain of N1, and serve as a storage node Q. The gates of P1, N1 are connected to the drains of P2, N2 and act as the inverted storage node QB. The drain electrode of the P1 is connected with the source electrode of the P3; the source of N1 is connected with the drain of N4. The source electrode of N2 and the source electrode of N4 are connected with VSS; the grid electrode of N3 is connected with a signal line WL; the drain electrode of N3 is connected with the signal line BL; the grid electrode of P3 is connected with a signal line WLA; the gate of N4 is connected to the signal line WLB.
In the 7T memory circuit provided in this embodiment, P1 and N1 constitute one inverter, and P2 and N2 constitute the other inverter; the two inverters constitute a cross-coupled latch structure and form two storage nodes Q and QB for storing and holding data. The signal line BL is connected to the latch structure through N3 as an input port for performing a data write operation by the 7T memory circuit and an output port for performing a multiplication operation. The signal line WLA is connected to the latch structure through P3 to control the on and off of the latch structure, the signal line WL is connected to the latch structure through N3 and used for inputting a high level signal with a specific pulse length to represent the weight of one operand in multiplication operation, and the signal line WLB is connected to the latch structure through N4 and used for inputting a high level signal with a specific level amplitude to represent the weight of the other operand in multiplication operation.
Specifically, the basic function of the 7T memory circuit and the operation principle thereof provided in this embodiment are described below in terms of the contents of two parts, namely, a memory function and a logic operation function.
1. Data storage function
The 7T memory circuit provided in this embodiment is the same as a conventional SRAM memory cell, and the most basic function is to implement reading, writing and holding of data. As shown in fig. 2, the operation logic of the 7T memory circuit for implementing the data retention state is as follows:
setting the signal line WL to a low level, setting WLA to a low level, and setting WLB to a high level; at this time, the latch structure in the 7T register circuit is in a conductive state, and positive feedback can be formed between the storage node Q and the storage node QB, so that the purpose of "data retention" can be achieved.
The operation logic for implementing data reading by the 7T memory circuit provided in this embodiment is as follows:
first, the signal line BL is precharged to a high level. Then, the signal WL is set to high, WLA is set to low, and WLB is set to high. At this time, the latch structure in the 7T memory circuit is still in a conductive state, and thus positive feedback can still be formed between the storage nodes Q and QB, which originally store the corresponding data. In this state, the signal line BL is equivalent to a capacitance due to the parasitic capacitance effect of the connection line; the bit line voltage of BL varies according to the data stored in the storage node Q as follows:
(1) As shown in fig. 3, when Q is high, i.e., the stored data is 1; BL is the same as Q potential, the gate voltage of N1 is 0, N1 is in an off state; BL cannot form a path from N3, N1, N4 to power ground VSS. Therefore, no voltage drop will occur across the BL, which remains high. Defining a bit line voltage V BL The state of high hold is 1, i.e.: the read data is 1.
(2) As shown in fig. 4, when Q is low, i.e., the stored data is 0; the gate voltage of N1 is high, a complete path is formed between BL and power ground VSS through N3, N1, N4, and BL discharges power ground VSS, thereby converting BL from high to low. Defining a bit line voltage V BL The state of voltage drop is 0, namely: the read data is 0.
In the 7T memory circuit provided in this embodiment, as shown in fig. 5, the operation logic for implementing data writing is as follows:
first, the signal line WL is set to high level, WLA is set to high level, and WLB is set to high level; at this time, the latch structure in the 7T memory circuit is broken; meanwhile, the signal line BL is set to a high level or a low level according to whether data to be written is "1" or "0".
In the process of writing specific data to any one of the write storage nodes Q through BL, the process of changing the circuit state occurring is also different due to the difference between the write data and the original data in the storage node Q. The method can be specifically divided into the following scenes:
1. When the storage node original level state is high (i.e., original data is "1") and data to be written is "0".
In the data write phase, BL needs to be set low all the time, and WLA and WLB are both set high. Next, when WL is turned to high, the storage node Q in the high state is discharged to BL through N3. After the discharging is completed, the level state of the storage node Q is inverted, that is, changed from the high level state to the low level state, and at this time, the storage data of the storage node becomes "0". Finally, WLA and WL are set to low level, and the whole operation of writing '0' is completed.
2. When the storage node original level state is low (i.e., original data is "0") and data to be written is "0".
In the data write phase, BL needs to be set low all the time, and WLA and WLB are both set high. Next, after WL is switched to high, both storage nodes Q and BL are at low level, no charge flow is formed between them, and the storage data of all storage nodes remains at low level, i.e., the storage data remains at "0". And finally, setting WLA and WL to low level to finish the current operation of writing '0'.
3. When the storage node original level state is high (i.e., original data is "1") and data to be written is "1".
In the data write phase, BL needs to be always high, and WLA and WLB are both high. Next, after WL is switched to high, both the storage nodes Q and BL are at high level, and no charge flow is formed therebetween, so that the storage data of the storage node Q remains at high level, i.e., the storage data remains at "0". And finally, setting WLA and WL to low level to finish the current operation of writing '1'.
4. When the storage node original level state is low (i.e., original data is "0") and data to be written is "1".
In the data write phase, BL needs to be always high, and WLA and WLB are both high. Next, when WL is switched to high, the storage node Q in low state is charged through N3 by the high state BL. After the charge is completed, the high BL causes the level state of the storage node Q to be inverted, i.e., the stored data is changed from "0" to "1". Finally, WLA and WL are set to low level, and the whole operation of writing '1' is completed.
2. Multiplication function
In the 7T memory circuit provided in this embodiment, as shown in fig. 6, the operation logic for implementing the multiplication operation is as follows:
a signal having a specific pulse width is generated based on the first operand and input to the signal line WL. Wherein the high-low state of WL represents the reference value "1" or "0" of the first operand, and the pulse width T of WL WL And representing the weight corresponding to the reference value of the first operand. Namely: in the multiplication operation of the 7T memory circuit of the present invention, the first operand is actually (T WL ·WL)。
The reference value "1" or "0" of the second operand is written in advance in the QB storage node of the 7T storage circuit. Meanwhile, a signal with a specific level amplitude is generated and input to the signal line WLB; level amplitude V using WLB WLB And representing the weight corresponding to the reference value of the second operand. Namely: in the multiplication operation of the 7T memory circuit of the present invention, the second operand is actually (V WLB ·QB)。
In the operation process, the level state of the signal line BL is sampled according to the current voltage V of the signal line BL BL The voltage drop is calculated, and the product operation result P is quantized according to the amplitude of the voltage drop of the bit line of BL:
Figure BDA0004115197620000091
in the above equation, Δv represents the voltage drop of the corresponding BL when the result is unit 1 in the current multiplication operation.
For example: assume that at a certain 7T register circuit, the pulse width T of the electrical signal to be input to WL WL The first operand (one multiplier) is divided into 8 gears from large to small, namely, 8 numbers in different states of 0-7 can be simulated, and the corresponding number is a 3-bit binary number: 000-111. Wherein the WL is low, which characterizes the first operand as "000", and the WL is high, and the pulse width T WL From narrow to wide, a total of 7 different numbers may be used for modules 001-111. At this time, the level state of the WL corresponds to the "reference" of the first operand, and the pulse width of the WL corresponds to the "weight" of the first operand.
Accordingly, for the second operand (another multiplier) of the multiplication operation, the present embodiment is characterized differently from the first operand. Specifically, the present embodiment uses the level value of the original storage node QB to characterize the "reference" of the second operand, and uses the level magnitude of the electrical signal input into WLB to characterize the "weight" of the second operand. In this state, assuming that the amplitude of the electrical signal input into WLB is divided into 8 different "gears", a number of the second operand of 0-7 and 8 different states can be simulated, and the corresponding binary number is 3 bits: 000-111. Specifically, when QB is in a low state, the second operand is represented as "000", and when QB is in a high state and the level amplitude of WLB is from low to high, a total of 7 different numbers from 001 to 111 can be simulated in sequence.
In the circuit provided in fig. 1, the operation procedure of the multiplication operation roughly includes three scenarios as follows:
Scenario 1:
if WL is in low state, N3 is in off state, and at this time, the storage node Q and the bit line BL cannot be turned on, and the BL cannot generate a voltage drop, i.e., the product result is 0. This may correspond to both "0×0=0" and "0×u=u" scenarios. And (3) injection: "U" herein refers to any multi-bit binary number. And "0" represents the digital 0 of the multi-bit binary system.
Scenario 2:
when the storage node QB is 0, it indicates that the storage node Q is at a high level, and at this time, a voltage drop still cannot be generated between the BL and the storage node Q which are also at the high level, so that the product result is still 0, that is, "ux0=0" in the multi-bit multiplication is realized.
Scenario 3:
when WL, WLB and QB are in a high state, the storage node Q is turned on with the signal line BL. And when the pulse width of WL and the level amplitude of WLB are different, the voltage drop amplitude of the signal line BL is different, and the drop amplitude of the bit line voltage can be approximately expressed by the following formula:
Figure BDA0004115197620000101
in the above, deltaV BL For the voltage drop across BL, Δt is the discharge time, i.e. word line pulse width, C BL Is the parasitic capacitance on BL; i D Represents the discharge current of BL in the circuit, and I D Satisfies the following formula:
Figure BDA0004115197620000102
in the above, mu n For electron mobility, C, of NMOS transistor N4 ox The unit area of the gate oxide capacitance of the NMOS transistor N4 is represented by W/L representing the width-to-length ratio, V of the NMOS transistor N4 GS In this case WLA, V TH Is the threshold voltage of NMOS transistor N4, V DS Is the voltage difference between the drain and the source of the NMOS transistor N4.
Therefore, by quantizing the voltage drop amplitude of the signal line BL, a corresponding product operation result, that is, an operation "u1×u2=u3" can be output. And (3) injection: "U1, U2, and U3" herein refer to three multi-bit binary numbers.
What needs to be specifically stated is: the above description will be given by way of example only of the 7T memory circuit of the present embodiment, taking multiplication between 3 bits as an example. In fact, if the level amplitude V according to WLB WLB And pulse width T of WL WL Further coarsening or thinning the "gear" of the two operands can simulate multiplication of different numbers of bits.
When any operand is a single-bit number, only the weight T of the corresponding operand is needed WL Or V WLB The value is set to 1. That is to say: the electric signals input to WL and WLB are not stepped in the signal input stage; WL always inputs a single pulse width electrical signal, WLB always inputs a single level amplitude electrical signal.
To sum up: the multiplication operation supported by the 7T memory circuit provided in this embodiment includes three kinds of single-bit number by single-bit number, single-bit number by multiple-bit number, and multiple-bit number by multiple-bit number.
Example 2
On the basis of embodiment 1, the present embodiment further provides a multiply-accumulate operation circuit that employs the aforementioned 7T memory circuit as a basic unit for performing multiplication operations, and accumulates the results of the respective multiplication operations by a shared bit line technique. As shown in fig. 7, the multiply-accumulate operation circuit provided in this embodiment includes: the memory device comprises an operation array, a bit line group, a word line group, a first input unit, a second input unit and an output unit.
The operation array comprises at least 1 calculation column, wherein the calculation column is formed by arranging N7T memory circuits according to columns. The bit line group comprises at least 1 bit line BL, and all 7T memory circuits in the calculation column are connected to the same bit line. The word line group includes three types of word lines WL, WLA, and WLB, and the number of each type of word line is N. Each 7T memory circuit of the same row in the operation array is connected to the same set of word lines WL, WLA, and WLB.
The first input unit is used for generating electric signals with specific levels and pulse widths according to a first operand in multiply-accumulate operation, and inputting the electric signals into the 7T storage circuits through word lines WL of each row. The first input unit is used for generating electric signals with specific level amplitude according to the second operand in the multiply-accumulate operation, and inputting the electric signals into the 7T storage circuits through word lines WLB of the rows. The output unit is connected to the bit line BL and is used for quantizing and outputting a corresponding multiply-accumulate operation result according to the voltage drop of the operation phase bit line BL.
In the multiply-accumulate operation circuit provided in this embodiment 1, the execution process of the multiply-accumulate operation is as follows:
(1) A pre-charging stage:
and writing a corresponding reference value of 1 or 0 in the storage node QB of each row of the operation array according to each second operand of the multiplication operation. The signal line BL is then precharged to a high level, and the latch structure is adjusted to a data hold state.
(2) An input stage:
WLA for each row of the operational array is set high. Then, a signal having a specific pulse width is generated based on the first operand of each row, and is input to the signal line WL. Wherein the high-low state of WL represents the reference value "1" or "0" of the first operand, and the pulse width T of WL WL The weight corresponding to the reference value representing the first operand is: the first operand is (T WL ·WL)。
At the same time, a signal having a specific level amplitude is generated from the second operand of each row and input to the signal line WLB. Wherein the data pre-stored in the storage node QB characterizes a reference value of the second operand, the level amplitude V of WLB WLB And representing the weight corresponding to the reference value of the second operand, namely: the second operand is (V WLB ·QB)。
(3) Product output stage:
the level state of the signal line BL is sampled according to the current voltage V of the signal line BL BL The voltage drop is calculated, and the product operation result MAC is quantized according to the amplitude of the voltage drop of the bit line of BL:
Figure BDA0004115197620000111
in the above equation, Δv represents the voltage drop of the corresponding BL when the result is unit 1 in the current multiply-accumulate operation.
The multiply-accumulate circuit of fig. 7 was further developed based on the 7T memory circuit of fig. 1 in embodiment 1. The main calculation unit is still the respective 7T memory circuit in fig. 1, the 7T memory circuit being used to complete the steps of the respective multiplication operations included in the multiply-accumulate operation; and then the bit line BL is used for accumulating the multiplication results of the storage units with the multiplication results of not 0 in all 7T storage circuits.
In the multiply-accumulate operation circuit, since all 7T storage circuits are connected to the same bit line BL through respective N3, if the product result of a certain 7T storage circuit is not 0, the storage node Q in the 7T storage circuit is turned on with BL, and the voltage of BL is reduced. Similarly, the result of the multiply-accumulate operation can be obtained by quantizing the voltage drop of the bit line BL.
In the multiply-accumulate operation circuit provided in this embodiment, the operation array needs only 1 row to combine to realize the corresponding multiply-accumulate operation task. If the operation array with multiple columns is adopted, the operation result output of different multiply-accumulate operations can be synchronously completed in different columns, and the operation efficiency of the circuit is improved.
Example 3
On the basis of embodiment 2, the present embodiment further provides a CIM chip based on a 7T memory circuit, which is packaged by a core circuit having a data storage function and a multiply-accumulate operation function, and an integrated circuit of other peripheral functional modules. As shown in fig. 8, the functional modules in the CIM chip based on the 7T memory circuit include: the device comprises a memory array, a word line group, a bit line group, a word line driver, a decoder, a pulse width modulation circuit, a pulse amplitude modulation circuit, a pre-charge circuit, a time sequence control module, a mode switching module and a quantization output module.
The memory array is formed by arranging N multiplied by M7T memory circuits in an array mode of N rows and M columns. The word line group includes three types of word lines WL, WLA, and WLB, and the number of each type of word line is N. Each 7T memory circuit of the same row in the memory array is connected to the same set of word lines WL, WLA, and WLB. The bit line group comprises M bit lines BL; all 7T memory circuits in the same column in the memory array are connected to the same bit line BL. The word line drivers are used to control the turning on of the respective word lines WL, WLA and WLB. The decoder is connected with the word line driver, and the decoder is used for decoding the address signals and transmitting the decoded address signals to the word line driver.
The pulse width modulation circuit is used for generating an electric signal with a specific level and pulse width according to a first operand in a multiplication operation or multiplication accumulation operation stage and inputting the electric signal into a corresponding 7T storage circuit through word lines WL of each row. The pulse amplitude modulation circuit is used for generating an electric signal with a specific level amplitude according to a second operand in multiplication operation or multiply-accumulate operation, and inputting the electric signal into a corresponding 7T storage circuit through word lines WLB of each row.
The precharge circuit is used for performing a precharge operation on the bit line BL in a data read-write stage or an operation stage. The timing control module is used for generating various clock signals required in the process of executing data storage tasks or multiplying operation and multiply-accumulate operation. The mode switching circuit is used for switching the working mode of the CIM chip, and the working mode of the in-memory operation circuit comprises a data storage mode and a logic operation mode.
The quantization output circuit is connected to the bit line BL; the quantization output circuit includes a data reading section and an operation output section. The data reading part is used for outputting the storage data of each storage node according to the level state of the bit line BL; the operation output section is used for monitoring the voltage of the bit line BL and outputting the voltage drop of the bit line BL as a multiplication operation result or an operation result of a multiply-accumulate operation through analog-to-digital conversion.
The CIM chip provided in this embodiment has the same data read-write and hold functions as a normal SRAM, and can also implement multiplication and multiply-accumulate operations using the same operation logic as in embodiment 1 or 2. Wherein, each multiplication operation can be completed by only taking one 7T memory circuit in the memory array as an execution unit. Each multiply-accumulate operation requires that a plurality of 7T memory circuits in the same column of the memory array be implemented together as an execution unit.
In addition, it is to be noted that: in practical application, the 9T 1C-SRAM-based in-memory operation circuit in the embodiment can be packaged into a 9T 1C-SRAM-based CIM chip, and the CIM chip is generated as a chip and sold to the outside.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. A 7T memory circuit based on low voltage technology, characterized by: the device has a data read-write holding function and a multiplication operation function; the 7T memory circuit consists of 3 PMOS tubes P1-P3 and 4 NMOS tubes N1-N4, and the circuit connection relation is as follows:
The sources of P1 and P2 are connected with a power supply VDD; the grid electrodes of P2 and N2 are connected with the source electrode of N3, the drain electrode of P3 and the drain electrode of N1 and serve as a storage node Q; the grid electrodes of P1 and N1 are connected with the drain electrodes of P2 and N2 and serve as an inverted storage node QB; the drain electrode of the P1 is connected with the source electrode of the P3; the source electrode of N1 is connected with the drain electrode of N4; the source electrode of N2 and the source electrode of N4 are connected with VSS; the grid electrode of N3 is connected with a signal line WL; the drain electrode of N3 is connected with the signal line BL; the grid electrode of P3 is connected with a signal line WLA; the gate of N4 is connected to the signal line WLB.
2. The low voltage technology based 7T memory circuit of claim 1, wherein: p1 and N1 in the 7T memory circuit form one inverter, and P2 and N2 form the other inverter; the two inverters form a cross-coupled latch structure and form two storage nodes Q and QB for storing and holding data; the signal line BL is connected with the latch structure through N3 and is used as an input port for performing data writing operation of the 7T memory circuit and an output port for performing multiplication operation; the signal line WLA is connected into the latch structure through P3, and is further used for controlling the on and off of the latch structure; the signal line WL is connected to the latch structure through N3 and is used for inputting a high level signal with a specific pulse length to characterize the weight of one operand in multiplication operation; the signal line WLB is connected to the latch structure via N4 and is used to input a high signal of a certain level magnitude to characterize the weight of another operand in the multiplication operation.
3. The low voltage technology based 7T memory circuit of claim 2, wherein: in the 7T memory circuit, the operation logic to realize the data hold state is as follows:
setting the signal line WL to a low level, setting WLA to a low level, and setting WLB to a high level; at this time, the latch structure in the 7T register circuit is in a conductive state, so that the storage nodes Q and QB can form positive feedback, thereby achieving the purpose of data retention.
4. The low voltage technology based 7T memory circuit of claim 2, wherein: in the 7T memory circuit, the operation logic for implementing data reading is as follows:
pre-charging the signal line BL to a high level; then, the WL is set to a high level, WLA is set to a low level, and WLB is set to a high level; at this time, the bit line voltage of the BL varies according to the data stored in the storage node Q as follows:
(1) When Q is high, i.e., the stored data is 1; BL is the same as Q potential, the gate voltage of N1 is 0, N1 is in an off state; BL cannot form a path from N3, N1, N4 to power ground VSS, BL remains high; i.e. the read data is 1;
(2) When Q is low, i.e., the stored data is 0; the grid voltage of N1 is high level, BL discharges power ground VSS through N3, N1 and N4, so that BL is converted from high level to low level; i.e. the read data is 0.
5. The low voltage technology based 7T memory circuit of claim 2, wherein: in the 7T memory circuit, the operation logic for implementing data writing is as follows:
first, the signal line BL is set to a high level or a low level according to whether data to be written is "1" or "0"; then, the signal line WL is set to high level, WLA is set to high level, and WLB is set to high level; at this time, the latch structure in the 7T memory circuit is interrupted and data starts to be written; after the data writing to the storage node is completed, WLA and WL are set to low level, so that the 7T storage circuit is restored to the data holding state.
6. The low voltage technology based 7T memory circuit of claim 2, wherein: in the 7T memory circuit, the operation logic for implementing the multiplication operation is as follows:
generating a signal with a specific pulse width according to the first operand and inputting the signal to the signal line WL; wherein the high-low state of WL represents the reference value "1" or "0" of the first operand, and the pulse width T of WL WL The weight corresponding to the reference value representing the first operand is: the first operand is (T WL ·WL)；
Writing a reference value of '1' or '0' of a second operand in advance in a QB storage node in the 7T storage circuit; and generates a signal having a specific level amplitude to be inputted to the signal line WLB, using the level amplitude V of WLB WLB And representing the weight corresponding to the second operand, namely: the second operand is (V WLB ·QB)；
The level state of the signal line BL is sampled according to the current voltage V of the signal line BL BL The voltage drop is calculated, and the product operation result P is quantized according to the amplitude of the voltage drop of the bit line of BL:
Figure FDA0004115197600000021
in the above equation, Δv represents the voltage drop of the corresponding BL when the result is unit 1 in the current multiplication operation.
7. The low voltage technology based 7T memory circuit of claim 6, wherein: the multiplication operation supported by the 7T storage circuit comprises three types of single-bit number multiplied by single-bit number, single-bit number multiplied by multi-bit number and multi-bit number multiplied by multi-bit number; wherein, according to WLB level amplitude V WLB And pulse width T of WL WL The different dividing numbers of the gear can realize multiplication among different bit numbers; when any operand is a single-bit number, only the weight T of the corresponding operand is needed WL Or V WLB The value is set to 1.
8. A multiply-accumulate operation circuit, characterized by: a 7T memory circuit according to any one of claims 1 to 7 is used as a basic unit for performing multiplication operations, and the results of the respective multiplication operations are accumulated by a shared bit line technique; the multiply-accumulate operation circuit includes:
An arithmetic array comprising at least 1 column of computation columns, the computation columns being arranged in columns by N7T memory circuits according to any one of claims 1 to 7;
a bit line group including at least 1 bit line BL, all 7T memory circuits in the computation column being connected to the same bit line;
a word line group including three types of word lines WL, WLA, and WLB, the number of each type of word line being N; each 7T memory circuit of the same row in the operation array is connected to the same group of word lines WL, WLA and WLB;
a first input unit for generating electric signals each having a specific level and pulse width from a first operand in a multiply-accumulate operation, and inputting the electric signals into each 7T memory circuit through word lines WL of each row;
a first input unit for generating electric signals each having a specific level amplitude from a second operand in the multiply-accumulate operation, and inputting into each 7T memory circuit through word lines WLB of each row; and
and the output unit is connected to the bit line BL and is used for quantizing according to the voltage drop of the bit line BL of the operation stage and outputting a corresponding multiply-accumulate operation result.
9. The multiply-accumulate circuit of claim 8, wherein the multiply-accumulate operation is performed as follows:
(1) A pre-charging stage:
writing a corresponding reference value of 1 or 0 in a storage node QB of each row of the operation array according to each second operand of the multiplication operation; then, the signal line BL is precharged to a high level, and the latch structure is adjusted to a data holding state;
(2) An input stage:
setting WLA of each row of the operation array to be high level; then, a signal with a specific pulse width is generated according to the first operand of each rowAnd input to the signal line WL; wherein the high-low state of WL represents the reference value "1" or "0" of the first operand, and the pulse width T of WL WL The weight corresponding to the reference value representing the first operand is: the first operand is (T WL ·WL)；
Meanwhile, a signal with a specific level amplitude is generated according to the second operand of each row and is input to the signal line WLB; wherein the data pre-stored in the storage node QB characterizes a reference value of the second operand, the level amplitude V of WLB WLB And representing the weight corresponding to the reference value of the second operand, namely: the second operand is (V WLB ·QB)；
(3) Product output stage:
the level state of the signal line BL is sampled according to the current voltage V of the signal line BL BL The voltage drop is calculated, and the product operation result MAC is quantized according to the amplitude of the voltage drop of the bit line of BL:
Figure FDA0004115197600000031
In the above equation, Δv represents the voltage drop of the corresponding BL when the result is unit 1 in the current multiply-accumulate operation.
10. The CIM chip based on the 7T memory circuit is characterized by being packaged by a core circuit with a data storage function and a multiply-accumulate operation function and an integrated circuit of other peripheral functional modules; the functional module in the CIM chip based on the 7T memory circuit comprises:
a memory array formed by arranging n×m 7T memory circuits according to any one of claims 1 to 7 in an array of N rows and M columns;
a word line group including three types of word lines WL, WLA, and WLB, the number of each type of word line being N; each 7T memory circuit of the same row in the memory array is connected to the same group of word lines WL, WLA and WLB;
a bit line group including M bit lines BL; all 7T memory circuits in the same column in the memory array are connected to the same bit line BL;
a word line driver for controlling the turn-on of each of the word lines WL, WLA, and WLB;
a decoder connected to the word line driver, the decoder being configured to decode an address signal and then transfer the decoded address signal to the word line driver;
a pulse width modulation circuit for generating an electric signal having a specific level and pulse width from a first operand in a multiplication or multiply-accumulate operation stage, and inputting the electric signal into a corresponding 7T memory circuit through word lines WL of each row;
A pulse amplitude modulation circuit for generating an electric signal having a specific level amplitude from a second operand in the multiplication operation or the multiply-accumulate operation, and inputting the electric signal into a corresponding 7T storage circuit through word lines WLB of each row;
the precharge circuit is used for performing precharge operation on the bit line BL in a data read-write stage or an operation stage;
a timing control module for generating respective clock signals required in performing a data storage task or in performing a multiplication operation and a multiply-accumulate operation;
the mode switching circuit is used for switching the working mode of the CIM chip, wherein the working mode of the CIM chip comprises a data storage mode and a logic operation mode; and
a quantization output circuit connected to the bit line BL; the quantization output circuit comprises a data reading part and an operation output part; the data reading part is used for outputting the storage data of each storage node according to the level state of the bit line BL; the operation output part is used for monitoring the voltage of the bit line BL and outputting the voltage drop of the bit line BL as a multiplication operation result or an operation result of multiplication accumulation operation through analog-to-digital conversion.
CN202310216702.2A 2023-03-03 2023-03-03 7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology Pending CN116204490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310216702.2A CN116204490A (en) 2023-03-03 2023-03-03 7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310216702.2A CN116204490A (en) 2023-03-03 2023-03-03 7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology

Publications (1)

Publication Number Publication Date
CN116204490A true CN116204490A (en) 2023-06-02

Family

ID=86517094

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310216702.2A Pending CN116204490A (en) 2023-03-03 2023-03-03 7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology

Country Status (1)

Country Link
CN (1) CN116204490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116931873A (en) * 2023-09-11 2023-10-24 安徽大学 Two-byte multiplication circuit, and multiplication circuit and chip with arbitrary bit width of 2-power

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116931873A (en) * 2023-09-11 2023-10-24 安徽大学 Two-byte multiplication circuit, and multiplication circuit and chip with arbitrary bit width of 2-power
CN116931873B (en) * 2023-09-11 2023-11-28 安徽大学 Two-byte multiplication circuit, and multiplication circuit and chip with arbitrary bit width of 2-power

Similar Documents

Publication Publication Date Title
US11568223B2 (en) Neural network circuit
CN110414677B (en) Memory computing circuit suitable for full-connection binarization neural network
CN111816231B (en) Memory computing device with double-6T SRAM structure
CN112558919B (en) Memory computing bit unit and memory computing device
US8379436B2 (en) Semiconductor memory device
CN112036562B (en) Bit cell applied to memory computation and memory computation array device
Chen et al. Analysis and optimization strategies toward reliable and high-speed 6T compute SRAM
CN110942792A (en) Low-power-consumption low-leakage SRAM (static random Access memory) applied to storage and calculation integrated chip
CN113257306B (en) Storage and calculation integrated array and accelerating device based on static random access memory
CN110176264B (en) High-low bit merging circuit structure based on internal memory calculation
CN113467751B (en) Analog domain memory internal computing array structure based on magnetic random access memory
CN116206650B (en) 8T-SRAM unit and operation circuit and chip based on 8T-SRAM unit
CN115244621A (en) Time-sharing in-memory computational bit cell
CN115588446A (en) Memory operation circuit, memory calculation circuit and chip thereof
CN116204490A (en) 7T memory circuit and multiply-accumulate operation circuit based on low-voltage technology
CN116364137A (en) Same-side double-bit-line 8T unit, logic operation circuit and CIM chip
CN112233712B (en) 6T SRAM (static random Access memory) storage device, storage system and storage method
Kumar et al. Stability and performance analysis of low power 6T SRAM cell and memristor based SRAM cell using 45NM CMOS technology
Rajput et al. Energy efficient 9T SRAM with R/W margin enhanced for beyond Von-Neumann computation
CN116126779A (en) 9T memory operation circuit, multiply-accumulate operation circuit, memory operation circuit and chip
CN111158635A (en) FeFET-based nonvolatile low-power-consumption multiplier and operation method thereof
CN115035931A (en) Circuit structure, chip and module based on 8T-SRAM unit
Bharti et al. Compute-in-memory using 6T SRAM for a wide variety of workloads
Kumar et al. Design and power analysis of 16× 16 SRAM Array Employing 7T I-LSVL
Monga et al. A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination