CN116931873A - Two-byte multiplication circuit, and multiplication circuit and chip with arbitrary bit width of 2-power - Google Patents
Two-byte multiplication circuit, and multiplication circuit and chip with arbitrary bit width of 2-power Download PDFInfo
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Abstract
The invention relates to a two-byte multiplication circuit, and a multiplication circuit and a chip with arbitrary bit width of 2 powers. The two-byte multiplication circuit includes four AND gate circuits and two half adder circuits. Each half-adder circuit includes three PMOS transistors and three NMOS transistors. The half adder circuit structure can achieve full swing output with only six transistors. Under the combination of four gate circuit modules and two half adder circuit modules, the design of a 2bit multiplier circuit is completed, meanwhile, the two-byte multiplication circuit can carry out the combination design of different circuits according to the requirements of multiplication operations with different bit widths, and the adder and the shifter are configured to ensure that the arithmetic unit carries out multiplication with arbitrary bit widths being the power of 2, so that a large-size multiplier of high-order operation can be avoided, flexible adjustment of the data bit widths can be realized, further more complex data operation can be realized, the chip operation power consumption is reduced, and the operation efficiency is greatly improved.
Description
Technical Field
The invention relates to a multiplication circuit in the field of integrated circuit design, in particular to a two-byte multiplication circuit, a multiplication circuit with arbitrary bit width of 2 powers formed by expanding the two-byte multiplication circuit, and a two-byte multiplication circuit chip formed by packaging the two-byte multiplication circuit.
Background
Multiply-accumulate (Multiply and Accumulate, MAC) is used as key hardware logic in hardware accelerators handling artificial neural networks, and accelerators of various new and old architectures are used on a large scale. Some typical convolutional neural network calculations (Convolutional Neural Network, CNN) typically require billions of MAC operations to test a single image classification. Therefore, the design of the multiply-accumulate circuit for performing edge computation must take into account the large-scale data throughput and the data parallel processing performance, so as to bear the requirement of the modern neural network on the large-scale data, and meanwhile, the problem of the area of the multiplier needs to be considered, so that the area ratio of the computing power of the whole in-memory computing core is at a lower level due to the fact that too much area is occupied.
Disclosure of Invention
Based on the above, in order to solve the technical problems that the existing multiplier can not take the excessive occupation of the area into account while improving the data throughput and the data parallel processing performance, the invention provides a two-byte multiplication circuit, a multiplication circuit with arbitrary bit width of 2 powers formed by expanding the two-byte multiplication circuit and a two-byte multiplication circuit chip formed by packaging the two-byte multiplication circuit.
The invention aims at realizing the following technical scheme: a two-byte multiplication circuit receives four input signals X [1], X [0], Y [1], Y [0] and outputs a binary output signal with MSB, LSB [2], LSB [1], LSB [0] from high order to low order; the two-byte multiplication circuit comprises four AND gates M0-M3 and two half adder circuits W0 and W1; each half adder circuit comprises three PMOS transistors P4-P6 and three NMOS transistors N4-N6; the grid electrode of P4, the drain electrode of P5, the drain electrode of N6, the drain electrode of P6 and the source electrode of N5 are all electrically connected and form a node C; the source electrode of P4, the grid electrode of P5, the source electrode of N4 and the grid electrode of N5 are all electrically connected and form a node D; the drain electrode of P4, the source electrode of N5, the drain electrode of N4 and the source electrode of N6 are all electrically connected and form a node SUM; the grid of N4 and the grid of N6 respectively receive a pair of opposite control signals CN and DN; the drain electrode of N5 is electrically connected with the drain electrode of P6 and forms a node CARRY; the grid electrode of P6 receives a control signal DN;
the four input signals are combined pairwise to form four groups of level input signal groups which are respectively used as four pairs of input signals M0-M3; the output of M0 is LSB 0; node C, D of W0 is electrically connected to the outputs of M1, M2, respectively, node SUM of W0 being LSB 1; node C, D of W [1] is electrically connected to the output of M [3] and to node CARRY of W [0], respectively, and SUM and CARRY of W [1] are LSB [2] and MSB, respectively.
As a further improvement of the above scheme, when four input signals X1, X0, Y1, Y0 constitute two binary input signals X1X 0, Y1Y 0 of two bytes, a pair of input signals with the lowest bits X0, Y0 being M0, a pair of input signals with the highest bits X1, Y1 being M3, a pair of input signals with X0, Y1 being M1, a pair of input signals with X1, Y0 being M2.
As a further improvement of the scheme, each AND gate circuit comprises three PMOS transistors P1-P3 and three NMOS transistors N1-N3; the grid electrode of P1 and the grid electrode of N1 are electrically connected and form a node A, and the drain electrode of P1, the drain electrode of P2 and the drain electrode of P3 are electrically connected with a power supply VDD; the source electrode of P1, the source electrode of P2, the drain electrode of N1, the grid electrode of N2 and the grid electrode of P3 are all electrically connected; the grid electrode of P2 and the grid electrode of N3 are electrically connected and form a node B; the source electrode of N1 is electrically connected with the drain electrode of N3, and the source electrodes of N3 and N2 are both electrically connected with a power supply VSS; the source electrode of P3 AND the drain electrode of N2 are electrically connected AND form a node AND; two nodes A, B serve as each set of inputs to the respective AND circuit, AND a node AND serves as the output of the respective AND circuit.
As a further improvement of the above scheme, the function of the half adder is completed in the state that the node C, D is opposite to the control signals CN, DN, respectively:
When the level received by the node C is opposite to the level provided by the control signal CN, and the level received by the node D is opposite to the level provided by the control signal DN, the arithmetic function performed in the circuit of each half adder is SUM =，CARRY = C·D。
The invention also provides a multiplication circuit with arbitrary bit width of 2 powers, which is combined and designed by utilizing the arbitrary two-byte multiplication circuit according to different bit widths of multiplication operation, and realizes multiplication with arbitrary bit width of 2 powers by configuring an adder and a shifter.
As a further improvement of the above scheme, the multiplication circuit is a 4bit×2bit multiplication circuit, including two of the above two-byte multiplication circuits, a shifter, and an adder;
wherein the 4bit x 2bit multiplication circuit receives six input signals A3, A2, A1, A0, B1, B0 and outputs a binary number output signal from high to low as Q5, Q4, Q3, Q2, Q1, Q0; the four input signals A3, A2, B1, B0 constitute the binary number of two bytes as the input signals X1X 0, Y1Y 0 of the two-byte multiplication circuit of the high order, the input signals A1, A0, B1, B0 constitute the binary number of two bytes as the input signals X1X 0, Y1Y 0, the output results MSB, LSB 2, LSB 1, LSB 0 of the two-byte multiplication circuit of the high order are the input signals I3, I2, I1, I0 of the shifter, the output results O5, O4, O3, O2, O1, O0 are the input signals of the adder, the output results of the two-byte multiplication circuit of the low order are the input signals C3, C2, C1, C0 of the adder, thereby obtaining the output signals Q5, Q4, Q2 bit Q2, Q4 bit Q2.
The invention also provides a two-byte multiplication circuit chip which is formed by packaging the two-byte multiplication circuit, wherein the two-byte multiplication circuit chip is provided with at least the following pins:
receiving four input signals X1, X0, Y1, Y0 from pin one to pin four respectively;
outputting a pin five to a pin eight of MSB, LSB [2], LSB [1] and LSB [0] respectively;
pin nine and pin ten, which receive a pair of opposite control signals CN, DN, respectively.
As a further improvement of the above scheme, the function of the half adder is completed in the state that the node C, D is opposite to the control signals CN, DN, respectively:
when the level received by the node C is opposite to the level provided by the control signal CN, and the level received by the node D is opposite to the level provided by the control signal DN, the arithmetic function performed in the circuit of each half adder is SUM =，CARRY = C·D。
As a further improvement of the scheme, each AND gate circuit comprises three PMOS transistors P1-P3 and three NMOS transistors N1-N3; the grid electrode of P1 and the grid electrode of N1 are electrically connected and form a node A, and the drain electrode of P1, the drain electrode of P2 and the drain electrode of P3 are electrically connected with a power supply VDD; the source electrode of P1, the source electrode of P2, the drain electrode of N1, the grid electrode of N2 and the grid electrode of P3 are all electrically connected; the grid electrode of P2 and the grid electrode of N3 are electrically connected and form a node B; the source electrode of N1 is electrically connected with the drain electrode of N3, and the source electrodes of N3 and N2 are both electrically connected with a power supply VSS; the source electrode of P3 AND the drain electrode of N2 are electrically connected AND form a node AND; two nodes A, B serve as each set of inputs to the respective AND circuit, AND a node AND serves as the output of the respective AND circuit.
Further, the two-byte multiplication circuit chip is provided with at least the following pins:
pin eleven and pin twelve respectively receive power supply VDD and power supply VSS.
Compared with the prior art, the two-byte multiplication circuit is a reformed half adder circuit, can realize full swing, and only uses a half adder with 6 transistors, and has certain transistor number advantages compared with the traditional 16T half adder, and has better area performance. In addition, the two-byte multiplication circuit has expandability, and the arithmetic unit (namely the expanded multiplication circuit) can carry out multiplication with arbitrary bit width being the power of 2 by configuring the adder and the shifter, so that flexible adjustment of the data bit width is realized.
Drawings
Fig. 1 is a block diagram of a two-byte multiplication circuit according to embodiment 1 of the present invention.
Fig. 2 is a block diagram of an and circuit in the two-byte multiplication circuit of fig. 1.
Fig. 3 is a block diagram of a half adder circuit in the two-byte multiplication circuit of fig. 1.
Fig. 4 is a waveform diagram illustrating the operation of the and circuit in fig. 2.
Fig. 5 is a waveform diagram illustrating the operation of the half adder circuit of fig. 3.
FIG. 6 is a waveform diagram illustrating operation of the two-byte multiplication circuit of FIG. 1 during a 2-bit multiplication operation.
FIG. 7 shows the calculated delays of the half adder of the present invention at different voltages and temperatures for the two-byte multiplication circuit of FIG. 1 in a 55nm CMOS process.
Fig. 8 is a circuit configuration diagram of a 4bit×2bit multiplication circuit extended by the two-byte multiplication circuit in fig. 1 provided in embodiment 2 of the present invention.
Fig. 9 is a schematic diagram of a multiplication process of the 4bit×2bit multiplication circuit in fig. 8.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
Please refer to fig. 1, which is a block diagram of a two-byte multiplication circuit according to embodiment 1 of the present invention. The 2bit multiplier circuit based on logic unit is used for realizing multiplication operation of two-bit data, and the circuit structure comprises four AND gates M0-M3 and two half adder circuits W0 and W1.
Each AND gate unit circuit is used for performing AND operation between different data in the 2bit multiplication operation process, so as to realize multi-bit data operation. As long as the and-gate circuit can complete the multiplication function of 2bit data in the circuit operation process, each and-gate circuit can include six transistors, and referring to fig. 2, in this embodiment, each and-gate circuit includes three PMOS transistors P1 to P3 and three NMOS transistors N1 to N3. The gates of P1 and N1 are electrically connected to form a node A, and the drains of P1, P2 and P3 are electrically connected to a power supply VDD. The source of P1, the source of P2, the drain of N1, the gate of N2, and the gate of P3 are all electrically connected. The gate of P2, the gate of N3 are electrically connected and form node B. The source electrode of N1 is electrically connected with the drain electrode of N3, and the source electrodes of N3 and N2 are both electrically connected with the power supply VSS. The source of P3, the drain of N2 are electrically connected AND form node AND. Two input nodes A, B serve as each set of inputs to the respective AND circuit, AND node AND serves as the output of the respective AND circuit.
In other words, each AND gate circuit structure includes:
the drains of the PMOS transistors P1 and P1 are electrically connected with VDD, the source of the P1 is electrically connected with the drain of the N1, the grid of the P1 is electrically connected with the grid of the N1, and a node A is arranged;
the drains of the PMOS transistors P2 and P2 are electrically connected with VDD, the source of P2 is electrically connected with the drain of N1, the grid of P2 is electrically connected with the grid of N3, and a node B is arranged;
the drains of the PMOS transistors P3 AND P3 are electrically connected with VDD, the source of P3 is electrically connected with the drain of N2, AND a node AND is arranged, AND the grid of P3 is electrically connected with the grid of N2 AND is arranged as a node NAND;
the drains of the NMOS transistors N1 and N1 are electrically connected with the source electrode of the P2, the source electrode of the N1 is electrically connected with the drain electrode of the N3, and the grid electrode of the N1 is electrically connected with the grid electrode of the P1;
the drains of the NMOS transistors N2 and N2 are electrically connected with the source electrode of the P3, the source electrode of the N2 is electrically connected with VSS, and the grid electrode of the N2 is electrically connected with the grid electrode of the P3;
the drains of the NMOS transistors N3, N3 are electrically connected with the source of N1, and the source of N3 is electrically connected with
The gates of VSS and N3 are electrically connected to the gate of P2.
Wherein, P1, P2, N1, N3 form a NAND gate, the output is NAND, connected with an inverter formed by the transistors P3, N2, the output is the result of A, B signal and logic.
Referring to fig. 3, each half adder unit circuit is used for performing addition operation on parity data, so as to obtain an operation result of four bits of data. The half adder unit circuit of the present invention includes six transistors, i.e., three PMOS transistors P4 to P6 and three NMOS transistors N4 to N6. The gate of P4, the drain of P5, the drain of N6, the drain of P6, the source of N5 are all electrically connected and form node C. The source of P4, the gate of P5, the source of N4, and the gate of N5 are all electrically connected and form node D. The drain of P4, the source of N5, the drain of N4, and the source of N6 are all electrically connected and form a node SUM. The gates of N4 and N6 receive a pair of opposite control signals CN and DN, respectively. The drain of N5 is electrically connected to the drain of P6 and forms node CARRY. The gate of P6 receives the control signal DN.
In other words, the sources of the PMOS transistors P4 and P4 are electrically connected to the source of the N4, the gate of the PMOS transistor P4 is electrically connected to the drain of the P5, the drain of the PMOS transistor P4 is electrically connected to the source of the P5, and the drain of the PMOS transistor P4 is set as the node SUM.
The sources of the PMOS transistors P5 and P5 are electrically connected to the drain of P4, the drains of the access nodes SUM and P5 are electrically connected to the drains of N6 and P6, and the gates of the access nodes C and P5 are electrically connected to the source of P4 and the access node D.
The sources of the PMOS transistors P6, P6 are electrically connected to the drain of the N5, and are set as nodes carrier, the drains of the P6 are electrically connected to the drains of the P5, N6, the gates of the access nodes C, P6 are electrically connected to the gate of the N6, and the node DN is set.
The source of the NMOS transistors N4, N4 is electrically connected to the source of the P4, the drain of the N4 is electrically connected to the source of the N6, and the gate of the access node SUM, N4 is connected to the gate of the node CN.
The source of the NMOS transistors N5, N5 is electrically connected to the drain of P6, the drain of N5 is electrically connected to the source of P6, the gate of the access node CARRY, N5 is electrically connected to the sources of P4, N4, and the access node D.
The source electrodes of the NMOS transistors N6, N6 are electrically connected to the drain electrode of N4, the drain electrodes of the access nodes SUM, N6 are electrically connected to the drain electrodes of P5, P6, the gate electrodes of the access nodes C, N6 are electrically connected to the gate electrode of P6, and the access node DN.
The half adder unit circuit only has 6 transistors, has the effect of achieving full swing, can effectively reduce the number of transistors of the multiplier in the calculation unit, simplifies the circuit structure of the calculation unit, and can complete the addition function of unit bit data in the working process. SUM is the output result signal, and CARRAY is the carry signal.
The two-byte multiplication circuit receives four input signals X [1], X [0], Y [1], Y [0] and outputs a binary number output signal with MSB, LSB [2], LSB [1], LSB [0] from high order to low order. In general, four input signals X1, X0, Y1, Y0 are formed into two binary input signals X1X 0, Y1Y 0, a pair of input signals with the lowest bits X0, Y0 being M0, a pair of input signals with the highest bits X1, Y1 being M3, a pair of input signals with X0, Y1 being M1, and a pair of input signals with X1, Y0 being M2.
In other words, the input signals A [0] and B [0] of the AND logic unit M [0] are respectively and electrically connected with X [0] and Y [0], and the output signal Z [0] is electrically connected with LSB [0]; the input signals A1 and B1 of the logic AND unit M1 are respectively and electrically connected with X0 and Y1, and the output signal Z1 is electrically connected with C0; the input signals A2 and B2 of the logic AND unit M2 are respectively and electrically connected with X1 and Y0, and the output signal Z2 is electrically connected with D0; the input signals A3 and B3 of the logic AND unit M3 are respectively and electrically connected with X1 and Y1, and the output signal Z3 is electrically connected with D1; the input signal C0 of the half adder unit W [0] is electrically connected with Z [1], the input signal D [0] is electrically connected with Z [2], the output signal SUM [0] is electrically connected with LSB [1], and the output signal CARRY [0] is electrically connected with C [1]; the input signal C1 of the half adder unit W1 is electrically connected with the CARRY 0, the input signal D1 is electrically connected with the Z3, the output signal SUM 1 is electrically connected with the LSB 2, and the output signal CARRY 1 is electrically connected with the MSB; in the multiplication unit circuit structure, input signals are X [0], X [1], Y [0], Y [1], and output signals are LSB [0], LSB [1], LSB [2], and MSB, respectively.
The function of the half adder is completed in the state that the node C, D is opposite to the control signals CN, DN, respectively: when the level received by the node C is opposite to the level provided by the control signal CN, and the level received by the node D is opposite to the level provided by the control signal DN, the arithmetic function performed in the circuit of each half adder is SUM = ，CARRY = C·D。
In summary, the input end of the 2bit multiplication unit circuit of the present invention is composed of two 2bit binary numbers X1X 0 and Y1Y 0, and the output signals are respectively from high order to low order: MSB, LSB [2], LSB [1], LSB [0]. The least significant bits X0 and Y0 of the two 2bit data are used as the input ends of the two input AND gates M0, the result after the operation is marked as LSB 0, the least significant bit of one input and the most significant bit X0, Y1 and Y0 and X1 are respectively used as the input ends of the two input AND gates M1 and M2, the result after the operation is marked as Z1 and Z2, the most significant bit X1 and Y1 of the two 2bit data are respectively used as the input ends of the two input AND gates M3, the result after the operation is marked as Z3, the output results Z1 and Z2 are used as the input ends of the half adder W0, so as to obtain the output results SUM 0 and CARRY 0, the output result Z3 of the half adder W1, so as to obtain the output signals SUM 1 and CARRY 1, the output signals SULSB 1 and the output signals SURRY 1 and SURRY 1 are electrically connected. Thus, the output of the 2bit multiplication operation consists of 4bit binary numbers: MSB, LSB [2], LSB [1], LSB [0].
Referring to fig. 4, fig. 4 is a waveform diagram illustrating the operation of the and circuit in fig. 2. As shown in fig. 4, when a=1, b=1 is input, AND operation result and=1, AND NAND operation result nand=0; when a=0, b=1 is input, AND operation result and=0, AND NAND operation result nand=1; when a=1, b=0 is input, AND operation result and=0, AND NAND operation result nand=1; when a=0, b=0 is input, AND operation result and=0, AND NAND operation result nand=1; the AND gate truth table is shown in Table 1.
Table 1 NAND gate truth table
Referring to fig. 5, fig. 5 is a waveform diagram illustrating the operation of the half adder circuit of fig. 3. As shown in fig. 5, when the inputs a=1, b=1, the half adder outputs the sum=0, and carry=1; when the inputs a=0, b=1, the half adder outputs the SUM sum=1, CARRY carry=0; when the inputs a=1, b=0, the half adder outputs the sum=1, CARRY = 0; when the inputs a=0, b=0, the half adder outputs the SUM sum=0, CARRY carry=0; the half-adder circuit truth table is shown in table 2.
Table 2 half adder circuit truth table
Referring to fig. 6, fig. 2 is a waveform diagram of the operation of a 2bit multiplication operation. The multiplication of 2 bits of 2-ary 2-bit data can obtain 7 different results, and because of the interchangeability of the multiplication, when the input X1X 0 and Y1Y 0 are interchanged, the obtained results are identical, and are not listed here, but only the typical input cases of 7 results are listed here.
When inputting X1]=1，X[0]=1，Y[1]=1，Y[0]=1, i.e. the input is a decimal number (3) 10 、(3) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=1, LSB [2 ]]=0，LSB[1]=0，LSB[0]=1, i.e. decimal number (9) 10 。
When inputting X1]=1，X[0]=0，Y[1]=1，Y[0]=1, i.e. the input is a decimal number (2) 10 、(3) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=0, LSB [2 ]]=1，LSB[1]=1，LSB[0]=0, i.e. decimal number (6) 10 。
When inputting X1 ]=0，X[0]=1，Y[1]=1，Y[0]=1, i.e. the input is a decimal number (1) 10 、(3) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=0, LSB [2 ]]=0，LSB[1]=1，LSB[0]=1, i.e. decimal number (3) 10。
When inputting X1]=0，X[0]=0，Y[1]=1，Y[0]=1, i.e. the input is a decimal number (0) 10 、(3) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=0, LSB [2 ]]=0，LSB[1]=0，LSB[0]=0, i.e. decimal number (0) 10 。
When inputting X1]=1，X[0]=0，Y[1]=1，Y[0]=0, i.e. the input is a decimal number (2) 10 、(2) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=0, LSB [2 ]]=1，LSB[1]=0，LSB[0]=0, i.e. decimal number (4) 10 。
When inputting X1]=0，X[0]=1，Y[1]=1，Y[0]=0, i.e. the input is a decimal number (1) 10 、(2) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=0, LSB [2 ]]=0，LSB[1]=1，LSB[0]=0, i.e. decimal number (2) 10 。
When inputting X1]=0，X[0]=1，Y[1]=0，Y[0]=1, i.e. the input is a decimal number (1) 10 、(1) 10 And when the 2bit multiplication operation result is from high to low, the steps are as follows: MSB=0, LSB [2 ]]=0，LSB[1]=0，LSB[0]=1, i.e. decimal number (1) 10 . The truth table for the 2bit multiplication circuit is shown in table 3.
Table 3 2b it multiplication circuit truth table
Referring to fig. 7, fig. 7 shows calculated delays of the half adder of the present invention at different voltages and temperatures for a 55nm CMOS process. The foregoing details the design of a half adder circuit of transistor number 6 in the present invention. Thanks to the design thought with the transmission gate structure, the half adder does not have the problems of threshold loss and voltage rising delay caused by a common or calculation unit. As can be seen from fig. 8, the delay to get the value of the sum of two numbers is greater than the value of the carry generated by two numbers. As can be seen from the circuit structure analysis, the generation of the CARRY (CARRY) is required to generate AN a·b signal, and the generation of the SUM of relative ratios (SUM) signal is required to generate AN exclusive or signal, i.e., AN a·bn+an·b signal. As can be seen from the analysis in fig. 7, at the same voltage, the calculation delay gradually increases with the temperature. Taking a supply voltage of 1.2V as an example, the temperature rises from 20 ℃ to 100 ℃ (temperature increase of 400%), and the summation delay rises from 50.97ps to 57.75ps, at which point the delay increases by 13.30%. At the same temperature, the calculation delay gradually increases as the voltage decreases. Taking the example of 27 ℃ at room temperature, the voltage is reduced from 1.2V to 0.9V (voltage drop of 25%), and the carry delay is gradually increased from 35.63ps to 58.78ps, at which point the delay is increased by 64.91%. The calculated delay of summation is almost 1.4 times of the stable carry delay under the same temperature and same voltage. From the above calculations, it can be deduced that (1) temperature has less effect on the stability of the inventive half adder with respect to voltage; (2) The voltage robustness of the half adder is higher, and under the condition that the external voltage and the temperature conditions are kept consistent, the two signal output delays can be kept to keep certain stability; (3) The half adder has a larger limitation, and the design borrows signals in the AND gate, so the half adder can only be used as a summation module in a multiplier. As a result of the foregoing analysis, the condition of using a half adder is only present in a 2bit×2bit multiplier. If the minimum granularity of the multiplication bit width is more than 2 bits, the half adder cannot meet the use condition, and at least the full adder can be used for completing addition operation with carry. However, if an operational full adder with carry is considered, the design concept of borrowing this half adder is not much different from that of a conventional full adder. If the minimum granularity of the multiplication bit width is less than 2 bits, a half adder is not needed at all, and the 1 bit multiplication operation can directly use the exclusive nor operation or the dot multiplication operation. Although the half adder has the advantages of a certain number of transistors, a certain performance intensity in operation speed and a certain robustness under the conditions of different voltages and temperatures, the half adder has a large limitation in consideration of use scenes.
The circuit structure provided in this embodiment has 2 operation modes, which are a half adder function and a two-bit 2bit data multiplication function, respectively.
1. Half adder function:
according to the half adder circuit structure, the signal C, D is respectively matched with the signals CN and DNAnd the function of the half adder is completed in the reverse state. When the input signal C is opposite to the signal CN and the input signal D is opposite to the signal DN, the operation function performed in the circuit of the half adder is SUM =，CARRY = C·D。
When the input signals are all low, i.e. "c= '0', d= '0', cn= '1', dn= '1'", the transistors P4, P5, N4, N6 are on and the transistors N5, P6 are off, while sum= "0", carrier= "0". Namely, the half adder circuit function is completed: sum=，CARRY = C·D。
When the input signal C is at low level and the input signal D is at high level, i.e. "c= '0', d= '1', cn= '1', dn= '0'", the transistors P4, P6, N4, N5 are turned on and the transistors P5, N6 are turned off, at which time sum= "1", carrier= "0". Namely, the half adder circuit function is completed: sum=，CARRY = C·D。
When the input signal C is at a high level and the input signal D is at a low level, i.e. "c= '1', d= '0', cn= '0', dn= '1'", the transistors P5, N6 are turned on and the transistors P4, P6, N4, N5 are turned off, at which time sum= "1", carrier= "0". Namely, the half adder circuit function is completed: sum= ，CARRY = C·D。
When the input signals are all at high level, i.e. "c= '1', d= '1', cn= '0', dn= '0'", the transistors P6, N5 are on, the transistors P4, P5, N4, N6 are off, and the sum= "0", carrier= "1". Namely, the half adder circuit function is completed: sum=，CARRY = C·D。
2. Two-bit 2bit data multiplication function:
according to the 2bit multiplication unit circuit, the input end of the multiplication unit circuit is composed of two 2bit binary numbers X1X 0 and Y1Y 0, and the output signals are respectively from high order to low order: MSB, LSB [2], LSB [1], LSB [0]; the least significant bits X0 and Y0 of the two 2bit data are used as the input ends of the two input AND gates M0, the result after the operation is marked as LSB 0, the least significant bit of one input and the most significant bit X0, Y1 and Y0 and X1 are respectively used as the input ends of the two input AND gates M1 and M2, the result after the operation is marked as Z1 and Z2, the most significant bit X1 and Y1 of the two 2bit data are respectively used as the input ends of the two input AND gates M3, the result after the operation is marked as Z3, the output results Z1 and Z2 are used as the input ends of the half adder W0, so as to obtain the output results SUM 0 and CARRY 0, the output result Z3 of the half adder W1, so as to obtain the output signals SUM 1 and CARRY 1, the output signals SULSB 1 and the output signals SURRY 1 and SURRY 1 are electrically connected. Thus, the output of the 2bit multiplication operation consists of 4bit binary numbers: MSB, LSB [2], LSB [1], LSB [0].
When the input signals are "X1X 0= '00', Y1Y 0= '00'", the output signals MSB, LSB 2, LSB 1, LSB 0 are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '00', Y1Y 0= '01'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '00', Y1Y 0= '10'", the output signals MSB, LSB 2, LSB 1, LSB 0 are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '00', Y1Y 0= '11'", the output signals MSB, LSB 2, LSB 1, LSB 0 are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '01', Y1Y 0= '00'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '01', Y1Y 0= '01'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0001", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '01', Y1Y 0= '10'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0010", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '01', Y1Y 0= '11'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0011", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '10', Y1Y 0= '00'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '10', Y1Y 0= '01'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0010", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '10', Y1Y 0= '10'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0100", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '10', Y1Y 0= '11'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0110", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '11', Y1Y 0= '00'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0000", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '11', Y1Y 0= '01'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0011", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '11', Y1Y 0= '10'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "0110", i.e. the 2bit multiplication function is completed.
When the input signals are "X1X 0= '11', Y1Y 0= '11'", the output signals MSB, LSB [2], LSB [1], LSB [0] are respectively: "1111", i.e. the 2bit multiplication function is completed.
Example 2
Referring to fig. 8, fig. 8 is a circuit diagram of a 4bit×2bit multiplication circuit extended by the two-byte multiplication circuit in fig. 1 according to embodiment 2 of the present invention. The circuit configuration includes two 2-bit multiplier modules (i.e., the two-byte multiplication circuit of embodiment 1), one shift register module (i.e., the shifter), and one adder-adder circuit module (i.e., the adder).
Each 2bit multiplication circuit is used for carrying out 2bit multiplication operation among different data in the 4bit multiplied by 2bit multiplication operation process, so as to realize multi-bit data operation. The shifter completes the function of shifting the high-order data multiplication result to high-order by two digits in the circuit, and the adder completes the function of adding the high-order data multiplication result and the low-order data multiplication result in the circuit, namely, the 4bit multiplied by 2bit multiplication function.
A4 bit by 2bit multiplication circuit receives six input signals A3, A2, A1, A0, B1, B0 and outputs a binary number output signal of Q5, Q4, Q3, Q2, Q1, Q0 from high to low. The output result of the high-order multiplier, LSB 2, LSB 1, LSB 0 as the input signals I3, I2, I1, I0 of the shifter, the output result of the low-order 2bit multiplier as the input signals C3, C2, C0 of the adder, Q5, Q4, Q3, Q2 bit, Q4 is the output result of the multiplier, the output result of the low-order 2bit multiplier is the input signals C3, C2, C0 of the adder.
In other words, the input signals A1A 0 and B1B 0 of the 2bit multiplier N0 are respectively and electrically connected with X1X 0 and Y1Y 0, the output signals MSB, LSB 2, LSB 1 and LSB 0 are respectively and electrically connected with the input signals C9, C8, C7 and C6 of the adder N3, the input signals A3A 2 and B1B 0 of the 2bit multiplier N1 are respectively and electrically connected with X1X 0 and Y1 MSB 0, the output signals I3, I2, LSB 1 and LSB 0 of the adder N2 are respectively and electrically connected with the output signals I5, O4, O3, O2, O1 and O0 of the shift register, and the input signals C5, C4, C3, C2, C3, C0 of the adder N3 are respectively and electrically connected with the input signals I3, I2, C1, C0 of the adder N2, the output signals O3 and the output signals Q4Q 2 of the shift register are respectively.
As shown in the calculation process of FIG. 9, when the input signals A3, A2, A1, A0, B1, B0 are 1, 0, 1 and 0, respectively, A3, A2, A1, A0 are divided into high-order data A3A 2 and low-order data A1A 0, respectively, and the high-order data result is shifted to high by two digits by a shifter and added with the ground data result to obtain the final result, namely, the output result of the 4bit×2bit multiplying circuit.
4bit x 2bit data multiplication function: according to the 4bit by 2bit multiplication circuit, the 4bit by 2bit multiplication circuit receives six input signals A3, A2, A1, A0, B1, B0 and outputs a binary output signal of Q5, Q4, Q3, Q2, Q1, Q0 from high to low.
The output result of the high-order multiplier, LSB 2, LSB 1, LSB 0 as the input signals I3, I2, I1, I0 of the shifter, the output result of the low-order 2bit multiplier as the input signals C3, C2, C0 of the adder, Q5, Q4, Q3, Q2 bit, Q4 is the output result of the multiplier, the output result of the low-order 2bit multiplier is the input signals C3, C2, C0 of the adder.
When the input signals are "A3A 2A 1A 0= '0000', B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0001', B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0010', B1B 0= '00'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0011', B1B 0= '00'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0100', B1B 0= '00'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0101', B1B 0= '00'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0110', and B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0111', and B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1000', B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1001' and B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1010', and B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1011', B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1100', B1B 0= '00'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1101', B1B 0= '00'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1110', B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1111', B1B 0= '00'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0000', B1B 0= '01'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0001', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0010', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000010", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0011', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000011", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0100', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000100", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0101', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000101", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0110', and B1B 0= '01'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000110", i.e. to complete the 4bit x 2bit multiplication function.
When the input signals are "A3A 2A 1A 0= '0111', and B1B 0= '01'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000111", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1000', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "001000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1001' and B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "001001", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0101', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000101", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '0110', and B1B 0= '01'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000110", i.e. to complete the 4bit x 2bit multiplication function.
When the input signals are "A3A 2A 1A 0= '0111', and B1B 0= '01'", the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "000111", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1000', B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are respectively: "001000", i.e. the 4bit x 2bit multiplication function is completed.
When the input signals are "A3A 2A 1A 0= '1001' and B1B 0= '01'", respectively, the output signals Q5Q 4Q 3Q 2Q 1Q 0 are: "000101", i.e. the 4bit x 2bit multiplication function is completed.
And so on, there are 64 input-output cases.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A two-byte multiplication circuit receives four input signals X [1], X [0], Y [1], Y [0] and outputs a binary output signal with MSB, LSB [2], LSB [1], LSB [0] from high order to low order; the two-byte multiplication circuit is characterized by comprising four AND gate circuits M0-M3 and two half adder circuits W0 and W1; each half adder circuit comprises three PMOS transistors P4-P6 and three NMOS transistors N4-N6; the grid electrode of P4, the drain electrode of P5, the drain electrode of N6, the drain electrode of P6 and the source electrode of N5 are all electrically connected and form a node C; the source electrode of P4, the grid electrode of P5, the source electrode of N4 and the grid electrode of N5 are all electrically connected and form a node D; the drain electrode of P4, the source electrode of N5, the drain electrode of N4 and the source electrode of N6 are all electrically connected and form a node SUM; the grid of N4 and the grid of N6 respectively receive a pair of opposite control signals CN and DN; the drain electrode of N5 is electrically connected with the drain electrode of P6 and forms a node CARRY; the grid electrode of P6 receives a control signal DN;
The four input signals are combined pairwise to form four groups of level input signal groups which are respectively used as four pairs of input signals M0-M3; the output of M0 is LSB 0; node C, D of W0 is electrically connected to the outputs of M1, M2, respectively, node SUM of W0 being LSB 1; node C, D of W [1] is electrically connected to the output of M [3] and to node CARRY of W [0], respectively, and SUM and CARRY of W [1] are LSB [2] and MSB, respectively.
2. The two-byte multiplication circuit according to claim 1, wherein when four input signals X1, X0, Y1, Y0 constitute two binary input signals X1X 0, Y1Y 0 of two bytes, a pair of input signals with the lowest bits X0, Y0 being M0, a pair of input signals with the highest bits X1, Y1 being M3, a pair of input signals with X0, Y1 being M1, and a pair of input signals with X1, Y0 being M2.
3. The two-byte multiplication circuit according to claim 1, wherein each and gate circuit includes three PMOS transistors P1 to P3 and three NMOS transistors N1 to N3; the grid electrode of P1 and the grid electrode of N1 are electrically connected and form a node A, and the drain electrode of P1, the drain electrode of P2 and the drain electrode of P3 are electrically connected with a power supply VDD; the source electrode of P1, the source electrode of P2, the drain electrode of N1, the grid electrode of N2 and the grid electrode of P3 are all electrically connected; the grid electrode of P2 and the grid electrode of N3 are electrically connected and form a node B; the source electrode of N1 is electrically connected with the drain electrode of N3, and the source electrodes of N3 and N2 are both electrically connected with a power supply VSS; the source electrode of P3 AND the drain electrode of N2 are electrically connected AND form a node AND; two nodes A, B serve as each set of inputs to the respective AND circuit, AND a node AND serves as the output of the respective AND circuit.
4. The two-byte multiplication circuit of claim 1, wherein the function of the half adder is performed in a state in which the node C, D is opposite to the control signals CN, DN, respectively:
the level received by node C is opposite to the level provided by control signal CN, nodeD receives a level opposite to the level provided by the control signal DN, the arithmetic function performed in the circuit of each half-adder is SUM =，CARRY = C·D。
5. A multiplication circuit with arbitrary bit width of 2 powers, characterized in that the two-byte multiplication circuit according to any one of claims 1 to 4 is used for combination design according to different bit widths of multiplication operation, and multiplication with arbitrary bit width of 2 powers is realized by configuring an adder and a shifter.
6. The multiplication circuit of claim 5, wherein the multiplication circuit is a 4bit x 2bit multiplication circuit, comprising two byte multiplication circuits of any one of claims 1 to 4, a shifter, and an adder;
wherein the 4bit x 2bit multiplication circuit receives six input signals A3, A2, A1, A0, B1, B0 and outputs a binary number output signal from high to low as Q5, Q4, Q3, Q2, Q1, Q0; the four input signals A3, A2, B1, B0 constitute the binary number of two bytes as the input signals X1X 0, Y1Y 0 of the two-byte multiplication circuit of the high order, the input signals A1, A0, B1, B0 constitute the binary number of two bytes as the input signals X1X 0, Y1Y 0, the output results MSB, LSB 2, LSB 1, LSB 0 of the two-byte multiplication circuit of the high order are the input signals I3, I2, I1, I0 of the shifter, the output results O5, O4, O3, O2, O1, O0 are the input signals of the adder, the output results of the two-byte multiplication circuit of the low order are the input signals C3, C2, C1, C0 of the adder, thereby obtaining the output signals Q5, Q4, Q2 bit Q2, Q4 bit Q2.
7. A two-byte multiplication circuit chip, which is formed by packaging the two-byte multiplication circuit according to claim 1, wherein the two-byte multiplication circuit chip has at least the following pins:
receiving four input signals X1, X0, Y1, Y0 from pin one to pin four respectively;
outputting a pin five to a pin eight of MSB, LSB [2], LSB [1] and LSB [0] respectively;
pin nine and pin ten, which receive a pair of opposite control signals CN, DN, respectively.
8. The two-byte multiplication circuit chip of claim 7, wherein the function of the half adder is performed in a state where the node C, D is opposite to the control signals CN, DN, respectively:
when the level received by the node C is opposite to the level provided by the control signal CN, and the level received by the node D is opposite to the level provided by the control signal DN, the arithmetic function performed in the circuit of each half adder is SUM =，CARRY = C·D。
9. The two-byte multiplication circuit chip according to claim 7, wherein each and gate circuit includes three PMOS transistors P1 to P3 and three NMOS transistors N1 to N3; the grid electrode of P1 and the grid electrode of N1 are electrically connected and form a node A, and the drain electrode of P1, the drain electrode of P2 and the drain electrode of P3 are electrically connected with a power supply VDD; the source electrode of P1, the source electrode of P2, the drain electrode of N1, the grid electrode of N2 and the grid electrode of P3 are all electrically connected; the grid electrode of P2 and the grid electrode of N3 are electrically connected and form a node B; the source electrode of N1 is electrically connected with the drain electrode of N3, and the source electrodes of N3 and N2 are both electrically connected with a power supply VSS; the source electrode of P3 AND the drain electrode of N2 are electrically connected AND form a node AND; two nodes A, B serve as each set of inputs to the respective AND circuit, AND a node AND serves as the output of the respective AND circuit.
10. The two-byte multiplication circuit chip of claim 9, further having at least the following pins:
pin eleven and pin twelve respectively receive power supply VDD and power supply VSS.
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| Publication number | Priority date | Publication date | Assignee | Title |
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