CN104300965A - Method for establishing K-value and ten-value half adder and K-value and ten-value half subtracter based on band-pass threshold loading technology and circuit obtained based on method - Google Patents

Abstract

The invention discloses a method for establishing a K-value and ten-value half adder and a K-value and ten-value half subtracter based on the band-pass threshold loading technology and a circuit obtained based on the method. According to the method for establishing the K-value and ten-value half adder and the K-value and ten-value half subtracter based on the band-pass threshold loading technology and the circuit obtained based on the method, the band-pass threshold loading technology is adopted, the demands in all stages are processed according to information, and band-pass thresholds required in different stages are loaded to a PMOS tube, so that the band-pass threshold of the PMOS tube can be changed at any time; the K-value half subtracter and the half adder are analyzed, the characteristic that a high-value area and a low-value area are unified is realized, based on the loading technology, two kinds of circuits can be replaced by one kind of circuits, the traditional method achieved based on a K-value logic gate is avoided, and the circuit structure is simplified greatly; the chaotic encryption method and the circuit can be popularized to K values from two values, K-value multiplication and division are replaced by K-value addition and subtraction, and the multiplication-and-division-free chaotic encryption method and circuit for K-value information are obtained. The method for establishing the K-value and ten-value half adder and the K-value and ten-value half subtracter based on the band-pass threshold loading technology and the circuit obtained based on the method are applied to the VLSIs such as the FPGAs, CPLDs, half-custom or full-custom ASICs and memorizers and the technical field of other digital ICs.

Description

The K value and ten of the logical threshold loading technique of band is adopted to be worth construction method and the circuit thereof of half adders and half-subtracter

(1) technical field

The invention belongs to digital integrated circuit field, specifically a kind ofly adopt the logical K value of threshold loading technique of band and the construction method of ten value half adders and half-subtracter and circuit thereof.

(2) background technology

Along with the develop rapidly of MOS integrated circuit technique, integrated scale is increasing, and integrated level is more and more higher, and some shortcomings appear in VLSI (very lagre scale integrated circuit (VLSIC)): 1. first on VLSI substrate, and wiring but takies the silicon area of 70 more than ℅; Also needed a large amount of interconnector able to programme in the programmable logic device, each logic function block or I/O have been coupled together, completed the circuit of specific function, wiring account for the very large cost of material.Reduce wiring cost and become major issue.2. from information transmission aspect, multi-valued signal is adopted to reduce session number; To every root line transmitting digital information, binary signal is the one that carry information amount is minimum, and multi-valued signal carry information amount is greater than binary signal.3. from information storage aspect, adopt multi-valued signal to improve information storage density, store information by metal-oxide-semiconductor grid capacitance, information memory capacity is many-valued larger than two-value, and many-valued DRAM can improve information storage density greatly than two-value DRAM.The development of current Multivalued devices is extensively carried out, the 16gbitNAND flash memory that Toshiba and U.S. SanDisk adopt 43nm technique and the many-valued technology of 2bit/ unit to realize.The 8Gbit product of Samsung exploitation adopts the CMOS technology of 63nm and the many-valued technology of 2bit/ unit.Succeeding in developing of 4 value memories is the important step of many-valued research with commercialization, and the development of Multivalued devices needs the switching threshold V controlling or change pipe _tn.

Prior art and existing problems:

1. realizing (K >=3) in multivalued circuit; existing semiconductor fabrication process controls metal-oxide-semiconductor threshold technology very large shortcoming: the limited extent (because ion implantation concentration is limited) 1. controlling threshold value; and in technique, control the performance that threshold amplitude often can change metal-oxide-semiconductor; the voltage-type multivalued circuit realized is not more than 4 value circuit, and more multivalued circuit application is more difficult.2. can only control the amplitude of threshold value, metal-oxide-semiconductor can not be changed and open character (as high pass, low pass, is with logical, band resistance control threshold), and multivalued circuit must have the metal-oxide-semiconductor of multiple control threshold character, and circuit structure just can be made the simplest.3. need to increase ion implantation additional process, threshold value can only be controlled in semiconductor fabrication process, increase process complexity, threshold value can not be controlled by user.

2. realizing in multivalued circuit, existing neuron mos management and control threshold technology has very large shortcoming: 1. increase with K value, ' input grid and the control gate electric capacity of single neuron mos pipe account for silicon area ' is increasing to the ratio of ' single metal-oxide-semiconductor accounts for silicon area ', ten times, hundred times or higher; 2. increase with K value, ' threshold value confusion region (break over region) the width Delta V of input grid ₁' to ' floating boom threshold value confusion region (break over region) width Delta V _fg' ratio (Δ V ₁/ Δ V _fg=C _tOT/ C ₁) increasing, because of Δ V _fgcertain, the threshold value confusion region Δ V of input grid ₁width is increasing, and input grid K value signal resolution capability is more and more reduced, and requires high to capacitance accuracy, is unfavorable for realizing the large multivalued circuit of K value reliably; 3. threshold value control characteristic (as with control threshold mode that is logical, band resistance) can not be changed, unfavorable to simplification K value circuit; 4. with the increase of K value, ratio (C _tOT/ C ₁) becoming large, input grid and control gate electric capacity increase, and high frequency performance is declined fast; 5. with the increase of K value, floating gate capacitance electric leakage can not be omitted, and there have multilevel information to refresh to be very difficult.6. neuron CMOS inverter is only 0 to binary signal quiescent dissipation, and to large K value, there is the state of NMOS tube and PMOS conducting simultaneously, quiescent dissipation is large all the better; It is capacitive load that neuron CMOS follower often exports, and its output voltage lifting track is different, has very large hysteresis voltage, is unfavorable for multivalued circuit.

3. threshold value is fixed, and can not change at any time, and this is the deficiency of existing variable threshold technology, by the needs in multilevel information process each stage, should have a pipe with each stage different characteristics of information processing with different threshold value; The present invention analyzes the consistency of the characteristic sum structure of K value half-subtracter and K value half adder, but needs PMOS to have different threshold values variable at any time, also namely needs to adopt the logical threshold loading technique of band; K value half-subtracter and K value half adder are the important devices realizing K value plus and minus calculation, and had K value half-subtracter and K value half adder, the realization of K value plus and minus calculation is just easy to.

(3) summary of the invention

The present invention seeks to openly a kind ofly to adopt the logical K value of threshold loading technique of band and the construction method of ten value half adders and half-subtracter and circuit thereof; Described object is realized by following technical scheme:

1. one kind adopts the construction method of the K value half-subtracter of the logical threshold loading technique of band: A in K value half-subtracter _ifor minuend, B _ifor subtrahend, S _ifor this is for poor, J _ifor borrow, wherein A _i, B _i, S _ibe K value signal, K value signal has K logical value: 0,1,2 ， ‥ ..., L, wherein L=K-1, K=4,5,6 ， ‥ ..., J _ibe 2 value signals, 2 value signals have 2 logical value: 0, L; Make A _i=k, B _i=j, to the j=1 ~ L determined, as k < j, S _i=K+k-j > k, i.e. S _i> A _i, as k=j, S _i=0, as k > j and j ≠ L time, S _i=k-j < k, i.e. S _i< A _i, as j=L, there is not k > j; To the j=0 determined, S _i=A _i; To j ≠ 0, as k < j, there is borrow, as k>=j, without borrow, to j=0, without borrow; The construction method of the K value half-subtracter of the logical threshold loading technique of band is adopted to be described below:

1. to the j determined, j=1 ~ L, by S _i> A _iand S _i< A _i, the computing of K value half-subtracter is divided into Spring layer and low value district, because of t _{b0 ~ j-1}=t _{/ hj}, t _{bj+1 ~ L}=t _hj+1(j ≠ L), adopts the controlled PMOS P of gating _e0and P _e1, P _e0there is low pass threshold t _{/ hj}characteristic, P _e1there is high pass threshold t _hj+1characteristic, (1) Spring layer: as k=0 ~ j-1, pipe P _e0conducting, realizes S _i> A _i; (2) low value district: as k=j+1 ~ L and j ≠ L time, pipe P _e1conducting, realizes S _i< A _i, as j=L, low value district is invalid, and only Spring layer is effective; As k=j, pipe P _e0, P _e1, P _d0all end, S _i=0; (3) use P _e2the PMOS not gate of composition exports and forms J _isignal, pipe P _e2grid adapter P _e0grid g _{/ hj}, as k < j, pipe P _e2conducting, J _ifor high level, indicate borrow, as k>=j, pipe P _e2cut-off, J _ifor low level, indicate without borrow;

(note: t _{b0 ~ j-1}represent that conducting interval is k=0 ~ j-1, t _{/ hj}represent that conducting interval is k < j, i.e. k=0 ~ j-1, so t _{b0 ~ j-1}=t _{/ hj}, and t _{bj+1 ~ L}represent that conducting interval is k=j+1 ~ L, t _hj+1represent that conducting interval is k>=j+1, i.e. k=j+1 ~ L, so t _{bj+1 ~ L}=t _hj+1; Because of low pass threshold t _{/ hj}with high pass threshold t _hj+1all belong to the logical threshold of band, namely special band leads to threshold t _{b0 ~ j-1}and t _{bj+1 ~ L}, so high general formula and low general formula variable threshold PMOS all can be described as band general formula variable threshold PMOS, then by the logical threshold feature of band, will t be met _{b0 ~ j-1}=t _{/ hj}and t _{bj+1 ~ L}=t _hj+1band lead to threshold, divide low pass threshold and high pass threshold respectively into; Note j ≠ 0 1.);

2. Spring layer circuit comprises band general formula variable threshold PMOS P _a00~ P _a0L-1with the diode D of series connection ₀₀~ D _0L-1, pipe P _a01~ P _a0L-1high pass threshold be followed successively by t _h1~ t _hL-1, pipe P _a00low pass threshold be t _{/ h1}, pipe P _a00~ P _a0L-1source electrode passes through P _e0switch on power V _dC, when k=j-1 ~ 0 and j ≠ 0 time, pipe P _e0conducting, S _iexport through m ₀individual conducting diode is switched to V _dC, with k by j-1 to 0, use pipe P _a0j-1~ P _a00conducting control m successively ₀by 0 to j-1, so S _iby L to L-j+1; Low value district circuit comprises high general formula variable threshold PMOS P _a11~ P _a1Lwith the diode D of series connection ₁₂~ D _1L, by D _1Lmeet D ₀₀, make D ₁₂~ D _1Land D ₀₀~ D _0L-1form a total series diode sequence D ₁₂~ D _0L-1, pipe P _a11~ P _a1Lhigh pass threshold be followed successively by t _h1~ t _hL, as k=L ~ j+1 and 0<j<L time, pipe P _e1conducting, pipe P _a11~ P _a1Lsource electrode pass through P _e1switch on power V _dC, S _iexport through m ₁individual conducting diode is switched to V _dC, with k by L to j+1, use pipe P _a1L~ P _a1j+1conducting control m successively ₁by j to L-1, so S _iexport by L-j to 1; When k=j ≠ 0, pipe P _e0, P _e1, P _d0all end, S _ioutput is 0;

3. to each j, j=0 ~ L, door U is differentiated by K logical value ₀~ U _ldifferentiate j value, logical value differentiates door U _mthe logical threshold of band is t _bjbe exactly ' only work as U _mu when being input as j _mexport as high level, otherwise, U _mexport as low level ', get U ₀~ U _lband lead to threshold and be respectively t _b0~ t _bL; All U ₀~ U _lbe input as j, U ₀~ U _loutput is respectively v _tg0~ v _tgL, v _tg0~ v _tgLrespectively hang oneself not gate M ₀~ M _lproduce anti-phase output v _{/ tg0}~ v _{/ tgL}; Complete thus: (1) to j ≠ 0, at variable threshold gating PMOS P _c1~ P _cLmiddle v _{/ tgj}drive P _cjconducting, pipe P _c1~ P _cLsource electrode threshold value to be passed is respectively t _{/ h1}~ t _{/ hL}, then pipe P _c1~ P _cLin only t _{/ h1}~ t _{/ hL}in t _{/ hj}be loaded into pipe P _e0, use pipe P _e0when conducting controls Spring layer (0, j-1) length j, j ≠ 0, j=L, Spring layer length is L; (2) to j ≠ 0, at variable threshold gate tube P _d1~ P _dLmiddle v _{/ tgj}drive P _djconducting, pipe P _d1~ P _dL-1, P _dLsource electrode threshold value to be passed is respectively t _h2~ t _hL, t _{/ h1}, as j < L, pipe P _d1~ P _dL-1in only make t _h2~ t _hLin t _hj+1be loaded into pipe P _e1; As j=L, pipe P _dLby t _{/ h1}be loaded into pipe P _e1, make low value district invalid; Use pipe P _e1and P _d0conducting controls low value district (j+1 ~ L) length L-j, j ≠ L; (3) at cmos transmission gate TG ₁~ TG _lmiddle v _tgjand v _{/ tgj}only drive TG _jconducting, j=1 ~ L, S _iby the TG of conducting _jmeet P _a0j-1drain electrode, S _imaximum condition is k=j-1, now S _iby the TG of conducting _jand P _a0j-1receive V _dC, realize S _i=L; (4), as j=0, use v _{/ tg0}drive TG ₀with pipe P _d0, P _c0conducting, P _d0source electrode meets V _dC, P _d0drain electrode adapter P _a11~ P _a1Lsource electrode, pipe P _a11~ P _a1Lsource electrode passes through P _d0be switched to V _dC, S _ipass through TG ₀meet P _a1Ldrain electrode, low value district circuit working and become digital follower, realizes S _i=A _i, now low value section length is L, Spring layer circuit malfunction; Pipe P _c0grid meets v _{/ tg0}, P _c0drain electrode meets P _e0grid, pipe P _c0source electrode meets direct voltage V _dC, J when making j=0 _iexport as the above-mentioned level indicated without borrow, J when supplementing 1. the j=0 lacked _ithe formation of signal.

(note: referring to embodiment 4: the explanation adopting band logical threshold loading technique, variable threshold gating PMOS and the controlled PMOS of gating of the present invention; v _{/ tgj}drive P _cjconducting, passes through P _cjconducting makes P _cjsource electrode threshold value t to be passed _{/ hj}be loaded into pipe P _e0, loading is exactly make P _e0there is threshold value t _{/ hj}characteristic, if P _cjcut-off, then this t _{/ hj}load and lost efficacy, another P need be driven _cj1conducting, by t _{/ hj1}be loaded into pipe P _e0; Similar fashion, drives P _djconducting, by t _hj+1be loaded into pipe P _e1, this loading makes P _e1there is threshold value t _hj+1characteristic; When j value changes, Spring layer and the change of low value district require pipe P _e0and P _e1threshold property loads with the logical threshold of new band and changes).

2. a kind of a kind of construction method adopting band to lead to the K value half adder of threshold loading technique adopting the construction method same characteristic features of the K value half-subtracter of the logical threshold loading technique of band to be formed according to technique scheme 1: in the construction method of K value half-subtracter adopting the logical threshold loading technique of band: (i) first, by U ₁~ U _lband lead to threshold and be taken as t respectively _bL~ t _b1; (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', will all have borrow to be taken as no-carry, be taken as carry without borrow and (comprised C _iexport high level V _dCrepresent no-carry, C _ioutput low level 0 indicates carry), pipe P _c0source electrode meets direct voltage V _d, C when making j=0 _iexport the level for above-mentioned expression no-carry, V _d≠ V _dC; (iii) last, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then adopt the construction method of the K value half-subtracter of the logical threshold loading technique of band just to become the construction method adopting band to lead to the K value half adder of threshold loading technique.

(note: referring to the proof that embodiment 1, K value half-subtracter is identical with half adder construction method feature).

3. a kind of a kind of K value half-subtracter circuit adopting the logical threshold loading technique of band adopting the construction method of the K value half-subtracter of the logical threshold loading technique of band to be formed according to technique scheme 1, show as Fig. 1, the K value half-subtracter circuit of the logical threshold loading technique of band is adopted to comprise: control signal forms circuit, Spring layer and high gating circuit, low value district and low gating circuit, S _ioutput circuit and J _ioutput circuit; Be described below referring to Fig. 1, K value half-subtracter particular circuit configurations:

1. control signal forms circuit by logical value differentiation door U ₀~ U _lwith CMOS not gate M ₀~ M _ltwo part compositions, differentiate door U ₀~ U _lrespectively by the band general formula variable threshold PMOS P that interval is minimum _b0~ P _bLwith constant-current source I ₀~ I _lform, pipe P _b0~ P _bLband lead to threshold and be respectively t _b0~ t _bL, wherein t _b0=t _{/ h1}, t _bL=t _hL, i.e. pipe P _b0and P _bLbe respectively interval minimum low general formula and high general formula variable threshold PMOS, pipe P _b0~ P _bLeffective input all meet B _i, pipe P _b0~ P _bLsource electrode meets power supply V _dC, pipe P _b0~ P _bLdrain electrode meets constant-current source I respectively ₀~ I _lupper end, I ₀~ I _lupper end is respectively as U ₀~ U _lexport v _tg0~ v _tgL, constant-current source I ₀~ I _llower end ground connection, constant-current source electric current is all flow to lower end, v by upper end _tg0~ v _tgLmeet not gate M respectively ₀~ M _linput, M ₀~ M _loutput is respectively v _{/ tg0}~ v _{/ tgL}, draw control signal v anti-phase each other thus _tg0~ v _tgLand v _{/ tg0}~ v _{/ tgL}, M ₀~ M _loperating voltage is V _dC, to each B _iinput j, j=0 ~ L, v _tg0~ v _tgLin only v _tgjbe high level, all the other outputs are all low levels;

2. Spring layer and high gating circuit: high gating circuit is by variable threshold gating PMOS P _c1~ P _cL, the controlled PMOS P of gating _e0with PMOS P _c0composition; Pipe P _c1~ P _cLsource electrode low pass threshold to be passed is respectively t _{/ h1}~ t _{/ hL}, pipe P _c1~ P _cLeffective input meet A _i, pipe P _c0~ P _cLgrid meets control signal v respectively _{/ tg0}~ v _{/ tgL}, and its drain electrode all adapter P _e0grid g _{/ hj}; To each B _iinput j, j=1 ~ L, pipe P _c1~ P _cLin only have a pipe P _cjconducting, all the other pipes end, so at t _{/ h1}~ t _{/ hL}in only by t _{/ hj}be loaded into pipe P _e0, pipe P _e0source electrode meets V _dC, its drain electrode adapter P _a00~ P _a0L-1source electrode; Spring layer circuit comprises the logical variable threshold PMOS P of band _a00~ P _a0L-1with series diode D ₀₀~ D _0L-1, pipe P _a01~ P _a0L-1high pass threshold be followed successively by t _h1~ t _hL-1, pipe P _a00low pass threshold be t _{/ h1}, pipe D ₀₀~ D _0L-2negative pole is adapter D separately ₀₁~ D _0L-1positive pole, pipe P _a00~ P _a0L-1effective input meets A _i, pipe P _a00~ P _a0L-1drain electrode adapter D separately ₀₀~ D _0L-1negative pole, A _ibe input as k, as k=0 ~ j-1 and j ≠ 0 time, pipe P _e0conducting, by pipe P _a00~ P _a0L-1source electrode passes through P _e0connect V _dC, Spring layer circuit working, uses pipe P _e0conducting controls Spring layer (0, j-1) length j, j ≠ 0, as k=j ~ L, and pipe P _e0cut-off, pipe P _a00~ P _a0L-1source electrode and V _dCdisconnect, Spring layer circuit does not work;

3. low value district and low gating circuit: low gating circuit is by variable threshold gating PMOS P _d1~ P _dL, the controlled PMOS P of gating _e1with PMOS P _d0composition; Pipe P _d1~ P _dL-1source electrode high pass threshold to be passed is respectively t _h2~ t _hL, P _dLsource electrode low pass threshold to be passed is t _{/ h1}; Pipe P _d0~ P _dLgrid meets control signal v respectively _{/ tg0}~ v _{/ tgL}, P _d1~ P _dLdrain electrode adapter P _e1grid, P _d1~ P _dLeffective input meets A _i; To each j, j=1 ~ L-1, pipe P _d1~ P _dL-1in only have a pipe P _djconducting, all the other pipes end, at t _h2~ t _hLin choose t _hj+1be loaded into pipe P _e1, and j=L, pipe P _dLconducting, t _{/ h1}be loaded into pipe P _e1; Pipe P _e1and P _d0drain electrode adapter P _a11~ P _a1Lsource electrode, P _e1and P _d0source electrode meets V _dC; As k=j+1 ~ L and 0<j<L time, pipe P _e1conducting, pipe P _a11~ P _a1Lsource electrode passes through P _e1connect V _dC, low value district circuit working; Low value district circuit comprises high pass variable threshold PMOS P _a11~ P _a1Lwith series diode D ₁₂~ D _1L, pipe D ₁₂~ D _1L-1negative pole is adapter D separately ₁₃~ D _1Lpositive pole, D _1Lnegative pole meets D ₀₀positive pole, by D ₁₂~ D _1Land D ₀₀~ D _0L-1series connection, forms 2L-1 series diode sequence, pipe P _a11~ P _a1Lhigh pass threshold be t separately _h1~ t _hL, it effectively inputs and meets A _i, pipe P _a12~ P _a1Ldrain electrode adapter D separately ₁₂~ D _1Lnegative pole, pipe P _a11drain electrode meets D ₁₂positive pole; As j=0, pipe P _d0conducting, pipe P _a11~ P _a1Lsource electrode passes through P _d0connect V _dC, Spring layer circuit is invalid, low value district circuit working and be formed as digital follower, uses pipe P _e1and P _d0conducting controls low value district (j+1, L) length L-j, j ≠ L; As k=0 ~ j and j ≠ L time, pipe P _e1cut-off, pipe P _a11~ P _a1Lsource electrode and V _dCdisconnect, low value district circuit does not work; To j=L, when k ≠ 0, pipe P _e1cut-off, and as k=0, pipe P _e1conducting, pipe P _a11~ P _a1Lfull cut-off, low value district circuit is invalid, Spring layer circuit working;

4. S _ioutput circuit and J _ioutput circuit; S _ioutput circuit is by cmos transmission gate TG ₀~ TG _lwith constant-current source I _sicomposition, transmission gate TG ₁~ TG _linput adapter P respectively _a00~ P _a0L-1drain electrode, TG ₀input adapter P _a1Ldrain electrode, TG ₀~ TG _lexport and all meet constant-current source I _siupper end, I _siupper end is as S _iexport, I _silower end ground connection, TG ₀~ TG _lpositive control end and negative control end meet v respectively _tg0~ v _tgLand v _{/ tg0}~ v _{/ tgL}, N is V _don, to each j, j=1 ~ L, at TG ₁~ TG _lin only have a TG _jconducting, S _iby the TG of conducting _jmeet P _a0j-1drain electrode, to j=0, S _iby the TG of conducting ₀adapter P _a1Ldrain electrode; Choose V _dC=LV _don+ △, △ are the side-play amount that K value storage unit circuit characteristic requirements compensates;

(note: NMOS tube N _tgawith PMOS P _tgadrain electrode connects, source electrode also connects, so form cmos transmission gate TG _a, pipe N _tgaand P _tgagrid be respectively transmission gate TG _apositive control end and negative control end);

J _ioutput circuit is by PMOS P _e2with constant-current source I _cicomposition, pipe P _e2source electrode meets V _dC, pipe P _e2grid adapter P _e0grid g _{/ hj}, pipe P _e2drain electrode meets constant-current source I _ciupper end, I _ciupper end is as J _iexport, I _cilower end ground connection, pipe P _c0grid meets v _{/ tg0}, P _c0drain electrode meets P _e0grid; To j ≠ 0, as k < j, pipe P _e0grid g _{/ hj}voltage V _g/hj< V _dC, pipe P _e2conducting, J _iexport as high level V _dC, indicate borrow, as k>=j, V _g/hj=V _dC, pipe P _e2cut-off, J _iexport as low level 0, indicate without borrow; Pipe P _c0source electrode meets direct voltage V _dC, J when making j=0 _iexport as the above-mentioned level (note: as j=0, the P that indicate without borrow _c0conducting, P _e0grid voltage V _g/hjequal this direct voltage V _dC, make pipe P _e2cut-off, J _iexport as high level V _dC, without borrow during expression j=0), all constant-current source senses of current flow to lower end by upper end.

4, a kind of a kind of K value half adder circuit adopting the logical threshold loading technique of band adopting the K value half-subtracter circuit same characteristic features of the logical threshold loading technique of band to be formed according to technique scheme 3, shows as Fig. 1, in K value half-subtracter circuit diagram 1, (i) first, by U ₁~ U _lband lead to threshold and be taken as t respectively _bL~ t _b1; (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', will all have borrow to be taken as no-carry, be taken as carry without borrow and (comprised C _iexport high level V _dCrepresent no-carry, C _ioutput low level 0 indicates carry), pipe P _c0source electrode meets direct voltage V _d, C when making j=0 _iexport the level for above-mentioned expression no-carry, V _dC-V _d=1.5 volts; (note: during j=0, P _c0conducting, pipe P _e0grid voltage V _g/hjequal this direct voltage V _d, make pipe P _e0conducting, C _iexport high level V _dC, represent no-carry, i.e. direct voltage V _dc when meeting j=0 _ioutput level represents no-carry); (iii) last, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then adopt the K value half-subtracter circuit of the logical threshold loading technique of band just to become the K value half adder circuit adopting band to lead to threshold loading technique, namely Fig. 1 becomes Fig. 2.

(note: comparison diagram 1,2 is found out: K value half-subtracter circuit diagram 1 is identical with K value half adder circuit Fig. 2 structure, the just change of parameter: 1. U ₁~ U _lband lead to threshold by t _b1~ t _bLchange t into _bL~ t _b1, 2. P _c0the direct voltage that source electrode connects is by V _dCchange V into _d, each element of circuit is identical with line, and without at all changing, but variable connotation presses half-subtracter and half adder determines; In addition, because of V _tn+ ∣ V _tp∣ < 1.5 volts, V _g/hj=V _dtime, pipe P _e0and P _e2conducting, V _g/hj=V _dCtime, pipe P _e0and P _e2cut-off).

The present invention also has following technical characteristic:

(1) a kind of a kind of K value half-subtracter circuit adopting the logical threshold loading technique of band adopting the construction method of the K value half-subtracter of the logical threshold loading technique of band to be formed according to technique scheme 3, show as Fig. 1, lead in the K value half-subtracter circuit of threshold loading technique at the employing band shown in Fig. 1, get K=10, then draw a kind of 10 value half-subtracter circuit adopting the logical threshold loading technique of band, show as Fig. 3,10 value half-subtracter circuit comprise: control signal forms circuit, Spring layer and high gating circuit, low value district and low gating circuit, S _ioutput circuit and J _ioutput circuit; Referring to Fig. 3,10 value half-subtracter particular circuit configurations are described below:

1. control signal forms circuit by logical value differentiation door U ₀~ U ₉with CMOS not gate M ₀~ M ₉two part compositions, differentiate door U ₀~ U ₉respectively by the band general formula variable threshold PMOS P that interval is minimum _b0~ P _b9with constant-current source I ₀~ I ₉form, pipe P _b0~ P _b9band lead to threshold and be respectively t _b0~ t _b9, wherein t _b0=t _{/ h1}, t _b9=t _h9, i.e. pipe P _b0and P _b9be respectively interval minimum low general formula and high general formula variable threshold PMOS, pipe P _b0~ P _b9effective input all meet B _i, pipe P _b0~ P _b9source electrode meets power supply V _dC, pipe P _b0~ P _b9drain electrode meets constant-current source I respectively ₀~ I ₉upper end, I ₀~ I ₉upper end is respectively as U ₀~ U ₉export v _tg0~ v _tg9, constant-current source I ₀~ I ₉lower end ground connection, constant-current source electric current is all flow to lower end, v by upper end _tg0~ v _tg9meet not gate M respectively ₀~ M ₉input, M ₀~ M ₉output is respectively v _{/ tg0}~ v _{/ tg9}, draw control signal v anti-phase each other thus _tg0~ v _tg9and v _{/ tg0}~ v _{/ tg9}, M ₀~ M ₉operating voltage is V _dC, to each B _iinput j, j=0 ~ 9, v _tg0~ v _tg9in only v _tgjbe high level, all the other outputs are all low levels;

2. Spring layer and high gating circuit: high gating circuit is by variable threshold gating PMOS P _c1~ P _c9, the controlled PMOS P of gating _e0with PMOS P _c0composition; Pipe P _c1~ P _c9source electrode low pass threshold to be passed is respectively t _{/ h1}~ t _{/ h9}, pipe P _c1~ P _c9effective input meet A _i, pipe P _c0~ P _c9grid meets control signal v respectively _{/ tg0}~ v _{/ tg9}, and its drain electrode all adapter P _e0grid g _{/ hj}; To each B _iinput j, j=1 ~ 9, pipe P _c1~ P _c9in only have a pipe P _cjconducting, all the other pipes end, so at t _{/ h1}~ t _{/ h9}in only by t _{/ hj}be loaded into pipe P _e0, pipe P _e0source electrode meets V _dC, its drain electrode adapter P _a00~ P _a08source electrode; Spring layer circuit comprises the logical variable threshold PMOS P of band _a00~ P _a08with series diode D ₀₀~ D ₀₈, pipe P _a01~ P _a08high pass threshold be followed successively by t _h1~ t _h8, pipe P _a00low pass threshold be t _{/ h1}, pipe D ₀₀~ D ₀₇negative pole is adapter D separately ₀₁~ D ₀₈positive pole, pipe P _a00~ P _a08effective input meets A _i, pipe P _a00~ P _a08drain electrode adapter D separately ₀₀~ D ₀₈negative pole; A _ibe input as k, as k=0 ~ j-1 and j ≠ 0 time, pipe P _e0conducting, by pipe P _a00~ P _a08source electrode passes through P _e0connect V _dC, Spring layer circuit working, uses pipe P _e0conducting controls Spring layer (0, j-1) length j, j ≠ 0, when k=j ~ 9, and pipe P _e0cut-off, pipe P _a00~ P _a08source electrode and V _dCdisconnect, Spring layer circuit does not work;

3. low value district and low gating circuit: low gating circuit is by variable threshold gating PMOS P _d1~ P _d9, the controlled PMOS P of gating _e1with PMOS P _d0composition; Pipe P _d1~ P _d8source electrode high pass threshold to be passed is respectively t _h2~ t _h9, P _d9source electrode low pass threshold to be passed is t _{/ h1}; Pipe P _d0~ P _d9grid meets control signal v respectively _{/ tg0}~ v _{/ tg9}, pipe P _d1~ P _d9drain electrode adapter P _e1grid, pipe P _d1~ P _d9effective input meets A _i; To each j, j=1 ~ 8, pipe P _d1~ P _d8in only have a pipe P _djconducting, all the other pipes end, at t _h2~ t _h9in choose t _hj+1be loaded into pipe P _e1, and j=9, pipe P _d9conducting, t _{/ h1}be loaded into pipe P _e1; Pipe P _e1and P _d0drain electrode adapter P _a11~ P _a19source electrode, pipe P _e1and P _d0source electrode meets V _dC; When k=j+1 ~ 9 and 0<j<9 time, pipe P _e1conducting, by pipe P _a11~ P _a19source electrode passes through P _e1connect V _dC, low value district circuit working; Low value district circuit comprises the logical variable threshold PMOS P of band _a11~ P _a19with series diode D ₁₂~ D ₁₉, pipe D ₁₂~ D ₁₈negative pole is adapter D separately ₁₃~ D ₁₉positive pole, D ₁₉negative pole meets D ₀₀positive pole, by D ₁₂~ D ₁₉and D ₀₀~ D ₀₈series connection, forms 17 series diode sequences, pipe P _a11~ P _a19high pass threshold be t separately _h1~ t _h9, it effectively inputs and meets A _i, pipe P _a12~ P _a19drain electrode adapter D separately ₁₂~ D ₁₉negative pole, pipe P _a11drain electrode meets D ₁₂positive pole; As j=0, pipe P _d0conducting, pipe P _a11~ P _a19source electrode passes through P _d0connect V _dC, Spring layer circuit is invalid, low value district circuit working and be formed as digital follower, uses pipe P _e1and P _d0conducting controls low value district (j+1,9) length 9-j, j ≠ 9; As k=0 ~ j and j ≠ 9 time, pipe P _e1cut-off, pipe P _a11~ P _a19source electrode and V _dCdisconnect, low value district circuit does not work; To j=9, when k ≠ 0, pipe P _e1cut-off, and as k=0, pipe P _e1conducting, pipe P _a11~ P _a19full cut-off, low value district circuit is invalid, Spring layer circuit working;

4. S _ioutput circuit and J _ioutput circuit; S _ioutput circuit is by cmos transmission gate TG ₀~ TG ₉with constant-current source I _sicomposition, transmission gate TG ₁~ TG ₉input adapter P respectively _a00~ P _a08drain electrode, TG ₀input adapter P _a19drain electrode, TG ₀~ TG ₉export and all meet constant-current source I _siupper end, I _siupper end is as S _iexport, I _silower end ground connection, TG ₀~ TG ₉positive control end and negative control end meet v respectively _tg0~ v _tg9and v _{/ tg0}~ v _{/ tg9}, N is V _don, at TG ₁~ TG ₉in, to each j, j=1 ~ 9, only have a TG _jconducting, S _iby the TG of conducting _jmeet P _a0j-1drain electrode, to j=0, S _iby the TG of conducting ₀adapter P _a19drain electrode; Choose V _dC=9V _don+ △, △ are the side-play amount that K value storage unit circuit characteristic requirements compensates;

J _ioutput circuit is by PMOS P _e2with constant-current source I _cicomposition, pipe P _e2source electrode meets V _dC, pipe P _e2grid adapter P _e0grid g _{/ hj}, pipe P _e2drain electrode meets constant-current source I _ciupper end, I _ciupper end is as J _iexport, I _cilower end ground connection, pipe P _c0grid meets v _{/ tg0}, P _c0drain electrode meets P _e0grid; To j ≠ 0, as k < j, pipe P _e0grid g _{/ hj}voltage V _g/hj< V _dC, pipe P _e2conducting, J _iexport as high level V _dC, indicate borrow, as k>=j, V _g/hj=V _dC, pipe P _e2cut-off, J _iexport as low level 0, indicate without borrow; Pipe P _c0source electrode meets direct voltage V _dC, J when making j=0 _iexport as above-mentioned level (J when namely making j=0 indicated without borrow _iexport as low level 0); All constant-current source senses of current flow to lower end by upper end.

(2) a kind of a kind of 10 value half adder circuits adopting the logical threshold loading technique of band adopting 10 value half-subtracter circuit same characteristic features of the logical threshold loading technique of band to be formed, according to technique scheme (1), show as Fig. 3, lead in 10 value half-subtracter circuit of threshold loading technique at the employing band shown in Fig. 3, (i) first, by U ₁~ U ₉band lead to threshold and be taken as t respectively _b9~ t _b1; (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', by all there being borrow to be taken as no-carry, be taken as carry without borrow, pipe P _c0source electrode meets direct voltage V _d, C when making j=0 _iexport the level for above-mentioned expression no-carry, V _dC-V _d=1.5 volts; (iii) last, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then adopt 10 value half-subtracter circuit of the logical threshold loading technique of band just to become the 10 value half adder circuits adopting band to lead to threshold loading technique, namely Fig. 3 just becomes Fig. 4.

(note: comparison diagram 3 is found out with Fig. 4: 10 value half-subtracter circuit are identical with 10 value half adder circuit structures, the just change of parameter: 1. U ₁~ U ₉band lead to threshold by t _b1~ t _b9change t into _b9~ t _b1, 2. P _c0the direct voltage that source electrode connects is by V _dCchange V into _d, each element of circuit is identical with line, and without at all changing, variable connotation presses half-subtracter and half adder determines; Because of V _tn+ ∣ V _tp∣ < 1.5 volts, pipe P _e0grid voltage V _g/hj=V _dtime, pipe P _e0conducting, V _g/hj=V _dCtime, pipe P _e0cut-off; In addition, ' J _iexport high level V _dCindicate borrow ' be taken as ' C _iexport high level V _dCrepresent no-carry ', ' J _ioutput low level 0 indicates without borrow ' be taken as ' C _ioutput low level 0 indicates carry ').

So far K value information stores the many of research, and it is fewer that the computing of K value information is studied, and its reason is that K value information computing circuit is all routinely based on the implementation method of the K value combinational logic circuit of K value door composition, and its difficulty is very large, and structure is very complicated; 1. general information computing and information processing each stage, all require that the threshold property of pipe is different, conventional variable threshold method does not meet needs, the present invention adopts the logical threshold loading technique of band, by information operation and the demand in information processing each stage, needed for different phase, be with logical threshold value to be loaded in PMOS stage by stage, make PMOS have band variable at any time to lead to threshold value, this is the new method and the new approaches that realize the computing of K value information and information processing; 2. on the logical threshold loading technique basis of band, the consistency of the characteristic sum structure of K value half-subtracter and K value half adder is analyzed in the present invention, because K value half-subtracter and half adder have identical Spring layer and low value district, its feature is unified, adopt the logical threshold loading technique of band, two kinds of circuit can be classified as a kind of circuit Uniting, and avoid the traditional thinking mode adopting K value combinational logic gate circuit realiration, and circuit structure greatly simplifies; K value half-subtracter and K value half adder are the important devices realizing K value plus and minus calculation, and had K value half-subtracter and K value half adder, the realization of K value computing is just easy to, and provides good basis to the computing of K value information and information processing in chaos encrypting method and encrypted circuit.

(4) accompanying drawing explanation

Fig. 1. be a kind of K value half-subtracter circuit diagram adopting the logical threshold loading technique of band of the present invention;

Fig. 2. be a kind of K value half adder circuit figure adopting the logical threshold loading technique of band of the present invention;

Fig. 3. be a kind of 10 value half-subtracter circuit diagrams adopting the logical threshold loading technique of band of the present invention;

Fig. 4. be a kind of 10 value half adder circuit figure adopting the logical threshold loading technique of band of the present invention;

Fig. 5. a kind of PMOS band of being correlated with for the present invention leads to variable threshold circuit diagram and band general formula variable threshold PMOS graphical diagram;

Fig. 6. a kind of PMOS high pass variable threshold circuit diagram of being correlated with for the present invention and high general formula variable threshold PMOS graphical diagram;

Fig. 7. a kind of PMOS low pass variable threshold circuit diagram of being correlated with for the present invention and low general formula variable threshold PMOS graphical diagram;

Fig. 8. a kind of variable threshold gating PMOS of being correlated with for the present invention and the controlled PMOS of gating and graphical diagram thereof;

Fig. 9. be the accurate mirror-image constant flow source circuit diagram of existing a kind of multi output and graphical diagram;

Figure 10. be the working waveform figure of 10 value half-subtracter circuit of the present invention during 180 ~ 410 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, J _iand g _{/ hj};

Figure 11. be the working waveform figure of 10 value half-subtracter circuit of the present invention during 180 ~ 240 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, J _iand g _{/ hj};

Figure 12. be the working waveform figure of 10 value half-subtracter circuit of the present invention during 240 ~ 300 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, J _iand g _{/ hj};

Figure 13. be the working waveform figure of 10 value half-subtracter circuit of the present invention during 300 ~ 360 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, J _iand g _{/ hj};

Figure 14. be the working waveform figure of 10 value half-subtracter circuit of the present invention during 350 ~ 410 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, J _iand g _{/ hj};

Figure 15. be 10 value half-subtracters of the present invention circuit control signal oscillogram during 180 ~ 410 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, v _tg9, v _tg8, v _tg7, v _tg6, v _tg5, v _tg4, v _tg3, v _tg2, v _tg1, v _tg0;

Figure 16. be the working waveform figure of 10 value half adder circuits of the present invention during 180 ~ 410 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, C _iand g _{/ hj};

Figure 17. be the working waveform figure of 10 value half adder circuits of the present invention during 180 ~ 240 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, C _iand g _{/ hj};

Figure 18. be the working waveform figure of 10 value half adder circuits of the present invention during 240 ~ 300 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, C _iand g _{/ hj};

Figure 19. be the working waveform figure of 10 value half adder circuits of the present invention during 300 ~ 360 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, S _i, C _iand g _{/ hj};

Figure 20. be the working waveform figure of 10 value half adder circuits of the present invention during 350 ~ 410 μ s, signal voltage voltage waveform from top to bottom precedence is: A _i, B _i, S _i, C _iand g _{/ hj};

Figure 21. be 10 value half adders of the present invention circuit control signal oscillogram during 180 ~ 410 μ s, voltage waveform signal from top to bottom precedence is: A _i, B _i, v _tg9, v _tg8, v _tg7, v _tg6, v _tg5, v _tg4, v _tg3, v _tg2, v _tg1, v _tg0;

(5) embodiment

Below by embodiment, the present invention is further illustrated:

Embodiment 1: the proof that K value half-subtracter of the present invention is identical with half adder construction method feature:

(1) K value half-subtracter feature: A _ifor minuend, B _ifor subtrahend, S _ifor this is for poor, J _ifor borrow, make A _i=k, B _i=j,

To the j=1 ~ L determined, as k < j, S _i=K+k-j > k, i.e. S _i> A _i; As k=j, S _i=0; As k > j and j ≠ L time, S _i=k-j < k, i.e. S _i< A _i, as j=L, there is not k > j; To the j=0 determined, S _i=A _i; To j ≠ 0, as k < j, there is borrow, as k>=j, without borrow, to j=0, without borrow;

(2) K value half adder feature: A _ifor summand, B _ifor addend, S _ifor this be and, C _ifor carry digit, make A _i=k, B _i=n, to the n determined, n=1 ~ L, as k+n < K, S _i=k+n > k, i.e. S _i> A _i, as k+n=K, S _i=0, as k+n > K and n ≠ 1 time, S _i=k+n-K < k, i.e. S _i< A _i, as n=1, there is not k+n > K; To the n=0 determined, S _i=A _i; To n ≠ 0, as k+n < K, no-carry, as k+n>=K, has carry, to n=0, and no-carry;

In (1) K value half-subtracter feature, to j=1 ~ L, get j=K-n, to j=0, get n=0, outside ' j=0 is taken as no-carry without borrow ', all will be taken as carry without borrow, borrow is had to be taken as no-carry, so drawn and the identical result of (2) K value half adder by (1): to the n determined, n=1 ~ L, as k < K-n, S _i=k+n > k, i.e. S _i> A _i, as k=K-n, S _i=0, as k > K-n and n ≠ 1 time, S _i=k-K+n < k, i.e. S _i< A _i, as n=1, there is not k+n > K; To the n=0 determined, S _i=A _i; To n ≠ 0, as k < K-n, no-carry, as k>=K-n, has carry, to n=0, and no-carry;

In (2) K value half adder feature, to n=1 ~ L, get n=K-j, to n=0, get j=0, except ' n=0, no-carry is taken as without borrow ' outside, whole no-carry is taken as borrow, has had carry to be taken as without borrow, drawn and the identical result of (1) K value half-subtracter by (2);

Epimere describes to be found out: the feature of the characteristic sum K value half adder of K value half-subtracter is consistent, therefore in the construction method of K value half-subtracter: (i) first, by U ₁~ U _lband lead to threshold and be taken as t successively _bL~ t _b1, embody j=1 ~ L, get n=K-j, (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', will all having borrow to be taken as no-carry, carry will be taken as without borrow, (iii) finally, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then the construction method of K value half-subtracter is just formed as the construction method of K value half adder.

Embodiment 2:K value half-subtracter S _ioutput situation illustrates:

When j ≠ 0 and k=1 ~ j-1 time, pipe P _e0conducting, pipe P _e0drain voltage V _pe0=V _dC, low value district circuit is invalid; As k=j-1, pipe P _a0j-1conducting, S _ipass through TG _jand P _a0j-1meet V _pe0, S _ioutput voltage V _si=V _dC, i.e. S _i=L; As k=j-2, pipe P _a0j-2, D _0j-1conducting, pipe P _a0j-1cut-off, S _ipass through TG _j, P _a0j-2, D _0j-1meet V _pe0, S _iand V _pe0between have 1 diode D _0j-1, V _si=V _dC-V _don, i.e. S _i=L-1; As k=j-3, pipe P _a0j-3, D _0j-1, D _0j-2conducting, pipe P _a0j-1and P _a0j-2cut-off, S _ipass through TG _j, P _a0j-3, D _0j-1, D _0j-2meet V _pe0, S _iand V _pe0between have 2 diodes, V _si=V _dC-2V _don, i.e. S _i=L-2; ‥ ..., as k=1, pipe P _a01, D ₀₂~ D _0j-1conducting, pipe P _a02~ P _a0j-1cut-off, S _ipass through TG _j, P _a01, D ₀₂~ D _0j-1meet V _pe0, S _iand V _pe0between have (j-2) individual diode, V _si=V _dC-(j-2) V _don, i.e. S _i=L-j+2; As k=0, pipe P _a00, D ₀₁~ D _0j-1conducting, pipe P _a01~ P _a0j-1cut-off, S _ipass through TG _j, P _a00, D ₀₁~ D _0j-1meet V _pe0, S _iand V _pe0between have (j-1) individual diode, V _si=V _dC-(j-1) V _don, i.e. S _i=L-j+1;

As k=j+1 ~ L and 0<j<L time, pipe P _e1conducting, P _e1drain voltage V _pe1=V _dC, pipe P _e0cut-off, only low value district circuit working, Spring layer circuit does not work, as k=L, pipe P _a1L, D ₀₀~ D _0j-1conducting, S _ipass through TG _j, P _a1L, D ₀₀~ D _0j-1meet V _pe1, S _iand V _pe1between have j diode, V _si=V _dC-jV _don, i.e. S _i=L-j; As k=L-1, pipe P _a1L-1, D _1L, D ₀₀~ D _0j-1conducting, pipe P _a1Lcut-off, S _ipass through TG _j, P _a1L-1, D _1L, D ₀₀~ D _0j-1meet V _pe1, S _iand V _pe1between have (j+1) individual diode, V _si=V _dC-(j+1) V _don, i.e. S _i=L-(j+1); As k=L-2, pipe P _a1L-2, D _1L-1, D _1L, D ₀₀~ D _0j-1conducting, pipe P _a1L-1, P _a1Lcut-off, S _ipass through TG _j, P _a1L-2, D _1L-1, D _1L, D ₀₀~ D _0j-1meet V _pe1, S _iand V _pe1between have (j+2) individual diode, V _si=V _dC-(j+2) V _don, i.e. S _i=L-(j+2); ‥ ‥ ‥ ‥, as k=j+2, pipe P _a1j+2, D _1j+3~ D _1L, D ₀₀~ D _0j-1conducting, pipe P _a1j+3~ P _a1Lcut-off, S _ipass through P _a1j+2, D _1j+3~ D _1L, D ₀₀~ D _0j-1meet V _pe1, S _iand V _pe1between have (L-2) individual diode, V _si=V _dC-(L-2) V _don=2V _don+ △, i.e. S _i=2; As k=j+1, pipe P _a1j+1, D _1j+2~ D _1L, D ₀₀~ D _0j-1conducting, pipe P _a1j+2~ P _a1Lcut-off, S _ipass through P _a1j+1, D _1j+2~ D _1L, D ₀₀~ D _0j-1meet V _pe1, S _iand V _pe1between have (L-1) individual diode, V _si=V _dC-(L-1) V _don=V _don+ △, i.e. S _i=1 (note: as j=L, this paragraph is ineffective, should all go by grid, and ' j ≠ 0 and k=1 ~ j-1 ', previous paragraphs end is: as k=0, V only previous paragraphs _si=V _dC-(L-1) V _don=V _don+ △, i.e. S _i=1.In order to simplify circuit, also low gating circuit pipe P can be removed by grid _d0~ P _dLand P _e1, by pipe P _a11~ P _a1Lsource electrode receives V _dC, do not affect the S of above-mentioned j ≠ 0 and k ≠ j _ioutput situation, as k=j, S _iby the P of conducting _a1j, D _1j+1~ D _1L, D ₀₀~ D _0j-1meet V _pe1, S _iand V _pe1between have L diode, V _si=V _dC-LV _don=△, i.e. S _i0 level V _si(0)=△, because △ is very little, in fact also feasible).

In addition, as k=j, pipe P _e0and P _e1cut-off, S _iwith V _dCdisconnect, V _si=0, i.e. S _i=0.

As j=0, S _iby the TG of conducting ₀meet P _a1Ldrain electrode, Spring layer circuit malfunction, low value district circuit becomes digital follower, realizes S _i=A _i, work as A _iwhen being followed successively by 0 ~ L, S _ibe followed successively by 0 ~ L; S is analyzed by above-mentioned same procedure _ioutput situation: with reference to above-mentioned k=j+1 ~ L paragraph, grid remove wherein D ₀₀~ D _0j-1, get j=0, such as, as k=L, pipe P _a1L, S _ipass through TG ₀, P _a1Lmeet V _pe1, S _iand V _pe1between have 0 diode, V _si=V _dC-0V _don, i.e. S _i=L ， ‥ ..., repeat no more; Or referenced patent 201310211023.2 (write circuit of any K value and 8 value DRAM and reading circuit).

Embodiment 3: PMOS band of the present invention leads to, the explanation of high pass and low pass variable threshold circuit function:

With reference to [1] patent 201110291038.5 ' PMOS band leads to-be with resistance and high pass-low pass variable threshold circuit ' (summary of the invention, drawings and Examples 1 etc.), patent [2] 201110280921.4 ' embedding 8 value information method for refreshing and interlock circuits of 8 value memory cell of DRAM storage matrix ' (drawings and Examples 4 etc.), is described below by feature variable threshold circuit of the present invention:

(1) PMOS band leads to variable threshold circuit: patent [1] or [2] Fig. 6 are repainted patent Fig. 5 of the present invention, wherein PMOS Q ₂, Q ₄, Q ₅, Q _b1be rewritten as P successively ₂, P ₄, P ₅, P _b1, NMOS tube Q ₁, Q ₃be rewritten as N successively ₁, N ₃, V _xbe rewritten as V _in, note v _bx1=V _ex1+ V _dC=V _ref1+ V _tn1+ ∣ V _tp2∣, v _bx0=V _ex0+ V _dC=V _ref0-V _tn3-∣ V _tp4∣; Pipe N ₁and P ₄grid meets input in, and input in voltage is V _in, pipe N ₃and P ₂grid meets reference voltage V respectively _ref0and V _ref1; First analyzer tube N ₁, P ₂branch road, only as pipe N ₁and P ₂two grid voltages difference V _g1-V _g2=V _in-V _ref1=V _gs1+ V _sg2> V _tn1+ ∣ V _tp2(V during ∣ _in> v _bx1), pipe N ₁, P ₂branch road conducting, otherwise, this subcircuit disables; Analyzer tube N again ₃, P ₄branch road, only as pipe N ₃and P ₄two grid voltages difference V _g3-V _g4=V _ref0-V _in> V _tn3+ ∣ V _tp4(V during ∣ _in< v _bx0), pipe N ₃, P ₄branch road conducting, otherwise, this subcircuit disables.Band resistance exports v _{/ dvi ~ j}through PMOS not gate generating strap logical output v _{dvi ~ j}, this not gate is by pipe P ₅with resistance R ₀form; v _{dvi ~ j}be transported to controlled PMOS P _b1grid, pipe P _b1source electrode meets V _dC, pipe P _b1drain electrode connects external circuit; Draw thus: work as v _bx1> V _in> v _bx0(V _inin band is interval) time, pipe N ₁, P ₂branch road and pipe N ₃, P ₄branch road all ends, resistance R ₁electric current be 0, v _{/ dvi ~ j}=V _dCso, P ₅cut-off, v _{dvi ~ j}=V _d< V _dC, make pipe P _b1conducting; Because in inputs K value signal, only as in=i ~ j, P _b1conducting; In is with interval to be (i, j); During in ≠ i ~ j, P _b1cut-off; Be connected to the PMOS P of the logical variable threshold circuit of band _b1be called band general formula variable threshold PMOS P _b1; Note t _{bi ~ j}=(i, j), t _{bi ~ j}for being with logical threshold, vt _{bi ~ j}for being with logical threshold voltage, vt _{bi ~ j}=(vt _bi-, vt _bj+), can vt be chosen _bj+=(V _in(j+1)+V _in(j))/2, vt _bi-=(V _in(i)+V _in(i-1))/2, meet vt _bi-< V _in< vt _bj+ time, P _b1conducting, otherwise, P _b1cut-off; Use t _{bi ~ j}or vt _{bi ~ j}be marked on pipe P _b1effective input is other, P on the right side of Fig. 5 _b1effective input squarely to represent (common PMOS grid small circular represents, distinguishes to some extent) with little, and effectively input meets input in (in meets N ₁and P ₄grid), claim this to be input as the logical variable threshold type PMOS P of band _b1effective input; Band interval minimum (only having a value i) during j=i, t _{bi ~ j}=t _bi=i, vt _{bi ~ j}=vt _bi, the band general formula variable threshold PMOS P that minimum band is interval _b1be called interval minimum band general formula variable threshold PMOS P _b1.

Note: (1) the muting logic level of logical value k is referred to as k level, the k level of in is designated as V _in(k); In logical value is that k is expressed as in=k; Brief note ' in=i, i+1, i+2 ‥ ..., j-1, j ' and be in=i ~ j, such as, t _{b2 ~ 5}=(2,5), in gets in band interval (2,5) 2,3,4,5, and referred to as in=2 ~ 5, the rest may be inferred; (2) resistance R ₀available NMOS tube N ₀replace, by pipe N ₀and P ₅form CMOS inverter (P ₅and N ₀grid connects grid, and drain electrode connects drain electrode, N ₀source electrode meets V _d); (3) the grid of NMOS and PMOS has very little threshold value confusion region (break over region), and the conducting of pipe and cut-off require that grid voltage is outside break over region, can not determine conducting and the cut-off of pipe, above-mentioned vt in very little break over region _bi-and vt _bj+be chosen for the median of two level, antijamming capability is the strongest; (4) pipe N in Fig. 5 ₁, P ₂branch road and pipe N ₃, P ₄branch road is separately to being called high pass branch road and low pass branch road.

(2) PMOS high pass variable threshold circuit: the pipe N leaving out low pass branch road in Fig. 5 ₃, P ₄and line (note: work as V _ref0when=0, pipe N ₃, P ₄branch road ends forever, ineffective, and grid go), draw the high pass variable threshold circuit shown in Fig. 6, analyzer tube N ₁, P ₂branch road, as pipe N ₁and P ₂grid voltage difference V _in-V _ref1> V _tn1+ ∣ V _tp2(V during ∣ _in> v _bx1), pipe N ₁, P ₂branch road conducting, otherwise, pipe N ₁, P ₂subcircuit disables; Because in is input as K value signal, only as in>=i (in=i ~ L), pipe N ₁, P ₂branch road conducting, so v _{dvi ~ L}for low level, make controlled PMOS P _b1conducting; Be connected to the PMOS P of high pass variable threshold circuit _b1be called high general formula variable threshold PMOS, because most high logic value is L, note t _hi=(i, L), t _hibe called high pass threshold, vt _hirepresent V _in> vt _hitime pipe P _b1conducting, uses t _hior vt _hibe marked on pipe P _b1effective input is other; High interval minimum during i=L, t _hi=t _hL, vt _hi=vt _hL; Minimum high interval high general formula variable threshold PMOS P _b1be called interval minimum high general formula variable threshold PMOS P _b1.

(3) PMOS low pass variable threshold circuit: the pipe N leaving out high pass branch road in Fig. 5 ₁, P ₂and line (note: work as V _ref1=V _dCtime, pipe N ₁, P ₂branch road ends forever, ineffective, and grid go), draw the low pass variable threshold circuit shown in Fig. 7, analyzer tube N ₃, P ₄branch road, as pipe N ₃and P ₄grid voltage difference V _ref0-V _in> V _tn3+ ∣ V _tp4(V during ∣ _in< v _bx0), pipe N ₃, P ₄branch road conducting, otherwise, pipe N ₃, P ₄subcircuit disables, because in inputs K value signal, only as in≤j (in=0 ~ j), P _b1conducting is (because of P ₅conducting, P ₅drain electrode v _{/ dv0 ~ j}for high level, v _{/ dv0 ~ j}receive by P ₆and N ₇the CMOS not gate input of composition, then this not gate exports v _{dv0 ~ j}for low level, v _{dv0 ~ j}make controlled PMOS P _b1conducting); Be connected to the PMOS P of low pass variable threshold circuit _b1be called low general formula variable threshold PMOS, note t _{/ hj+1}=(0, j), t _{/ hj+1}be called low pass threshold, vt _{/ hj+1}represent V _in< vt _{/ hj+1}time pipe P _b1conducting; Use t _ljor vt _ljbe marked on pipe P _b1effective input is other; During j=0, low interval is minimum, t _{/ hj+1}=t _{/ h1}, vt _{/ hj+1}=vt _{/ h1}, the low general formula variable threshold PMOS P in minimum low interval _b1be called interval minimum low general formula variable threshold PMOS P _b1.

Note: (1) the substrate of PMOS is met supply voltage V _dC(maximum potential is V _dC), by the Substrate ground (potential minimum is ground) of NMOS tube; If use potential minimum V instead _minlower than earth potential, use maximum potential V instead _maxcompare V _dCcurrent potential is high, then the substrate reconfiguration V of PMOS _max, the substrate reconfiguration V of NMOS tube _min, for observing conveniently, the connection of omitting substrate in figure is not drawn; (2) change reference voltage V _ref0and V _ref1v can be regulated respectively _bx0and v _bx1size, thus realize above-mentioned band respectively and lead to threshold, the adjustment of high pass threshold and low pass threshold, to meet various actual demand.

Embodiment 4: the explanation adopting band logical threshold loading technique, variable threshold gating PMOS and the controlled PMOS of gating of the present invention:

When j value changes, Spring layer and low value section length all require pipe P _e0and P _e1threshold property loads with new threshold value and changes, general information process each stage, all requires that pipe is (as P _e0and P _e1) threshold property different; Fig. 5, exports v in 6 and 7 _{dv0 ~ j}all be delivered directly to controlled PMOS P _b1grid, threshold value immobilizes, and can not meet and change requirement at any time; It is in 8 figure that circuit in frame empty in Fig. 5 repaints by the present invention, and 8 figure export v _{dvi ~ j}by pipe P _c1source-drain electrode is transported to controlled PMOS P _b1grid, v _{dvi ~ j}adapter P _c1source electrode, pipe P _c1drain electrode adapter P _b1grid, pipe P _c1grid meets control signal v _tg, at v _tgunder low level effect, pipe P _c1conducting, so v _{dvi ~ j}by conduction pipe P _c1source-drain electrode is transported to controlled PMOS P _b1grid, make controlled PMOS P _b1having the logical threshold of band is t _{bi ~ j}characteristic; Be connected to the PMOS P of the logical variable threshold circuit of band _c1be called variable threshold gating PMOS P _c1, and pipe P _b1be called the controlled PMOS of gating, by the graphical diagram shown in Fig. 8 right part, effectively input in connects little square side, pipe P _c1source electrode connects little below square, pipe P _c1source markers source electrode band to be passed leads to threshold t _{bi ~ j}, as control signal v _tgdriving tube P _c1conducting, by the pipe P of conducting _c1by logical for band threshold t _{bi ~ j}be loaded into pipe P _b1, loading is exactly make gating be subject to keyholed back plate P _b1there is the logical threshold t of band _{bi ~ j}characteristic: the pipe P as in=i ~ j _b1conducting, otherwise, pipe P _b1cut-off.When being loaded into pipe P _b1band lead to threshold when requiring variable at any time, the timesharing of multiple variable threshold gating PMOS can be adopted to be loaded into gating by keyholed back plate P _b1, such as, the variable threshold gating PMOS P shown in Fig. 3 _c1~ P _c9, pipe P _c1~ P _c9effective input meet A _i, and its all selecting that drains is logical by keyholed back plate P _e0grid g _{/ hj}, pipe P _c0~ P _c9grid meets control signal v respectively _{/ tg0}~ v _{/ tg9}, pipe P _c1~ P _c9source electrode low pass threshold to be passed is respectively t _{/ h1}~ t _{/ h9}; To each j, j=1 ~ 9, pipe P _c1~ P _c9in only have a pipe P _cjconducting, all the other pipes end, so at t _{/ h1}~ t _{/ h9}in only by t _{/ hj}be loaded into pipe P _e0; V in Fig. 5 ~ 8 _dC-V _d=1.5 volts.

Low pass threshold t _{/ hj}with high pass threshold t _hj+1all belong to the logical threshold of band, the logical threshold t of band _{bi ~ L}represent that conducting interval is (i, L), high pass threshold t _hirepresent that conducting interval is also (i, L), i.e. t _{bi ~ L}=t _hi; The logical threshold t of band _{b0 ~ j-1}represent that conducting interval is (0, j-1), low pass threshold t _{/ hj}represent that conducting interval is also (0, j-1), i.e. t _{b0 ~ j-1}=t _{/ hj}, therefore t _{/ hj}and t _hj+1for special band leads to threshold t _{b0 ~ j-1}and t _{bj+1 ~ L}, high pass threshold t _hiwith low pass threshold t _{/ hj}the logical threshold t of band can be called _{bi ~ L}and t _{b0 ~ j-1}, high pass threshold is t _hihigh general formula variable threshold PMOS and low pass threshold be t _{/ hj}low general formula variable threshold PMOS can be called the logical threshold of band be t _{bi ~ L}and t _{b0 ~ j-1}band general formula variable threshold PMOS, in addition, referring to Fig. 5 ~ 8, containing two driver output v in the variable threshold circuit belonging to a band general formula variable threshold PMOS _{dvi ~ j}and v _{/ dvi ~ j}, can realize being with logical threshold t simultaneously _{bi ~ j}with band resistance threshold t _{/ bi ~ j}, therefore, to same effective input in, the logical threshold t of band _{bi ~ j}band general formula variable threshold PMOS, band resistance threshold t _{/ bi ~ j}band resistive variable threshold PMOS and have same band lead to threshold or band resistance threshold variable threshold gating PMOS all share same variable threshold circuit; High general formula and low general formula variable threshold PMOS are classified as special band general formula variable threshold PMOS, have same shared performance, repeat no more.Such as, Fig. 1 gets the bid t _{/ h2}or t _h2pipe P _c2, P _a02, P _d1and P _a12share same variable threshold circuit, drive 4 PMOS respectively by same variable threshold circuit, thus simplify circuit.

Embodiment 5: other illustrates:

J _ipipe P in output circuit _e2pipe P in circuit is formed with control signal _b0~ P _bLthere is level conversion effect, the output voltage of tube grid driving voltage little for amplitude of variation conversion vary within wide limits (is exported 0 and V _dCbetween change), such as, Figure 11 ~ 14 are found out, pipe P _e2gate drive voltage g _{/ hj}amplitude is little, and exports J _iamplitude is large, g _{/ hj}and J _imutually anti-phase.

NMOS tube N _tgawith PMOS P _tgadrain electrode connects, source electrode connects, then form cmos transmission gate TG _a, pipe N _tgaand P _tgagrid be respectively TG _apositive control end and negative control end, work as TG _apositive and negative control end is respectively V _dCwith 0 time, TG _aconducting, and positive and negative control end is respectively 0 and V _dCtime, TG _acut-off; Constant-current source used is referring to the accurate mirror-image constant flow source circuit diagram of the existing a kind of multi output shown in Fig. 9 and graphical diagram, and for reducing power consumption and improving performance etc., constant-current source electric current gets smaller value by physical possibility; Diode used is silicon diode, and conduction voltage drop is V _don, On current gets smaller value by physical possibility; V _dC=LV _don+ △, △ are the side-play amount that K value storage unit circuit characteristic requirements compensates.

Embodiment 6: to the explanation of Pspice computer simulation waveform Figure 10 ~ 21 of Fig. 3 and 4.

Fig. 3 is 10 value half-subtracter circuit diagrams of the present invention, Pspice computer simulation is carried out to Fig. 3,1. the signal voltage working waveform figure of 10 value half-subtracter circuit during 180 ~ 410 μ s shown in Figure 10 is first simulated, can its course of work of whole observation, waveform from top to bottom precedence is: A _i, B _i, S _i, J _iand g _{/ hj}, wherein A _ithe periodic signal of to be the cycle be 16 μ s is A in 16 μ s in the cycle _ibe raised to 9 successively by 0, then be raised to 7, B successively by 2 _ithe periodic signal of to be the cycle be 100 μ s is B in 100 μ s in the cycle _i9 are raised to successively by 0; 2. be clear inspection A _iand B _ithe result of subtraction during all probable values, amplifies Figure 10 transverse axis, draws the oscillogram during 180 ~ 240 μ s, 240 ~ 300 μ s, 300 ~ 360 μ s and 350 ~ 410 μ s, show respectively as Figure 11,12,13 and 14, observe Figure 11 ~ 14 successively, and at A _iand B _istablize moment inspection, work as B _iwhen=0, to A _ibe respectively 0 ~ 90 kind of situation inspection to draw, S _i=A _i, J _i=0; Work as B _i=1, draw with upper type inspection, work as A _iwhen>=1, S _i=A _i-1, J _i=0, work as A _iwhen=0, S _i=9, J _i=9; Work as B _iwhen=2, inspection draws, works as A _iwhen>=2, S _i=A _i-2, J _i=0, work as A _iduring < 2, S _i=A _i+ 8, J _i=9; ‥ ‥ ‥ works as B _iwhen=8, inspection draws, works as A _iwhen>=8, S _i=A _i-8, J _i=0, work as A _iduring < 8, S _i=A _i+ 2, J _i=9; Work as B _iwhen=9, inspection draws, works as A _iwhen=9, S _i=0, J _i=0, work as A _iduring < 9, S _i=A _i+ 1, J _i=9; J _i=9 indicate borrow, J _i=0 indicates without borrow, g _{/ hj}and J _ipipe P respectively _e2grid input and drain electrode export, and observe Figure 11 ~ 14 and find out, g _{/ hj}amplitude is little, J _iamplitude is large, g _{/ hj}and J _imutually anti-phase; Inspection shows that 10 value half-subtracter circuit diagrams 3 meet the result of 10 value subtractions; Figure 15 is a kind of 10 value half-subtracters of the present invention circuit control signal oscillograms during 180 ~ 410 μ s, and waveform from top to bottom precedence is: A _i, B _i, v _tg9, v _tg8, v _tg7, v _tg6, v _tg5, v _tg4, v _tg3, v _tg2, v _tg1, v _tg0, under control signal effect, complete above-mentioned computing, wherein V _dC=6.5V, V _d=5V.

Fig. 4 is 10 value half adder circuit figure of the present invention, Pspice computer simulation is carried out to Fig. 4,1. the signal voltage working waveform figure of 10 value half adder circuits during 180 ~ 410 μ s shown in Figure 16 is first simulated, can its course of work of whole observation, waveform from top to bottom precedence is: A _i, B _i, S _i, C _iand g _{/ hj}, wherein A _iand B _iit is identical that cycle and waveform and aforementioned 10 are worth half-subtracter; 2. for A can be checked clearly _iand B _ithe result of add operation during all probable values, Figure 16 transverse axis is amplified, signal voltage working waveform figure during drawing 180 ~ 240 μ s, during 240 ~ 300 μ s, during 300 ~ 360 μ s and during 350 ~ 410 μ s, show as Figure 17,18,19 and 20 respectively, observe Figure 17 ~ 20 successively, and at A _iand B _istablize moment inspection, work as B _iwhen=0, to A _ibe respectively 0 ~ 90 kind of situation inspection to draw, S _i=A _i, C _i=9; Work as B _i=1, inspection draws, works as A _iduring < 9, S _i=A _i+ 1, C _i=9, work as A _iwhen=9, S _i=0, C _i=0; Work as B _iwhen=2, inspection draws, works as A _iduring < 8, S _i=A _i+ 2, C _i=9, work as A _iwhen>=8, S _i=A _i-8, C _i=0; ‥ ‥ ‥ works as B _iwhen=8, inspection draws, works as A _iduring < 2, S _i=A _i+ 8, J _i=9, work as A _iwhen>=2, S _i=A _i-2, C _i=0; Work as B _iwhen=9, inspection draws, works as A _iwhen=0, S _i=9, C _i=9, work as A _iwhen>=1, S _i=A _i-1, C _i=0; C _i=9 represent no-carry, C _i=0 indicates carry, g _{/ hj}and C _ipipe P respectively _e2grid input and drain electrode export, and observe Figure 17 ~ 20 and find out, g _{/ hj}amplitude is little, C _iamplitude is large, g _{/ hj}and C _imutually anti-phase; Inspection shows that 10 value half adder circuit Fig. 4 meet the result of 10 value add operations.Figure 21 is a kind of 10 value half adders of the present invention circuit control signal oscillograms during 180 ~ 410 μ s, and waveform from top to bottom precedence is: A _i, B _i, v _tg9, v _tg8, v _tg7, v _tg6, v _tg5, v _tg4, v _tg3, v _tg2, v _tg1, v _tg0, under control signal effect, complete above-mentioned computing, notice that Figure 21 and Figure 15 control signal waveform is different, v in two figure _tg9~ v _tg1waveform has difference, meets 10 value half-subtracters and half adder feature.

Embodiment 7:PMOS pipe racks is logical, high pass, low pass variable threshold circuit and neuron mos management and control threshold technology compare.

Threshold voltage is taken as the mid point of the break over region between pipe conducting and cut-off, in fact can not distinguish metal-oxide-semiconductor conducting and cut-off in break over region, therefore break over region can be considered threshold value confusion region; Draw thus, (1) the equivalent threshold value confusion region of PMOS high pass variable threshold circuit does not increase with K value and changes, it, to K value signal input resolution higher than neuron mos pipe (neuron mos pipe equivalence threshold value confusion region increases with the increase of K value), allows signal input corresponding standard value to have certain departing from; (2) although PMOS high pass variable threshold circuit 2 (or 4) individual metal-oxide-semiconductor and 1 resistance R ₁, but several metal-oxide-semiconductor to account for silicon area much less than neuron mos pipe electric capacity, R ₁(available constant-current source replacement) is the drive singal forming controlled PMOS conducting, to R ₁required precision is extremely low; And neuron mos pipe utilizes capacitively coupled to change threshold voltage, require very high to capacitance accuracy, increase the difficulty realized; (3) PMOS high pass variable threshold circuit input capacitance is much less than neuron mos pipe input capacitance, and high frequency performance is better.Neuron mos management and control threshold technology has very large shortcoming; Neuron mos pipe has following formula:

$V_{\mathrm{fg}}=(Q_0+C_1{V}_1+\underset{j=2}{\overset{n}{\mathrm{\&Sigma;}}}{C}_j{V}_j)/C_{\mathrm{TOT}},C_{\mathrm{TOT}}=C_0+\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{C}_i{V}_j---\left(14\right)$

Wherein V _fgfor floating gate, V ₁for signal input gate voltage, V _jfor control-grid voltage, threshold value according to demand selects direct voltage V _j(j=2,3,4 ..., n), formula (14) only has V _fgand V ₁two variablees, differential draws, dV _fg=(C ₁/ C _tOT) dV ₁; Floating boom threshold value confusion region width Delta V _fgwith the threshold value confusion region width Delta V of input grid ₁meet,

ΔV _fg＝(C ₁/C _TOT)ΔV ₁，ΔV ₁＝(C _TOT/C ₁)ΔV _fg ( ¹⁵)

Increase with K value, need the number changing input grid threshold value to increase, the ratio C of requirement _tOT/ C ₁increase, and Δ V in formula (15) ₁Δ V _fgc _tOT/ C ₁doubly, width Delta V _fgdetermine, so Δ V ₁increase, show thus: increase with K value, 1. input the threshold value confusion region width Delta V of grid ₁increase, input grid K value signal resolution capability is reduced, use when being unfavorable for large K value; 2. ratio C _tOT/ C ₁increase, C ₁can not reduce, then all control gate electric capacity accounts for silicon area increase; Such as 10 value circuit, K=10, C ₀=C _fg=30fF, C ₁=0.8pF, calculating input control grid total capacitance is 9.37pF (C _tOT=11.33C ₁); SiO between floating boom NMOS tube control gate and floating boom ₂thickness is 35nm, and corresponding specific capacitance is 1fF/ μm ², 9.37pF electric capacity takies silicon area 9370 μm ², a NMOS tube accounts for 30 μm ², the electric capacity of the 9.37pF of a neuron mos pipe takies the area of about 312 NMOS tube, and namely to account for silicon area very large for control gate electric capacity.With the development of semiconductor integrated circuit technology, metal-oxide-semiconductor size is more and more less, and neuron mos management and control gate capacitance area is inevitable increasing to the area ratio of NMOS tube.3. neuron mos tube grid loop adds too much electric capacity to high frequency performance is harmful, characteristic size reduces and the increase of metal connecting line depth-width ratio causes interconnection capacitance to increase, cause multiple-grid interpolar cross-interference issue, and parasitic capacitance strengthens, produce extra interconnect delay and power consumption, show that it is harmful for adding too much electric capacity to high frequency performance.4. the electric leakage of neuron mos pipe floating gate capacitance can not be omitted.Common nonvolatile memory is 2.85x10 at leakage current ^-22when A, threshold voltage reduces 3V needs 10 years altogether.Increase with K value, require that threshold voltage drop low amplitude is very little, obviously do not allow to reduce 3V, show that ' that to be 0 ' be neuron mos pipe is desirable with unpractical based on floating gate capacitance electric leakage.5. neuron CMOS inverter is 0 to binary signal quiescent dissipation, increases with K value, there is the state of NMOS tube and PMOS conducting simultaneously in K value signal, and result quiescent dissipation is larger, conducting during difference when only having K value signal minimum and maximum value, and quiescent dissipation is 0; 6. neuron CMOS follower often exports is capacitive load, and output voltage lifting track is different, has very large hysteresis voltage, is unfavorable for using in K value circuit.Neuron mos pipe threshold confusion region width is Δ V ₁, Δ V when K value is large ₁c is increased by formula (15) _tOT/ C ₁doubly, Δ V ₁may be close to or more than the stepped-up voltage of K value signal, make neuron mos tube failure.

Claims (6)

1. adopt a construction method for the K value half-subtracter of the logical threshold loading technique of band, it is characterized in that: A in K value half-subtracter _ifor minuend, B _ifor subtrahend, S _ifor this is for poor, J _ifor borrow, wherein A _i, B _i, S _ibe K value signal, K value signal has K logical value: 0,1,2 ..., L, wherein L=K-1, K=4,5,6 ..., J _ibe 2 value signals, 2 value signals have 2 logical value: 0, L; Make A _i=k, B _i=j, to the j=1 ~ L determined, as k < j, S _i=K+k-j > k, i.e. S _i> A _i, as k=j, S _i=0, as k > j and j ≠ L time, S _i=k-j < k, i.e. S _i< A _i, as j=L, there is not k > j; To the j=0 determined, S _i=A _i; To j ≠ 0, as k < j, there is borrow, as k>=j, without borrow, to j=0, without borrow; The construction method of the K value half-subtracter of the logical threshold loading technique of band is adopted to be described below:

1. to the j determined, j=1 ~ L, by S _i> A _iand S _i< A _i, the computing of K value half-subtracter is divided into Spring layer and low value district, because of t _{b0 ~ j-1}=t _{/ hj}, t _{bj+1 ~ L}=t _hj+1(j ≠ L), adopts the controlled PMOS P of gating _e0and P _e1, P _e0there is low pass threshold t _{/ hj}characteristic, P _e1there is high pass threshold t _hj+1characteristic, (1) Spring layer: as k=0 ~ j-1, pipe P _e0conducting, realizes S _i> A _i; (2) low value district: as k=j+1 ~ L and j ≠ L time, pipe P _e1conducting, realizes S _i< A _i, as j=L, low value district is invalid, and only Spring layer is effective; As k=j, pipe P _e0, P _e1, P _d0all end, S _i=0; (3) use P _e2the PMOS not gate of composition exports and forms J _isignal, pipe P _e2grid adapter P _e0grid g _{/ hj}, as k < j, pipe P _e2conducting, J _ifor high level, indicate borrow, as k>=j, pipe P _e2cut-off, J _ifor low level, indicate without borrow;

2. Spring layer circuit comprises band general formula variable threshold PMOS P _a00~ P _a0L-1with the diode D of series connection ₀₀~ D _0L-1, pipe P _a01~ P _a0L-1high pass threshold be followed successively by t _h1~ t _hL-1, pipe P _a00low pass threshold be t _{/ h1}, pipe P _a00~ P _a0L-1source electrode passes through P _e0switch on power V _dC, when k=j-1 ~ 0 and j ≠ 0 time, pipe P _e0conducting, S _iexport through m ₀individual conducting diode is switched to V _dC, with k by j-1 to 0, use pipe P _a0j-1~ P _a00conducting control m successively ₀by 0 to j-1, so S _iby L to L-j+1; Low value district circuit comprises high general formula variable threshold PMOS P _a11~ P _a1Lwith the diode D of series connection ₁₂~ D _1L, by D _1Lmeet D ₀₀, make D ₁₂~ D _1Land D ₀₀~ D _0L-1form a total series diode sequence D ₁₂~ D _0L-1, pipe P _a11~ P _a1Lhigh pass threshold be followed successively by t _h1~ t _hL, as k=L ~ j+1 and 0<j<L time, pipe P _e1conducting, pipe P _a11~ P _a1Lsource electrode pass through P _e1switch on power V _dC, S _iexport through m ₁individual conducting diode is switched to V _dC, with k by L to j+1, use pipe P _a1L~ P _a1j+1conducting control m successively ₁by j to L-1, so S _iexport by L-j to 1; When k=j ≠ 0, pipe P _e0, P _e1, P _d0all end, S _ioutput is 0;

3. to each j, j=0 ~ L, door U is differentiated by K logical value ₀~ U _ldifferentiate j value, logical value differentiates door U _mthe logical threshold of band is t _bjbe exactly ' only work as U _mu when being input as j _mexport as high level, otherwise, U _mexport as low level ', get U ₀~ U _lband lead to threshold and be respectively t _b0~ t _bL; All U ₀~ U _lbe input as j, U ₀~ U _loutput is respectively v _tg0~ v _tgL, v _tg0~ v _tgLrespectively hang oneself not gate M ₀~ M _lproduce anti-phase output v _{/ tg0}~ v _{/ tgL}; Complete thus: (1) to j ≠ 0, at variable threshold gating PMOS P _c1~ P _cLmiddle v _{/ tgj}drive P _cjconducting, pipe P _c1~ P _cLsource electrode threshold value to be passed is respectively t _{/ h1}~ t _{/ hL}, then pipe P _c1~ P _cLin only t _{/ h1}~ t _{/ hL}in t _{/ hj}be loaded into pipe P _e0, use pipe P _e0conducting controls Spring layer (0, j-1) length j, j ≠ 0; During j=L, Spring layer length is L; (2) to j ≠ 0, at variable threshold gate tube P _d1~ P _dLmiddle v _{/ tgj}drive P _djconducting, pipe P _d1~ P _dL-1, P _dLsource electrode threshold value to be passed is respectively t _h2~ t _hL, t _{/ h1}, as j < L, pipe P _d1~ P _dL-1in only make t _h2~ t _hLin t _hj+1be loaded into pipe P _e1; As j=L, pipe P _dLby t _{/ h1}be loaded into pipe P _e1, make low value district invalid; Use pipe P _e1and P _d0conducting controls low value district (j+1 ~ L) length L-j, j ≠ L; (3) at cmos transmission gate TG ₁~ TG _lmiddle v _tgjand v _{/ tgj}only drive TG _jconducting, j=1 ~ L, S _iby the TG of conducting _jmeet P _a0j-1drain electrode, S _imaximum condition is k=j-1, now S _iby the TG of conducting _jand P _a0j-1receive V _dC, realize S _i=L; (4), as j=0, use v _{/ tg0}drive TG ₀with pipe P _d0, P _c0conducting, P _d0source electrode meets V _dC, P _d0drain electrode adapter P _a11~ P _a1Lsource electrode, pipe P _a11~ P _a1Lsource electrode passes through P _d0be switched to V _dC, S _ipass through TG ₀meet P _a1Ldrain electrode, low value district circuit working and become digital follower, realizes S _i=A _i, now low value section length is L, Spring layer circuit malfunction; Pipe P _c0grid meets v _{/ tg0}, P _c0drain electrode meets P _e0grid, pipe P _c0source electrode meets direct voltage V _dC, J when making j=0 _iexport as the above-mentioned level indicated without borrow, J when supplementing 1. the j=0 lacked _ithe formation of signal.

2. a kind of a kind of construction method adopting the K value half adder of the logical threshold loading technique of band adopting the construction method same characteristic features of the K value half-subtracter of the logical threshold loading technique of band to be formed according to claim 1, it is characterized in that: in the construction method of K value half-subtracter adopting the logical threshold loading technique of band: (i) first, by U ₁~ U _lband lead to threshold and be taken as t respectively _bL~ t _b1; (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', by all there being borrow to be taken as no-carry, be taken as carry without borrow, pipe P _c0source electrode meets direct voltage V _d, C when making j=0 _iexport the level for above-mentioned expression no-carry, V _d≠ V _dC; (iii) last, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then adopt the construction method of the K value half-subtracter of the logical threshold loading technique of band just to become the construction method adopting band to lead to the K value half adder of threshold loading technique.

3. a kind of a kind of K value half-subtracter circuit adopting the logical threshold loading technique of band adopting the construction method of the K value half-subtracter of the logical threshold loading technique of band to be formed according to claim 1, it is characterized in that: the K value half-subtracter circuit that described employing band leads to threshold loading technique comprises: control signal forms circuit, Spring layer and high gating circuit, low value district and low gating circuit, S _ioutput circuit and J _ioutput circuit, K value half-subtracter particular circuit configurations is described below:

1. control signal forms circuit by logical value differentiation door U ₀~ U _lwith CMOS not gate M ₀~ M _ltwo part compositions, differentiate door U ₀~ U _lrespectively by the band general formula variable threshold PMOS P that interval is minimum _b0~ P _bLwith constant-current source I ₀~ I _lform, pipe P _b0~ P _bLband lead to threshold and be respectively t _b0~ t _bL, wherein t _b0=t _{/ h1}, t _bL=t _hL, i.e. pipe P _b0and P _bLbe respectively interval minimum low general formula and high general formula variable threshold PMOS, pipe P _b0~ P _bLeffective input all meet B _i, pipe P _b0~ P _bLsource electrode meets power supply V _dC, pipe P _b0~ P _bLdrain electrode meets constant-current source I respectively ₀~ I _lupper end, I ₀~ I _lupper end is respectively as U ₀~ U _lexport v _tg0~ v _tgL, constant-current source I ₀~ I _llower end ground connection, constant-current source electric current is all flow to lower end, v by upper end _tg0~ v _tgLmeet not gate M respectively ₀~ M _linput, M ₀~ M _loutput is respectively v _{/ tg0}~ v _{/ tgL}, draw control signal v anti-phase each other thus _tg0~ v _tgLand v _{/ tg0}~ v _{/ tgL}, M ₀~ M _loperating voltage is V _dC, to each B _iinput j, j=0 ~ L, v _tg0~ v _tgLin only v _tgjbe high level, all the other outputs are all low levels;

2. Spring layer and high gating circuit: high gating circuit is by variable threshold gating PMOS P _c1~ P _cL, the controlled PMOS P of gating _e0with PMOS P _c0composition; Pipe P _c1~ P _cLsource electrode low pass threshold to be passed is respectively t _{/ h1}~ t _{/ hL}, pipe P _c1~ P _cLeffective input meet A _i, pipe P _c0~ P _cLgrid meets control signal v respectively _{/ tg0}~ v _{/ tgL}, and its drain electrode all adapter P _e0grid g _{/ hj}; To each B _iinput j, j=1 ~ L, pipe P _c1~ P _cLin only have a pipe P _cjconducting, all the other pipes end, so at t _{/ h1}~ t _{/ hL}in only by t _{/ hj}be loaded into pipe P _e0, pipe P _e0source electrode meets V _dC, its drain electrode adapter P _a00~ P _a0L-1source electrode; Spring layer circuit comprises the logical variable threshold PMOS P of band _a00~ P _a0L-1with series diode D ₀₀~ D _0L-1, pipe P _a01~ P _a0L-1high pass threshold be followed successively by t _h1~ t _hL-1, pipe P _a00low pass threshold be t _{/ h1}, pipe D ₀₀~ D _0L-2negative pole is adapter D separately ₀₁~ D _0L-1positive pole, pipe P _a00~ P _a0L-1effective input meets A _i, pipe P _a00~ P _a0L-1drain electrode adapter D separately ₀₀~ D _0L-1negative pole, A _ibe input as k, as k=0 ~ j-1 and j ≠ 0 time, pipe P _e0conducting, by pipe P _a00~ P _a0L-1source electrode passes through P _e0connect V _dC, Spring layer circuit working, uses pipe P _e0conducting controls Spring layer (0, j-1) length j, j ≠ 0, as k=j ~ L, and pipe P _e0cut-off, pipe P _a00~ P _a0L-1source electrode and V _dCdisconnect, Spring layer circuit does not work;

3. low value district and low gating circuit: low gating circuit is by variable threshold gating PMOS P _d1~ P _dL, the controlled PMOS P of gating _e1with PMOS P _d0composition; Pipe P _d1~ P _dL-1source electrode high pass threshold to be passed is respectively t _h2~ t _hL, P _dLsource electrode low pass threshold to be passed is t _{/ h1}; Pipe P _d0~ P _dLgrid meets control signal v respectively _{/ tg0}~ v _{/ tgL}, P _d1~ P _dLdrain electrode adapter P _e1grid, P _d1~ P _dLeffective input meets A _i; To each j, j=1 ~ L-1, pipe P _d1~ P _dL-1in only have a pipe P _djconducting, all the other pipes end, at t _h2~ t _hLin choose t _hj+1be loaded into pipe P _e1, and j=L, pipe P _dLconducting, t _{/ h1}be loaded into pipe P _e1; Pipe P _e1and P _d0drain electrode adapter P _a11~ P _a1Lsource electrode, P _e1and P _d0source electrode meets V _dC; As k=j+1 ~ L and 0<j<L time, pipe P _e1conducting, pipe P _a11~ P _a1Lsource electrode passes through P _e1connect V _dC, low value district circuit working; Low value district circuit comprises high pass variable threshold PMOS P _a11~ P _a1Lwith series diode D ₁₂~ D _1L, pipe D ₁₂~ D _1L-1negative pole is adapter D separately ₁₃~ D _1Lpositive pole, D _1Lnegative pole meets D ₀₀positive pole, by D ₁₂~ D _1Land D ₀₀~ D _0L-1series connection, forms 2L-1 series diode sequence, pipe P _a11~ P _a1Lhigh pass threshold be t separately _h1~ t _hL, it effectively inputs and meets A _i, pipe P _a12~ P _a1Ldrain electrode adapter D separately ₁₂~ D _1Lnegative pole, pipe P _a11drain electrode meets D ₁₂positive pole; As j=0, pipe P _d0conducting, pipe P _a11~ P _a1Lsource electrode passes through P _d0connect V _dC, Spring layer circuit is invalid, low value district circuit working and be formed as digital follower, uses pipe P _e1and P _d0conducting controls low value district (j+1, L) length L-j, j ≠ L; As k=0 ~ j and j ≠ L time, pipe P _e1cut-off, pipe P _a11~ P _a1Lsource electrode and V _dCdisconnect, low value district circuit does not work; To j=L, when k ≠ 0, pipe P _e1cut-off, and as k=0, pipe P _e1conducting, pipe P _a11~ P _a1Lfull cut-off, low value district circuit is invalid, Spring layer circuit working;

4. S _ioutput circuit and J _ioutput circuit; S _ioutput circuit is by cmos transmission gate TG ₀~ TG _lwith constant-current source I _sicomposition, transmission gate TG ₁~ TG _linput adapter P respectively _a00~ P _a0L-1drain electrode, TG ₀input adapter P _a1Ldrain electrode, TG ₀~ TG _lexport and all meet constant-current source I _siupper end, I _siupper end is as S _iexport, I _silower end ground connection, TG ₀~ TG _lpositive control end and negative control end meet v respectively _tg0~ v _tgLand v _{/ tg0}~ v _{/ tgL}, N is V _don, to each j, j=1 ~ L, at TG ₁~ TG _lin only have a TG _jconducting, S _iby the TG of conducting _jmeet P _a0j-1drain electrode, to j=0, S _iby the TG of conducting ₀adapter P _a1Ldrain electrode; Choose V _dC=LV _don+ △, △ are the side-play amount that K value storage unit circuit characteristic requirements compensates;

J _ioutput circuit is by PMOS P _e2with constant-current source I _cicomposition, pipe P _e2source electrode meets V _dC, pipe P _e2grid adapter P _e0grid g _{/ hj}, pipe P _e2drain electrode meets constant-current source I _ciupper end, I _ciupper end is as J _iexport, I _cilower end ground connection, pipe P _c0grid meets v _{/ tg0}, P _c0drain electrode meets P _e0grid; To j ≠ 0, as k < j, pipe P _e0grid g _{/ hj}voltage V _g/hj< V _dC, pipe P _e2conducting, J _iexport as high level V _dC, indicate borrow, as k>=j, V _g/hj=V _dC, pipe P _e2cut-off, J _iexport as low level 0, indicate without borrow; Pipe P _c0source electrode meets direct voltage V _dC, J when making j=0 _iexport as the above-mentioned level indicated without borrow; All constant-current source senses of current flow to lower end by upper end.

4. a kind of a kind of K value half adder circuit adopting the logical threshold loading technique of band adopting the K value half-subtracter circuit same characteristic features of the logical threshold loading technique of band to be formed according to claim 3, is characterized in that: in described K value half-subtracter circuit, (i) first, by U ₁~ U _lband lead to threshold and be taken as t respectively _bL~ t _b1; (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', by all there being borrow to be taken as no-carry, be taken as carry without borrow, pipe P _c0source electrode meets direct voltage V _d, C when making j=0 _iexport the level for above-mentioned expression no-carry, V _dC-V _d=1.5 volts; (iii) last, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then adopt the K value half-subtracter circuit of the logical threshold loading technique of band just to become the K value half adder circuit adopting band to lead to threshold loading technique.

5. a kind of a kind of K value half-subtracter circuit adopting the logical threshold loading technique of band adopting the construction method of the K value half-subtracter of the logical threshold loading technique of band to be formed according to claim 3, it is characterized in that: lead in the K value half-subtracter circuit of threshold loading technique at described employing band, get K=10, then draw a kind of 10 value half-subtracter circuit adopting the logical threshold loading technique of band, 10 value half-subtracter circuit comprise: control signal forms circuit, Spring layer and high gating circuit, low value district and low gating circuit, S _ioutput circuit and J _ioutput circuit; 10 value half-subtracter particular circuit configurations are described below:

1. control signal forms circuit by logical value differentiation door U ₀~ U ₉with CMOS not gate M ₀~ M ₉two part compositions, differentiate door U ₀~ U ₉respectively by the band general formula variable threshold PMOS P that interval is minimum _b0~ P _b9with constant-current source I ₀~ I ₉form, pipe P _b0~ P _b9band lead to threshold and be respectively t _b0~ t _b9, wherein t _b0=t _{/ h1}, t _b9=t _h9, i.e. pipe P _b0and P _b9be respectively interval minimum low general formula and high general formula variable threshold PMOS, pipe P _b0~ P _b9effective input all meet B _i, pipe P _b0~ P _b9source electrode meets power supply V _dC, pipe P _b0~ P _b9drain electrode meets constant-current source I respectively ₀~ I ₉upper end, I ₀~ I ₉upper end is respectively as U ₀~ U ₉export v _tg0~ v _tg9, constant-current source I ₀~ I ₉lower end ground connection, constant-current source electric current is all flow to lower end, v by upper end _tg0~ v _tg9meet not gate M respectively ₀~ M ₉input, M ₀~ M ₉output is respectively v _{/ tg0}~ v _{/ tg9}, draw control signal v anti-phase each other thus _tg0~ v _tg9and v _{/ tg0}~ v _{/ tg9}, M ₀~ M ₉operating voltage is V _dC, to each B _iinput j, j=0 ~ 9, v _tg0~ v _tg9in only v _tgjbe high level, all the other outputs are all low levels;

2. Spring layer and high gating circuit: high gating circuit is by variable threshold gating PMOS P _c1~ P _c9, the controlled PMOS P of gating _e0with PMOS P _c0composition; Pipe P _c1~ P _c9source electrode low pass threshold to be passed is respectively t _{/ h1}~ t _{/ h9}, pipe P _c1~ P _c9effective input meet A _i, pipe P _c0~ P _c9grid meets control signal v respectively _{/ tg0}~ v _{/ tg9}, and its drain electrode all adapter P _e0grid g _{/ hj}; To each B _iinput j, j=1 ~ 9, pipe P _c1~ P _c9in only have a pipe P _cjconducting, all the other pipes end, so at t _{/ h1}~ t _{/ h9}in only by t _{/ hj}be loaded into pipe P _e0, pipe P _e0source electrode meets V _dC, its drain electrode adapter P _a00~ P _a08source electrode; Spring layer circuit comprises the logical variable threshold PMOS P of band _a00~ P _a08with series diode D ₀₀~ D ₀₈, pipe P _a01~ P _a08high pass threshold be followed successively by t _h1~ t _h8, pipe P _a00low pass threshold be t _{/ h1}, pipe D ₀₀~ D ₀₇negative pole is adapter D separately ₀₁~ D ₀₈positive pole, pipe P _a00~ P _a08effective input meets A _i, pipe P _a00~ P _a08drain electrode adapter D separately ₀₀~ D ₀₈negative pole; A _ibe input as k, as k=0 ~ j-1 and j ≠ 0 time, pipe P _e0conducting, by pipe P _a00~ P _a08source electrode passes through P _e0connect V _dC, Spring layer circuit working, uses pipe P _e0conducting controls Spring layer (0, j-1) length j, j ≠ 0, when k=j ~ 9, and pipe P _e0cut-off, pipe P _a00~ P _a08source electrode and V _dCdisconnect, Spring layer circuit does not work;

3. low value district and low gating circuit: low gating circuit is by variable threshold gating PMOS P _d1~ P _d9, the controlled PMOS P of gating _e1with PMOS P _d0composition; Pipe P _d1~ P _d8source electrode high pass threshold to be passed is respectively t _h2~ t _h9, P _d9source electrode low pass threshold to be passed is t _{/ h1}; Pipe P _d0~ P _d9grid meets control signal v respectively _{/ tg0}~ v _{/ tg9}, pipe P _d1~ P _d9drain electrode adapter P _e1grid, pipe P _d1~ P _d9effective input meets A _i; To each j, j=1 ~ 8, pipe P _d1~ P _d8in only have a pipe P _djconducting, all the other pipes end, at t _h2~ t _h9in choose t _hj+1be loaded into pipe P _e1, and j=9, pipe P _d9conducting, t _{/ h1}be loaded into pipe P _e1; Pipe P _e1and P _d0drain electrode adapter P _a11~ P _a19source electrode, pipe P _e1and P _d0source electrode meets V _dC; When k=j+1 ~ 9 and 0<j<9 time, pipe P _e1conducting, by pipe P _a11~ P _a19source electrode passes through P _e1connect V _dC, low value district circuit working; Low value district circuit comprises the logical variable threshold PMOS P of band _a11~ P _a19with series diode D ₁₂~ D ₁₉, pipe D ₁₂~ D ₁₈negative pole is adapter D separately ₁₃~ D ₁₉positive pole, D ₁₉negative pole meets D ₀₀positive pole, by D ₁₂~ D ₁₉and D ₀₀~ D ₀₈series connection, forms 17 series diode sequences, pipe P _a11~ P _a19high pass threshold be t separately _h1~ t _h9, it effectively inputs and meets A _i, pipe P _a12~ P _a19drain electrode adapter D separately ₁₂~ D ₁₉negative pole, pipe P _a11drain electrode meets D ₁₂positive pole; As j=0, pipe P _d0conducting, pipe P _a11~ P _a19source electrode passes through P _d0connect V _dC, Spring layer circuit is invalid, low value district circuit working and be formed as digital follower, uses pipe P _e1and P _d0conducting controls low value district (j+1,9) length 9-j, j ≠ 9; As k=0 ~ j and j ≠ 9 time, pipe P _e1cut-off, pipe P _a11~ P _a19source electrode and V _dCdisconnect, low value district circuit does not work; To j=9, when k ≠ 0, pipe P _e1cut-off, and as k=0, pipe P _e1conducting, pipe P _a11~ P _a19full cut-off, low value district circuit is invalid, Spring layer circuit working;

4. S _ioutput circuit and J _ioutput circuit; S _ioutput circuit is by cmos transmission gate TG ₀~ TG ₉with constant-current source I _sicomposition, transmission gate TG ₁~ TG ₉input adapter P respectively _a00~ P _a08drain electrode, TG ₀input adapter P _a19drain electrode, TG ₀~ TG ₉export and all meet constant-current source I _siupper end, I _siupper end is as S _iexport, I _silower end ground connection, TG ₀~ TG ₉positive control end and negative control end meet v respectively _tg0~ v _tg9and v _{/ tg0}~ v _{/ tg9}, N is V _don, at TG ₁~ TG ₉in, to each j, j=1 ~ 9, only have a TG _jconducting, S _iby the TG of conducting _jmeet P _a0j-1drain electrode, to j=0, S _iby the TG of conducting ₀adapter P _a19drain electrode; Choose V _dC=9V _don+ △, △ are the side-play amount that K value storage unit circuit characteristic requirements compensates;

J _ioutput circuit is by PMOS P _e2with constant-current source I _cicomposition, pipe P _e2source electrode meets V _dC, pipe P _e2grid adapter P _e0grid g _{/ hj}, pipe P _e2drain electrode meets constant-current source I _ciupper end, I _ciupper end is as J _iexport, I _cilower end ground connection, pipe P _c0grid meets v _{/ tg0}, P _c0drain electrode meets P _e0grid; To j ≠ 0, as k < j, pipe P _e0grid g _{/ hj}voltage V _g/hj< V _dC, pipe P _e2conducting, J _iexport as high level V _dC, indicate borrow, as k>=j, V _g/hj=V _dC, pipe P _e2cut-off, J _iexport as low level 0, indicate without borrow; Pipe P _c0source electrode meets direct voltage V _dC, J when making j=0 _iexport as the above-mentioned level indicated without borrow; All constant-current source senses of current flow to lower end by upper end.

6. a kind of a kind of 10 value half adder circuits adopting the logical threshold loading technique of band adopting 10 value half-subtracter circuit same characteristic features of the logical threshold loading technique of band to be formed according to claim 5, it is characterized in that: lead in 10 value half-subtracter circuit of threshold loading technique at described employing band, (i) first, by U ₁~ U ₉band lead to threshold and be taken as t respectively _b9~ t _b1; (ii) then, by borrow J _ibe taken as carry digit C _i, except ' being taken as no-carry without borrow during j=0 ', by all there being borrow to be taken as no-carry, be taken as carry without borrow, pipe P _c0source electrode meets direct voltage V _d, C when making j=0 _iexport the level for above-mentioned expression no-carry, V _dC-V _d=1.5 volts; (iii) last, half-subtracter is taken as half adder, by A _i, B _iand S _ibe taken as summand successively, addend and one's own department or unit and, then adopt 10 value half-subtracter circuit of the logical threshold loading technique of band just to become the 10 value half adder circuits adopting band to lead to threshold loading technique.