CN104300965B - Using the K values of band logical threshold loading technique and the construction method and its circuit of ten value half adders and half-subtracter - Google Patents

Abstract

The invention discloses a construction method and circuit of a K-value and ten-value half-adder and half-subtractor using band-pass threshold loading technology; The required band-pass threshold of the stage is loaded into the PMOS tube, so that the PMOS tube has a band-pass threshold variable at any time; the present invention analyzes the K value half subtractor and half adder, and draws the characteristics of the unity of the high value area and the low value area , based on the loading technology, the two circuits can be classified into a unified circuit design, which avoids the traditional way of implementing K-valued logic gates, and greatly simplifies the circuit structure; the chaotic encryption method and circuit can be extended from 2 values to K values, Use K value addition and subtraction operations instead of K value multiplication and division operations to realize the non-multiplication and division chaotic encryption method and circuit of K value information; it is used in VLSI and other digital IC technology fields such as FPGA, CPLD, semi-or full-specified ASIC and memory.

Description

Construction methods of K-value and ten-value half-adders and half-subtractors using band-pass threshold loading technique method and circuit

technical field

The invention belongs to the field of digital integrated circuits, in particular to a construction method of a K-value and ten-value half-adder and half-subtractor using band-pass threshold loading technology and a circuit thereof.

Background technique

With the rapid development of MOS integrated circuit technology, the scale of integration is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70℅ of silicon Chip area; in programmable logic devices, a large number of programmable internal wiring is also required to connect each logic function block or input/output to complete a specific function circuit, and wiring accounts for a large cost of materials. Reducing wiring costs becomes an important issue. ② From the perspective of information transmission, the use of multi-valued signals can reduce the number of connections; for each connection to transmit digital information, binary signals carry the lowest amount of information, and multi-valued signals carry more information than binary signals. ③ From the perspective of information storage, the use of multi-value signals can increase the information storage density, and the gate capacitance of MOS transistors is used to store information. The amount of stored information is larger than that of binary values. Multi-value DRAM can greatly increase the information storage density than binary DRAM. At present, the development of multi-value devices has been widely carried out. Toshiba and SanDisk of the United States have adopted 43nm technology and 16gbit NAND flash memory realized by 2bit/unit multi-value technology. The 8Gbit product developed by Samsung adopts 63nm CMOS technology and 2bit/unit multi-value technology. The successful development and commercialization of 4-value memory is an important step in multi-value research. The development of multi-value devices needs to control or change the switching threshold V _tn of the transistor.

Existing technology and existing problems:

1. In the realization of multi-valued circuits (K≥3), the existing semiconductor manufacturing process to control the threshold of MOS transistors has great disadvantages: ① The range of the control threshold is limited (due to the limited concentration of ion implantation), and the range of the control threshold in the process is often By changing the performance of the MOS tube, the voltage-type multi-valued circuit realized is not larger than the 4-valued circuit, and the application of more-valued circuits is difficult. ② Only the magnitude of the threshold can be controlled, and the opening properties of the MOS tube cannot be changed (such as high-pass, low-pass, band-pass, band-resistance control threshold), and the multi-valued circuit must have a variety of MOS tubes with threshold-controlling properties to make the circuit structure most optimal. simple. ③ It is necessary to add an additional process of ion implantation, and the threshold can only be controlled in the semiconductor manufacturing process, increasing the complexity of the process, and the threshold cannot be controlled by the user.

2. In the realization of multi-valued circuits, the existing neuron MOS transistor control threshold technology has great disadvantages: ① With the increase of K value, 'the input gate and control gate capacitance of a single neuron MOS transistor occupies the area of the silicon chip' versus 'a single neuron MOS transistor'. The ratio of MOS transistors to the area of the silicon chip is getting bigger and bigger, ten times, a hundred times or higher; ②As the K value increases, the width of the threshold fuzzy area (turning area) of the input gate ΔV ₁ 'to the threshold fuzzy area of the floating gate (Turning area) The ratio of the width ΔV _fg ' (ΔV ₁ /ΔV _fg = C _TOT /C ₁ ) is getting bigger and bigger, because ΔV _fg is constant, the width of the threshold fuzzy zone ΔV ₁ of the input grid is getting bigger and bigger, so that The input gate K value signal resolution ability is getting lower and lower, and the requirement for capacitance accuracy is high, which is not conducive to the reliable realization of multi-valued circuits with large K value; ③The threshold control characteristics cannot be changed (such as band-pass and band-stop control threshold methods) , which is unfavorable to simplify the K value circuit; ④ With the increase of K value, the ratio (C _TOT /C ₁ ) becomes larger, and the capacitance of the input grid and the control grid increases, so that the high frequency performance drops rapidly; ⑤ With the increase of K value, the floating gate Capacitor leakage cannot be ignored, and it is difficult to refresh multi-valued information. ⑥The static power consumption of the neuron CMOS inverter is 0 only for the binary signal. For a large K value, there is a state where the NMOS tube and the PMOS tube are turned on at the same time, and the static power consumption is even greater; the output of the neuron CMOS follower is usually For capacitive loads, the output voltage rising and falling tracks are different, and there is a large hysteresis voltage, which is not conducive to multi-valued circuits.

3. The threshold is fixed and cannot be changed at any time. This is the deficiency of the existing variable threshold technology. According to the needs of each stage of multi-valued information processing, there should be a tube with different thresholds with different characteristics of each stage of information processing; the present invention analyzes K The characteristics and structure of the K-value half subtractor and the K-value half-adder are consistent, but the PMOS tubes are required to have different thresholds that can be changed at any time, that is, the band-pass threshold loading technology is required; the K-value half-subtractor and the K-value half-add The device is an important device to realize the addition and subtraction of the K value. With the K value half subtractor and the K value half adder, the realization of the K value addition and subtraction operation is very easy.

Contents of the invention

The object of the invention is to disclose a construction method and circuit thereof of a K value and a ten-value half adder and a half subtractor that adopt band-pass threshold loading technology; the described purpose is realized through the following technical solutions:

1. A construction method of a K-value half-subtractor that adopts band-pass threshold loading technology: A _i is the minuend in the K-value half-subtractor, B _i is the subtrahend, S _i is originally a difference, and J _i is a borrowed digits, where A _i , B _i , and S _i are all K-value signals, and K-value signals have K logical values: 0, 1, 2, ‥..., L, where L=K-1, K=4, 5 , 6, ‥..., J _i is a binary signal, and a binary signal has two logical values: 0, L; let A _i =k, B _i =j, for a certain j=1~L, when k<j When , S _i =K+k-j>k, that is, S _i >A _i , when k=j, S _i =0, when k>j and j≠L, S _i =k-j<k, That is, S _i <A _i , when j=L, there is no k>j; for a certain j=0, S _i =A _i ; for j≠0, when k<j, there is a borrow, when k≥ When j, there is no borrowing, and to j=0, there is no borrowing; the construction method of the K value half reducer adopting the band-pass threshold loading technique is described as follows:

① For the determined j, j=1~L, according to S _i >A _i and S _i <A _i , the K-value half subtractor operation is divided into a high-value area and a low-value area, because t _b0~j-1 = t _/hj , t _bj+1～L ＝t _hj+1 , j≠L, using gate-controlled PMOS transistors P _e0 and P _e1 , P _e0 has the characteristics of low-pass threshold t _/hj , and P _e1 has high-pass threshold The characteristics of t _hj+1 , (1) high-value area: when k=0~j-1, the tube P _e0 is turned on, and S _i >A _i is realized; (2) low-value area: when k=j+1~L and j When ≠L, the tube P _e1 is turned on, and S _i <A _i is realized. When j=L, the low-value area is invalid, and only the high-value area is valid; when k=j, the tubes P _e0 , P _e1 , and P _d0 are all Cut off, S _i = 0; (3) use the PMOS non-gate output composed of P _e2 to form the J _i signal, the gate of the tube P _e2 takes over the gate g _/hj of P _e0 , when k<j, the tube P _e2 is turned on, J _i is high level, indicating that there is a borrow, when k≥j, the tube P _e2 is cut off, and J _i is low, indicating that there is no borrow;

(Note: t _b0~j-1 means that the conduction interval is k=0~j-1, t _/hj means that the conduction interval is k<j, that is, k=0~j-1, so t _b0~j-1 =t _/hj , and t _bj+1~L means that the conduction interval is k=j+1~L, and t _hj+1 means that the conduction interval is k≥j+1, that is, k=j+1~L, so t _bj+1～L ＝t _hj+1 ; because the low-pass threshold t _/hj and the high-pass threshold t _hj+1 belong to the band-pass threshold, that is, the special band-pass threshold t _b0～j-1 and t _{bj+1～ L} , so high-pass and low-pass variable-threshold PMOS transistors can be called band-pass variable-threshold PMOS transistors, and then according to the characteristics of the band-pass threshold, it will satisfy t _b0～j-1 =t _/hj and t _bj+1～ The band-pass threshold of _L =t _hj+1 is divided into low-pass threshold and high-pass threshold respectively; note that j≠0 in ①);

②The circuit in the high-value region includes band-pass variable threshold PMOS transistors P a00 ～P _{a0L -1} and diodes D ₀₀ ～D _0L-1 connected in series. The high-pass thresholds of transistors P _a01 ～P _a0L-1 are t _h1 ～t _hL in turn _-1 , the low-pass threshold of the tube P _a00 is t _/h1 , the source of the tube P a00 ~ P _{a0L -1} is connected to the power supply V _DC through P _e0 , when k=j-1 ~ 0 and j≠0, the tube P _e0 is turned on, the output of S _i is connected to V _DC through m ₀ conduction diodes, and as k changes from j-1 to 0, the tubes P _a0j-1 ~ P _a00 are sequentially turned on to control m ₀ from 0 to j-1 , so S _i is from L to L-j+1; the low-value region circuit includes high-pass variable threshold PMOS transistors P _a11 ~P _a1L and series diodes D ₁₂ ~D _1L , connect D _1L to D ₀₀ , so that D ₁₂ ~ D _1L and D ₀₀ ～D _0L-1 form a total series diode sequence D ₁₂ ～D _0L-1 , the high-pass thresholds of tubes P _a11 ～P _a1L are t _h1 ～t _hL in turn, when k=L～j+1 and When 0<j<L, the tube P _e1 is turned on, the sources of the tubes P _a11 ~ P _a1L are connected to the power supply V _DC through P _e1 , and the output of S _i is connected to V _DC through m ₁ conduction diodes, and the k is From L to j+1, use the tubes P _a1L ~ P _a1j+1 to conduct sequentially to control m ₁ from j to L-1, so the output of S _i is from L-j to 1; when k=j≠0, the tube P _e0 , P _e1 , and P _d0 are all cut off, and the output of S _i is 0;

③For each j, j=0~L, the value of j is judged by K logical value discrimination gates U ₀ ~U _L , and the band-pass threshold of logic value discrimination gate U _m is t _bj , that is, only when the input of U _m is j. The output of _m is high level, otherwise, the output of U _m is low level, and the band-pass thresholds of U ₀ ~ U _L are respectively t _b0 ~ t _bL ; all U ₀ ~ U _L inputs are j, U ₀ ~ U _L The outputs are respectively v _tg0 ~v _tgL , and v _tg0 ~v _tgL generate inverting output v _/tg0 ~v _/tgL through the NOT gates M ₀ ~M _L respectively; thus it is completed: (1) For j≠0, gate at variable threshold v _/tgj in PMOS transistors P _c1 ～P _cL drives P _cj to turn on, and the thresholds of the sources of transistors P _c1 ～P _cL to be transmitted are t _/h1 ～t _/hL respectively, so only t _/h1 in transistors P _c1 ～P _cL The t _/hj in ~t _/hL is loaded into the tube P _e0 , and the tube P _e0 is used to control the length of the high-value area (0, j-1) j-2, j≠0, and the length of the high-value area when j=L is L; (2) For j ≠ 0, v _/tgj drives P _dj to be turned on in the threshold-variable gate transistors P _d1 ~ P _dL , and the thresholds of the sources of the transistors P _d1 ~ P _dL-1 and P _dL are respectively t _h2 ~ t _hL , t _/h1 , when j<L, only t _hj+1 of t _h2 ～t _hL in tubes P _d1 ～P _dL-1 is loaded into tube P _e1 ; when j=L, tube P _dL Load t _/h1 to the tube P _e1 to invalidate the low-value area; turn on the tube P _e1 and P _d0 to control the low-value area j+1~L length L-j, j≠L; (3) in the CMOS transmission gate TG ₁ v _tgj and v _/tgj in ~TG _L only drive TG _j to turn on, j=1~L, S _i connects to the drain of P _a0j-1 through the turned-on TG _j , and the maximum condition of S _i is k=j- 1. At this time, S _i is connected to V _DC through the turned-on TG _j and P _a0j-1 to realize S _i =L; (4) When j=0, use v _{/tg0 to} drive TG ₀ and tubes P _d0 and P _c0 to conduct connected, the source of P _d0 is connected to V _DC , the drain of P _d0 is connected to the source of P _a11 ~P _a1L , the source of P _a11 ~P _a1L is connected to V _DC through P _d0 , and S _i is connected to the drain of P _a1L through TG ₀ pole, the circuit in the low-value area works and becomes a digital follower, realizing S _i =A _i , at this time, the length of the low-value area is L, and the circuit in the high-value area is invalid; the gate of the tube P _c0 is connected to v _/tg0 , and the drain of P _c0 is connected to The gate of P _e0 and the source of tube P _c0 are connected to DC voltage V _DC , so that when j=0, the output of J _i is the above-mentioned level indicating no borrowing, and the formation of J _i signal when j=0 is supplemented in ①.

(note: referring to embodiment 4: the present invention adopts band-pass threshold loading technology, variable-threshold gating PMOS transistor and gating-controlled PMOS transistor explanation; v _/tgj drives P _cj conduction, and P _cj conduction makes P The threshold t _/hj of the _cj source to be transmitted is loaded to the tube P _e0 , and the loading is to make P _e0 have the characteristic of the threshold t _/hj . If the P _cj is cut off, the t _/hj loading will fail, and another P _cj1 needs to be turned on. Load t _/hj1 to the tube P _e0 ; in a similar way, drive P _dj to conduct, load t _hj+1 to the tube P _e1 , this load makes P _e1 have the characteristic of threshold t _hj+1 ; when the value of j changes, The high-value and low-value region changes require the threshold characteristics of the tubes P _e0 and P _e1 to be loaded with a new band-pass threshold).

2. A kind of construction method of the K value half-adder that adopts the band-pass threshold loading technology that adopts the construction method of the K value half-adder of the band-pass threshold loading technology according to the construction method of a kind of K value half-subtractor of the band-pass threshold loading technology described in above-mentioned technical scheme 1: In the construction method of the K value half reducer using the band-pass threshold loading technology: (1) Firstly, the band-pass thresholds of U ₁ ~ U _L are respectively taken as t _bL ~ t _b1 ; (2) Then, the borrowing digits J _i Take it as the carry number C _i , except that when j=0, no borrow is taken as no carry, all borrows are taken as no carry, and no borrow is taken as a carry (including C _i outputs a high level V _DC to indicate No carry, C _i output low level 0 means there is a carry), the source of the tube P _c0 is connected to the DC voltage V _d , so that when j=0, the output of C _i is the above-mentioned level indicating no carry, V _d ≠ V _DC ; (iii) Finally, the half subtractor is taken as a half adder, and A _i , B _i and S _i are taken as the addend, the addend and the basic sum in turn, and the construction method of the K value half subtractor using the band-pass threshold loading technology It becomes the construction method of the K value half adder adopting the band-pass threshold loading technology.

(note: referring to embodiment 1, the proof that the K value half reducer and half adder construction method features are the same).

3. a kind of K value half reducer circuit that adopts band-pass threshold loading technology to form according to a kind of construction method of the K value half reducer that adopts band-pass threshold loading technology described in above-mentioned technical scheme 1, as shown in Fig. 1, The K value half reducer circuit adopting the band-pass threshold loading technology includes: control signal forming circuit, high value area and high gating circuit, low value area and low gating circuit, S _i output circuit and J _i output circuit; see Fig. 1. The specific circuit structure of the K value half reducer is described as follows:

①The control signal forming circuit is composed of logic value discrimination gates U ₀ ~U _L and _CMOS NOT gates _{M 0} ~ _{ML .} P _bL and constant current source I ₀ ~ _IL constitute, the band-pass thresholds of tubes P _b0 ~P _bL are t _b0 ~t _bL respectively, where t _b0 =t _/h1 , t _bL =t _hL , that is, tubes P _b0 and P _bL are the low-pass and high-pass variable-threshold PMOS transistors with the smallest interval respectively. The effective inputs of the tubes P _b0 ~ P _bL are all connected to Bi, the sources of the tubes P _b0 ~ P _bL are connected to the power supply _{V DC} , and the tubes P _b0 ~ P _{The bL} drains are respectively connected to the upper end of the constant current source I ₀ ～ _IL , and the upper end of I ₀ ～ _IL is used as U ₀ ～U _L to output v _tg0 ～v _{tgL respectively} , and the lower end of the constant current source I ₀ ～ _IL is grounded, and the constant current source current Both flow from the upper end to the lower end, v _tg0 ~ v _tgL are respectively connected to the input of the NOT gate M ₀ ~ M _L , and the outputs of M ₀ ~ M _L are respectively v _/tg0 ~ v _/tgL , thus obtaining mutually inverse control signals v _tg0 ～v _tgL and v _/tg0 ～v _/tgL , M ₀ ～M _L operating voltage is V _DC , input j for each B _i , j=0～L, only v _tgj is high among v _tg0 ～v _tgL level, other outputs are low level;

_②High value area and high gating circuit: the high gating circuit is _composed of variable threshold gating PMOS transistors P _c1 ~ P _cL , gating controlled PMOS transistor P _e0 and PMOS transistor P _c0 ; The low-pass thresholds are t _/h1 ~ t _/hL respectively, the effective input of the tubes P _c1 ~ P _cL is connected to A _i , the gates of the tubes P _c0 ~ P _cL are connected to the control signal v _/tg0 ~ v _{/tgL respectively} , and the drain All poles take over the grid g _/hj of P _e0 ; for each B _i input j, j=1~L, only one tube P _cj is turned on among the tubes P _c1 ~P _cL , and the other tubes are cut off, so at t _/h1 ~ In t _/hL , only t _/hj is loaded to the tube P _e0 , the source of the tube P _e0 is connected to V _DC , and its drain is connected to the source of P a00 ~ P _{a0L -1} ; the circuit in the high-value area includes a PMOS tube P with a pass-through threshold a00 ～P _{a0L -1} and series diodes D ₀₀ ～D _0L-1 , the high-pass thresholds of tubes P _a01 ～P _a0L-1 are t _h1 ～t _hL-1 in turn, and the low-pass thresholds of tube P _a00 are t _/h1 , The negative poles of tubes D ₀₀ ~ D _0L-2 are respectively connected to the positive poles of D ₀₁ ~ D _0L-1 , the effective input of tubes P a00 ~ P _{a0L -1} is connected to A _i , and the drains of tubes P a00 ~ P _{a0L -1} are respectively connected to D ₀₀ ~ D The negative pole of _0L-1 , the input of A _i is k, when k=0~j-1 and j≠0, the tube P _e0 is turned on, and the source of the tubes P a00 ~ P _{a0L -1} is connected to V _DC through P _e0 , the circuit works in the high-value area, use the tube P _e0 to turn on and control the length j-2 of the high-value area (0, j-1), j≠0, when k=j~L, the tube P _e0 is cut off, and the tube P _a00 ~ The source of P _a0L-1 is disconnected from V _DC , and the circuit in the high value area does not work;

③Low value area and low gating circuit: The low gating circuit is composed of variable threshold gating PMOS transistors P _d1 ~P _dL , gating controlled PMOS transistor P _e1 and PMOS transistor P _d0 ; the source of the transistor P _d1 ~P _dL-1 The high-pass thresholds of the poles to be transmitted are t _h2 ~ t _hL respectively, and the low-pass thresholds of the sources of P _dL to be transmitted are t _{/ h1} ; the gates of the transistors P _d0 ~ P _dL are connected to the control signals v _/tg0 ~ v _{/tgL respectively} , and P _d1 ~ The drain of P _dL takes over the gate of P _e1 , and the effective input of P _d1 ~ P _dL is connected to A _i ; for each j, j=1 ~ L-1, only one of P _d1 ~ P _dL-1 is turned on, P _dj , the rest of the tubes are cut off, and t _hj+1 is selected from t _h2 ~ t _hL to load the tube P _e1 , and j=L, the tube P _dL is turned on, and t _/h1 is loaded to the tube P _e1 ; the tubes P _e1 and P _d0 are drained The pole takes over the source of P _a11 ~P _a1L , the source of P _e1 and P _d0 is connected to V _DC ; when k=j+1~L and 0<j<L, the tube P _e1 is turned on, and the source of P _a11 ~P _a1L The pole is connected to V _DC through P _e1 , and the circuit in the low-value area works; the circuit in the low-value area includes high-threshold PMOS transistors P _a11 ～P _a1L and series diodes D ₁₂ ～D _1L , and the negative poles of tubes D ₁₂ ～D _1L-1 take over respectively D ₁₃ ～D _1L positive pole, D _1L negative pole connected to D ₀₀ positive pole, connect D ₁₂ ～D _1L and D ₀₀ ～D _0L-1 in series to form 2L-1 series diode series, the high-pass thresholds of tubes P _a11 ～P _a1L are respectively It is t _h1 ～t _hL , its effective input is connected to A _i , the drains of tubes P _a12 ～P _a1L are respectively connected to the negative poles of D ₁₂ ～D _1L , and the drain of tube P _a11 is connected to the positive pole of D ₁₂ ; when j=0, tube P _d0 Turn on, the source of the tubes P _a11 ~ P _a1L is connected to V _DC through P _d0 , the circuit in the high value area is invalid, the circuit in the low value area works and forms a digital follower, and the low value area is controlled by the conduction of the tubes P _e1 and P _d0 (j+1, L) length L-j-2, j≠L; when k=0~j and j≠L, the tube P _e1 is cut off, and the sources of the tubes P _a11 ~P _a1L are disconnected from V _DC , The circuit in the low-value area does not work; for j=L, when k≠0, the tube P _e1 is cut off, and when k=0, the tube P _e1 is turned on, and the tubes P _a11 ~ P _{a1L are} all cut off, and the circuit in the low-value area is invalid , circuit work in high value area;

④S _i output circuit and J _i output circuit: S _i output circuit is composed of CMOS transmission gate TG ₀ ~TG _L and constant current source I _Si , the input of transmission gate TG ₁ ~TG _L respectively takes over the drain of P a00 ~P _{a0L -1} , the input of TG ₀ takes over the drain of P _a1L , the output of TG ₀ ~ _TGL is connected to the upper end of the constant current source I _Si , the upper end of I _Si is used as the output of _Si , the lower end of I _Si is grounded, the positive control end of TG ₀ ~ TG _L and the negative control The terminals are respectively connected to v _tg0 ~v _tgL and v _/tg0 ~v _/tgL , the diode conduction voltage drop is V _Don , for each j, j=1~L, only one TG _j among TG ₁ ~TG _L is turned on , S _i connects to the drain of P _a0j-1 through the turned-on TG _j , for j=0, S _i takes over the drain of P _a1L through the turned-on TG ₀ ; select V _DC = LV _Don + △, △ is stored as K value The offset required by the unit circuit characteristics;

(Note: The drains of the NMOS transistor N _tga and the PMOS transistor P _tga are connected, and the source is also connected, thus forming a CMOS transmission gate TG _a , and the gates of the transistors N _tga and P _tga are respectively the positive control of the transmission gate TG _a terminal and negative control terminal);

J _i output circuit consists of PMOS tube P _e2 and constant current source I _Ci , the source of tube P _e2 is connected to V _DC , the gate of tube P _e2 is connected to P _e0 gate g _/hj , and the drain of tube P _e2 is connected to constant current source I The upper end of _Ci , the upper end of I _Ci is output as J _i , the lower end of I _Ci is grounded, the gate of P _c0 is connected to v _/tg0 , the drain of P _c0 is connected to the gate of P _e0 ; for j≠0, when k<j, the pipe P _e0 Gate g _/hj voltage V _g/hj < V _DC , tube P _e2 is turned on, J _i outputs high level V _DC , which means there is a borrow. When k≥j, V _g/hj = V _DC , tube P e2 When P _e2 is cut off, the output of J _i is low level 0, indicating no borrow; the source of the tube P _c0 is connected to the DC voltage V _DC , so that when j=0, the output of J _i is the above-mentioned level indicating no borrow (note: when When j=0, P _c0 is turned on, and the gate voltage V _g/hj of P _e0 is equal to the DC voltage V _DC , so that the transistor P _e2 is cut off, and the output of J _i is a high level V _DC , indicating that there is no borrow when j=0 ), the current direction of all constant current sources flows from the upper end to the lower end.

4, a kind of K value half adder circuit that adopts the K value half adder circuit of band pass threshold loading technology to form according to the same feature of a kind of K value half adder circuit that adopts band pass threshold loading technology described in above-mentioned technical scheme 3, as shown in Fig. 1, In the circuit diagram 1 of the K-value half subtractor, (1) firstly, the band-pass thresholds of U ₁ ~ U _L are respectively taken as t _bL ~ t _b1 ; (2) Then, the borrow number J _i is taken as the carry number C _i , Except when j=0, no borrow is taken as no carry, all borrows are taken as no carry, and no borrow is taken as carry (including C _i output high level V _DC means no carry, C _i output low Level 0 means there is a carry), the source of the tube P _c0 is connected to the DC voltage V _d , so that when j=0, the C _i output is the above-mentioned level indicating no carry, V _DC -V _d = 1.5 volts; (Note: j = At 0, P _c0 is turned on, and the gate voltage V _g/hj of the tube P _e0 is equal to the DC voltage V _d , so that the tube P _e0 is turned on, and C _i outputs a high level V _DC , indicating that there is no carry, that is, the DC voltage V _d C _i output level represents no carry when j=0 is satisfied); (iii) at last, the half subtractor is taken as a half adder, and A _i , B _i and S _i are taken successively as the summand, the addend and the basic sum, Then the K-value half-adder circuit using the band-pass threshold loading technology becomes a K-value half-adder circuit using the band-pass threshold loading technology, that is, Fig. 1 becomes Fig. 2 .

(Note: Comparing Figures 1 and 2, it can be seen that the structure of the K-value half-adder circuit Figure 1 and the K-value half-adder circuit Figure 2 are exactly the same, but the parameters are changed: ① The band-pass threshold of U ₁ to U _L is from t _b1 to t _bL Change to t _bL ~ t _b1 , ②The DC voltage connected to the source of P _c0 is changed from V _DC to V _d , the components and wiring of the circuit are exactly the same, without any change, but the meaning of the variable is determined by the half subtractor and half adder; In addition, since V _tn + |V _tp |<1.5 volts, when V _g/hj =V _d , the tubes P _e0 and P _e2 are turned on, and when V _g/hj =V _DC , the tubes P _e0 and P _e2 are turned off).

The present invention also has the following technical characteristics:

(1) A kind of K-value half-subtractor circuit adopting band-pass threshold-loading technology formed according to the construction method of a kind of K-value half-subtractor adopting band-pass threshold-loading technology described in above-mentioned technical scheme 3, as shown in Fig. 1 , in the K-value half-subtractor circuit using the band-pass threshold loading technique shown in Figure 1, if K=10, a 10-value half-subtractor circuit using the band-pass threshold loading technique is obtained, as shown in Figure 3 , the 10-value half reducer circuit includes: control signal forming circuit, high value area and high gating circuit, low value area and low gating circuit, S _i output circuit and J _i output circuit; referring to Fig. 3, 10 value half reduction The specific circuit structure of the device is described as follows:

①The control signal forming circuit is composed of logic value discrimination gates U ₀ ~ U ₉ and CMOS NOT gates M ₀ ~ M _9. The discrimination gates U ₀ ~ U ₉ are respectively composed of band-pass variable threshold PMOS transistors P _b0 ~ P _b9 and constant current sources I ₀ ~ I ₉ are formed, and the band-pass thresholds of tubes P _b0 ~ P _b9 are t _b0 ~ t _b9 respectively, where t _b0 = t _/h1 , t _b9 = t _h9 , that is, tubes P _b0 and P _b9 are the low-pass and high-pass variable-threshold PMOS transistors with the smallest interval respectively. The effective inputs of the tubes P _b0 ~ P _b9 are all connected to Bi, the sources of the tubes P _b0 ~ P _b9 are connected to the power supply _{V DC} , and the tubes P _b0 ~ P The drains of _b9 are respectively connected to the upper end of the constant current source I ₀ ~ I ₉ , and the upper end of I ₀ ~ I ₉ is respectively used as U ₀ ~ U ₉ to output v _tg0 ~ v _tg9 , the lower end of the constant current source I ₀ ~ I ₉ is grounded, and the constant current source current Both flow from the upper end to the lower end, v _tg0 ~ v _tg9 are respectively connected to the input of the NOT gate M ₀ ~ M ₉ , and the outputs of M ₀ ~ M ₉ are respectively v _/tg0 ~ v _/tg9 , thus obtaining mutually inverse control signals v _tg0 ～v _tg9 and v _/tg0 ～v _/tg9 , the working voltage of M ₀ ～M ₉ is V _DC , input j for each B _i , j=0～9, only v _tgj among v _tg0 ～v _tg9 is high level, other outputs are low level;

②High value area and high gating circuit: the high gating circuit is composed of variable threshold gating PMOS transistors P _c1 ~ P _c9 , gating controlled PMOS transistor P _e0 and PMOS transistor P _c0 ; the sources of the transistors P _c1 ~ P _c9 are waiting The low-pass thresholds are respectively t _/h1 ~ t _/h9 , the effective input of the tubes P _c1 ~ P _c9 is connected to A _i , the gates of the tubes P _c0 ~ P _c9 are respectively connected to the control signal v _/tg0 ~ v _/tg9 , and the drain All poles take over P _e0 gate g _/hj ; input j for each B _i , j=1~9, only one tube P _cj is turned on among the tubes P _c1 ~P _c9 , and the other tubes are cut off, so at t _/h1 ~ In t _/h9 , only t _/hj is loaded to the tube P _e0 , the source of the tube P _e0 is connected to V _DC , and its drain is connected to the source of P _a00 ~ P _a08 ; the circuit in the high value area includes PMOS tubes P a00 ~ P _a00 ~ P _a08 and diodes D ₀₀ ～ D ₀₈ in series, the high-pass thresholds of tubes P _a01 ～ P _a08 are t _h1 ～ t _h8 in turn, the low-pass threshold of tube P _a00 is t _{/ h1} , and the negative poles of tubes D ₀₀ ～ D ₀₇ respectively take over D ₀₁ ~ D ₀₈ are positive, the effective input of tubes P _a00 ~ P _a08 is connected to A _i , and the drains of tubes P _a00 ~ P _a08 are respectively connected to the negative poles of D ₀₀ ~ D ₀₈ ; the input of A _i is k, when k = 0 ~ j-1 And when j≠0, the tube P _e0 is turned on, the sources of the tubes P _a00 ~ P _a08 are connected to V _DC through P _e0 , the circuit in the high-value area works, and the tube P _e0 is turned on to control the high-value area (0, j- 1) The length j-2, j≠0, when k=j~9, the tube P _e0 is cut off, the source of the tubes P _a00 ~P _a08 is disconnected from V _DC , and the circuit in the high value area does not work;

③Low value area and low gating circuit: The low gating circuit is composed of variable threshold gating PMOS transistors P _d1 ~ P _d9 , gating controlled PMOS transistor P _e1 and PMOS transistor P _d0 ; the sources of the transistors P _d1 ~ P _d8 are waiting The high-pass thresholds for transmission are t _h2 ~ t _h9 , and the low-pass thresholds for P _d9 sources to be transmitted are t _{/ h1} ; the gates of the tubes P _d0 ~ P _d9 are respectively connected to the control signal v _/tg0 ~ v _/tg9 , and the tubes P _d1 ~ P The drain of _d9 is connected to the gate of P _e1 , and the effective input of the tubes P _d1 ~ P _d9 is connected to A _i ; for each j, j=1 ~ 8, only one tube P _dj of the tubes P _d1 ~ P _d8 is turned on, and the other tubes are cut off , select t _hj+1 from t _h2 to t _h9 to load to the tube P _e1 , and j=9, the tube P _d9 is turned on, and t _/h1 is loaded to the tube P _e1 ; the drains of the tubes P _e1 and P _d0 take over P _a11 ~P _a19 source, the source of the tube P _e1 and P _d0 is connected to V _DC ; when k=j+1~9 and 0<j<9, the tube P _e1 is turned on, and the source of the tube P _a11 ~P _a19 is passed through When P _e1 is connected to V _DC , the circuit in the low-value area works; the circuit in the low-value area includes PMOS transistors P _a11 ~ P _a19 with pass-through thresholds and series diodes D ₁₂ ~ D ₁₉ , and the negative poles of tubes D ₁₂ ~ D ₁₈ respectively take over D ₁₃ ~ The positive pole of D ₁₉ , the negative pole of D ₁₉ is connected to the positive pole of D ₀₀ , and D ₁₂ ~ D ₁₉ and D ₀₀ ~ D ₀₈ are connected in series to form 17 series diode sequences. The high-pass thresholds of tubes P _a11 ~ P _a19 are t _h1 ~ t _h9 respectively, Its effective input is connected to A _i , the drains of the tubes P _a12 ~ P _a19 are respectively connected to the negative poles of D ₁₂ ~ D ₁₉ , and the drain of the tube P _a11 is connected to the positive pole of D ₁₂ ; when j=0, the tube P _d0 is turned on, and the tubes P _a11 ~ The source of P _a19 is connected to V _DC through P _d0 , the circuit in the high value area is invalid, the circuit in the low value area works and forms a digital follower, and the conduction of the tubes P _e1 and P _d0 is used to control the low value area (j+1, 9) Length 9-j-2, j≠9; when k=0~j and j≠9, the tube P _e1 is cut off, the sources of the tubes P _a11 ~ P _a19 are disconnected from V _DC , and the circuit in the low value area does not work; For j=9, when k≠0, the tube P _e1 is cut off, and when k=0, the tube P _e1 is turned on, the tubes P _a11 to P _a19 are all cut off, the circuit in the low value area is invalid, and the circuit in the high value area works;

④S _i output circuit and J _i output circuit: S _i output circuit is composed of CMOS transmission gate TG ₀ ~ TG ₉ and constant current source I _Si , the input of transmission gate TG ₁ ~ TG ₉ respectively takes over the drain of P _a00 ~ P _a08 , TG The ₀ input takes over the drain of P _a19 , the outputs of TG ₀ ~ TG ₉ are all connected to the upper end of the constant current source I _Si , the upper end of I _Si is used as the output of _Si , the lower end of I _Si is grounded, and the positive control end and negative control end of TG ₀ ~ TG ₉ are respectively Connect v _tg0 ~ v _tg9 and v _/tg0 ~ v _/tg9 , the diode conduction voltage drop is V _Don , in TG ₁ ~ TG ₉ , for each j, j=1 ~ 9, only one TG _j is turned on, S _i connects to the drain of P _a0j-1 through the turned-on TG _j , for j=0, S _i takes over the drain of P _a19 through the turned-on TG ₀ ; select V _DC =9V _Don + △, △ is the K value storage unit The circuit characteristics require the offset to be compensated;

J _i output circuit consists of PMOS tube P _e2 and constant current source I _Ci , the source of tube P _e2 is connected to V _DC , the gate of tube P _e2 is connected to P _e0 gate g _/hj , and the drain of tube P _e2 is connected to constant current source I The upper end of _Ci , the upper end of I _Ci is output as J _i , the lower end of I _Ci is grounded, the gate of P _c0 is connected to v _/tg0 , the drain of P _c0 is connected to the gate of P _e0 ; for j≠0, when k<j, the pipe P _e0 Gate g _/hj voltage V _g/hj < V _DC , tube P _e2 is turned on, J _i outputs high level V _DC , which means there is a borrow. When k≥j, V _g/hj = V _DC , tube P e2 When P _e2 is cut off, the output of J _i is low level 0, indicating that there is no borrow; the source of the tube P _c0 is connected to the DC voltage V _DC , so that when j=0, the output of J _i is the above-mentioned level indicating no borrow (that is, to use When j=0, the output of J _i is low level (0); the current direction of all constant current sources is from the upper end to the lower end.

(2), a kind of 10-value half-adder circuit that adopts the band-pass threshold loading technique that adopts the 10-value half-adder circuit of the band-pass threshold loading technique according to the above-mentioned technical scheme (1) described in the same feature, shows As shown in Figure 3, in the 10-value half-subtractor circuit using the band-pass threshold loading technique shown in Figure 3, (1) First, the band-pass thresholds of U ₁ to U ₉ are respectively taken as t _b9 to t _b1 ; (ii) Next, take the number of borrows J _i as the number of carries C _i , except that when j=0, no borrows are taken as no carry, all those with borrows are taken as no carry, and those without borrows are taken as have a carry, regardless of P The source of _c0 is connected to the DC voltage V _d , so that when j=0, the C _i output is the above-mentioned level indicating no carry, V _DC -V _d = 1.5 volts; (3) Finally, the half subtractor is used as a half adder, and A _i , B _i and S _i are successively taken as the summand, the addend and the basic sum, then the 10-value half-subtractor circuit using the band-pass threshold loading technology becomes a 10-value half-adder circuit using the band-pass threshold loading technology, That is, Figure 3 becomes Figure 4.

(Note: Comparing Figure 3 and Figure 4, it can be seen that the structure of the 10-value half-adder circuit and the 10-value half-adder circuit are exactly the same, but the parameters are changed: ① The band-pass threshold of U ₁ ~ U ₉ is changed from t _b1 ~ t _b9 t _b9 ~ t _b1 , ②The DC voltage connected to the source of P _c0 is changed from V _DC to V _d . _tn +∣V _tp ∣<1.5 volts, when the gate voltage of the tube P _e0 is V _g/hj =V _d , the tube P _e0 is turned on, and when V _g/hj =V _DC , the tube P _e0 is turned off; in addition, J _i outputs High level V _DC indicates that there is a borrow, and C _i outputs high level V _DC , indicating that there is no carry, J _i outputs low level 0, indicating that there is no borrow, and C _i outputs low level 0, indicating that there is a carry).

So far, there have been many researches on K-value information storage, but K-value information calculation research is relatively small. The reason is that the K-value information calculation circuits are all based on the conventional realization method of K-value combinational logic circuits composed of K-value gates, which is very difficult. , the structure is very complicated; ① the threshold characteristics of the tubes are required to be different in each stage of general information calculation and information processing, and the conventional variable threshold method does not meet the needs. According to the requirements of the stages, the band-pass thresholds required for different stages are loaded into the PMOS tubes in stages, so that the PMOS tubes have a band-pass threshold that can be changed at any time. This is a new method and new idea to realize K value information calculation and information processing;② On the basis of the band-pass threshold loading technology, the present invention analyzes the characteristics and structural consistency of the K value half subtractor and the K value half adder, because the K value half subtractor and the half adder have the same high value area and low value area, its characteristics are unified, and the band-pass threshold loading technology is adopted. The two circuits can be classified into one circuit unified design, and avoid the traditional way of thinking realized by using K-value combinational logic gate circuits, and the circuit structure is greatly simplified; K-value The half subtractor and the K value half adder are important devices to realize the addition and subtraction of the K value. With the K value half subtractor and the K value half adder, the realization of the K value operation is very easy. The chaotic encryption method and encryption circuit Provide a good foundation for medium K value information calculation and information processing.

Description of drawings

Fig. 1. is a kind of K value half reducer circuit diagram that adopts band-pass threshold loading technology of the present invention;

Fig. 2. is a kind of K value half adder circuit diagram that adopts band-pass threshold loading technology of the present invention;

Fig. 3. is a kind of 10 value half subtractor circuit diagram that adopts band-pass threshold loading technology of the present invention;

Fig. 4. is a kind of 10 value half adder circuit diagram that adopts band-pass threshold loading technology of the present invention;

Fig. 5. is a kind of PMOS tube band-pass variable threshold circuit diagram and band-pass type variable threshold PMOS tube symbol diagram related to the present invention;

Fig. 6. is a kind of PMOS tube high-pass variable threshold circuit diagram and high-pass type variable threshold PMOS tube symbol diagram related to the present invention;

Fig. 7. is a kind of PMOS tube low-pass variable threshold circuit diagram and low-pass type variable threshold PMOS tube symbol diagram related to the present invention;

Fig. 8. is a kind of variable-threshold gating PMOS transistor and gating-controlled PMOS transistor and its symbol diagram related to the present invention;

Figure 9 is a circuit diagram and symbol diagram of an existing multi-output precision mirror constant current source;

Fig. 10. is the working waveform diagram of the 10-value half reducer circuit of the present invention during 180-410 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , S _i , J _i and g _/hj ;

Fig. 11. is the working waveform diagram of the 10-value half subtractor circuit of the present invention during 180-240 μs, and the order of signal voltage waveforms from top to bottom is: A _i , B _i , S _i , J _i and g _/hj ;

Fig. 12. is the working waveform diagram of the 10-valued half reducer circuit of the present invention during 240-300 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , S _i , J _i and g _/hj ;

Fig. 13. is the working waveform diagram of the 10-value half reducer circuit of the present invention during 300-360 μs, and the order of signal voltage waveforms from top to bottom is: A _i , B _i , S _i , J _i and g _/hj ;

Fig. 14. is the working waveform diagram of the 10-value half subtractor circuit of the present invention during 350-410 μs, and the order of signal voltage waveforms from top to bottom is: A _i , B _i , S _i , J _i and g _/hj ;

Fig. 15 is a circuit control signal waveform diagram of the 10-value half reducer of the present invention during 180-410 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , v _tg9 , v _tg8 , v _tg7 , v _tg6 , v _tg5 , v _tg4 , v _tg3 , v _tg2 , v _tg1 , v _tg0 ;

Fig. 16. is the working waveform diagram of the 10-valued half adder circuit of the present invention during 180-410 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , S _i , C _i and g _/hj ;

Fig. 17 is the working waveform diagram of the 10-valued half-adder circuit of the present invention during 180-240 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , S _i , C _i and g _/hj ;

Fig. 18. is the working waveform diagram of the 10-value half adder circuit of the present invention during 240-300 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , S _i , C _i and g _/hj ;

Fig. 19. is the working waveform diagram of the 10-valued half adder circuit of the present invention during 300-360 μs, and the order of the signal voltage waveforms from top to bottom is: A _i , B _i , S _i , C _i and g _/hj ;

Fig. 20 is the working waveform diagram of the 10-valued half adder circuit of the present invention during 350-410 μs, the signal voltage waveforms are in the order from top to bottom: A _i , B _i , S _i , C _i and g _/hj ;

Fig. 21 is a circuit control signal waveform diagram of the 10-valued half adder of the present invention during 180-410 μs. The order of signal voltage waveforms from top to bottom is: A _i , B _i , v _tg9 , v _tg8 , v _tg7 , v _tg6 , v _tg5 , v _tg4 , v _tg3 , v _tg2 , v _tg1 , v _tg0 ;

detailed description

Below by embodiment the present invention will be further described:

Embodiment 1: the proof that K value half subtractor of the present invention and half adder construction method feature are identical:

(1) K value half subtractor feature: A _i is the minuend, B _i is the subtrahend, S _i is the difference, and J _i is the number of borrowings, so that A _i =k, B _i =j,

For a certain j=1~L, when k<j, S _i =K+k-j>k, that is, S _i >A _i ; when k=j, S _i =0; when k>j and j When ≠L, S _i =k-j<k, that is, S _i <A _i , when j=L, there is no k>j; for certain j=0, S _i =A _i ; for j≠0, When k<j, there is a borrow, when k≥j, there is no borrow, and for j=0, there is no borrow;

(2) K value half-adder feature: A _i is the summand, B _i is the addend, S _i is originally and, C _i is the carry number, make A _i =k, B _i =n, to definite n, n=1~L, when k+n<K, S _i =k+n>k, that is, S _i >A _i , when k+n=K, S _i =0, when k+n> When K and n≠1, S _i =k+n-K<k, that is, S _i <A _i , when n=1, there is no k+n>K; for a certain n=0, S _i =A _i ; for n≠0, when k+n<K, there is no carry, when k+n≥K, there is carry, for n=0, there is no carry;

In (1) K-value half reducer feature, for j=1～L, take j=K-n, for j=0, take n=0, except that j=0, no borrow is taken as no carry , all no borrows are taken as carry, and borrows are taken as no carry, so (1) draws the same result as (2) K value half adder: to the determined n, n=1～L , when k<K-n, S _i =k+n>k, that is, S _i >A _i , when k=K-n, S _i =0, when k>K-n and n≠1, S _i =k-K+n<k, that is, S _i <A _i , when n=1, k+n>K does not exist; for a certain n=0, S _i =A _i ; for n≠0, When k<K-n, there is no carry, when k≥K-n, there is carry, for n=0, there is no carry;

In (2) K-value half adder feature, to n=1～L, get n=K-j, to n=0, get j=0, except n=0, no carry is taken as no borrow , all no carry is taken as having a borrow, and all carry is taken as no borrow, and (2) draws the same result as (1) K value half reducer;

It can be seen from the above description that the characteristics of the K-value half-subtractor are consistent with those of the K-value half-adder. Therefore, in the construction method of the K-value half-subtractor: (1) First, the bandpass thresholds of U ₁ ~ U _L are sequentially Take it as t _bL ～t _b1 , which means that for j=1～L, take n=K－j, (2) Next, take the borrow number J _i as the carry number C _i , and take no borrow when j=0 In addition to carry, take all borrows as no carry, and take no borrow as carry, (iii) finally, take the half subtractor as a half adder, and take A _i , B _i and S _i as the added Number, addend and basic sum, then the construction method of K value half adder just forms the construction method of K value half adder.

Embodiment 2: Description of the output of the K value half reducer S _i :

When j≠0 and k=1~j-1, the tube P _e0 is turned on, the drain voltage of the tube P _e0 is V _Pe0 =V _DC , and the circuit in the low value area is invalid; when k=j-1, the tube P _{a0j- 1} is turned on, S _i is connected to V _Pe0 through TG _j and P _a0j-1 , and S _i outputs voltage V _Si =V _DC , that is, S _i =L; when k=j-2, tubes P _a0j-2 and D _{0j -1} is turned on, the tube P _a0j-1 is cut off, Si is connected to V _Pe0 through TG _j , P _a0j-2 and D _0j-1 , there is a diode D _0j-1 between _{Si and V Pe0 ,} V _Si ＝ _{V DC} -V _Don , that is, S _i =L-1; when k=j-3, the tubes P _a0j-3 , D _0j-1 , and D _0j-2 are turned on, and the tubes P _a0j-1 and P _{a0j-2 are} cut off , S _i is connected to V Pe0 through TG _j , P _a0j-3 , D _0j-1 , D _0j-2 , there are two _diodes between S _i and V _Pe0 , V _Si =V _DC -2V _Don , that is, S _i =L -2; ‥..., when k=1, the tubes P _a01 , D ₀₂ ～D _0j-1 are on, the tubes P _a02 ～P _a0j-1 are off, and S _i passes through TG _j , P _a01 , D ₀₂ ～D _{0j -1} is connected to V _Pe0 , there are ( _j -2) diodes between Si and V _Pe0 , V _Si = V _DC - (j-2) V _Don , that is, Si = L- _j +2; when k = 0 , the tubes P _a00 , D ₀₁ ～D _0j-1 are on, the tubes P _a01 ～P _a0j-1 are off, S _i is connected to V _Pe0 through TG _j , P _a00 , D ₀₁ ～D _0j-1 , S _i and V _Pe0 There are (j-1) diodes between them, V _Si = V _DC - (j-1) V _Don , that is, S _i = L-j+1;

When k=j+1～L and 0<j<L, the tube P _e1 is turned on, the drain voltage of P _e1 is V _Pe1 =V _DC , the tube P _e0 is cut off, only the circuit in the low value area works, and the circuit in the high value area does not work, when k=L, the tubes P _a1L , D ₀₀ ～D _0j-1 are turned on, Si is connected to V _Pe1 through TG _j , P _a1L , D ₀₀ ～D _0j-1 , and there is _j between Si and _{V Pe1} Diodes, V _Si =V _DC -jV _Don , that is, S _i =L-j; when k=L-1, the tubes P _a1L-1 , D _1L , D ₀₀ ~D _0j-1 are turned on, and the tube P _{a1L is} cut off, Si is connected to V _Pe1 through TG _j , P _{a1L -1} , D _1L , D ₀₀ ～D _0j-1 , there are ( _j +1) diodes between Si and V _Pe1 , V _Si ＝V _DC －( j+1)V _Don , that is, S _i =L-(j+1); when k=L-2, the tubes P _a1L-2 , D _1L-1 , D _1L , D ₀₀ ～D _0j-1 are turned on , the tubes P _a1L-1 and P _{a1L are} cut off, S _i is connected to V _Pe1 through TG _j , P _a1L-2 , D _1L-1 , D _1L , D ₀₀ ～D _{0j-1 , there} is (j +2) diodes, V _Si ＝V _DC－ (j+2)V _Don , that is, S _i ＝L－(j+2);‥‥‥‥, when k=j+2, the tube P _a1j+2 , D _1j+3 ～D _1L , D ₀₀ ～D _0j-1 conduction, pipe P _a1j+3 ～P _{a1L cuts} off, S _i passes through P _a1j+2 , D _1j+3 ～D _1L , D ₀₀ ～D _{0j -1} is connected to V _Pe1 , there are (L-2) diodes between Si and _{V Pe1} , V _Si = V _DC - (L-2) V _Don = 2V _Don + △, that is, Si = 2; when k = _j When +1, the tubes P _a1j+1 , D _1j+2 ～D _1L , D ₀₀ ～D _0j-1 are on, the tubes P _a1j+2 ～P _{a1L are} off, and S _i passes through P _a1j+1 , D _1j+2 ～D _1L , D ₀₀ ～D _0j-1 are connected to V _Pe1 , there are (L-1) diodes between Si and _{V Pe1} , V _Si ＝V _DC -(L-1)V _Don ＝V _Don +△, namely S _i = 1 (Note: when j=L, this paragraph has lost its effect and should be completely deleted, only the previous paragraph 'j≠0 and k=1~j-1', the end of the previous paragraph is: when k= When 0, V _Si = V _DC - (L - 1) V _Don = V _Don + △, that is, S _i = 1. In order to simplify the circuit, the low gate circuit transistors P _d0 ~ P _dL and P _e1 can also be removed , connect the sources of the transistors P _a11 ~ P _a1L to V _DC , which does not affect the above-mentioned Si output situation where _j ≠ ₀ and k≠ _{j .} ～D _1L , D ₀₀ ～D _0j-1 are connected to V _Pe1 , there are L diodes between S _i and V _Pe1 , V _Si ＝V _DC －LV _Don ＝△, that is, the 0 level of S _i V _Si (0)＝ △, because △ is very small, it is actually feasible).

In addition, when k=j, the tubes P _e0 and P _e1 are cut off, S _i is disconnected from V _DC , V _Si =0, that is, S _i =0.

When j=0, S _i is connected to the drain of P _a1L through the turned-on TG ₀ , the circuit in the high-value area becomes invalid, and the circuit in the low-value area becomes a digital follower, realizing S _i =A _i , when A _i is 0～ When L, S _i is 0~L in turn; analyze the output of S _i according to the same method as above: refer to the above k=j+1~L paragraphs, remove the D ₀₀ ~D _0j-1 among them, and take j=0, for example, When k=L, the tubes P _a1L and S _i are connected to V _Pe1 through TG ₀ and P _a1L , there is 0 diode between S _i and V _Pe1 , V _Si =V _DC -0V _Don , that is, S _i =L, ‥… , no more details; or refer to patent 201310211023.2 (writing circuit and reading circuit of arbitrary K value and 8-value DRAM).

Embodiment 3: Description of the PMOS transistor band-pass, high-pass and low-pass variable threshold circuit functions of the present invention:

Refer to [1] patent 201110291038.5 'PMOS tube band-pass-band-resistance and high-pass-low-pass variable threshold circuit' (invention content, drawings and embodiment 1, etc.), patent [2] 201110280921.4' 8-value storage embedded in DRAM storage matrix The 8-value information refreshing method of unit and related circuit' (accompanying drawing and embodiment 4 etc.), according to the characteristic variable threshold circuit of the present invention, describe as follows:

〔1〕PMOS tube with pass-variable threshold circuit: redraw the figure 6 of the patent [1] or [2] to the figure 5 of the patent of the present invention, in which the PMOS tubes Q ₂ , Q ₄ , Q ₅ , and Q _B1 are sequentially rewritten as P _{2 . _ _ _ _ _ _ _ _ _ _ _ _ _} V _tp2 ∣, v _bx0 ＝V _ex0 +V _DC ＝V _ref0 －V _tn3 －∣V _tp4 ∣; the gates of transistor N ₁ and P ₄ are connected to input in, the voltage of input in is V _in , the gate of transistor N ₃ and P ₂ The poles are respectively connected to the reference voltages V _ref0 and V _ref1 ; first analyze the branch circuits of the tubes N ₁ and P ₂ , only when the voltage difference between the two gates of the tubes N ₁ and P ₂ is V _g1 -V _g2 =V _in -V _ref1 =V _gs1 + When V _sg2 >V _tn1 +∣V _tp2 ∣ (V _in >v _bx1 ), the branches of tubes N ₁ and P ₂ are turned _{on ;} When the voltage difference between the gates of N ₃ and P ₄ is V _g3 -V _g4 =V _ref0 -V _in >V _tn3 +∣V _tp4 ∣ (V _in <v _bx0 ), the branches of tubes N ₃ and P ₄ conduct otherwise, the branch is cut off. The band-stop output v _/dvi~j passes through the PMOS NOT gate to generate the band-pass output v _dvi~j , which is composed of the tube _P5 and the resistor R0 _; v _dvi~j is sent to the gate of the controlled PMOS tube P _b1 , and the tube The source of P _b1 is connected to V _DC , and the drain of tube P _b1 is connected to the external circuit; it can be concluded that: when v _bx1 >V _in >v _bx0 ( _{in the range of V in} ), the branches of tubes N ₁ and P ₂ and the tube Both N ₃ and P ₄ branches are cut off, the current of resistor R ₁ is 0, v _/dvi～j =V _DC , so P ₅ is cut off, v _dvi～j =V _D <V _DC , so that the tube P _b1 is turned on; Because in inputs the K value signal, only when in=i~j, P _b1 is turned on; the band interval of in is (i, j); when in≠i~j, P _b1 is cut off; The PMOS transistor P _b1 is called a band-pass variable-threshold PMOS transistor P _b1 ; record t _bi~j = (i, j), t _bi~j is the band-pass threshold, vt _bi~j is the band-pass threshold voltage, vt _{bi~ j} ＝(vt _bi－ ，vt _bj+ ), you can choose vt _bj+ ＝(V _in (j+1)+V _in (j))/2， vt _bi－ ＝(V _in (i)+V _in (i－ 1))/2, when vt _bi－ <V _in <vt _bj+ is satisfied, P _b1 is on, otherwise, P _b1 is off; use t _bi~j or vt _{bi~j to} mark next to the effective input of tube P _b1 , as shown in Figure 5 The effective input of P _b1 on the right is represented by a small square (the gate of the ordinary PMOS transistor is represented by a small circle, which is distinguished), and the effective input is connected to the input in (in is connected to the gate of N ₁ and P ₄ ), and this input is called a band pass Variable threshold type PMOS transistor P _b1 is effectively input; when j=i, the band interval is the smallest (only one value i), t _bi~j =t _bi =i, vt _bi~j =vt _bi , the bandpass variable of the smallest band interval The threshold PMOS transistor P _b1 is called the band-pass variable threshold PMOS transistor P _b1 with the smallest interval.

Note: (1) The logic level of logic value k without noise is referred to as k level for short, and the k level of in is recorded as _Vin (k); the logic value of in is expressed as in=k; the abbreviation 'in=i, i +1, i+2‥..., j－1, j' is in=i~j, for example, t _b2~5 = (2, 5), in takes 2, 3, 4, 5, abbreviated as in=2~5, and so on; (2) Resistor R ₀ can be replaced by NMOS tube N ₀ , and tube N ₀ and P ₅ constitute a CMOS inverter (P ₅ and N ₀ gates are connected to the grid pole, drain connected to drain, N ₀ source connected to V _D ); (3) the gates of NMOS and PMOS transistors have a small threshold fuzzy area (turning area), and the turn-on and cut-off of the tube requires the gate voltage to be outside the turning area , the conduction and cut-off of the tube cannot be determined in a very small turning area, the above-mentioned vt _bi- and vt _bj+ are selected as the middle value of the two levels, and the anti-interference ability is the strongest; (4) the N ₁ and P ₂ branches of the tube in Fig. 5 The N ₃ and P ₄ branches of the summation tube are symmetrically called the high-pass branch and the low-pass branch respectively.

〔2〕PMOS tube high-pass variable threshold circuit: delete the tubes N ₃ , P ₄ and their connections in the low-pass branch in Figure 5 (note: when V _ref0 =0, the tubes N ₃ and P ₄ are always closed , the effect is lost, and the gate is removed), and the high-threshold circuit shown in Figure 6 is obtained, and the branch circuit of the tube N ₁ and P ₂ is analyzed. When the gate voltage difference between the tube N ₁ and P ₂ is V _in -V _ref1 >V _tn1 +∣V _tp2 ∣(V _in >v _bx1 ), the branches of tubes N ₁ and P ₂ are turned on, otherwise, the branches of tubes N ₁ and P ₂ are cut off; because the input of in is a K value signal, only when in≥ When i (in=i~L), the branches of tubes N ₁ and P ₂ are turned on, so v _dvi~L is low level, which makes the controlled PMOS tube P _b1 turn on; the PMOS tube connected with a high-threshold circuit P _b1 is called a high-pass variable-threshold PMOS transistor, because the highest logic value is L, record t _hi = (i, L), t _hi is called a high-pass threshold, vt _hi means that when _Vin > vt _hi , the tube P _b1 is turned on, Use t _hi or vt _hi to mark next to the effective input of the tube P _b1 ; when i=L, the high interval is the smallest, t _hi =t _hL , vt _hi =vt _hL ; the high-pass variable-threshold PMOS transistor P _b1 in the minimum high interval is called the interval The smallest high-pass variable-threshold PMOS transistor P _b1 .

〔3〕PMOS tube low pass variable threshold circuit: delete the tubes N ₁ and P ₂ of the high pass branch in Figure 5 and their connections (note: when V _ref1 =V _DC , the tubes N ₁ and P ₂ cut off, lose function, and gate), and obtain the low-threshold circuit shown in Fig. 7, analyze the branch circuit of tube N ₃ and P ₄ , when the gate voltage difference V _ref0 －V _in of tube N ₃ and P ₄ > When V _tn3 +∣V _tp4 ∣(that is, V _in <v _bx0 ), the branches of tubes N ₃ and P ₄ are turned on, otherwise, the branches of tubes N ₃ and P ₄ are cut off. When ≤j (in=0~j), P _b1 is turned on (because P ₅ is turned on, the drain of P ₅ v _/dv0~j is high level, and v _/dv0~j is connected to the circuit composed of P ₆ and N ₇ CMOS non-gate input, then the non-gate output v _dv0~j is low level, v _dv0~j makes the controlled PMOS transistor P _b1 conduction); the PMOS transistor P _b1 connected with the low-pass threshold circuit is called low The general formula variable threshold PMOS transistor, record t _/hj+1 = (0, j), t _/hj+1 is called the low-pass threshold, vt _/hj+1 means that when V _in <vt _/hj+1 , the tube P _b1 leads Pass; use t _lj or vt _lj to mark next to the effective input of tube P _b1 ; when j=0, the low interval is the smallest, t _/hj+1 = t _/h1 , vt _/hj+1 = vt _/h1 , the minimum low interval is low The general variable-threshold PMOS transistor P _b1 is called the low-pass variable-threshold PMOS transistor P _b1 with the smallest interval.

Note: (1) Connect the substrate of the PMOS transistor to the power supply voltage V _DC (the highest potential is V _DC ), and ground the substrate of the NMOS transistor (the lowest potential is ground); if the lowest potential V _min is lower than the ground potential, use The highest potential V _max is higher than the V _DC potential, then the substrate of the PMOS transistor is connected to V _max , and the substrate of the NMOS transistor is connected to V _min . For the convenience of observation, the connection of the substrate is omitted in the figure; (2) Change the reference voltage V _ref0 and V _ref1 can adjust the size of v _bx0 and v _bx1 respectively, so as to realize the adjustment of the above-mentioned band-pass threshold, high-pass threshold and low-pass threshold respectively, so as to meet various practical needs.

Embodiment 4: Description of the present invention adopting band-pass threshold loading technology, variable threshold gate PMOS transistor and gate controlled PMOS transistor:

When the value of j changes, both the length of the high-value region and the length of the low-value region require that the threshold characteristics of P _e0 and P _e1 change with the new threshold loading. Generally, each stage of information processing requires the threshold of the tube (such as P _e0 and P _e1 ) The characteristics are different; in Figures 5, 6 and 7, the output v _dv0~j are all directly delivered to the gate of the controlled PMOS transistor P _b1 , and the threshold value is fixed, which cannot meet the requirements of changing at any time; the present invention uses the virtual frame in Figure 5 The internal circuit is redrawn as Figure 8, the output v _dvi~j of Figure 8 is sent to the gate of the controlled PMOS transistor P _b1 through the source and drain of the tube P _c1 , v _dvi~j takes over the source of P _c1 , and the drain of the tube P _c1 takes over The gate of P _b1 , the gate of the tube P _c1 is connected to the control signal v _tg , under the action of the low level of v _tg , the tube P _c1 is turned on, so v _dvi~j are transmitted to the controlled PMOS through the source and drain of the conduction tube P _c1 The gate of the transistor P _b1 makes the controlled PMOS transistor P _b1 have the characteristics of a band-pass threshold of t _bi~j ; the PMOS transistor P _c1 connected with a band-pass variable threshold circuit is called a variable threshold gate PMOS transistor P _c1 , and The tube P _b1 is called a gate-controlled PMOS tube. According to the symbol diagram shown in the right part of Figure 8, the effective input in is connected to the side of the small square, the source of the tube P _c1 is connected to the bottom of the small square, and the source of the tube P _c1 is marked as the source The band-pass threshold t _bi~j to be transmitted, when the control signal v _tg drives the tube P _c1 to be turned on, the turned-on tube P _c1 will load the band-pass threshold t _bi~j to the tube P _b1 , and the loading is to make the gating controlled The tube P _b1 has the characteristic of the band-pass threshold t _bi~j : when in=i~j, the tube P _b1 is turned on; otherwise, the tube P _b1 is cut off. When the band-pass threshold loaded to the tube P _b1 is required to be variable at any time, multiple variable-threshold gating PMOS tubes can be used to load the gate-controlled tube P _b1 in time-sharing, for example, the variable-threshold gating PMOS shown in Figure 3 The effective input of tubes P _c1 ~ P _c9 , the effective input of tubes P _c1 ~ P _c9 is connected to A _i , and its drains are all connected to gate g _/hj of controlled tube P _e0 , and the gates of tubes P _c0 ~ P _c9 are respectively connected to control For signals v _/tg0 ～v _/tg9 , the low-pass thresholds of the sources of tubes P _c1 ～P _c9 to be transmitted are respectively t _/h1 ～t _/h9 ; for each j, j=1～9, in tubes P _c1 ～P _c9 Only one tube P _cj is turned on, and the other tubes are turned off, so only t _/hj is loaded to the tube P _e0 during t _/h1 ~ t _/h9 ; V _DC - V _D = 1.5 volts in Fig. 5 ~ 8.

Both the low-pass threshold t _/hj and the high-pass threshold t _hj+1 belong to the band-pass threshold. The band-pass threshold t _{bi ~ L} indicates that the conduction interval is (i, L), and the high-pass threshold t _hi indicates that the conduction interval is also (i, L ), that is, t _bi～L = t _hi ; the band-pass threshold t _b0～j-1 indicates that the conduction interval is (0, j-1), and the low-pass threshold t _/hj indicates that the conduction interval is also (0, j-1 ), namely t _b0～j-1 =t _/hj , so t _/hj and t _hj+1 are special band-pass thresholds t _b0～j-1 and t _bj+1～L , high-pass threshold t _hi and low-pass threshold Threshold t _/hj can be referred to as band-pass threshold _tbi~L and _{tb0 ~j-1} respectively, high-pass variable-threshold PMOS transistor with high-pass threshold thi and low-pass variable-threshold PMOS transistor with low-pass threshold t _/hj The tubes can be called band-pass thresholds as _tbi~L and _tb0~j-1 band-pass variable-threshold PMOS tubes respectively. In addition, referring to Figures 5-8, the variable-threshold circuit to which a band-pass variable-threshold PMOS tube belongs Contains two driving outputs v _dvi~j and v _/dvi~j , which can simultaneously realize the band-pass threshold t _bi~j and the band-stop threshold t _/bi~j , therefore, for the same effective input in, the band-pass threshold t _bi~ The band-pass variable-threshold PMOS transistor of _j , the band-stop variable-threshold PMOS transistor of band-stop threshold t _/bi～j , and the variable-threshold gate PMOS transistor with the same band-pass threshold or band-stop threshold all share the same variable-threshold circuit ; The high-pass and low-pass variable-threshold PMOS transistors are classified as special band-pass variable-threshold PMOS transistors, which have the same shared performance and will not be described again. For example, the tubes P _c2 , P _a02 , P _d1 and P _a12 marked t _/h2 or t _h2 in Figure 1 share the same variable threshold circuit, and the same variable threshold circuit drives four PMOS transistors respectively, thereby simplifying the circuit.

Embodiment 5: other instructions:

The tube P _e2 in the J _i output circuit and the tubes P _b0 ~ P _bL in the control signal forming circuit have a level conversion function, and convert the gate drive voltage of the tube with a small range of change into an output voltage with a large range of change (the output is between 0 and V _DC For example, it can be seen from Figures 11 to 14 that the magnitude of the gate drive voltage g _/hj of the transistor P _e2 is small, while the magnitude of the output J _i is large, and g _/hj and J _i are opposite to each other.

The drains and sources of the NMOS transistor N _tga and the PMOS transistor P _tga are connected to form a CMOS transmission gate TG _a , and the gates of the transistor N _tga and P _tga are the positive control terminal and the negative control terminal of TG _a respectively. When the positive and negative control terminals of TG _a are V _DC and 0 respectively, TG _a is turned on, and when the positive and negative control terminals are 0 and V _DC respectively, TG _a is cut off; for the constant current source used, refer to the existing one shown in Figure 9 A multi-output precision mirror constant current source circuit diagram and symbol diagram. In order to reduce power consumption and improve performance, etc., the constant current source current takes a smaller value according to actual possibility; the diode used is a silicon diode, and the conduction voltage drop is V _Don , The conduction current takes a smaller value according to the actual possibility; V _DC = LV _Don + △, △ is the compensation offset required by the circuit characteristic of the K value storage unit.

Embodiment 6: Explanation of the Pspice computer simulation waveform diagrams 10-21 of FIGS. 3 and 4.

Fig. 3 is the 10-value half-subtractor circuit diagram of the present invention, carries out Pspice computer simulation to Fig. 3, 1. at first simulates the signal voltage working waveform figure of the 10-value half-subtractor circuit shown in Fig. 10 during 180～410 μ s, can whole Observing its working process, the order of waveforms from top to bottom is: A _i , B _i , S _i , J _i and g _/hj , where A _i is a periodic signal with a period of 16 μs, and A _i changes from 0 to 0 within a period of 16 μs. Increase to 9 in turn, and then rise from 2 to 7 in turn, Bi is a periodic signal with a period of 100μs _, and _Bi rises from 0 to 9 in turn within a period of 100μs; ②In order to clearly test all possible values of A _i and _Bi As a result of the subtraction operation, the horizontal axis of Figure 10 is enlarged to obtain the waveform diagrams during 180-240μs, 240-300μs, 300-360μs and 350-410μs, which are shown in Figures 11, 12, 13 and 14 respectively. 11 to 14, and check at the time when A _i and B _i are stable. When B _i =0, test the ten cases where A _i is 0 to 9 respectively. S _i =A _i , J _i =0; when B i _i = 1, the same way as the above test shows that when A _i ≥ 1, S _i = A _i -1, J _i = 0, when A _i = 0, S _i = 9, J _i = 9; when B _i =2, the test shows that when A _i ≥ 2, S _i =A _i -2, J _i =0, when A _i <2, S _i =A _i +8, J _i =9;‥‥ ‥When B _i =8, the test shows that when A _i ≥ 8, S _i =A _i -8, J _i =0, when A _i <8, S _i =A _i +2, J _i = 9; when B _i =9, the test shows that when A _i =9, S _i =0, J _i =0, when A _i <9, S _i =A _i +1, J _i =9; J _i = 9 means there is a borrow, J _i = 0 means there is no borrow, g _/hj and _Ji are the gate input and drain output of the tube P _e2 respectively, and it can be seen from Figures 11 to 14 that the amplitude of g _/hj is small , the magnitude of J _i is large, and g _/hj and J _i are mutually inverse; the test shows that the 10-valued half-subtractor circuit Fig. 3 satisfies the result of the 10-valued subtraction operation; Fig. 15 is a kind of 10-valued half-subtractor of the present invention at 180～410 μ s During the circuit control signal waveform diagram, the order of waveforms from top to bottom is: A _i , B _i , v _tg9 , v _tg8 , v _tg7 , v _tg6 , v _tg5 , v _tg4 , v _tg3 , v _tg2 , v _tg1 , v _tg0 , under the action of the control signal, the above operation is completed, wherein V _DC =6.5V, V _d =5V.

Fig. 4 is the 10-value half-adder circuit diagram of the present invention, carries out Pspice computer simulation to Fig. 4, 1. at first simulates the signal voltage working waveform figure of the 10-value half-adder circuit shown in Fig. 16 during 180～410 μ s, can whole Observing its working process, the order of waveforms from top to bottom is: A _i , B _i , S _i , C _i and g _/hj , where the cycles and waveforms of A _i and B _i are the same as those of the aforementioned 10-value half reducer; ② is The results of the addition operation for all possible values of A _i and B _i can be clearly checked, and the horizontal axis of Figure 16 is enlarged to obtain the signal voltages during 180-240 μs, 240-300 μs, 300-360 μs and 350-410 μs The working waveform diagrams are shown in Figures 17, 18, 19 and 20 respectively. Observe Figures 17 to 20 in turn, and check when A _i and B _i are stable. When B _i = 0, the values for A _i are 0 to 90 In this case, S _i =A _i , C _i =9; when B _i =1, it is found that when A _i <9, S _i =A _i +1, C _i =9, when A _i =9, S _i =0, C _i =0; when B _i =2, the test shows that when A _i <8, S _i =A _i +2, C _i =9, when A _i ≥8 , S _{i ＝} A _{i －8 ,} C _{i ＝} 0 _; When A _i ≥ 2, S _i =A _i -2, C _i =0; when B _i =9, the test shows that when A _i =0, S _i =9, C _i =9, when A _i When ≥1, S _i =A _i -1, C _i =0; C _i =9 means no carry, C _i =0 means carry, g _/hj and C _i are the gate input and drain of the tube P _e2 respectively Output, observing Figures 17 to 20, it can be seen that the amplitude of g _/hj is small, the amplitude of C _i is large, and g _/hj and C _i are mutually inverse; the test shows that the 10-value half adder circuit Figure 4 satisfies the result of the 10-value addition operation. Fig. 21 is a circuit control signal waveform diagram of a 10-valued half adder of the present invention during 180-410 μs, and the order of the waveforms from top to bottom is: A _i , B _i , v _tg9 , v _tg8 , v _tg7 , v _tg6 , v _tg5 , v _tg4 , v _tg3 , v _tg2 , v _tg1 , v _tg0 , under the action of the control signal, complete the above operation, note that the control signal waveforms in Figure 21 and Figure 15 are different, and the waveforms of v _tg9 ~ v _tg1 in the two figures are The difference conforms to the characteristics of the 10-valued half subtractor and half adder.

Embodiment 7: Comparison of PMOS tube band-pass, high-pass, low-pass variable threshold circuit and neuron MOS tube control threshold technology.

The threshold voltage is taken as the midpoint of the transition zone between the conduction and cut-off of the tube. In fact, it is impossible to distinguish the conduction and cut-off of the MOS tube in the transition zone, so the transition zone can be regarded as the threshold fuzzy zone; The equivalent threshold fuzzy area of the threshold circuit does not change with the increase of the K value, and its ability to distinguish K value signal input is higher than that of the neuron MOS tube (the equivalent threshold fuzzy area of the neuron MOS tube increases with the increase of the K value), The signal input is allowed to have a certain deviation from the standard value; (2) Although the PMOS tube high-threshold circuit uses 2 (or 4) MOS tubes and 1 resistor R ₁ , several MOS tubes occupy a silicon chip area larger than the neuron MOS tube capacitance Much smaller, R ₁ (which can be replaced by a constant current source) is the drive signal to form the conduction of the controlled PMOS tube, which requires very low accuracy for R ₁ ; while the neuron MOS tube uses capacitive coupling to change the threshold voltage, which requires high capacitance accuracy , increasing the difficulty of implementation; (3) The input capacitance of the PMOS tube high-pass variable threshold circuit is much smaller than that of the neuron MOS tube, and the high-frequency performance is better. The neuron MOS tube control threshold technology has great disadvantages; the neuron MOS tube has the following formula:

Among them, V _fg is the floating gate voltage, V ₁ is the signal input gate voltage, V _j is the control gate voltage, and the DC voltage V _j (j=2, 3, 4...,n) is selected according to the threshold value of the demand, and the formula (14) only The two variables V _fg and V ₁ are differentiated, dV _fg = (C ₁ /C _TOT )dV ₁ ; the width of the threshold fuzzy area of the floating gate △V _fg and the width of the threshold fuzzy area of the input gate △V ₁ satisfy,

ΔV _fg = (C ₁ /C _TOT ) ΔV ₁ , ΔV ₁ = (C _TOT /C ₁ ) ΔV _fg (15)

As the value of K increases, the number of input gate thresholds that need to be changed increases, and the required ratio C _TOT /C ₁ increases, and △V ₁ in formula (15) is ₁ times C _TOT /C of △V _fg , and the width △V _fg is determined, so △V ₁ increases, which shows that: with the increase of K value, ①The width of the threshold fuzzy area △V ₁ of the input gate increases, which reduces the signal resolution of the input gate K value, which is not conducive to large K values ② When the ratio C _TOT /C ₁ increases, C ₁ cannot be reduced, and the area occupied by all control gate capacitances will increase; for example, in a 10-value circuit, K=10, C ₀ =C _fg =30fF, C ₁ =0.8pF, the total capacitance of the input control gate is calculated to be 9.37pF (C _TOT =11.33C ₁ ); the thickness of SiO ₂ between the control gate and floating gate of the floating gate NMOS transistor is 35nm, and the corresponding unit capacitance is 1fF/μm ² , A 9.37pF capacitor occupies an area of 9370μm ² on a silicon wafer, an NMOS transistor occupies about 30μm ² , and a 9.37pF capacitor of a neuron MOS transistor occupies an area of about 312 NMOS transistors, that is, the control gate capacitance occupies a large area of silicon wafer. With the development of semiconductor integrated circuit technology, the size of MOS transistors is getting smaller and smaller, and the area ratio of the control gate capacitance area of neuron MOS transistors to the area of NMOS transistors is bound to be larger and larger. ③ Adding too much capacitance to the gate circuit of the neuron MOS transistor is harmful to high-frequency performance. The reduction of the feature size and the increase of the aspect ratio of the metal connection lead to an increase in the interconnection capacitance, causing crosstalk between multiple gates, and parasitic Increased capacitance creates additional interconnect delay and power consumption, indicating that adding too much capacitance is detrimental to high-frequency performance. ④Neuron MOS transistor floating gate capacitance leakage cannot be omitted. It takes a total of 10 years for a common non-volatile memory to lower the threshold voltage by 3V at a leakage current of 2.85x10 ^-22 A. As the value of K increases, the threshold voltage is required to decrease very little, and it is obviously not allowed to decrease by 3V, which shows that it is ideal and unrealistic that the leakage of the neuron MOS transistor is 0 based on the floating gate capacitance. ⑤ The static power consumption of the neuron CMOS inverter is 0 for the binary signal. As the K value increases, there is a state where the NMOS tube and the PMOS tube are turned on at the same time in the K value signal. As a result, the static power consumption is greater, and only the K value signal is the largest. If it is not turned on at the same time as the minimum value, the static power consumption is 0; ⑥The output of the neuron CMOS follower is often a capacitive load, and the output voltage rises and falls on a different track, which has a large hysteresis voltage, which is not conducive to the use in K value circuits. The width of the neuron MOS transistor threshold fuzzy area is △V ₁ , and when the K value is large, △V ₁ increases C _TOT /C by ₁ times according to formula (15), and △V ₁ may approach or exceed the step voltage of the K value signal, making the neuron Element MOS tube failure.

Claims (6)

1. A construction method of the K value half-subtractor adopting the band-pass threshold loading technique, is characterized in that: A _i is the minuend in the K value half-subtractor, B _i is the subtrahend, and S _i is originally a difference, J _i is the number of borrowing digits, where A _i , B _i , and S _i are K-value signals, and K-value signals have K logic values: 0, 1, 2, ..., L, where L=K-1, K =4, 5, 6, ..., J _i is a binary signal, and the binary signal has 2 logic values: 0, L; let A _i =k, B _i =j, for the determined j=1～L, When k<j, S _i =K+k-j>k, that is, S _i >A _i , when k=j, S _i =0, when k>j and j≠L, S _i =k- j<k, that is, S _i <A _i , when j=L, there is no k>j; for a certain j=0, S _i =A _i ; for j≠0, when k<j, there is a borrow , when k≥j, there is no borrowing, and for j=0, there is no borrowing; the construction method of the K value half reducer adopting the band-pass threshold loading technique is described as follows: ① For the determined j, j=1~L, according to S _i >A _i and S _i <A _i , the K-value half subtractor operation is divided into a high-value area and a low-value area, because t _b0~j-1 = t _/hj , t _bj+1～L ＝t _hj+1 , j≠L, using gate-controlled PMOS transistors P _e0 and P _e1 , P _e0 has the characteristics of low-pass threshold t _/hj , and P _e1 has high-pass threshold The characteristics of t _hj+1 , (1) high-value area: when k=0~j-1, the tube P _e0 is turned on, and S _i >A _i is realized; (2) low-value area: when k=j+1~L and j When ≠L, the tube P _e1 is turned on, and S _i <A _i is realized. When j=L, the low-value area is invalid, and only the high-value area is valid; when k=j, the tubes P _e0 , P _e1 , and P _d0 are all Cut off, S _i = 0; (3) use the PMOS non-gate output composed of P _e2 to form the J _i signal, the gate of the tube P _e2 takes over the gate g _/hj of P _e0 , when k<j, the tube P _e2 is turned on, J _i is high level, indicating that there is a borrow, when k≥j, the tube P _e2 is cut off, and J _i is low, indicating that there is no borrow; ②The circuit in the high-value region includes band-pass variable threshold PMOS transistors P a00 ～P _{a0L -1} and diodes D ₀₀ ～D _0L-1 connected in series. The high-pass thresholds of transistors P _a01 ～P _a0L-1 are t _h1 ～t _hL in turn _-1 , the low-pass threshold of the tube P _a00 is t _/h1 , the source of the tube P a00 ~ P _{a0L -1} is connected to the power supply V _DC through P _e0 , when k=j-1 ~ 0 and j≠0, the tube P _e0 is turned on, the output of S _i is connected to V _DC through m ₀ conduction diodes, and as k changes from j-1 to 0, the tubes P _a0j-1 ~ P _a00 are sequentially turned on to control m ₀ from 0 to j-1 , so S _i is from L to L-j+1; the low-value region circuit includes high-pass variable threshold PMOS transistors P _a11 ~P _a1L and series diodes D ₁₂ ~D _1L , connect D _1L to D ₀₀ , so that D ₁₂ ~ D _1L and D ₀₀ ～D _0L-1 form a total series diode sequence D ₁₂ ～D _0L-1 , the high-pass thresholds of tubes P _a11 ～P _a1L are t _h1 ～t _hL in turn, when k=L～j+1 and When 0<j<L, the tube P _e1 is turned on, the sources of the tubes P _a11 ~ P _a1L are connected to the power supply V _DC through P _e1 , and the output of S _i is connected to V _DC through m ₁ conduction diodes, and the k is From L to j+1, use the tubes P _a1L ~ P _a1j+1 to conduct sequentially to control m ₁ from j to L-1, so the output of S _i is from L-j to 1; when k=j≠0, the tube P _e0 , P _e1 , and P _d0 are all cut off, and the output of S _i is 0; ③For each j, j=0~L, the value of j is judged by K logical value discrimination gates U ₀ ~U _L , and the band-pass threshold of logic value discrimination gate U _m is t _bj , that is, only when the input of U _m is j. The output of _m is high level, otherwise, the output of U _m is low level, and the band-pass thresholds of U ₀ ~ U _L are respectively t _b0 ~ t _bL ; all U ₀ ~ U _L inputs are j, U ₀ ~ U _L The outputs are respectively v _tg0 ~v _tgL , and v _tg0 ~v _tgL generate inverting output v _/tg0 ~v _/tgL through the NOT gates M ₀ ~M _L respectively; thus it is completed: (1) For j≠0, gate at variable threshold v _/tgj in PMOS transistors P _c1 ～P _cL drives P _cj to turn on, and the thresholds of the sources of transistors P _c1 ～P _cL to be transmitted are t _/h1 ～t _/hL respectively, so only t _/h1 in transistors P _c1 ～P _cL The t _/hj in ~t _/hL is loaded into the tube P _e0 , and the tube P _e0 is used to control the length of the high-value area (0, j-1) j-2, j≠0; when j=L, the length of the high-value area is L; (2) For j ≠ 0, v _/tgj drives P _dj to be turned on in the threshold-variable gate transistors P _d1 ~ P _dL , and the thresholds of the sources of the transistors P _d1 ~ P _dL-1 and P _dL are respectively t _h2 ~ t _hL , t _/h1 , when j<L, only t _hj+1 of t _h2 ～t _hL in tubes P _d1 ～P _dL-1 is loaded into tube P _e1 ; when j=L, tube P _dL Load t _/h1 to the tube P _e1 to invalidate the low-value area; turn on the tube P _e1 and P _d0 to control the low-value area j+1~L length L-j, j≠L; (3) in the CMOS transmission gate TG ₁ v _tgj and v _/tgj in ~TG _L only drive TG _j to turn on, j=1~L, S _i connects to the drain of P _a0j-1 through the turned-on TG _j , and the maximum condition of S _i is k=j- 1. At this time, S _i is connected to V _DC through the turned-on TG _j and P _a0j-1 to realize S _i =L; (4) When j=0, use v _{/tg0 to} drive TG ₀ and tubes P _d0 and P _c0 to conduct connected, the source of P _d0 is connected to V _DC , the drain of P _d0 is connected to the source of P _a11 ~P _a1L , the source of P _a11 ~P _a1L is connected to V _DC through P _d0 , and S _i is connected to the drain of P _a1L through TG ₀ pole, the circuit in the low-value area works and becomes a digital follower, realizing S _i =A _i , at this time, the length of the low-value area is L, and the circuit in the high-value area is invalid; the gate of the tube P _c0 is connected to v _/tg0 , and the drain of P _c0 is connected to The gate of P _e0 and the source of tube P _c0 are connected to DC voltage V _DC , so that when j=0, the output of J _i is the above-mentioned level indicating no borrowing, and the formation of J _i signal when j=0 is supplemented in ①. 2. a kind of construction method of the K-value half-adder that adopts band-pass threshold loading technology according to claim 1 forms a kind of construction method of the K-value half-adder that adopts band-pass threshold loading technology that the same feature forms, its feature It is: in the construction method of the K-value half-subtractor adopting the band-pass threshold loading technology: (1) Firstly, the band-pass thresholds of U ₁ ~ U _L are respectively taken as t _bL ~ t _b1 ; (2) Next, borrow The number J _i is taken as the number of carry C _i , except that when j=0, no borrow is taken as no carry, all borrows are taken as no carry, and no borrow is taken as there is carry, and the source of the tube P _c0 is connected to DC Voltage V _d , when j=0, C _i output is the above-mentioned level indicating no carry, V _d ≠ V _DC ; (iii) finally, the half subtractor is taken as a half adder, and A _i , B _i and S _i are sequentially Take it as the summand, the addend and the basic sum, then the construction method of the K-value half-subtractor using the band-pass threshold loading technology becomes the construction method of the K-value half-adder using the band-pass threshold loading technology. 3. a kind of construction method that adopts the K value half-subtractor of band-pass threshold loading technique according to claim 1 forms a kind of K-value half-subtractor circuit that adopts band-pass threshold loading technique, it is characterized in that: The K-value half-subtractor circuit using the band-pass threshold loading technique includes: a control signal forming circuit, a high value area and a high gating circuit, a low value area and a low gating circuit, an S _i output circuit and a J _i output circuit, K The specific circuit structure of the value half reducer is described as follows: ①The control signal forming circuit is composed of logic value discrimination gates U ₀ ~U _L and _CMOS NOT gates _{M 0} ~ _{ML .} P _bL and constant current source I ₀ ~ _IL constitute, the band-pass thresholds of tubes P _b0 ~P _bL are t _b0 ~t _bL respectively, where t _b0 =t _/h1 , t _bL =t _hL , that is, tubes P _b0 and P _bL are the low-pass and high-pass variable-threshold PMOS transistors with the smallest interval respectively. The effective inputs of the tubes P _b0 ~ P _bL are all connected to Bi, the sources of the tubes P _b0 ~ P _bL are connected to the power supply _{V DC} , and the tubes P _b0 ~ P _{The bL} drains are respectively connected to the upper end of the constant current source I ₀ ～ _IL , and the upper end of I ₀ ～ _IL is used as U ₀ ～U _L to output v _tg0 ～v _{tgL respectively} , and the lower end of the constant current source I ₀ ～ _IL is grounded, and the constant current source current Both flow from the upper end to the lower end, v _tg0 ~ v _tgL are respectively connected to the input of the NOT gate M ₀ ~ M _L , and the outputs of M ₀ ~ M _L are respectively v _/tg0 ~ v _/tgL , thus obtaining mutually inverse control signals v _tg0 ～v _tgL and v _/tg0 ～v _/tgL , M ₀ ～M _L operating voltage is V _DC , input j for each B _i , j=0～L, only v _tgj is high among v _tg0 ～v _tgL level, other outputs are low level; _②High value area and high gating circuit: the high gating circuit is _composed of variable threshold gating PMOS transistors P _c1 ~ P _cL , gating controlled PMOS transistor P _e0 and PMOS transistor P _c0 ; The low-pass thresholds are t _/h1 ~ t _/hL respectively, the effective input of the tubes P _c1 ~ P _cL is connected to A _i , the gates of the tubes P _c0 ~ P _cL are connected to the control signal v _/tg0 ~ v _{/tgL respectively} , and the drain All poles take over the grid g _/hj of P _e0 ; for each B _i input j, j=1~L, only one tube P _cj is turned on among the tubes P _c1 ~P _cL , and the other tubes are cut off, so at t _/h1 ~ In t _/hL , only t _/hj is loaded to the tube P _e0 , the source of the tube P _e0 is connected to V _DC , and its drain is connected to the source of P a00 ~ P _{a0L -1} ; the circuit in the high-value area includes a PMOS tube P with a pass-through threshold a00 ～P _{a0L -1} and series diodes D ₀₀ ～D _0L-1 , the high-pass thresholds of tubes P _a01 ～P _a0L-1 are t _h1 ～t _hL-1 in turn, and the low-pass thresholds of tube P _a00 are t _/h1 , The negative poles of tubes D ₀₀ ~ D _0L-2 are respectively connected to the positive poles of D ₀₁ ~ D _0L-1 , the effective input of tubes P a00 ~ P _{a0L -1} is connected to A _i , and the drains of tubes P a00 ~ P _{a0L -1} are respectively connected to D ₀₀ ~ D The negative pole of _0L-1 , the input of A _i is k, when k=0~j-1 and j≠0, the tube P _e0 is turned on, and the source of the tubes P a00 ~ P _{a0L -1} is connected to V _DC through P _e0 , the circuit works in the high-value area, use the tube P _e0 to turn on and control the length j-2 of the high-value area (0, j-1), j≠0, when k=j~L, the tube P _e0 is cut off, and the tube P _a00 ~ The source of P _a0L-1 is disconnected from V _DC , and the circuit in the high value area does not work; ③Low value area and low gating circuit: The low gating circuit is composed of variable threshold gating PMOS transistors P _d1 ~P _dL , gating controlled PMOS transistor P _e1 and PMOS transistor P _d0 ; the source of the transistor P _d1 ~P _dL-1 The high-pass thresholds of the poles to be transmitted are t _h2 ~ t _hL respectively, and the low-pass thresholds of the sources of P _dL to be transmitted are t _{/ h1} ; the gates of the transistors P _d0 ~ P _dL are connected to the control signals v _/tg0 ~ v _{/tgL respectively} , and P _d1 ~ The drain of P _dL takes over the gate of P _e1 , and the effective input of P _d1 ~ P _dL is connected to A _i ; for each j, j=1 ~ L-1, only one of P _d1 ~ P _dL-1 is turned on, P _dj , the rest of the tubes are cut off, and t _hj+1 is selected from t _h2 ~ t _hL to load the tube P _e1 , and j=L, the tube P _dL is turned on, and t _/h1 is loaded to the tube P _e1 ; the tubes P _e1 and P _d0 are drained The pole takes over the source of P _a11 ~P _a1L , the source of P _e1 and P _d0 is connected to V _DC ; when k=j+1~L and 0<j<L, the tube P _e1 is turned on, and the source of P _a11 ~P _a1L The pole is connected to V _DC through P _e1 , and the circuit in the low-value area works; the circuit in the low-value area includes high-threshold PMOS transistors P _a11 ～P _a1L and series diodes D ₁₂ ～D _1L , and the negative poles of tubes D ₁₂ ～D _1L-1 take over respectively D ₁₃ ～D _1L positive pole, D _1L negative pole connected to D ₀₀ positive pole, connect D ₁₂ ～D _1L and D ₀₀ ～D _0L-1 in series to form 2L-1 series diode series, the high-pass thresholds of tubes P _a11 ～P _a1L are respectively It is t _h1 ～t _hL , its effective input is connected to A _i , the drains of tubes P _a12 ～P _a1L are respectively connected to the negative poles of D ₁₂ ～D _1L , and the drain of tube P _a11 is connected to the positive pole of D ₁₂ ; when j=0, tube P _d0 Turn on, the source of the tubes P _a11 ~ P _a1L is connected to V _DC through P _d0 , the circuit in the high value area is invalid, the circuit in the low value area works and forms a digital follower, and the low value area is controlled by the conduction of the tubes P _e1 and P _d0 (j+1, L) length L-j-2, j≠L; when k=0~j and j≠L, the tube P _e1 is cut off, and the sources of the tubes P _a11 ~P _a1L are disconnected from V _DC , The circuit in the low-value area does not work; for j=L, when k≠0, the tube P _e1 is cut off, and when k=0, the tube P _e1 is turned on, and the tubes P _a11 ~ P _{a1L are} all cut off, and the circuit in the low-value area is invalid , circuit work in high value area; ④S _i output circuit and J _i output circuit: S _i output circuit is composed of CMOS transmission gate TG ₀ ~TG _L and constant current source I _Si , the input of transmission gate TG ₁ ~TG _L respectively takes over the drain of P a00 ~P _{a0L -1} , the input of TG ₀ takes over the drain of P _a1L , the output of TG ₀ ~ _TGL is connected to the upper end of the constant current source I _Si , the upper end of I _Si is used as the output of _Si , the lower end of I _Si is grounded, the positive control end of TG ₀ ~ TG _L and the negative control The terminals are respectively connected to v _tg0 ~v _tgL and v _/tg0 ~v _/tgL , the diode conduction voltage drop is V _Don , for each j, j=1~L, only one TG _j among TG ₁ ~TG _L is turned on , S _i connects to the drain of P _a0j-1 through the turned-on TG _j , for j=0, S _i takes over the drain of P _a1L through the turned-on TG ₀ ; select V _DC = LV _Don + △, △ is stored as K value The offset required by the unit circuit characteristics; J _i output circuit consists of PMOS tube P _e2 and constant current source I _Ci , the source of tube P _e2 is connected to V _DC , the gate of tube P _e2 is connected to P _e0 gate g _/hj , and the drain of tube P _e2 is connected to constant current source I The upper end of _Ci , the upper end of I _Ci is output as J _i , the lower end of I _Ci is grounded, the gate of P _c0 is connected to v _/tg0 , the drain of P _c0 is connected to the gate of P _e0 ; for j≠0, when k<j, the pipe P _e0 Gate g _/hj voltage V _g/hj < V _DC , tube P _e2 is turned on, J _i outputs high level V _DC , which means there is a borrow. When k≥j, V _g/hj = V _DC , tube P e2 When P _e2 is cut off, the output of J _i is low level 0, indicating no borrow; the source of the tube P _c0 is connected to the DC voltage V _DC , so that when j=0, the output of J _i is the above-mentioned level indicating no borrow; all constant current The source current direction is from the upper end to the lower end. 4. a kind of construction method that adopts the K value half-subtractor of band-pass threshold-loading technology to form according to claim 3 a kind of K-value half-subtractor circuit that adopts band-pass threshold-loading technology is characterized in that: In the K-value half-subtractor circuit of adopting band-pass threshold loading technology described above, get K=10, then draw a kind of 10-value half-subtractor circuit that adopts band-pass threshold loading technology, 10-value half-subtractor circuit comprises: control Signal forming circuit, high value area and high gating circuit, low value area and low gating circuit, S _i output circuit and J _i output circuit; the specific circuit structure of the 10-value half reducer is described as follows: ①The control signal forming circuit is composed of logic value discrimination gates U ₀ ~ U ₉ and CMOS NOT gates M ₀ ~ M _9. The discrimination gates U ₀ ~ U ₉ are respectively composed of band-pass variable threshold PMOS transistors P _b0 ~ P _b9 and constant current sources I ₀ ~ I ₉ are formed, and the band-pass thresholds of tubes P _b0 ~ P _b9 are t _b0 ~ t _b9 respectively, where t _b0 = t _/h1 , t _b9 = t _h9 , that is, tubes P _b0 and P _b9 are the low-pass and high-pass variable-threshold PMOS transistors with the smallest interval respectively. The effective inputs of the tubes P _b0 ~ P _b9 are all connected to Bi, the sources of the tubes P _b0 ~ P _b9 are connected to the power supply _{V DC} , and the tubes P _b0 ~ P The drains of _b9 are respectively connected to the upper end of the constant current source I ₀ ~ I ₉ , and the upper end of I ₀ ~ I ₉ is respectively used as U ₀ ~ U ₉ to output v _tg0 ~ v _tg9 , the lower end of the constant current source I ₀ ~ I ₉ is grounded, and the constant current source current Both flow from the upper end to the lower end, v _tg0 ~ v _tg9 are respectively connected to the input of the NOT gate M ₀ ~ M ₉ , and the outputs of M ₀ ~ M ₉ are respectively v _/tg0 ~ v _/tg9 , thus obtaining mutually inverse control signals v _tg0 ～v _tg9 and v _/tg0 ～v _/tg9 , the working voltage of M ₀ ～M ₉ is V _DC , input j for each B _i , j=0～9, only v _tgj among v _tg0 ～v _tg9 is high level, other outputs are low level; ②High value area and high gating circuit: the high gating circuit is composed of variable threshold gating PMOS transistors P _c1 ~ P _c9 , gating controlled PMOS transistor P _e0 and PMOS transistor P _c0 ; the sources of the transistors P _c1 ~ P _c9 are waiting The low-pass thresholds are respectively t _/h1 ~ t _/h9 , the effective input of the tubes P _c1 ~ P _c9 is connected to A _i , the gates of the tubes P _c0 ~ P _c9 are respectively connected to the control signal v _/tg0 ~ v _/tg9 , and the drain All poles take over P _e0 gate g _/hj ; input j for each B _i , j=1~9, only one tube P _cj is turned on among the tubes P _c1 ~P _c9 , and the other tubes are cut off, so at t _/h1 ~ In t _/h9 , only t _/hj is loaded to the tube P _e0 , the source of the tube P _e0 is connected to V _DC , and its drain is connected to the source of P _a00 ~ P _a08 ; the circuit in the high value area includes PMOS tubes P a00 ~ P _a00 ~ P _a08 and diodes D ₀₀ ～ D ₀₈ in series, the high-pass thresholds of tubes P _a01 ～ P _a08 are t _h1 ～ t _h8 in turn, the low-pass threshold of tube P _a00 is t _{/ h1} , and the negative poles of tubes D ₀₀ ～ D ₀₇ respectively take over D ₀₁ ~ D ₀₈ are positive, the effective input of tubes P _a00 ~ P _a08 is connected to A _i , and the drains of tubes P _a00 ~ P _a08 are respectively connected to the negative poles of D ₀₀ ~ D ₀₈ ; the input of A _i is k, when k = 0 ~ j-1 And when j≠0, the tube P _e0 is turned on, the sources of the tubes P _a00 ~ P _a08 are connected to V _DC through P _e0 , the circuit in the high-value area works, and the tube P _e0 is turned on to control the high-value area (0, j- 1) The length j-2, j≠0, when k=j~9, the tube P _e0 is cut off, the source of the tubes P _a00 ~P _a08 is disconnected from V _DC , and the circuit in the high value area does not work; ③Low value area and low gating circuit: The low gating circuit is composed of variable threshold gating PMOS transistors P _d1 ~ P _d9 , gating controlled PMOS transistor P _e1 and PMOS transistor P _d0 ; the sources of the transistors P _d1 ~ P _d8 are waiting The high-pass thresholds for transmission are t _h2 ~ t _h9 , and the low-pass thresholds for P _d9 sources to be transmitted are t _{/ h1} ; the gates of the tubes P _d0 ~ P _d9 are respectively connected to the control signal v _/tg0 ~ v _/tg9 , and the tubes P _d1 ~ P The drain of _d9 is connected to the gate of P _e1 , and the effective input of the tubes P _d1 ~ P _d9 is connected to A _i ; for each j, j=1 ~ 8, only one tube P _dj of the tubes P _d1 ~ P _d8 is turned on, and the other tubes are cut off , select t _hj+1 from t _h2 to t _h9 to load to the tube P _e1 , and j=9, the tube P _d9 is turned on, and t _/h1 is loaded to the tube P _e1 ; the drains of the tubes P _e1 and P _d0 take over P _a11 ~P _a19 source, the source of the tube P _e1 and P _d0 is connected to V _DC ; when k=j+1~9 and 0<j<9, the tube P _e1 is turned on, and the source of the tube P _a11 ~P _a19 is passed through When P _e1 is connected to V _DC , the circuit in the low-value area works; the circuit in the low-value area includes PMOS transistors P _a11 ~ P _a19 with pass-through thresholds and series diodes D ₁₂ ~ D ₁₉ , and the negative poles of tubes D ₁₂ ~ D ₁₈ respectively take over D ₁₃ ~ The positive pole of D ₁₉ , the negative pole of D ₁₉ is connected to the positive pole of D ₀₀ , and D ₁₂ ~ D ₁₉ and D ₀₀ ~ D ₀₈ are connected in series to form 17 series diode sequences. The high-pass thresholds of tubes P _a11 ~ P _a19 are t _h1 ~ t _h9 respectively, Its effective input is connected to A _i , the drains of the tubes P _a12 ~ P _a19 are respectively connected to the negative poles of D ₁₂ ~ D ₁₉ , and the drain of the tube P _a11 is connected to the positive pole of D ₁₂ ; when j=0, the tube P _d0 is turned on, and the tubes P _a11 ~ The source of P _a19 is connected to V _DC through P _d0 , the circuit in the high value area is invalid, the circuit in the low value area works and forms a digital follower, and the conduction of the tubes P _e1 and P _d0 is used to control the low value area (j+1, 9) Length 9-j-2, j≠9; when k=0~j and j≠9, the tube P _e1 is cut off, the sources of the tubes P _a11 ~ P _a19 are disconnected from V _DC , and the circuit in the low value area does not work; For j=9, when k≠0, the tube P _e1 is cut off, and when k=0, the tube P _e1 is turned on, the tubes P _a11 to P _a19 are all cut off, the circuit in the low value area is invalid, and the circuit in the high value area works; ④S _i output circuit and J _i output circuit: S _i output circuit is composed of CMOS transmission gate TG ₀ ~ TG ₉ and constant current source I _Si , the input of transmission gate TG ₁ ~ TG ₉ respectively takes over the drain of P _a00 ~ P _a08 , TG The ₀ input takes over the drain of P _a19 , the outputs of TG ₀ ~ TG ₉ are all connected to the upper end of the constant current source I _Si , the upper end of I _Si is used as the output of _Si , the lower end of I _Si is grounded, and the positive control end and negative control end of TG ₀ ~ TG ₉ are respectively Connect v _tg0 ~ v _tg9 and v _/tg0 ~ v _/tg9 , the diode conduction voltage drop is V _Don , in TG ₁ ~ TG ₉ , for each j, j=1 ~ 9, only one TG _j is turned on, S _i connects to the drain of P _a0j-1 through the turned-on TG _j , for j=0, S _i takes over the drain of P _a19 through the turned-on TG ₀ ; select V _DC =9V _Don + △, △ is the K value storage unit The circuit characteristics require the offset to be compensated; J _i output circuit consists of PMOS tube P _e2 and constant current source I _Ci , the source of tube P _e2 is connected to V _DC , the gate of tube P _e2 is connected to P _e0 gate g _/hj , and the drain of tube P _e2 is connected to constant current source I The upper end of _Ci , the upper end of I _Ci is output as J _i , the lower end of I _Ci is grounded, the gate of P _c0 is connected to v _/tg0 , the drain of P _c0 is connected to the gate of P _e0 ; for j≠0, when k<j, the pipe P _e0 Gate g _/hj voltage V _g/hj < V _DC , tube P _e2 is turned on, J _i outputs high level V _DC , which means there is a borrow. When k≥j, V _g/hj = V _DC , tube P e2 When P _e2 is cut off, the output of J _i is low level 0, indicating no borrow; the source of the tube P _c0 is connected to the DC voltage V _DC , so that when j=0, the output of J _i is the above-mentioned level indicating no borrow; all constant current The source current direction is from the upper end to the lower end. 5. a kind of K value half-adder circuit that adopts band-pass threshold loading technology of a kind of K value half-adder circuit that adopts band-pass threshold loading technology to form according to claim 3 is characterized in that: in said In the K-value half subtractor circuit described above, (1) firstly, the band-pass thresholds of U ₁ ~ U _L are respectively taken as t _bL ~ t _b1 ; (2) Then, the borrow number J _i is taken as the carry number C _i , Except when j=0, no borrow is taken as no carry, all borrows are taken as no carry, and no borrow is taken as carry, the source of the tube P _c0 is connected to the DC voltage V _d , so that when j=0, C The output of _i is the above-mentioned level indicating no carry, V _DC - V _d = 1.5 volts; (iii) finally, the half subtractor is taken as a half adder, A _i , B _i and S _i are taken as the summand in turn, and the addition The number and standard sum, then the K-value half-subtractor circuit using the band-pass threshold loading technology becomes the K-value half-adder circuit using the band-pass threshold loading technology. 6. a kind of 10-value half-adder circuit that adopts band-pass threshold-loading technology to form a kind of 10-value half-adder circuit that adopts band-pass threshold-loading technology according to claim 4 is characterized in that: in said In the 10-value half-subtractor circuit using the band-pass threshold loading technique described above, (1) firstly, set the band-pass thresholds of U ₁ to U ₉ as t _b9 to t _b1 respectively; (2) then, set the borrow number J _i Take it as the carry number C _i , except that when j=0, no borrow is taken as no carry, all borrows are taken as no carry, and no borrow is taken as a carry, and the source of the tube P _c0 is connected to the DC voltage V _d , when j=0, the C _i output is the above-mentioned level indicating no carry, V _DC -V _d =1.5 volts; (iii) finally, the half subtractor is taken as a half adder, and A _i , B _i and S _i are sequentially Take it as the summand, the addend and the basic sum, then the 10-value half-subtractor circuit using the band-pass threshold loading technique becomes the 10-value half-adder circuit using the band-pass threshold loading technique.