CN104300965B

CN104300965B - Using the K values of band logical threshold loading technique and the construction method and its circuit of ten value half adders and half-subtracter

Info

Publication number: CN104300965B
Application number: CN201410520679.7A
Authority: CN
Inventors: 方振贤; 刘莹; 方倩
Original assignee: Heilongjiang University
Current assignee: Heilongjiang University
Priority date: 2014-10-01
Filing date: 2014-10-01
Publication date: 2017-06-30
Anticipated expiration: 2034-10-01
Also published as: CN104300965A

Abstract

The present invention discloses a kind of K values of use band logical threshold loading technique and the construction method and its circuit of ten value half adders and half-subtracter；The present invention uses band logical threshold loading technique, by the demand in information processing each stage, band logical threshold needed for different phase is loaded into PMOS, PMOS is had band logical threshold variable at any time；The present invention analysis K values half-subtracter and half adder, draw the unified feature of Spring layer and low value area, and based on loading technique, two kinds of circuits can be classified as a kind of circuit Uniting, avoid the traditional approach realized using K values gate, and circuit structure is greatly simplified；Chaos encrypting method and circuit can be generalized to K values from 2 values, K value multiplication and division computings are replaced with K value plus and minus calculations, realize K value informations without multiplication and division chaos encrypting method and circuit；VLSI and other digital IC technology fields such as ASIC and memory are formulated for FPGA, CPLD, half or complete.

Description

Using the K values of band logical threshold loading technique and the structure side of ten value half adders and half-subtracter Method and its circuit

Technical field

The invention belongs to digital integrated electronic circuit field, specifically a kind of K values and ten of use band logical threshold loading technique The construction method and its circuit of value half adder and half-subtracter.

Background technology

With developing rapidly for MOS integrated circuit techniques, collect increasing on a large scale, integrated level more and more higher, VLSI is (super Large scale integrated circuit) there are some shortcomings：1. first on VLSI substrates, wiring but takes the silicon area of 70 more than ℅； Also need largely to may be programmed interconnector in the programmable logic device, each logic function block or input/output coupled together, The circuit of specific function is completed, wiring account for the very big cost of material.Reducing wiring cost turns into major issue.2. passed from information From the aspect of defeated, session number can be reduced using multi-valued signal；To every line transmitting digital information, binary signal is to carry information content Minimum one kind, multi-valued signal is carried and contained much information in binary signal.3. from from the aspect of information Store, can be carried using multi-valued signal Information storage density high, with metal-oxide-semiconductor grid capacitance storage information, information memory capacity is many-valued bigger than two-value, and many-valued DRAM compares two-value DRAM is greatly improved information storage density.The development of current Multivalued devices is carried out extensively, and Toshiba uses with U.S. SanDisk The 16gbitNAND flash memories that 43nm techniques and the many-valued technology of 2bit/ units are realized.The 8Gbit products of Samsung exploitation are using 63nm's The many-valued technology of CMOS technology and 2bit/ units.Succeed in developing and the commercialization of 4 value memories are important one of many-valued research Step, the development of Multivalued devices needs to control or change the switching threshold V of pipe_tn。

Prior art and there is problem：

1. in multivalued circuit is realized (K >=3), existing semiconductor fabrication process control metal-oxide-semiconductor threshold technology has very big lacking Point：1. the limited extent (because ion implantation concentration is limited) of threshold value is controlled, and control threshold amplitude can often change MOS in technique The performance of pipe, the voltage-type multivalued circuit of realization is not more than 4 value circuits, and more multivalued circuit application is more difficult.2. threshold can only be controlled The amplitude of value, it is impossible to change metal-oxide-semiconductor and open property (such as high pass, low pass, band logical, band resistance control threshold), and multivalued circuit must have various The metal-oxide-semiconductor of threshold property is controlled, can just make circuit structure most simple.3. need to increase ion implanting additional process, can only be in semiconductor system Make and control in technique threshold value, increase process complexity, it is impossible to which threshold value is controlled by user.

2. in multivalued circuit is realized, existing neuron mos management and control threshold technology has very big shortcoming：1. increase with K values, ' the input grid and control gate capacitance of single neuron mos pipe account for silicon area ' is to the ratio of ' single metal-oxide-semiconductor accounts for silicon area ' It is increasing, ten times, hundred times or higher；2. increase with K values, ' threshold value confusion region (break over region) width Delta V of input grid₁' right ' floating boom threshold value confusion region (break over region) width Delta V_fg' ratio (Δ V₁/ΔV_fg=C_TOT/C₁) increasing, because of Δ V_fgIt is one It is fixed, it is input into the threshold value confusion region Δ V of grid₁Width is increasing, input grid K value signal resolution capabilities is increasingly reduced, and It is high to capacitance accuracy requirement, it is unfavorable for reliably realizing the multivalued circuit that K values are big；3. threshold value control characteristic (such as band can not be changed Control threshold mode logical, with resistance), it is unfavorable to simplifying K value circuits；4. with the increase of K values, ratio (C_TOT/C₁) become big, input Grid and control gate capacitance increase, and make high frequency performance rapid decrease；5. with the increase of K values, floating gate capacitance electric leakage can not be omitted, and be had Multilevel information refreshes highly difficult.6. neuron CMOS inverter is 0 only to binary signal quiescent dissipation, to big K values, there is NMOS The state that pipe and PMOS are simultaneously turned on, quiescent dissipation is big all the better；The output of neuron CMOS followers is often capacitive load, its Output voltage lifting track is different, there is very big hysteresis voltage, is unfavorable for multivalued circuit.

3. threshold value is fixed, it is impossible to changed at any time, and this is the deficiency of existing variable threshold technology, and each stage is processed by multilevel information Need, there should be a pipe with each stage different characteristics of information processing with different threshold values；The present invention analysis K values half-subtracter with The feature of K value half adders and the uniformity of structure, but PMOS is needed with different threshold values variable at any time, namely need to use Band logical threshold loading technique；K values half-subtracter and K value half adders are the important devices for realizing K value plus and minus calculations, there is K value half-subtracters With K value half adders, the realization of K value plus and minus calculations is just easy to.

The content of the invention

The present invention seeks to disclose a kind of K values of use band logical threshold loading technique and the structure of ten value half adders and half-subtracter Method and its circuit；Described purpose is realized by following technical scheme：

1. a kind of construction method of the K value half-subtracters of use band logical threshold loading technique：A in K value half-subtracters_iIt is minuend, B_i It is subtrahend, S_iFor this is poor, J_iIt is borrow, wherein A_i, B_i, S_iK value signals are, K value signals have K logical value：0,1, 2 , ‥ ..., L, wherein L=K-1, K=4,5,6 , ‥ ..., J_iIt is 2 value signals, 2 value signals have 2 logical values：0, L；Make A_i=k, B_i=j, couple j=1~L for determining, as k ＜ j, S_i=K+k-j ＞ k, i.e. S_i＞ A_i, as k=j, S_i=0, as k ＞ j and j During ≠ L, S_i=k-j ＜ k, i.e. S_i＜ A_i, as j=L, in the absence of k ＞ j；Pair determine j=0, S_i=A_i；To j ≠ 0, as k ＜ During j, borrow, as k >=j, without borrowing, to j=0, nothing is borrowed；Using the structure of the K value half-subtracters of band logical threshold loading technique Method is described as follows：

Couple 1. j, the j=1~L for determining, by S_i＞ A_iAnd S_i＜ A_i, K value half-subtracter computings are divided into Spring layer and low value Area, because of t_B0~j-1=t_/hj, t_Bj+1~L=t_hj+1, j ≠ L, using the controlled PMOS P of gating_e0And P_e1, P_e0With low pass threshold t_/hj's Characteristic, P_e1With high pass threshold t_hj+1Characteristic, (1) Spring layer：As k=0~j-1, pipe P_e0Conducting, realizes S_i＞ A_i；(2) it is low Value area：As k=j+1~L and j ≠ L, pipe P_e1Conducting, realizes S_i＜ A_i, as j=L, low value area is invalid, and only Spring layer has Effect；As k=j, pipe P_e0、P_e1、P_d0All end, S_i=0；(3) P is used_e2The PMOS not gates of composition export to form J_iSignal, pipe P_e2Grid Pole adapter P_e0Grid g_/hj, as k ＜ j, pipe P_e2Conducting, J_iIt is high level, indicates and borrow, as k >=j, pipe P_e2Cut-off, J_i It is low level, indicates without borrowing；

(note：t_B0~j-1Represent that conducting is interval for k=0~j-1, t_/hjRepresent and turn on interval for k ＜ j, i.e. k=0~j-1, So t_B0~j-1=t_/hj, and t_Bj+1~LRepresent that conducting is interval for k=j+1~L, t_hj+1Represent that conducting is interval for k >=j+1, i.e. k=j + 1~L, so t_Bj+1~L=t_hj+1；Because of low pass threshold t_/hjWith high pass threshold t_hj+1Belong to band logical threshold, i.e., special band logical threshold t_B0~j-1 And t_Bj+1~L, so formula high and low pass formula variable threshold PMOS all can be described as band formula variable threshold PMOS, it is then special by band logical threshold Levy, t will be met_B0~j-1=t_/hjAnd t_Bj+1~L=t_hj+1Band logical threshold, divide low pass threshold and high pass threshold into respectively；Note 1. middle j ≠ 0)；

2. Spring layer circuit includes band formula variable threshold PMOS P_a00~P_a0L-1With the diode D of series connection₀₀~D_0L-1, pipe P_a01 ~P_a0L-1High pass threshold be followed successively by t_h1~t_hL-1, pipe P_a00Low pass threshold be t_/h1, pipe P_a00~P_a0L-1Source electrode passes through P_e0Connect electricity Source V_DC, when k=j-1~0 and j ≠ 0, pipe P_e0Conducting, S_iOutput is by m₀Individual conducting diode is switched to V_DC, with k by j-1 To 0, pipe P is used_A0j-1~P_a00Sequentially turn on control m₀By 0 to j-1, then S_iBy L to L-j+1；Low value area circuit includes high pass Formula variable threshold PMOS P_a11~P_a1LWith the diode D of series connection₁₂~D_1L, by D_1LMeet D₀₀, make D₁₂~D_1LAnd D₀₀~D_0L-1Form one Individual total series diode sequence D₁₂~D_0L-1, pipe P_a11~P_a1LHigh pass threshold be followed successively by t_h1~t_hL, as k=L~j+1 and 0<j<L When, pipe P_e1Conducting, pipe P_a11~P_a1LSource electrode pass through P_e1Switch on power V_DC, S_iOutput is by m₁Individual conducting diode is switched to V_DC, with k by L to j+1, use pipe P_a1L~P_a1j+1Sequentially turn on control m₁By j to L-1, then S_iOutput is by L-j to 1；Work as k= During j ≠ 0, pipe P_e0、P_e1、P_d0All end, S_iIt is output as 0；

3. to each j, j=0~L, door U is differentiated by K logical value₀~U_LDifferentiate j values, logical value differentiates door U_mBand logical Threshold is t_bjIt is exactly only to work as U_mIt is input into U during for j_mIt is output as high level, otherwise, U_mLow level is output as, U is taken₀~U_LBand logical threshold point Wei not t_b0~t_bL；All U₀~U_LIt is j to be input into, U₀~U_LOutput is respectively v_tg0~v_tgL, v_tg0~v_tgLRespectively hang oneself not gate M₀~M_L Produce anti-phase output v_/tg0~v_/tgL；Thus complete：(1) to j ≠ 0, in variable threshold gating PMOS P_c1~P_cLMiddle v_/tgjDrive P_cjLead It is logical, pipe P_c1~P_cLSource electrode threshold value to be passed is respectively t_/h1~t_/hL, then pipe P_c1~P_cLIn only t_/h1~t_/hLIn t_/hjIt is loaded into pipe P_e0, use pipe P_e0Conducting control Spring layer (0, j-1) length j-2, j ≠ 0, high level section length is L during j=L；(2) to j ≠ 0, Variable threshold gate tube P_d1~P_dLMiddle v_/tgjDrive P_djConducting, pipe P_d1~P_dL-1、P_dLSource electrode threshold value to be passed is respectively t_h2~t_hL、t_/h1, As j ＜ L, pipe P_d1~P_dL-1In only make t_h2~t_hLIn t_hj+1It is loaded into pipe P_e1；As j=L, pipe P_dLBy t_/h1It is loaded into pipe P_e1, make low value area invalid；Use pipe P_e1And P_d0Conducting control low value area j+1~L length L-j, j ≠ L；(3) in cmos transmission gate TG₁~TG_LMiddle v_tgjAnd v_/tgjOnly drive TG_jConducting, j=1~L, S_iBy the TG for turning on_jMeet P_a0j-1Drain electrode, S_iMaximum bar Part is k=j-1, now S_iBy the TG for turning on_jAnd P_a0j-1It is connected to V_DC, realize S_i=L；(4) as j=0, v is used_/tg0Drive TG₀ With pipe P_d0、P_c0Conducting, P_d0Source electrode meets V_DC, P_d0Drain electrode adapter P_a11~P_a1LSource electrode, pipe P_a11~P_a1LSource electrode passes through P_d0It is switched to V_DC, S_iBy TG₀Meet P_a1LDrain electrode, low value area circuit work and as digital follower, realize S_i=A_i, the now low value head of district It is L to spend, Spring layer circuit malfunction；Pipe P_c0Grid meets v_/tg0, P_c0Drain electrode meets P_e0Grid, pipe P_c0Source electrode meets DC voltage V_DC, make j J when=0_iBe output as it is above-mentioned indicate without the level for borrowing, supplement 1. in lack j=0 when J_iThe formation of signal.

(note：Referring to embodiment 4：Use band logical threshold loading technique of the invention, variable threshold gating PMOS and gating are controlled The explanation of PMOS；v_/tgjDrive P_cjConducting, by P_cjConducting makes P_cjSource electrode threshold value t to be passed_/hjIt is loaded into pipe P_e0, loading is exactly Make P_e0With threshold value t_/hjCharacteristic, if P_cjEnd, then the t_/hjLoading failure, need to drive another P_cj1Conducting, by t_/hj1It is loaded into Pipe P_e0；Similar fashion, drives P_djConducting, by t_hj+1It is loaded into pipe P_e1, the loading makes P_e1With threshold value t_hj+1Characteristic；When j values During change, Spring layer and the change of low value area require pipe P_e0And P_e1Threshold property is loaded to change with new band logical threshold).

2. the construction method of the K value half-subtracters of a kind of use band logical threshold loading technique according to above-mentioned technical proposal 1 A kind of construction method of the K value half adders of use band logical threshold loading technique that same characteristic features are formed：Using band logical threshold loading skill In the construction method of the K value half-subtracters of art：(1) first, by U₁~U_LBand logical threshold be taken as t respectively_bL~t_b1；(ii) then, will borrow Digit J_iIt is taken as carry digit C_i, without in addition to borrowing and being taken as no-carry when j=0, no-carry is taken as by all borrowing, without borrowing It has been taken as carry (including C_iOutput high level V_DCRepresent no-carry, C_iOutput low level 0 indicates carry), pipe P_c0Source electrode connects directly Stream voltage V_d, C when making j=0_iIt is output as the level of above-mentioned expression no-carry, V_d≠V_DC；(iii) it is last, half-subtracter is taken as half and is added Device, by A_i, B_iAnd S_iBe taken as summand successively, addend and one's own department or unit and, then using band logical threshold loading technique K value half-subtracters structure Construction method just turns into the construction method using the K value half adders of band logical threshold loading technique.

(note：Referring to embodiment 1, K values half-subtracter and half adder construction method feature identical are proved).

3. the construction method of the K value half-subtracters of a kind of use band logical threshold loading technique according to above-mentioned technical proposal 1 A kind of K value half-subtracter circuits of the use band logical threshold loading technique for being formed, show such as Fig. 1, using band logical threshold loading technique K values partly Subtracting device circuit includes：Control signal forms circuit, Spring layer and gating circuit high, low value area and low gating circuit, S_iOutput electricity Road and J_iOutput circuit；Referring to Fig. 1, K value half-subtracter particular circuit configurations are described as follows：

1. control signal forms circuit by logical value differentiation door U₀~U_LWith CMOS not gates M₀~M_LTwo parts constitute, and differentiate Door U₀~U_LRespectively by interval minimum band formula variable threshold PMOS P_b0~P_bLWith constant-current source I₀~I_LConstitute, pipe P_b0~P_bLBand Logical threshold is respectively t_b0~t_bL, wherein t_b0=t_/h1, t_bL=t_hL, i.e. pipe P_b0And P_bLRespectively interval minimum low pass formula and high pass Formula variable threshold PMOS, pipe P_b0~P_bLEffective input all meet B_i, pipe P_b0~P_bLSource electrode meets power supply V_DC, pipe P_b0~P_bLDrain electrode difference Meet constant-current source I₀~I_LUpper end, I₀~I_LUpper end is respectively as U₀~U_LOutput v_tg0~v_tgL, constant-current source I₀~I_LLower end is grounded, permanent Stream ource electric current is all to flow to lower end, v by upper end_tg0~v_tgLNot gate M is met respectively₀~M_LInput, M₀~M_LOutput is respectively v_/tg0~ v_/tgL, it follows that control signal v anti-phase each other_tg0~v_tgLAnd v_/tg0~v_/tgL, M₀~M_LOperating voltage is V_DC, to each B_i Input j, j=0~L, v_tg0~v_tgLIn only v_tgjIt is high level, remaining output is all low level；

2. Spring layer and gating circuit high：Gating circuit high is by variable threshold gating PMOS P_c1~P_cL, gate controlled PMOS P_e0With PMOS P_c0Composition；Pipe P_c1~P_cLSource electrode low pass threshold to be passed is respectively t_/h1~t_/hL, pipe P_c1~P_cLEffective input connect A_i, pipe P_c0~P_cLGrid meets control signal v respectively_/tg0~v_/tgL, and its drain electrode all adapter P_e0Grid g_/hj；To each B_iInput J, j=1~L, pipe P_c1~P_cLMiddle only one of which pipe P_cjConducting, remaining pipe cut-off, then in t_/h1~t_/hLIn only by t_/hjLoading To pipe P_e0, pipe P_e0Source electrode meets V_DC, its drain electrode adapter P_a00~P_a0L-1Source electrode；Spring layer circuit includes band logical variable threshold PMOS P_a00 ~P_a0L-1With series diode D₀₀~D_0L-1, pipe P_a01~P_a0L-1High pass threshold be followed successively by t_h1~t_hL-1, pipe P_a00Low pass threshold be t_/h1, pipe D₀₀~D_0L-2The respective adapter D of negative pole₀₁~D_0L-1Positive pole, pipe P_a00~P_a0L-1Effectively input meets A_i, pipe P_a00~P_a0L-1Leakage Extremely respective adapter D₀₀~D_0L-1Negative pole, A_iIt is k to be input into, as k=0~j-1 and j ≠ 0, pipe P_e0Conducting, by pipe P_a00~ P_a0L-1Source electrode passes through P_e0Connect V_DC, Spring layer circuit work, use pipe P_e0Conducting control Spring layer (0, j-1) length j-2, j ≠ 0, as k=j~L, pipe P_e0Cut-off, pipe P_a00~P_a0L-1Source electrode and V_DCDisconnect, Spring layer circuit does not work；

3. low value area and low gating circuit：Low gating circuit is by variable threshold gating PMOS P_d1~P_dL, gate controlled PMOS P_e1With PMOS P_d0Composition；Pipe P_d1~P_dL-1Source electrode high pass threshold to be passed is respectively t_h2~t_hL, P_dLSource electrode low pass threshold to be passed is t_/h1；Pipe P_d0~P_dLGrid meets control signal v respectively_/tg0~v_/tgL, P_d1~P_dLDrain electrode adapter P_e1Grid, P_d1~P_dLIt is effectively defeated Enter to meet A_i；To each j, j=1~L-1, pipe P_d1~P_dL-1In only a pipe P_djConducting, remaining pipe cut-off, in t_h2~t_hLMiddle choosing Take t_hj+1It is loaded into pipe P_e1, and j=L, pipe P_dLConducting, t_/h1It is loaded into pipe P_e1；Pipe P_e1And P_d0Drain electrode adapter P_a11~P_a1LSource electrode, P_e1And P_d0Source electrode meets V_DC；As k=j+1~L and 0<j<During L, pipe P_e1Conducting, pipe P_a11~P_a1LSource electrode passes through P_e1Connect V_DC, it is low Value area's circuit work；Low value area circuit includes high pass variable threshold PMOS P_a11~P_a1LWith series diode D₁₂~D_1L, pipe D₁₂~ D_1L-1The respective adapter D of negative pole₁₃~D_1LPositive pole, D_1LNegative pole meets D₀₀Positive pole, by D₁₂~D_1LAnd D₀₀~D_0L-1Series connection, constitutes 2L-1 Individual series diode sequence, pipe P_a11~P_a1LHigh pass threshold be respectively t_h1~t_hL, it is effectively input into and meets A_i, pipe P_a12~P_a1LDrain electrode Respective adapter D₁₂~D_1LNegative pole, pipe P_a11Drain electrode meets D₁₂Positive pole；As j=0, pipe P_d0Conducting, pipe P_a11~P_a1LSource electrode passes through P_d0 Connect V_DC, Spring layer circuit is invalid, and low value area circuit works and is formed as digital follower, uses pipe P_e1And P_d0Conducting control is low Value area (j+1, L) length L-j-2, j ≠ L；As k=0~j and j ≠ L, pipe P_e1Cut-off, pipe P_a11~P_a1LSource electrode and V_DC Disconnect, low value area circuit does not work；To j=L, when k ≠ 0, pipe P_e1Cut-off, and as k=0, pipe P_e1Conducting, pipe P_a11~ P_a1LFull cut-off, low value area circuit is invalid, the work of Spring layer circuit；

④S_iOutput circuit and J_iOutput circuit：S_iOutput circuit is by cmos transmission gate TG₀~TG_LWith constant-current source I_SiComposition, Transmission gate TG₁~TG_LIt is input into adapter P respectively_a00~P_a0L-1Drain electrode, TG₀Input adapter P_a1LDrain electrode, TG₀~TG_LOutput all connects perseverance Stream source I_SiUpper end, I_SiUpper end is used as S_iOutput, I_SiLower end is grounded, TG₀~TG_LPositive control end and negative control end meet v respectively_tg0 ~v_tgLAnd v_/tg0~v_/tgL, N is V_Don, to each j, j=1~L, in TG₁~TG_LMiddle only one of which TG_jLead It is logical, S_iBy the TG for turning on_jMeet P_a0j-1Drain electrode, to j=0, S_iBy the TG for turning on₀Adapter P_a1LDrain electrode；Choose V_DC=LV_Don+ △, △ are the side-play amount of K value storage unit circuits characteristic requirements compensation；

(note：NMOS tube N_tgaWith PMOS P_tgaDrain electrode connect, source electrode also connects, and then constitutes cmos transmission gate TG_a, Pipe N_tgaAnd P_tgaGrid be respectively transmission gate TG_aPositive control end and negative control end)；

J_iOutput circuit is by PMOS P_e2With constant-current source I_CiComposition, pipe P_e2Source electrode meets V_DC, pipe P_e2Grid adapter P_e0Grid g_/hj, pipe P_e2Drain electrode meets constant-current source I_CiUpper end, I_CiUpper end is used as J_iOutput, I_CiLower end is grounded, pipe P_c0Grid meets v_/tg0, P_c0Drain electrode Meet P_e0Grid；To j ≠ 0, as k ＜ j, pipe P_e0Grid g_/hjVoltage V_g/hj＜ V_DC, pipe P_e2Conducting, J_iIt is output as high level V_DC, Indicate and borrow, as k >=j, V_g/hj=V_DC, pipe P_e2Cut-off, J_iLow level 0 is output as, is indicated without borrowing；Pipe P_c0Source electrode connects directly Stream voltage V_DC, J when making j=0_iIt is output as above-mentioned expression without the level (note for borrowing：As j=0, P_c0Conducting, P_e0Grid voltage V_g/hjEqual to DC voltage V_DC, make pipe P_e2Cut-off, J_iIt is output as high level V_DC, without borrowing when representing j=0), all constant-current sources The sense of current is to flow to lower end by upper end.

4th, the identical spy of K value half-subtracter circuits of a kind of use band logical threshold loading technique according to above-mentioned technical proposal 3 A kind of K value half adder circuits of the use band logical threshold loading technique to be formed are levied, is shown such as Fig. 1, in K value half-subtracters circuit diagram 1, (1) first, by U₁~U_LBand logical threshold be taken as t respectively_bL~t_b1；(ii) then, by borrow J_iIt is taken as carry digit C_i, during except j=0 It is taken as outside no-carry without borrowing, no-carry is taken as by all borrowing, carry (including C has been taken as without borrowing_iOutput high level V_DCRepresent no-carry, C_iOutput low level 0 indicates carry), pipe P_c0Source electrode meets DC voltage V_d, C when making j=0_iIt is output as State the level for representing no-carry, V_DC- V_d=1.5 volts；(note：During j=0, P_c0Conducting, pipe P_e0Grid voltage V_g/hjEqual to the direct current Voltage V_d, make pipe P_e0Conducting, C_iOutput high level V_DC, represent no-carry, i.e. DC voltage V_dC when meeting j=0_iOutput level table Show no-carry)；(iii) it is last, half-subtracter is taken as half adder, by A_i, B_iAnd S_iBe taken as summand successively, addend and one's own department or unit and, then K value half-subtracters circuit using band logical threshold loading technique just turns into using the K value half adder circuits of band logical threshold loading technique, that is, scheme 1 turns into Fig. 2.

(note：Compare Fig. 1,2 find out：K value half-subtracters circuit diagram 1 is identical with K value half adder circuit Fig. 2 structures, simply The change of parameter：①U₁~U_LBand logical threshold by t_b1~t_bLIt is changed to t_bL~t_b1, 2. P_c0The DC voltage that source electrode connects is by V_DCIt is changed to V_d, each element of circuit is identical with line, and without at all change, but variable connotation press half-subtracter and half adder decision；In addition, because V_tn+∣V_tp1.5 volts of ∣ ＜, V_g/hj=V_dWhen, pipe P_e0And P_e2Conducting, V_g/hj=V_DCWhen, pipe P_e0And P_e2Cut-off).

The present invention also has following technical characteristic：

(1) construction method of the K value half-subtracters of a kind of use band logical threshold loading technique according to above-mentioned technical proposal 3 A kind of K value half-subtracter circuits of the use band logical threshold loading technique for being formed, show such as Fig. 1, are loaded in the use band logical threshold shown in Fig. 1 In the K value half-subtracter circuits of technology, K=10 is taken, then draw a kind of 10 value half-subtracter circuits of use band logical threshold loading technique, shown Such as Fig. 3,10 value half-subtracter circuits include：Control signal forms circuit, Spring layer and gating circuit high, low value area and low gating electricity Road, S_iOutput circuit and J_iOutput circuit；Referring to Fig. 3,10 value half-subtracter particular circuit configurations are described as follows：

1. control signal forms circuit by logical value differentiation door U₀~U₉With CMOS not gates M₀~M₉Two parts constitute, and differentiate Door U₀~U₉Respectively by interval minimum band formula variable threshold PMOS P_b0~P_b9With constant-current source I₀~I₉Constitute, pipe P_b0~P_b9Band Logical threshold is respectively t_b0~t_b9, wherein t_b0=t_/h1, t_b9=t_h9, i.e. pipe P_b0And P_b9Respectively interval minimum low pass formula and high pass Formula variable threshold PMOS, pipe P_b0~P_b9Effective input all meet B_i, pipe P_b0~P_b9Source electrode meets power supply V_DC, pipe P_b0~P_b9Drain electrode difference Meet constant-current source I₀~I₉Upper end, I₀~I₉Upper end is respectively as U₀~U₉Output v_tg0~v_tg9, constant-current source I₀~I₉Lower end is grounded, permanent Stream ource electric current is all to flow to lower end, v by upper end_tg0~v_tg9Not gate M is met respectively₀~M₉Input, M₀~M₉Output is respectively v_/tg0~ v_/tg9, it follows that control signal v anti-phase each other_tg0~v_tg9And v_/tg0~v_/tg9, M₀~M₉Operating voltage is V_DC, to each B_i Input j, j=0~9, v_tg0~v_tg9In only v_tgjIt is high level, remaining output is all low level；

2. Spring layer and gating circuit high：Gating circuit high is by variable threshold gating PMOS P_c1~P_c9, gate controlled PMOS P_e0With PMOS P_c0Composition；Pipe P_c1~P_c9Source electrode low pass threshold to be passed is respectively t_/h1~t_/h9, pipe P_c1~P_c9Effective input connect A_i, pipe P_c0~P_c9Grid meets control signal v respectively_/tg0~v_/tg9, and its drain electrode all adapter P_e0Grid g_/hj；To each B_iInput J, j=1~9, pipe P_c1~P_c9Middle only one of which pipe P_cjConducting, remaining pipe cut-off, then in t_/h1~t_/h9In only by t_/hjLoading To pipe P_e0, pipe P_e0Source electrode meets V_DC, its drain electrode adapter P_a00~P_a08Source electrode；Spring layer circuit includes band logical variable threshold PMOS P_a00~ P_a08With series diode D₀₀~D₀₈, pipe P_a01~P_a08High pass threshold be followed successively by t_h1~t_h8, pipe P_a00Low pass threshold be t_/h1, pipe D₀₀~D₀₇The respective adapter D of negative pole₀₁~D₀₈Positive pole, pipe P_a00~P_a08Effectively input meets A_i, pipe P_a00~P_a08The respective adapter D of drain electrode₀₀ ~D₀₈Negative pole；A_iIt is k to be input into, as k=0~j-1 and j ≠ 0, pipe P_e0Conducting, by pipe P_a00~P_a08Source electrode passes through P_e0Connect Logical V_DC, Spring layer circuit work, use pipe P_e0Conducting control Spring layer (0, j-1) length j-2, j ≠ 0, when k=j~9, pipe P_e0Cut-off, pipe P_a00~P_a08Source electrode and V_DCDisconnect, Spring layer circuit does not work；

3. low value area and low gating circuit：Low gating circuit is by variable threshold gating PMOS P_d1~P_d9, gate controlled PMOS P_e1With PMOS P_d0Composition；Pipe P_d1~P_d8Source electrode high pass threshold to be passed is respectively t_h2~t_h9, P_d9Source electrode low pass threshold to be passed is t_/h1； Pipe P_d0~P_d9Grid meets control signal v respectively_/tg0~v_/tg9, pipe P_d1~P_d9Drain electrode adapter P_e1Grid, pipe P_d1~P_d9It is effectively defeated Enter to meet A_i；To each j, j=1~8, pipe P_d1~P_d8In only a pipe P_djConducting, remaining pipe cut-off, in t_h2~t_h9Middle selection t_hj+1It is loaded into pipe P_e1, and j=9, pipe P_d9Conducting, t_/h1It is loaded into pipe P_e1；Pipe P_e1And P_d0Drain electrode adapter P_a11~P_a19Source electrode, pipe P_e1And P_d0Source electrode meets V_DC；When k=j+1~9 and 0<j<When 9, pipe P_e1Conducting, by pipe P_a11~P_a19Source electrode passes through P_e1Connect V_DC, The circuit work of low value area；Low value area circuit includes band logical variable threshold PMOS P_a11~P_a19With series diode D₁₂~D₁₉, pipe D₁₂~ D₁₈The respective adapter D of negative pole₁₃~D₁₉Positive pole, D₁₉Negative pole meets D₀₀Positive pole, by D₁₂~D₁₉And D₀₀~D₀₈Series connection, constitutes 17 series connection Diode sequence, pipe P_a11~P_a19High pass threshold be respectively t_h1~t_h9, it is effectively input into and meets A_i, pipe P_a12~P_a19Drain electrode each connects Pipe D₁₂~D₁₉Negative pole, pipe P_a11Drain electrode meets D₁₂Positive pole；As j=0, pipe P_d0Conducting, pipe P_a11~P_a19Source electrode passes through P_d0Connect V_DC, Spring layer circuit is invalid, and low value area circuit works and is formed as digital follower, uses pipe P_e1And P_d0Conducting control low value area (j+1,9) length 9-j-2, j ≠ 9；As k=0~j and j ≠ 9, pipe P_e1Cut-off, pipe P_a11~P_a19Source electrode and V_DCDisconnect, Low value area circuit does not work；To j=9, when k ≠ 0, pipe P_e1Cut-off, and as k=0, pipe P_e1Conducting, pipe P_a11~P_a19It is complete to cut Only, low value area circuit is invalid, the work of Spring layer circuit；

④S_iOutput circuit and J_iOutput circuit：S_iOutput circuit is by cmos transmission gate TG₀~TG₉With constant-current source I_SiComposition, Transmission gate TG₁~TG₉It is input into adapter P respectively_a00~P_a08Drain electrode, TG₀Input adapter P_a19Drain electrode, TG₀~TG₉Output all connects constant current Source I_SiUpper end, I_SiUpper end is used as S_iOutput, I_SiLower end is grounded, TG₀~TG₉Positive control end and negative control end meet v respectively_tg0~ v_tg9And v_/tg0~v_/tg9, N is V_Don, in TG₁~TG₉In, to each j, j=1~9, only one of which TG_jLead It is logical, S_iBy the TG for turning on_jMeet P_a0j-1Drain electrode, to j=0, S_iBy the TG for turning on₀Adapter P_a19Drain electrode；Choose V_DC=9V_Don+ △, △ are the side-play amount of K value storage unit circuits characteristic requirements compensation；

J_iOutput circuit is by PMOS P_e2With constant-current source I_CiComposition, pipe P_e2Source electrode meets V_DC, pipe P_e2Grid adapter P_e0Grid g_/hj, pipe P_e2Drain electrode meets constant-current source I_CiUpper end, I_CiUpper end is used as J_iOutput, I_CiLower end is grounded, pipe P_c0Grid meets v_/tg0, P_c0Drain electrode Meet P_e0Grid；To j ≠ 0, as k ＜ j, pipe P_e0Grid g_/hjVoltage V_g/hj＜ V_DC, pipe P_e2Conducting, J_iIt is output as high level V_DC, Indicate and borrow, as k >=j, V_g/hj=V_DC, pipe P_e2Cut-off, J_iLow level 0 is output as, is indicated without borrowing；Pipe P_c0Source electrode connects directly Stream voltage V_DC, J when making j=0_iIt is output as above-mentioned expression without level (J when namely making j=0 for borrowing_iIt is output as low level 0)； All constant-current source senses of current are to flow to lower end by upper end.

(2) a kind of, 10 value half-subtracter circuit phases of the use band logical threshold loading technique according to above-mentioned technical proposal (1) A kind of 10 value half adder circuits of the use band logical threshold loading technique formed with feature, show such as Fig. 3, in the use band shown in Fig. 3 In 10 value half-subtracter circuits of logical threshold loading technique, (one) first, by U₁~U₉Band logical threshold be taken as t respectively_b9~t_b1；(ii) connect , by borrow J_iIt is taken as carry digit C_i, without in addition to borrowing and being taken as no-carry when j=0, no-carry is taken as by all borrowing, Carry is taken as without borrowing, pipe P_c0Source electrode meets DC voltage V_d, C when making j=0_iThe level of above-mentioned expression no-carry is output as, V_DC- V_d=1.5 volts；(iii) it is last, half-subtracter is taken as half adder, by A_i, B_iAnd S_iSummand, addend and one's own department or unit are taken as successively With then 10 using band logical threshold loading technique are worth half-subtracter circuits and just turn into using 10 value half adder electricity of band logical threshold loading technique Road, i.e. Fig. 3 just turn into Fig. 4.

(note：Compare Fig. 3 and Fig. 4 finds out：10 value half-subtracter circuits and 10 value half adder circuit structures are identical, simply The change of parameter：①U₁~U₉Band logical threshold by t_b1~t_b9It is changed to t_b9~t_b1, 2. P_c0The DC voltage that source electrode connects is by V_DCIt is changed to V_d, each element of circuit is identical with line, and without at all change, variable connotation press half-subtracter and half adder decision；Because of V_tn+∣V_tp∣ 1.5 volts of ＜, pipe P_e0Grid voltage V_g/hj=V_dWhen, pipe P_e0Conducting, V_g/hj=V_DCWhen, pipe P_e0Cut-off；In addition, J_iOutput high level V_DCIndicate to borrow and be taken as C_iOutput high level V_DCRepresent no-carry, J_iOutput low level 0 to be indicated and be taken as C without borrowing_iOutput is low Level 0 indicates carry).

The comparing of the research of K value informations storage so far is more, and it is fewer that the computing of K value informations is studied, and its reason is K value informations Computing circuit is all the implementation method of the K value combinational logic circuits routinely based on K values door composition, and its difficulty is very big, structure It is sufficiently complex；1. general information computing and information processing each stage, require that the threshold property of pipe is different, conventional variable threshold side Method has not met needs, and the present invention uses band logical threshold loading technique, by information operation and the demand in information processing each stage, sublevel Be loaded into band logical threshold value needed for different phase in PMOS by section, PMOS is had band logical threshold value variable at any time, and this is to realize K Value information computing and the new method and new approaches of information processing；2. on the basis of band logical threshold loading technique, in present invention analysis K values The uniformity of the feature and structure of half-subtracter and K value half adders, because K values half-subtracter and half adder have identical Spring layer and low value Area, the unification of its feature, using band logical threshold loading technique, two kinds of circuits can be classified as a kind of circuit Uniting, and avoid using K values The traditional thinking mode that combinational logic gate circuit is realized, circuit structure is greatly simplified；K values half-subtracter and K value half adders are to realize K Be worth the important devices of plus and minus calculation, there is K values half-subtracter and K value half adders, the realization of K value computings is just easy to, to chaos plus The computing of K value informations and information processing provide good basis in decryption method and encrypted circuit.

Brief description of the drawings

Fig. 1 are a kind of K value half-subtracter circuit diagrams of use band logical threshold loading technique of the invention；

Fig. 2 are a kind of K value half adder circuit figures of use band logical threshold loading technique of the invention；

Fig. 3 are a kind of 10 value half-subtracter circuit diagrams of use band logical threshold loading technique of the invention；

Fig. 4 are a kind of 10 value half adder circuit figures of use band logical threshold loading technique of the invention；

Fig. 5 are related a kind of PMOS band logical variable threshold circuit diagram of the invention and band formula variable threshold PMOS graphical diagram；

Fig. 6 are related a kind of PMOS high pass variable threshold circuit diagram and formula variable threshold PMOS graphical diagram high of the invention；

Fig. 7 are related a kind of PMOS low pass variable threshold circuit diagram and low pass formula variable threshold PMOS graphical diagram of the invention；

Fig. 8 are related a kind of variable threshold gating PMOS of the invention and the controlled PMOS of gating and its graphical diagram；

Fig. 9 are a kind of existing multi output precision mirror-image constant flow source circuit diagram and graphical diagram；

Figure 10 are working waveform figure of the 10 value half-subtracter circuit of the invention during 180~410 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、J_iAnd g_/hj；

Figure 11 are working waveform figure of the 10 value half-subtracter circuit of the invention during 180~240 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、J_iAnd g_/hj；

Figure 12 are working waveform figure of the 10 value half-subtracter circuit of the invention during 240~300 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、J_iAnd g_/hj；

Figure 13 are working waveform figure of the 10 value half-subtracter circuit of the invention during 300~360 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、J_iAnd g_/hj；

Figure 14 are working waveform figure of the 10 value half-subtracter circuit of the invention during 350~410 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、J_iAnd g_/hj；

Figure 15 are of the invention 10 value half-subtracter circuit control signal oscillograms, signal voltage during 180~410 μ s Precedence is waveform from top to bottom：A_i、B_i、v_tg9、v_tg8、v_tg7、v_tg6、v_tg5、v_tg4、v_tg3、v_tg2、v_tg1、v_tg0；

Figure 16 are working waveform figure of the 10 value half adder circuit of the invention during 180~410 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、C_iAnd g_/hj；

Figure 17 are working waveform figure of the 10 value half adder circuit of the invention during 180~240 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、C_iAnd g_/hj；

Figure 18 are working waveform figure of the 10 value half adder circuit of the invention during 240~300 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、C_iAnd g_/hj；

Figure 19 are working waveform figure of the 10 value half adder circuit of the invention during 300~360 μ s, signal voltage ripple Precedence is shape from top to bottom：A_i、B_i、S_i、C_iAnd g_/hj；

Figure 20 are working waveform figure of the 10 value half adder circuit of the invention during 350~410 μ s, signal voltage electricity Precedence is corrugating from top to bottom：A_i、B_i、S_i、C_iAnd g_/hj；

Figure 21 are of the invention 10 value half adder circuit control signal oscillograms, signal voltage during 180~410 μ s Precedence is waveform from top to bottom：A_i、B_i、v_tg9、v_tg8、v_tg7、v_tg6、v_tg5、v_tg4、v_tg3、v_tg2、v_tg1、v_tg0；

Specific embodiment

Below by embodiment, the present invention is further illustrated：

Embodiment 1：K values half-subtracter of the invention and half adder construction method feature identical are proved：

(1) K values half-subtracter feature：A_iIt is minuend, B_iIt is subtrahend, S_iFor this is poor, J_iIt is borrow, makes A_i=k, B_i= J,

Pair determine j=1~L, as k ＜ j, S_i=K+k-j ＞ k, i.e. S_i＞ A_i；As k=j, S_i=0；As k ＞ j And during j ≠ L, S_i=k-j ＜ k, i.e. S_i＜ A_i, as j=L, in the absence of k ＞ j；Pair determine j=0, S_i=A_i；To j ≠ 0, when During k ＜ j, borrow, as k >=j, without borrowing, to j=0, nothing is borrowed；

(2) K values half adder feature：A_iIt is summand, B_iIt is addend, S_iTo be originally and C_iIt is carry digit, makes A_i=k, B_i= N, couple n, the n=1~L that determine, as k+n ＜ K, S_i=k+n ＞ k, i.e. S_i＞ A_i, as k+n=K, S_i=0, as k+n ＞ K and During n ≠ 1, S_i=k+n-K ＜ k, i.e. S_i＜ A_i, as n=1, in the absence of k+n ＞ K；Pair determine n=0, S_i=A_i；To n ≠ 0, As k+n ＜ K, no-carry, as k+n >=K, there is carry, to n=0, no-carry；

In (1) K value half-subtracter features, to j=1~L, j=K-n is taken, to j=0, take n=0, except j=0, nothing is borrowed It is taken as outside no-carry, all will be taken as carry without borrowing, borrow and be taken as no-carry, is then drawn and (2) K values by (1) The identical result of half adder：Pair determine n, n=1~L, as k ＜ K-n, S_i=k+n ＞ k, i.e. S_i＞ A_i, work as k= During K-n, S_i=0, as k ＞ K-n and n ≠ 1, S_i=k-K+n ＜ k, i.e. S_i＜ A_i, as n=1, in the absence of k+n ＞ K；It is right The n=0 of determination, S_i=A_i；To n ≠ 0, as k ＜ K-n, no-carry, as k >=K-n, there is carry, to n=0, no-carry；

In (2) K value half adder features, to n=1~L, n=K-j is taken, to n=0, j=0 is taken, except n=0, no-carry It is taken as, without outside borrowing, whole no-carrys being taken as borrowing, has carry to be taken as, without borrowing, being drawn by (2) and partly subtract with (1) K values The identical result of device；

Upper segment description is found out：The feature of K value half-subtracters is consistent with the feature of K value half adders, therefore in the structure of K value half-subtracters In construction method：(1) first, by U₁~U_LBand logical threshold be taken as t successively_bL~t_b1, embody to j=1~L, n=K-j is taken, (ii) connect , by borrow J_iIt is taken as carry digit C_i, without in addition to borrowing and being taken as no-carry when j=0, no-carry is taken as by all borrowing, Carry will be taken as without borrowing, (iii) finally, half-subtracter be taken as half adder, by A_i, B_iAnd S_iBe taken as summand successively, addend and One's own department or unit is with then the construction method of K values half-subtracter is just formed as the construction method of K value half adders.

Embodiment 2：K value half-subtracters S_iOutput situation explanation：

When j ≠ 0 and k=1~j-1, pipe P_e0Conducting, pipe P_e0Drain voltage V_Pe0=V_DC, low value area circuit is invalid；Work as k During=j-1, pipe P_a0j-1Conducting, S_iBy TG_jAnd P_a0j-1Meet V_Pe0, S_iOutput voltage V_Si=V_DC, i.e. S_i=L；Work as k=j-2 When, pipe P_a0j-2、D_0j-1Conducting, pipe P_a0j-1Cut-off, S_iBy TG_j、P_a0j-2、D_0j-1Meet V_Pe0, S_iAnd V_Pe0Between have 1 diode D_0j-1, V_Si=V_DC- V_Don, i.e. S_i=L-1；As k=j-3, pipe P_a0j-3、D_0j-1、D_0j-2Conducting, pipe P_a0j-1And P_a0j-2Cut Only, S_iBy TG_j、P_a0j-3、D_0j-1、D_0j-2Meet V_Pe0, S_iAnd V_Pe0Between have 2 diodes, V_Si=V_DC- 2V_Don, i.e. S_i=L- 2；‥ ..., as k=1, pipe P_a01、D₀₂~D_0j-1Conducting, pipe P_a02~P_a0j-1Cut-off, S_iBy TG_j、P_a01、D₀₂~D_0j-1Connect V_Pe0, S_iAnd V_Pe0Between have (j-2) individual diode, V_Si=V_DC- (j-2) V_Don, i.e. S_i=L-j+2；As k=0, pipe P_a00、 D₀₁~D_0j-1Conducting, pipe P_a01~P_a0j-1Cut-off, S_iBy TG_j、P_a00、D₀₁~D_0j-1Meet V_Pe0, S_iAnd V_Pe0Between have (j-1) individual two Pole pipe, V_Si=V_DC- (j-1) V_Don, i.e. S_i=L-j+1；

As k=j+1~L and 0<j<During L, pipe P_e1Conducting, P_e1Drain voltage V_Pe1=V_DC, pipe P_e0Cut-off, only low value area electricity Road works, and Spring layer circuit does not work, as k=L, pipe P_a1L、D₀₀~D_0j-1Conducting, S_iBy TG_j、P_a1L、D₀₀~D_0j-1Connect V_Pe1, S_iAnd V_Pe1Between have j diode, V_Si=V_DC- jV_Don, i.e. S_i=L-j；As k=L-1, pipe P_a1L-1、D_1L、D₀₀~ D_0j-1Conducting, pipe P_a1LCut-off, S_iBy TG_j、P_a1L-1、D_1L、D₀₀~D_0j-1Meet V_Pe1, S_iAnd V_Pe1Between have (j+1) individual diode, V_Si=V_DC- (j+1) V_Don, i.e. S_i=L- (j+1)；As k=L-2, pipe P_a1L-2、D_1L-1、D_1L、D₀₀~D_0j-1Conducting, pipe P_a1L-1、P_a1LCut-off, S_iBy TG_j、P_a1L-2、D_1L-1、D_1L、D₀₀~D_0j-1Meet V_Pe1, S_iAnd V_Pe1Between have (j+2) individual diode, V_Si =V_DC- (j+2) V_Don, i.e. S_i=L- (j+2)；‥ ‥ ‥ ‥, as k=j+2, pipe P_a1j+2、D_1j+3~D_1L、D₀₀~D_0j-1Lead It is logical, pipe P_a1j+3~P_a1LCut-off, S_iBy P_a1j+2、D_1j+3~D_1L、D₀₀~D_0j-1Meet V_Pe1, S_iAnd V_Pe1Between have (L-2) individual two pole Pipe, V_Si=V_DC- (L-2) V_Don=2V_Don+ △, i.e. S_i=2；As k=j+1, pipe P_a1j+1、D_1j+2~D_1L、D₀₀~D_0j-1Lead It is logical, pipe P_a1j+2~P_a1LCut-off, S_iBy P_a1j+1、D_1j+2~D_1L、D₀₀~D_0j-1Meet V_Pe1, S_iAnd V_Pe1Between have (L-1) individual two pole Pipe, V_Si=V_DC- (L-1) V_Don=V_Don+ △, i.e. S_i=1 (note：As j=L, the paragraph is ineffective, answers whole grid to go, Only ' j ≠ 0 and k=1~j-1 ', previous paragraphs end is previous paragraphs：As k=0, V_Si=V_DC- (L-1) V_Don=V_Don+ △, That is S_i=1.In order to simplify circuit, can also grid remove low gating circuit pipe P_d0~P_dLAnd P_e1, by pipe P_a11~P_a1LSource electrode is connected to V_DC, The S of above-mentioned j ≠ 0 and k ≠ j is not influenceed_iOutput situation, as k=j, S_iBy the P for turning on_a1j、D_1j+1~D_1L、D₀₀~D_0j-1Connect V_Pe1, S_iAnd V_Pe1Between have L diode, V_Si=V_DC- LV_Don=△, i.e. S_i0 level V_Si(0)=△, it is actual because of △ very littles On it is also feasible).

Additionally, as k=j, pipe P_e0And P_e1Cut-off, S_iWith V_DCDisconnect, V_Si=0, i.e. S_i=0.

As j=0, S_iBy the TG for turning on₀Meet P_a1LDrain electrode, Spring layer circuit malfunction, low value area circuit turn into numeral Follower, realizes S_i=A_i, work as A_iWhen being followed successively by 0~L, S_iIt is followed successively by 0~L；S is analyzed by above-mentioned same procedure_iOutput situation：Ginseng It is admitted to and states k=j+1~L paragraphs, grid removes wherein D₀₀~D_0j-1, j=0 is taken, for example, as k=L, pipe P_a1L、S_iBy TG₀、P_a1L Meet V_Pe1, S_iAnd V_Pe1Between have 0 diode, V_Si=V_DC- 0V_Don, i.e. S_i=L , ‥ ..., repeat no more；Or referenced patent 201310211023.2 (write circuits and reading circuit of any K values and 8 value DRAM).

Embodiment 3：The explanation of PMOS band logical of the invention, high pass and low pass variable threshold circuit function：

With reference to [1] patent 201110291038.5 ' PMOS band logical-band resistance and high pass-low pass become threshold cirtuit ' (in invention Hold, drawings and Examples 1 etc.), ' 8 values of 8 value memory cell of embedded DRAM storage matrix of patent [2] 201110280921.4 Information method for refreshing and interlock circuit ' (drawings and Examples 4 etc.), become threshold cirtuit by the features of the present invention and be described as follows：

(1) PMOS band logical becomes threshold cirtuit：Patent [1] or [2] Fig. 6 are repainted into patent Fig. 5 of the present invention, wherein PMOS Q₂、Q₄、Q₅、Q_B1P is rewritten as successively₂、P₄、P₅、P_b1, NMOS tube Q₁、Q₃N is rewritten as successively₁、N₃, V_xIt is rewritten as V_in, remember v_bx1= V_ex1+V_DC=V_ref1+V_tn1+∣V_tp2∣, v_bx0=V_ex0+V_DC=V_ref0- V_tn3- ∣ V_tp4∣；Pipe N₁And P₄Grid meets input in, input In voltages are V_in, pipe N₃And P₂Grid meets reference voltage V respectively_ref0And V_ref1；Analyzer tube N first₁、P₂Branch road, only as pipe N₁With P₂Two grid voltages difference V_g1- V_g2=V_in- V_ref1=V_gs1+V_sg2＞ V_tn1+∣V_tp2(V during ∣_in＞ v_bx1), pipe N₁、P₂Branch road is led It is logical, otherwise, branch road cut-off；Analyzer tube N again₃、P₄Branch road, only as pipe N₃And P₄Two grid voltages difference V_g3- V_g4=V_ref0- V_in＞ V_tn3+∣V_tp4(V during ∣_in＜ v_bx0), pipe N₃、P₄Branch road is turned on, otherwise, branch road cut-off.Band resistance output v_{/ dvi~j}By PMOS Not gate produces band logical output v_Dvi~j, the not gate is by pipe P₅With resistance R₀Constitute；v_Dvi~jIt is transported to controlled PMOS P_b1Grid, pipe P_b1Source electrode meets V_DC, pipe P_b1Drain electrode connects external circuit；Thus draw：Work as v_bx1＞ V_in＞ v_bx0(V_inIn band is interval) when, pipe N₁、P₂Branch Road and pipe N₃、P₄Branch road all ends, resistance R₁Electric current be 0, v_{/ dvi~j}=V_DC, then P₅Cut-off, v_Dvi~j=V_D＜ V_DC, make pipe P_b1Conducting；Because in is input into K value signals, only as in=i~j, P_b1Conducting；It is (i, j) that in bands are interval；During in ≠ i~j, P_b1Cut Only；It is connected to the PMOS P that band logical becomes threshold cirtuit_b1Referred to as band formula variable threshold PMOS P_b1；Note t_Bi~j=(i, j), t_Bi~jIt is band logical Threshold, vt_Bi~jIt is band logical threshold voltage, vt_Bi~j=(vt_Bi-, vt_bj+), vt can be chosen_bj+=(V_in(j+1)+V_in(j))/2, vt_Bi- =(V_in(i)+V_in(i-1))/2, vt is met_Bi-＜ V_in＜ vt_bj+When, P_b1Conducting, otherwise, P_b1Cut-off；Use t_Bi~jOr vt_Bi~j It is marked on pipe P_b1Effectively input is other, Fig. 5 right sides P_b1Effectively input with it is small it is square represent (common PMOS grid represents with small circular, Distinguish), effective input meets input in, and (in meets N₁And P₄Grid), this input is called that band logical becomes threshold-type PMOS P_b1It is effectively defeated Enter；Band interval minimum (only one of which value i), t during j=i_Bi~j=t_bi=i, vt_Bi~j=vt_bi, it is minimum to become with interval band formula Threshold PMOS P_b1Referred to as interval minimum band formula variable threshold PMOS P_b1。

Note：(1) the muting logic levels of logical value k are referred to as k level, and the k level of in is designated as V_in(k)；In logical values are K is expressed as in=k；Brief note ' in=i, i+1, i+2 ‥ ..., j-1, j ' is in=i~j, for example, t_B2~5=(2,5), in takes band In interval (2,5) 2,3,4,5, in=2~5 are abbreviated as, the rest may be inferred；(2) resistance R₀NMOS tube N can be used₀Instead of by pipe N₀With P₅Constitute CMOS inverter (P₅And N₀Grid connects grid, and drain electrode connects drain electrode, N₀Source electrode meets V_D)；(3) the grid of NMOS and PMOS has The threshold value confusion region (break over region) of very little, the conducting and cut-off of pipe require grid voltage outside break over region, in very little break over region The conducting and cut-off of pipe, above-mentioned vt are not can determine that_Bi-And vt_bj+The median of two level is chosen for, antijamming capability is most strong；(4) scheme Pipe N in 5₁、P₂Branch road and pipe N₃、P₄Branch road is each to being referred to as high pass branch road and low pass branch road.

(2) PMOS high pass becomes threshold cirtuit：Leave out the pipe N of low pass branch road in Fig. 5₃、P₄And its line (note：Work as V_ref0=0 When, pipe N₃、P₄Branch road ends forever, ineffective, and grid go), show that the high pass shown in Fig. 6 becomes threshold cirtuit, analyzer tube N₁、P₂Branch Road, as pipe N₁And P₂Grid voltage difference V_in- V_ref1＞ V_tn1+∣V_tp2(V during ∣_in＞ v_bx1), pipe N₁、P₂Branch road is turned on, no Then, pipe N₁、P₂Branch road ends；Because in inputs are K value signals, only as in >=i (in=i~L), pipe N₁、P₂Branch road is turned on, in It is v_Dvi~LIt is low level, makes controlled PMOS P_b1Conducting；It is connected to the PMOS P that high pass becomes threshold cirtuit_b1Formula variable threshold referred to as high PMOS, because highest logical value is L, remembers t_hi=(i, L), t_hiReferred to as high pass threshold, vt_hiRepresent V_in＞ vt_hiWhen pipe P_b1Conducting, Use t_hiOr vt_hiIt is marked on pipe P_b1Effectively input is other；It is high interval minimum during i=L, t_hi=t_hL, vt_hi=vt_hL；Minimum interval height high Formula variable threshold PMOS P_b1Referred to as interval minimum formula variable threshold PMOS P high_b1。

(3) PMOS low pass becomes threshold cirtuit：Leave out the pipe N of high pass branch road in Fig. 5₁、P₂And its line (note：Work as V_ref1=V_DC When, pipe N₁、P₂Branch road ends forever, ineffective, and grid go), show that the low pass shown in Fig. 7 becomes threshold cirtuit, analyzer tube N₃、P₄Branch Road, as pipe N₃And P₄Grid voltage difference V_ref0- V_in＞ V_tn3+∣V_tp4(V during ∣_in＜ v_bx0), pipe N₃、P₄Branch road is turned on, no Then, pipe N₃、P₄Branch road ends, because in is input into K value signals, only as in≤j (in=0~j), P_b1Conducting is (because of P₅Conducting, P₅Leakage Pole v_{/ dv0~j}It is high level, v_{/ dv0~j}It is connected to by P₆And N₇The CMOS not gates of composition are input into, then not gate output v_Dv0~jIt is low electricity It is flat, v_Dv0~jMake controlled PMOS P_b1Conducting)；It is connected to the PMOS P that low pass becomes threshold cirtuit_b1Referred to as low pass formula variable threshold PMOS, remembers t_/hj+1=(0, j), t_/hj+1Referred to as low pass threshold, vt_/hj+1Represent V_in＜ vt_/hj+1When pipe P_b1Conducting；Use t_ljOr vt_ljIt is marked on pipe P_b1 Effectively input is other；It is low interval minimum during j=0, t_/hj+1=t_/h1, vt_/hj+1=vt_/h1, minimum low interval low pass formula variable threshold PMOS Pipe P_b1Referred to as interval minimum low pass formula variable threshold PMOS P_b1。

Note：(1) the substrate of PMOS is met into supply voltage V_DC(maximum potential is V_DC), by the Substrate ground of NMOS tube (most Low potential is ground)；If using potential minimum V instead_minIt is lower than ground potential, use maximum potential V instead_maxCompare V_DCCurrent potential is high, then PMOS Substrate reconfiguration V_max, the substrate reconfiguration V of NMOS tube_min, for observation is convenient, the connection that substrate is omitted in figure is not drawn；(2) reference is changed Voltage V_ref0And V_ref1V can respectively be adjusted_bx0And v_bx1Size, so as to realize above-mentioned band logical threshold respectively, high pass threshold and low pass threshold Regulation, to meet various actual demands.

Embodiment 4：Use band logical threshold loading technique of the invention, variable threshold gate PMOS and gate saying for controlled PMOS It is bright：

When j values change, Spring layer and low value section length require pipe P_e0And P_e1Threshold property being loaded with new threshold value and changed Become, in general information treatment each stage, require pipe (such as P_e0And P_e1) threshold property it is different；Exported in Fig. 5,6 and 7 v_Dv0~jAll it is to be delivered directly to controlled PMOS P_b1Grid, threshold value immobilizes, it is impossible to meets and changes requirement at any time；The present invention Circuit in dashed box in Fig. 5 is repainted as in 8 figures, 8 figures export v_Dvi~jBy pipe P_c1Source-drain electrode is transported to controlled PMOS P_b1Grid Pole, v_Dvi~jAdapter P_c1Source electrode, pipe P_c1Drain electrode adapter P_b1Grid, pipe P_c1Grid meets control signal v_tg, in v_tgLow level is acted on Under, pipe P_c1Turn on, then v_Dvi~jBy conduction pipe P_c1Source-drain electrode is transported to controlled PMOS P_b1Grid, make controlled PMOS P_b1It is t with band logical threshold_Bi~jCharacteristic；It is connected to the PMOS P that band logical becomes threshold cirtuit_c1Referred to as variable threshold gating PMOS P_c1, and manage P_b1Controlled PMOS is referred to as gated, the graphical diagram as shown in Fig. 8 right parts, effectively input in connects small square side, pipe P_c1Source electrode connects It is small square following, pipe P_c1Source markers source electrode band logical threshold t to be passed_Bi~j, as control signal v_tgDriving tube P_c1Conducting, by what is turned on Pipe P_c1By band logical threshold t_Bi~jIt is loaded into pipe P_b1, loading is exactly gating is received keyholed back plate P_b1With band logical threshold t_Bi~jCharacteristic：Work as in= Pipe P during i~j_b1Conducting, otherwise, pipe P_b1Cut-off.When being loaded into pipe P_b1The requirement of band logical threshold it is variable at any time when, can be become using multiple Threshold gating PMOS timesharing is loaded into gating by keyholed back plate P_b1, for example, the variable threshold gating PMOS P shown in Fig. 3_c1~P_c9, pipe P_c1~ P_c9Effective input meet A_i, and its drain electrode all selecting is logical by keyholed back plate P_e0Grid g_/hj, pipe P_c0~P_c9Grid connects control signal respectively v_/tg0~v_/tg9, pipe P_c1~P_c9Source electrode low pass threshold to be passed is respectively t_/h1~t_/h9；To each j, j=1~9, pipe P_c1~P_c9In only There is a pipe P_cjConducting, remaining pipe cut-off, then in t_/h1~t_/h9In only by t_/hjIt is loaded into pipe P_e0；V in Fig. 5~8_DC- V_D= 1.5 volts.

Low pass threshold t_/hjWith high pass threshold t_hj+1Belong to band logical threshold, band logical threshold t_Bi~LRepresent that conducting interval is (i, L), high pass Threshold t_hiRepresent that conducting interval is also (i, L), i.e. t_Bi~L=t_hi；Band logical threshold t_B0~j-1Represent that conducting interval is (0, j-1), low pass Threshold t_/hjRepresent that conducting interval is also (0, j-1), i.e. t_B0~j-1=t_/hj, therefore t_/hjAnd t_hj+1It is special band logical threshold t_B0~j-1With t_Bj+1~L, high pass threshold t_hiWith low pass threshold t_/hjBand logical threshold t can be referred to as_Bi~LAnd t_B0~j-1, high pass threshold is t_hiFormula variable threshold high PMOS and low pass threshold are t_/hjLow pass formula variable threshold PMOS can be referred to as band logical threshold for t_Bi~LAnd t_B0~j-1Band formula variable threshold PMOS, in addition, referring to Fig. 5~8, one is contained within two and drives output with the change threshold cirtuit belonging to formula variable threshold PMOS v_Dvi~jAnd v_{/ dvi~j}, can simultaneously realize band logical threshold t_Bi~jWith band resistance threshold t_{/ bi~j}, therefore, to same effective input in, band logical threshold t_Bi~jBand formula variable threshold PMOS, band resistance threshold t_{/ bi~j}With resistive variable threshold PMOS and have same band logical threshold or with resistance threshold Variable threshold gating PMOS all shares same change threshold cirtuit；Formula high and low pass formula variable threshold PMOS are classified as special band formula variable threshold PMOS, with same shared performance, repeats no more.For example, Fig. 1 acceptances of the bid t_/h2Or t_h2Pipe P_c2、P_a02、P_d1And P_a12Share Same change threshold cirtuit, drives 4 PMOSs, so as to simplify circuit respectively by same change threshold cirtuit.

Embodiment 5：Other explanations：

J_iPipe P in output circuit_e2With pipe P in control signal formation circuit_b0~P_bLThere is level conversion to act on, width will be changed (output is in 0 and V for the big output voltage of the small tube grid driving voltage conversion amplitude of variation of degree_DCBetween change), for example, Figure 11~14 Find out, pipe P_e2Gate drive voltage g_/hjAmplitude is small, and exports J_iAmplitude is big, g_/hjAnd J_iIt is mutually anti-phase.

NMOS tube N_tgaWith PMOS P_tgaDrain electrode connect, source electrode connects, then constitute cmos transmission gate TG_a, pipe N_tgaWith P_tgaGrid be respectively TG_aPositive control end and negative control end, work as TG_aPositive and negative control end is respectively V_DCDuring with 0, TG_aConducting, And positive and negative control end is respectively 0 and V_DCWhen, TG_aCut-off；Constant-current source used is referring to the existing a kind of multi output essence shown in Fig. 9 Close mirror-image constant flow source circuit diagram and graphical diagram, are to reduce power consumption and improve performance etc., constant current ource electric current by physical possibility take compared with Small value；Diode used is silicon diode, and conduction voltage drop is V_Don, conducting electric current takes smaller value by physical possibility；V_DC=LV_Don + △, △ are the side-play amount of K value storage unit circuits characteristic requirements compensation.

Embodiment 6：Explanation to the Pspice computer simulations oscillogram 10~21 of Fig. 3 and 4.

Fig. 3 is of the invention 10 value half-subtracter circuit diagrams, and Pspice computer simulations are carried out to Fig. 3, is 1. simulated first 10 value signal voltage working waveform figures of the half-subtracter circuits during 180~410 μ s shown in Figure 10, can whole observation its work Process, precedence is waveform from top to bottom：A_i、B_i、S_i、J_iAnd g_/hj, wherein A_iBe the cycle be 16 μ s periodic signal, in week Phase is A in 16 μ s_i9 are raised to successively by 0, then are raised to 7, B successively by 2_iBe the cycle be 100 μ s periodic signal, the cycle be 100 μ B in s_i9 are raised to successively by 0；2. it is clear inspection A_iAnd B_iThe result of subtraction during all probable values, Figure 10 transverse axis is put Greatly, draw the oscillogram during 180~240 μ s, 240~300 μ s, 300~360 μ s and 350~410 μ s, show respectively as Figure 11, 12nd, 13 and 14, Figure 11~14 are observed successively, and in A_iAnd B_iThe inspection of stabilization moment, works as B_iWhen=0, to A_iRespectively 0~90 kinds Situation is checked and drawn, S_i=A_i, J_i=0；Work as B_i=1, drawn with upper type inspection, work as A_iWhen >=1, S_i=A_i- 1, J_i=0, when A_iWhen=0, S_i=9, J_i=9；Work as B_iWhen=2, inspection draws, works as A_iWhen >=2, S_i=A_i- 2, J_i=0, work as A_iDuring ＜ 2, S_i=A_i + 8, J_i=9；‥ ‥ ‥ work as B_iWhen=8, inspection draws, works as A_iWhen >=8, S_i=A_i- 8, J_i=0, work as A_iDuring ＜ 8, S_i=A_i+ 2, J_i=9；Work as B_iWhen=9, inspection draws, works as A_iWhen=9, S_i=0, J_i=0, work as A_iDuring ＜ 9, S_i=A_i+ 1, J_i=9；J_i=9 tables It is shown with and borrows, J_i=0 indicates without borrowing, g_/hjAnd J_iIt is respectively pipe P_e2Grid is input into and drain electrode output, and observation Figure 11~14 are seen Go out, g_/hjAmplitude is small, J_iAmplitude is big, g_/hjAnd J_iIt is mutually anti-phase；Inspection shows that 10 value half-subtracter circuit diagram 3 meets 10 value subtractions fortune The result of calculation；Figure 15 is a kind of 10 value half-subtracter circuit control signal oscillogram, waveform during 180~410 μ s of the invention Precedence is from top to bottom：A_i、B_i、v_tg9、v_tg8、v_tg7、v_tg6、v_tg5、v_tg4、v_tg3、v_tg2、v_tg1、v_tg0, make in control signal Under, above-mentioned computing, wherein V are completed_DC=6.5V, V_d=5V.

Fig. 4 is of the invention 10 value half adder circuit figures, and Pspice computer simulations are carried out to Fig. 4, is 1. simulated first 10 value signal voltage working waveform figures of the half adder circuits during 180~410 μ s shown in Figure 16, can whole observation its work Process, precedence is waveform from top to bottom：A_i、B_i、S_i、C_iAnd g_/hj, wherein A_iAnd B_iCycle and waveform partly subtract with foregoing 10 value Device is identical；2. it is that can clearly check A_iAnd B_iThe result of add operation during all probable values, Figure 16 transverse axis is amplified, and is drawn Signal voltage operating wave during 180~240 μ s, during 240~300 μ s, during 300~360 μ s and during 350~410 μ s Shape figure, shows such as Figure 17,18,19 and 20 respectively, and Figure 17~20 are observed successively, and in A_iAnd B_iThe inspection of stabilization moment, works as B_iWhen=0, To A_iRespectively 0~90 kinds of situations are checked and drawn, S_i=A_i, C_i=9；Work as B_i=1, inspection draws, works as A_iDuring ＜ 9, S_i=A_i+ 1, C_i=9, work as A_iWhen=9, S_i=0, C_i=0；Work as B_iWhen=2, inspection draws, works as A_iDuring ＜ 8, S_i=A_i+ 2, C_i=9, work as A_i≥8 When, S_i=A_i- 8, C_i=0；‥ ‥ ‥ work as B_iWhen=8, inspection draws, works as A_iDuring ＜ 2, S_i=A_i+ 8, J_i=9, work as A_iWhen >=2, S_i=A_i- 2, C_i=0；Work as B_iWhen=9, inspection draws, works as A_iWhen=0, S_i=9, C_i=9, work as A_iWhen >=1, S_i=A_i- 1, C_i= 0；C_i=9 represent no-carry, C_i=0 indicates carry, g_/hjAnd C_iIt is respectively pipe P_e2Grid is input into and drain electrode output, observes Figure 17 ~20 find out, g_/hjAmplitude is small, C_iAmplitude is big, g_/hjAnd C_iIt is mutually anti-phase；Inspection shows that 10 value half adder circuit Fig. 4 meet 10 values The result of add operation.Figure 21 is a kind of 10 value half adder circuit control signal waveform during 180~410 μ s of the invention Figure, precedence is waveform from top to bottom：A_i、B_i、v_tg9、v_tg8、v_tg7、v_tg6、v_tg5、v_tg4、v_tg3、v_tg2、v_tg1、v_tg0, in control Under signal function, above-mentioned computing is completed, notice that Figure 21 is different from Figure 15 control signal waveforms, v in two figures_tg9~v_tg1Waveform has difference Not, 10 value half-subtracters and half adder feature are met.

Embodiment 7：PMOS band logical, high pass, low pass become threshold cirtuit and neuron mos management and control threshold technology compares.

Threshold voltage is taken as the midpoint of the break over region between pipe conducting and cut-off, actually cannot distinguish between metal-oxide-semiconductor in break over region Conducting and cut-off, therefore break over region can be considered threshold value confusion region；It follows that (1) PMOS high pass becomes the equivalent threshold value mould of threshold cirtuit Paste area does not increase and changes with K values, and it is higher than neuron mos pipe to K value signals input resolution, and (neuron mos pipe is equivalent Threshold value confusion region increases and increases with K values), it is allowed to signal input corresponding standard value has certain deviation；(2) PMOS high pass becomes Threshold cirtuit is although used 2 (or 4) individual metal-oxide-semiconductors and 1 resistance R₁, but several metal-oxide-semiconductors account for silicon area than neuron mos pipe electric capacity It is much smaller, R₁(can be replaced with constant-current source) is the drive signal to form controlled PMOS conducting, to R₁Required precision is extremely low；And it is refreshing Change threshold voltage using capacitively coupled through first metal-oxide-semiconductor, it is very high to capacitance accuracy requirement, increase the difficulty realized；(3) PMOS High pass variable threshold circuit input capacitance is more much smaller than neuron mos pipe input capacitance, and high frequency performance is preferable.Neuron mos management and control system Threshold technology has the shortcomings that very big；The existing equation below of neuron mos pipe：

Wherein V_fgIt is floating gate, V₁It is signal input gate voltage, V_jIt is control-grid voltage, threshold value choosing according to demand is straight Stream voltage V_j(j=2,3,4 ..., n), formula (14) only has V_fgAnd V₁Two variables, differential draws, dV_fg=(C₁/C_TOT)dV₁；Floating boom The fuzzy sector width △ V of threshold value_fgSector width △ V fuzzy with the threshold value of input grid₁Meet,

△V_fg=(C₁/C_TOT)△V₁, △ V₁=(C_TOT/C₁)△V_fg (15)

With K values increase, it is necessary to change input grid threshold value number increase, it is desirable to ratio C_TOT/C₁Increase, and formula (15) Middle △ V₁It is △ V_fgC_TOT/C₁Times, width △ V_fgIt is to determine, then △ V₁Increase, is indicated above：Increase with K values, it is 1. defeated Enter the fuzzy sector width △ V of threshold value of grid₁Increase, makes the reduction of input grid K value signals resolution capability, is unfavorable for being used during big K values；② Ratio C_TOT/C₁Increase, C₁Can not reduce, then all control gate capacitance account for silicon area increase；Such as 10 value circuits, K=10, C₀ =C_fg=30fF, C₁=0.8pF, it is 9.37pF (C to calculate input control gate total capacitance_TOT=11.33C₁)；Floating boom NMOS SiO between pipe control gate and floating boom₂Thickness is 35nm, and corresponding specific capacitance is 1fF/ μm², 9.37pF electric capacity occupancy silicon area 9370μm², a NMOS tube accounts for 30 μm², about 312 faces for NMOS tube of electric capacity occupancy of the 9.37pF of neuron mos pipe Product, that is, control gate capacitance to account for silicon area very big.With the development of semiconductor integrated circuit technology, metal-oxide-semiconductor size is less and less, god It is more increasing than inevitable to the area of NMOS tube through first metal-oxide-semiconductor control gate capacity area.3. neuron mos tube grid loop adds Excessive electric capacity is harmful to high frequency performance, and characteristic size reduces and metal connecting line depth-width ratio increase causes interconnection capacitance to increase Greatly, cause multiple-grid interpolar cross-interference issue, and parasitic capacitance to increase, produce extra interconnection delay and power consumption, show to add Many electric capacity is harmful to high frequency performance.4. neuron mos pipe floating gate capacitance electric leakage can not be omitted.Commonly non-volatile is deposited Reservoir is 2.85x10 in leakage current^-22In the case of A, threshold voltage reduction 3V needs 10 years altogether.Increase with K values, it is desirable to threshold Threshold voltage reduction amplitude very little, it is clear that do not allow to reduce 3V, shows that ' neuron mos pipe is based on floating gate capacitance and leaks electricity for 0 ' is reason It is thinking and unpractical.5. neuron CMOS inverter is 0 to binary signal quiescent dissipation, is increased with K values, is deposited in K value signals In the state that NMOS tube and PMOS are simultaneously turned on, as a result quiescent dissipation is bigger, only K value signals maximum and minimum value when it is different When turn on, quiescent dissipation is 0；6. neuron CMOS followers output is often capacitive load, and output voltage lifting track is different, has Very big hysteresis voltage, is unfavorable for being used in K value circuits.The fuzzy sector width of neuron mos pipe threshold is △ V₁, △ V when K values are big₁ Increase C by formula (15)_TOT/C₁Times, △ V₁May be close to or more than the stepped-up voltage of K value signals, make neuron mos tube failure.

Claims

1. a kind of construction method of the K value half-subtracters of use band logical threshold loading technique, it is characterised in that：A in K value half-subtracters_iBe by Subtrahend, B_iIt is subtrahend, S_iFor this is poor, J_iIt is borrow, wherein A_i, B_i, S_iK value signals are, K value signals have K logical value： 0,1,2 ... ..., L, wherein L=K-1, K=4,5,6 ... ..., J_iIt is 2 value signals, 2 value signals have 2 logical values：0, L；Make A_i =k, B_i=j, couple j=1~L for determining, as k ＜ j, S_i=K+k-j ＞ k, i.e. S_i＞ A_i, as k=j, S_i=0, as k ＞ j And during j ≠ L, S_i=k-j ＜ k, i.e. S_i＜ A_i, as j=L, in the absence of k ＞ j；Pair determine j=0, S_i=A_i；To j ≠ 0, when During k ＜ j, borrow, as k >=j, without borrowing, to j=0, nothing is borrowed；Using the structure of the K value half-subtracters of band logical threshold loading technique Construction method is described as follows：

Couple 1. j, the j=1~L for determining, by S_i＞ A_iAnd S_i＜ A_i, K value half-subtracter computings are divided into Spring layer and low value area, because t_B0~j-1=t_/hj, t_Bj+1~L=t_hj+1, j ≠ L, using the controlled PMOS P of gating_e0And P_e1, P_e0With low pass threshold t_/hjCharacteristic, P_e1With high pass threshold t_hj+1Characteristic, (1) Spring layer：As k=0~j-1, pipe P_e0Conducting, realizes S_i＞ A_i；(2) low value area： As k=j+1~L and j ≠ L, pipe P_e1Conducting, realizes S_i＜ A_i, as j=L, low value area is invalid, and only Spring layer is effective；Work as k During=j, pipe P_e0、P_e1、P_d0All end, S_i=0；(3) P is used_e2The PMOS not gates of composition export to form J_iSignal, pipe P_e2Grid is taken over P_e0Grid g_/hj, as k ＜ j, pipe P_e2Conducting, J_iIt is high level, indicates and borrow, as k >=j, pipe P_e2Cut-off, J_iIt is low electricity It is flat, indicate without borrowing；

2. Spring layer circuit includes band formula variable threshold PMOS P_a00~P_a0L-1With the diode D of series connection₀₀~D_0L-1, pipe P_a01~ P_a0L-1High pass threshold be followed successively by t_h1~t_hL-1, pipe P_a00Low pass threshold be t_/h1, pipe P_a00~P_a0L-1Source electrode passes through P_e0Switch on power V_DC, when k=j-1~0 and j ≠ 0, pipe P_e0Conducting, S_iOutput is by m₀Individual conducting diode is switched to V_DC, with k by j-1 to 0, use pipe P_A0j-1~P_a00Sequentially turn on control m₀By 0 to j-1, then S_iBy L to L-j+1；Low value area circuit includes formula high Variable threshold PMOS P_a11~P_a1LWith the diode D of series connection₁₂~D_1L, by D_1LMeet D₀₀, make D₁₂~D_1LAnd D₀₀~D_0L-1Form one Total series diode sequence D₁₂~D_0L-1, pipe P_a11~P_a1LHigh pass threshold be followed successively by t_h1~t_hL, as k=L~j+1 and 0<j<L When, pipe P_e1Conducting, pipe P_a11~P_a1LSource electrode pass through P_e1Switch on power V_DC, S_iOutput is by m₁Individual conducting diode is switched to V_DC, with k by L to j+1, use pipe P_a1L~P_a1j+1Sequentially turn on control m₁By j to L-1, then S_iOutput is by L-j to 1；Work as k= During j ≠ 0, pipe P_e0、P_e1、P_d0All end, S_iIt is output as 0；

3. to each j, j=0~L, door U is differentiated by K logical value₀~U_LDifferentiate j values, logical value differentiates door U_mBand logical threshold is t_bjIt is exactly only to work as U_mIt is input into U during for j_mIt is output as high level, otherwise, U_mLow level is output as, U is taken₀~U_LBand logical threshold be respectively t_b0~t_bL；All U₀~U_LIt is j to be input into, U₀~U_LOutput is respectively v_tg0~v_tgL, v_tg0~v_tgLRespectively hang oneself not gate M₀~M_LProduce Anti-phase output v_/tg0~v_/tgL；Thus complete：(1) to j ≠ 0, in variable threshold gating PMOS P_c1~P_cLMiddle v_/tgjDrive P_cjConducting, Pipe P_c1~P_cLSource electrode threshold value to be passed is respectively t_/h1~t_/hL, then pipe P_c1~P_cLIn only t_/h1~t_/hLIn t_/hjIt is loaded into pipe P_e0, Use pipe P_e0Conducting control Spring layer (0, j-1) length j-2, j ≠ 0；High level section length is L during j=L；(2) to j ≠ 0, in variable threshold Gate tube P_d1~P_dLMiddle v_/tgjDrive P_djConducting, pipe P_d1~P_dL-1、P_dLSource electrode threshold value to be passed is respectively t_h2~t_hL、t_/h1, work as j During ＜ L, pipe P_d1~P_dL-1In only make t_h2~t_hLIn t_hj+1It is loaded into pipe P_e1；As j=L, pipe P_dLBy t_/h1It is loaded into pipe P_e1, Make low value area invalid；Use pipe P_e1And P_d0Conducting control low value area j+1~L length L-j, j ≠ L；(3) in cmos transmission gate TG₁~ TG_LMiddle v_tgjAnd v_/tgjOnly drive TG_jConducting, j=1~L, S_iBy the TG for turning on_jMeet P_a0j-1Drain electrode, S_iMaximum condition is k =j-1, now S_iBy the TG for turning on_jAnd P_a0j-1It is connected to V_DC, realize S_i=L；(4) as j=0, v is used_/tg0Drive TG₀And pipe P_d0、P_c0Conducting, P_d0Source electrode meets V_DC, P_d0Drain electrode adapter P_a11~P_a1LSource electrode, pipe P_a11~P_a1LSource electrode passes through P_d0It is switched to V_DC, S_i By TG₀Meet P_a1LDrain electrode, low value area circuit work and as digital follower, realize S_i=A_i, now low value section length be L, Spring layer circuit malfunction；Pipe P_c0Grid meets v_/tg0, P_c0Drain electrode meets P_e0Grid, pipe P_c0Source electrode meets DC voltage V_DC, when making j=0 J_iBe output as it is above-mentioned indicate without the level for borrowing, supplement 1. in lack j=0 when J_iThe formation of signal.

2. construction method same characteristic features of the K value half-subtracters of a kind of use band logical threshold loading technique according to claim 1 A kind of construction method of the K value half adders of the use band logical threshold loading technique for being formed, it is characterised in that：Using the loading of band logical threshold In the construction method of the K value half-subtracters of technology：(1) first, by U₁~U_LBand logical threshold be taken as t respectively_bL~t_b1；(ii) then, will Borrow J_iIt is taken as carry digit C_i, without in addition to borrowing and being taken as no-carry when j=0, no-carry is taken as by all borrowing, without borrowing Position has been taken as carry, pipe P_c0Source electrode meets DC voltage V_d, C when making j=0_iIt is output as the level of above-mentioned expression no-carry, V_d≠ V_DC；(iii) it is last, half-subtracter is taken as half adder, by A_i, B_iAnd S_iBe taken as summand successively, addend and one's own department or unit and, then using band logical The construction method of the K value half-subtracters of threshold loading technique just turns into the construction method using the K value half adders of band logical threshold loading technique.

3. a kind of K value half-subtracters of use band logical threshold loading technique according to claim 1 construction method formed one Plant using the K value half-subtracter circuits of band logical threshold loading technique, it is characterised in that：The K values of described use band logical threshold loading technique Half-subtracter circuit includes：Control signal forms circuit, Spring layer and gating circuit high, low value area and low gating circuit, S_iOutput Circuit and J_iOutput circuit, K value half-subtracter particular circuit configurations are described as follows：

1. control signal forms circuit by logical value differentiation door U₀~U_LWith CMOS not gates M₀~M_LTwo parts constitute, and differentiate door U₀~ U_LRespectively by interval minimum band formula variable threshold PMOS P_b0~P_bLWith constant-current source I₀~I_LConstitute, pipe P_b0~P_bLBand logical threshold point Wei not t_b0~t_bL, wherein t_b0=t_/h1, t_bL=t_hL, i.e. pipe P_b0And P_bLRespectively interval minimum low pass formula and formula variable threshold high PMOS, pipe P_b0~P_bLEffective input all meet B_i, pipe P_b0~P_bLSource electrode meets power supply V_DC, pipe P_b0~P_bLDrain electrode connects constant current respectively Source I₀~I_LUpper end, I₀~I_LUpper end is respectively as U₀~U_LOutput v_tg0~v_tgL, constant-current source I₀~I_LLower end is grounded, constant-current source electricity Stream is all to flow to lower end, v by upper end_tg0~v_tgLNot gate M is met respectively₀~M_LInput, M₀~M_LOutput is respectively v_/tg0~v_/tgL, by This draws control signal v anti-phase each other_tg0~v_tgLAnd v_/tg0~v_/tgL, M₀~M_LOperating voltage is V_DC, to each B_iInput j, J=0~L, v_tg0~v_tgLIn only v_tgjIt is high level, remaining output is all low level；

2. Spring layer and gating circuit high：Gating circuit high is by variable threshold gating PMOS P_c1~P_cL, gate controlled PMOS P_e0With PMOS P_c0Composition；Pipe P_c1~P_cLSource electrode low pass threshold to be passed is respectively t_/h1~t_/hL, pipe P_c1~P_cLEffective input meet A_i, pipe P_c0~P_cLGrid meets control signal v respectively_/tg0~v_/tgL, and its drain electrode all adapter P_e0Grid g_/hj；To each B_iInput j, j=1 ~L, pipe P_c1~P_cLMiddle only one of which pipe P_cjConducting, remaining pipe cut-off, then in t_/h1~t_/hLIn only by t_/hjIt is loaded into pipe P_e0, Pipe P_e0Source electrode meets V_DC, its drain electrode adapter P_a00~P_a0L-1Source electrode；Spring layer circuit includes band logical variable threshold PMOS P_a00~P_a0L-1With Series diode D₀₀~D_0L-1, pipe P_a01~P_a0L-1High pass threshold be followed successively by t_h1~t_hL-1, pipe P_a00Low pass threshold be t_/h1, pipe D₀₀ ~D_0L-2The respective adapter D of negative pole₀₁~D_0L-1Positive pole, pipe P_a00~P_a0L-1Effectively input meets A_i, pipe P_a00~P_a0L-1Drain electrode each connects Pipe D₀₀~D_0L-1Negative pole, A_iIt is k to be input into, as k=0~j-1 and j ≠ 0, pipe P_e0Conducting, by pipe P_a00~P_a0L-1Source electrode leads to Cross P_e0Connect V_DC, Spring layer circuit work, use pipe P_e0Conducting control Spring layer (0, j-1) length j-2, j ≠ 0, as k=j~L When, pipe P_e0Cut-off, pipe P_a00~P_a0L-1Source electrode and V_DCDisconnect, Spring layer circuit does not work；

3. low value area and low gating circuit：Low gating circuit is by variable threshold gating PMOS P_d1~P_dL, gate controlled PMOS P_e1With PMOS P_d0Composition；Pipe P_d1~P_dL-1Source electrode high pass threshold to be passed is respectively t_h2~t_hL, P_dLSource electrode low pass threshold to be passed is t_/h1；Pipe P_d0~P_dLGrid meets control signal v respectively_/tg0~v_/tgL, P_d1~P_dLDrain electrode adapter P_e1Grid, P_d1~P_dLEffectively input meets A_i； To each j, j=1~L-1, pipe P_d1~P_dL-1In only a pipe P_djConducting, remaining pipe cut-off, in t_h2~t_hLMiddle selection t_hj+1 It is loaded into pipe P_e1, and j=L, pipe P_dLConducting, t_/h1It is loaded into pipe P_e1；Pipe P_e1And P_d0Drain electrode adapter P_a11~P_a1LSource electrode, P_e1With P_d0Source electrode meets V_DC；As k=j+1~L and 0<j<During L, pipe P_e1Conducting, pipe P_a11~P_a1LSource electrode passes through P_e1Connect V_DC, low value area Circuit works；Low value area circuit includes high pass variable threshold PMOS P_a11~P_a1LWith series diode D₁₂~D_1L, pipe D₁₂~D_1L-1It is negative Extremely respective adapter D₁₃~D_1LPositive pole, D_1LNegative pole meets D₀₀Positive pole, by D₁₂~D_1LAnd D₀₀~D_0L-1Series connection, constitutes 2L-1 series connection Diode sequence, pipe P_a11~P_a1LHigh pass threshold be respectively t_h1~t_hL, it is effectively input into and meets A_i, pipe P_a12~P_a1LDrain electrode each connects Pipe D₁₂~D_1LNegative pole, pipe P_a11Drain electrode meets D₁₂Positive pole；As j=0, pipe P_d0Conducting, pipe P_a11~P_a1LSource electrode passes through P_d0Connect V_DC, Spring layer circuit is invalid, and low value area circuit works and is formed as digital follower, uses pipe P_e1And P_d0Conducting control low value area (j+1, L) length L-j-2, j ≠ L；As k=0~j and j ≠ L, pipe P_e1Cut-off, pipe P_a11~P_a1LSource electrode and V_DCDisconnect, Low value area circuit does not work；To j=L, when k ≠ 0, pipe P_e1Cut-off, and as k=0, pipe P_e1Conducting, pipe P_a11~P_a1LIt is complete to cut Only, low value area circuit is invalid, the work of Spring layer circuit；

④S_iOutput circuit and J_iOutput circuit：S_iOutput circuit is by cmos transmission gate TG₀~TG_LWith constant-current source I_SiComposition, transmission Door TG₁~TG_LIt is input into adapter P respectively_a00~P_a0L-1Drain electrode, TG₀Input adapter P_a1LDrain electrode, TG₀~TG_LOutput all connects constant-current source I_SiUpper end, I_SiUpper end is used as S_iOutput, I_SiLower end is grounded, TG₀~TG_LPositive control end and negative control end meet v respectively_tg0~v_tgL And v_/tg0~v_/tgL, N is V_Don, to each j, j=1~L, in TG₁~TG_LMiddle only one of which TG_jConducting, S_i By the TG for turning on_jMeet P_a0j-1Drain electrode, to j=0, S_iBy the TG for turning on₀Adapter P_a1LDrain electrode；Choose V_DC=LV_Don+ △, △ It is the side-play amount of K value storage unit circuits characteristic requirements compensation；

J_iOutput circuit is by PMOS P_e2With constant-current source I_CiComposition, pipe P_e2Source electrode meets V_DC, pipe P_e2Grid adapter P_e0Grid g_/hj, pipe P_e2Drain electrode meets constant-current source I_CiUpper end, I_CiUpper end is used as J_iOutput, I_CiLower end is grounded, pipe P_c0Grid meets v_/tg0, P_c0Drain electrode meets P_e0 Grid；To j ≠ 0, as k ＜ j, pipe P_e0Grid g_/hjVoltage V_g/hj＜ V_DC, pipe P_e2Conducting, J_iIt is output as high level V_DC, represent Borrow, as k >=j, V_g/hj=V_DC, pipe P_e2Cut-off, J_iLow level 0 is output as, is indicated without borrowing；Pipe P_c0Source electrode connects direct current Pressure V_DC, J when making j=0_iIt is output as above-mentioned expression without the level for borrowing；All constant-current source senses of current are to flow to lower end by upper end.

4. a kind of K value half-subtracters of use band logical threshold loading technique according to claim 3 construction method formed one Plant using the K value half-subtracter circuits of band logical threshold loading technique, it is characterised in that：In the K of described use band logical threshold loading technique In value half-subtracter circuit, K=10 is taken, then draw a kind of 10 value half-subtracter circuits of use band logical threshold loading technique, 10 values partly subtract Device circuit includes：Control signal forms circuit, Spring layer and gating circuit high, low value area and low gating circuit, S_iOutput circuit And J_iOutput circuit；10 value half-subtracter particular circuit configurations are described as follows：

1. control signal forms circuit by logical value differentiation door U₀~U₉With CMOS not gates M₀~M₉Two parts constitute, and differentiate door U₀~ U₉Respectively by interval minimum band formula variable threshold PMOS P_b0~P_b9With constant-current source I₀~I₉Constitute, pipe P_b0~P_b9Band logical threshold point Wei not t_b0~t_b9, wherein t_b0=t_/h1, t_b9=t_h9, i.e. pipe P_b0And P_b9Respectively interval minimum low pass formula and formula variable threshold high PMOS, pipe P_b0~P_b9Effective input all meet B_i, pipe P_b0~P_b9Source electrode meets power supply V_DC, pipe P_b0~P_b9Drain electrode connects constant current respectively Source I₀~I₉Upper end, I₀~I₉Upper end is respectively as U₀~U₉Output v_tg0~v_tg9, constant-current source I₀~I₉Lower end is grounded, constant-current source electricity Stream is all to flow to lower end, v by upper end_tg0~v_tg9Not gate M is met respectively₀~M₉Input, M₀~M₉Output is respectively v_/tg0~v_/tg9, by This draws control signal v anti-phase each other_tg0~v_tg9And v_/tg0~v_/tg9, M₀~M₉Operating voltage is V_DC, to each B_iInput j, J=0~9, v_tg0~v_tg9In only v_tgjIt is high level, remaining output is all low level；

2. Spring layer and gating circuit high：Gating circuit high is by variable threshold gating PMOS P_c1~P_c9, gate controlled PMOS P_e0With PMOS P_c0Composition；Pipe P_c1~P_c9Source electrode low pass threshold to be passed is respectively t_/h1~t_/h9, pipe P_c1~P_c9Effective input meet A_i, pipe P_c0~P_c9Grid meets control signal v respectively_/tg0~v_/tg9, and its drain electrode all adapter P_e0Grid g_/hj；To each B_iInput j, j=1 ~9, pipe P_c1~P_c9Middle only one of which pipe P_cjConducting, remaining pipe cut-off, then in t_/h1~t_/h9In only by t_/hjIt is loaded into pipe P_e0, Pipe P_e0Source electrode meets V_DC, its drain electrode adapter P_a00~P_a08Source electrode；Spring layer circuit includes band logical variable threshold PMOS P_a00~P_a08And string Di- pole pipe D₀₀~D₀₈, pipe P_a01~P_a08High pass threshold be followed successively by t_h1~t_h8, pipe P_a00Low pass threshold be t_/h1, pipe D₀₀~D₀₇It is negative Extremely respective adapter D₀₁~D₀₈Positive pole, pipe P_a00~P_a08Effectively input meets A_i, pipe P_a00~P_a08The respective adapter D of drain electrode₀₀~D₀₈It is negative Pole；A_iIt is k to be input into, as k=0~j-1 and j ≠ 0, pipe P_e0Conducting, by pipe P_a00~P_a08Source electrode passes through P_e0Connect V_DC, high level Area's circuit work, uses pipe P_e0Conducting control Spring layer (0, j-1) length j-2, j ≠ 0, when k=j~9, pipe P_e0Cut-off, pipe P_a00~P_a08Source electrode and V_DCDisconnect, Spring layer circuit does not work；

3. low value area and low gating circuit：Low gating circuit is by variable threshold gating PMOS P_d1~P_d9, gate controlled PMOS P_e1With PMOS P_d0Composition；Pipe P_d1~P_d8Source electrode high pass threshold to be passed is respectively t_h2~t_h9, P_d9Source electrode low pass threshold to be passed is t_/h1；Pipe P_d0 ~P_d9Grid meets control signal v respectively_/tg0~v_/tg9, pipe P_d1~P_d9Drain electrode adapter P_e1Grid, pipe P_d1~P_d9Effectively input connects A_i；To each j, j=1~8, pipe P_d1~P_d8In only a pipe P_djConducting, remaining pipe cut-off, in t_h2~t_h9Middle selection t_hj+1Plus It is downloaded to pipe P_e1, and j=9, pipe P_d9Conducting, t_/h1It is loaded into pipe P_e1；Pipe P_e1And P_d0Drain electrode adapter P_a11~P_a19Source electrode, pipe P_e1With P_d0Source electrode meets V_DC；When k=j+1~9 and 0<j<When 9, pipe P_e1Conducting, by pipe P_a11~P_a19Source electrode passes through P_e1Connect V_DC, low value Area's circuit work；Low value area circuit includes band logical variable threshold PMOS P_a11~P_a19With series diode D₁₂~D₁₉, pipe D₁₂~D₁₈It is negative Extremely respective adapter D₁₃~D₁₉Positive pole, D₁₉Negative pole meets D₀₀Positive pole, by D₁₂~D₁₉And D₀₀~D₀₈Series connection, constitutes 17 two poles of series connection Pipe sequence, pipe P_a11~P_a19High pass threshold be respectively t_h1~t_h9, it is effectively input into and meets A_i, pipe P_a12~P_a19Drain electrode each adapter D₁₂~D₁₉Negative pole, pipe P_a11Drain electrode meets D₁₂Positive pole；As j=0, pipe P_d0Conducting, pipe P_a11~P_a19Source electrode passes through P_d0Connect V_DC, Spring layer circuit is invalid, and low value area circuit works and is formed as digital follower, uses pipe P_e1And P_d0Conducting control low value area (j+ 1,9) length 9-j-2, j ≠ 9；As k=0~j and j ≠ 9, pipe P_e1Cut-off, pipe P_a11~P_a19Source electrode and V_DCDisconnect, it is low Value area circuit does not work；To j=9, when k ≠ 0, pipe P_e1Cut-off, and as k=0, pipe P_e1Conducting, pipe P_a11~P_a19It is complete to cut Only, low value area circuit is invalid, the work of Spring layer circuit；

④S_iOutput circuit and J_iOutput circuit：S_iOutput circuit is by cmos transmission gate TG₀~TG₉With constant-current source I_SiComposition, transmission Door TG₁~TG₉It is input into adapter P respectively_a00~P_a08Drain electrode, TG₀Input adapter P_a19Drain electrode, TG₀~TG₉Output all meets constant-current source I_Si Upper end, I_SiUpper end is used as S_iOutput, I_SiLower end is grounded, TG₀~TG₉Positive control end and negative control end meet v respectively_tg0~v_tg9With v_/tg0~v_/tg9, N is V_Don, in TG₁~TG₉In, to each j, j=1~9, only one of which TG_jConducting, S_i By the TG for turning on_jMeet P_a0j-1Drain electrode, to j=0, S_iBy the TG for turning on₀Adapter P_a19Drain electrode；Choose V_DC=9V_Don+ △, △ It is the side-play amount of K value storage unit circuits characteristic requirements compensation；

5. a kind of K value half-subtracter circuits same characteristic features of use band logical threshold loading technique according to claim 3 are formed A kind of K value half adder circuits of use band logical threshold loading technique, it is characterised in that：In described K value half-subtracter circuits, (one) First, by U₁~U_LBand logical threshold be taken as t respectively_bL~t_b1；(ii) then, by borrow J_iIt is taken as carry digit C_i, without borrowing during except j=0 Position is taken as outside no-carry, and no-carry is taken as by all borrowing, and has been taken as carry without borrowing, pipe P_c0Source electrode connects DC voltage V_d, C when making j=0_iIt is output as the level of above-mentioned expression no-carry, V_DC- V_d=1.5 volts；(iii) it is last, half-subtracter is taken as half and is added Device, by A_i, B_iAnd S_iBe taken as summand successively, addend and one's own department or unit and, then using the K value half-subtracter circuits of band logical threshold loading technique Just turn into using the K value half adder circuits of band logical threshold loading technique.

6. a kind of 10 value half-subtracter circuit same characteristic features of use band logical threshold loading technique according to claim 4 are formed A kind of 10 value half adder circuits of use band logical threshold loading technique, it is characterised in that：In described use band logical threshold loading technique 10 value half-subtracter circuits in, (one) first, by U₁~U₉Band logical threshold be taken as t respectively_b9~t_b1；(ii) then, by borrow J_i It is taken as carry digit C_i, without in addition to borrowing and being taken as no-carry when j=0, no-carry is taken as by all borrowing, it has been taken as without borrowing Carry, pipe P_c0Source electrode meets DC voltage V_d, C when making j=0_iIt is output as the level of above-mentioned expression no-carry, V_DC- V_d=1.5 volts； (iii) it is last, half-subtracter is taken as half adder, by A_i, B_iAnd S_iBe taken as summand successively, addend and one's own department or unit and, then using band logical threshold 10 value half-subtracter circuits of loading technique just turn into using 10 value half adder circuits of band logical threshold loading technique.