CN118312468B - In-memory operation circuit with symbol multiplication and CIM chip - Google Patents

Abstract

The present invention belongs to the technical field of integrated circuits, and specifically relates to an in-memory operation circuit with signed multiplication and a CIM chip thereof. The in-memory operation circuit includes at least one column of operation units, and the operation unit includes a weight storage part and a calculation part; the weight storage part adopts an SRAM unit with a double word line; the circuit connection relationship of the calculation part is: the drains of P1 and N3 are connected to the calculation bit line CBL; the gate of N3 is connected to the bit line BL, and the gate of P1 is connected to the bit line BLB; the source of N3 is connected to the drain of N4; the source of P1 is connected to the drain of P2; the gate of N4 is connected to the input word line INN; the gate of P2 is connected to the input word line INP; the source of N4 is connected to VSS; the source of P2 is connected to VDD; the capacitor C is connected between CBL and VSS; the scheme solves the problems of large area overhead and low operation efficiency that are common in various existing CIM circuits with signed multiplication and multiplication-accumulation operation functions.

Description

A signed multiplication in-memory operation circuit and CIM chip

Technical Field

The invention belongs to the technical field of integrated circuits, and in particular relates to an in-memory operation circuit with signed multiplication and a CIM chip using the circuit.

Background Art

With the rapid development and popularization of artificial intelligence, convolutional neural networks (CNN) and deep neural networks (DNN) have become one of the most influential innovations in the field of computer vision. Neural networks such as CNN and DNN need to perform a large number of multiplication and multiply-accumulate (MAC) operations when processing data. When such operations are processed in computers based on the von Neumann architecture. The need to frequently move data between the processor and the memory results in high energy consumption and latency, a problem known as the von Neumann bottleneck or memory wall. Demonstrations of DNN processors and accelerators based on the von Neumann architecture show that energy consumption and latency depend mainly on the input data between the processor and the memory. Therefore, traditional von Neumann computers are not suitable for processing artificial intelligence-related computing tasks such as neural networks.

In order to overcome the von Neumann bottleneck, technicians proposed a memory-based computing-in-memory (CIM) architecture. This new computer architecture directly uses memory to perform logical operations, eliminating the need to move data between memory and processor. It can greatly improve data processing efficiency and reduce device operating power consumption.

Convolutional neural networks contain a large number of signed multiplication and multiplication-accumulation operations. Existing CIM circuits that can implement multi-bit signed multiplication or multiplication-accumulation generally separate positive and negative weights in the calculation process, and perform positive weight multiplication and negative weight multiplication in different SRAM units respectively. This design will increase the area overhead of the circuit and reduce the operation efficiency, thereby significantly prolonging the reasoning time of the neural network. In order to solve the problems of large area overhead and low operation efficiency commonly existing in various existing CIM circuits with signed multiplication and multiplication-accumulation functions, the present invention provides a signed multiplication in-memory operation circuit and a CIM chip using the circuit.

Summary of the invention

The technical solution provided by the present invention is:

A signed multiplication in-memory operation circuit includes at least one column of operation units, each column of operation units includes a weight storage part and a calculation part. The weight storage part uses an SRAM unit with a double word line. The drains of the two transmission tubes in the SRAM unit are respectively connected to the two bit lines, and the gates of the two transmission tubes are respectively connected to the two word lines. The calculation part is composed of two NMOS tubes N3 and N4, two PMOS tubes P1 and P2, and a capacitor C; the circuit connection relationship is:

The drains of P1 and N3 are connected to the calculation bit line CBL; the gate of N3 is connected to the bit line BL, and the gate of P1 is connected to the bit line BLB; the source of N3 is connected to the drain of N4; the source of P1 is connected to the drain of P2; the gate of N4 is connected to the input word line INN; the gate of P2 is connected to the input word line INP; the source of N4 is connected to VSS; the source of P2 is connected to VDD; one end of capacitor C is connected to the calculation bit line CBL, and the other end is connected to VSS.

The operation unit of each column is used to implement the multiplication operation between the signed 2-bit first operand and the unsigned second operand; the operation logic for performing the multiplication operation is:

The second operand is pre-stored in the SRAM cell, and the bit line CBL is pre-charged to an intermediate potential; the first operand is input by encoding the level states of WLL, WLR, INN and INP; the product of the first operand and the second operand is reflected in the change of the bit line voltage of the calculated bit line CBL.

As a further improvement of the present invention, the SRAM cell adopts a 6T-SRAM cell or other SRAM cells with double word lines obtained by adding MOS tubes to the 6T-SRAM cell.

In the present invention, the 6T-SRAM cell includes two NMOS tubes N1 and N2, and two inverters INV0 and INV1. The circuit connection relationship is as follows: the input end of INV0 and the output end of INV1 are connected to the source of N1 and serve as the storage node Q. The output end of INV0 and the input end of INV1 are connected to the source of N2 and serve as the storage node QB. The drains of N1 and N2 are connected to the bit lines BL and BLB respectively, and the gates of N1 and N2 are connected to the word lines WLL and WLR respectively.

As a further improvement of the present invention, during the multiplication operation, when the first operand in the multiplication operation is "+1", WLL, INN and INP are set to a low level, and WLR is set to a high level. When the first operand in the multiplication operation is "-1", WLL, INN and INP are set to a high level, and WLR is set to a low level. When the first operand in the multiplication operation is "0", WLL and INN are set to a low level, and WLR and INP are set to a high level.

As a further improvement of the present invention, during the multiplication operation, when the bit line voltage of the calculated bit line CBL rises, the product is "+1"; when the bit line voltage of the calculated bit line CBL drops, the product is "-1"; when the bit line voltage of the calculated bit line CBL remains unchanged, the product is "0".

As a further improvement of the present invention, the weight storage part includes multiple SRAM cells arranged in columns; each SRAM cell is connected to the same group of bit lines BL and BLB; each SRAM cell is also connected to independent word lines WLL and WLR of the corresponding row; each SRAM cell in the same column shares the circuit of the same calculation part.

As a further improvement of the present invention, in the calculation part, the width-to-length ratios of transistors N3 and N4 are the same; the width-to-length ratios of transistors P1 and P2 are the same.

As a further improvement of the present invention, by adjusting the capacitance of the capacitor C in each column calculation part, the weight of the second operand of the multiplication operation performed in the operation unit of different columns is distinguished. Among them, the multiple of the capacitor C in each column relative to the unit capacitance is the weight of the second operand in the operation process.

As a further improvement of the present invention, the in-memory operation circuit with signed multiplication includes N columns of operation units, and the capacitance value multiples of the capacitor C in each column of the operation unit are 1, 2, 4, 8, ..., 2 ^N-1 respectively. A transmission gate TG for connecting the calculation bit lines CBL of the two columns is respectively set between adjacent columns of operation units.

By using the in-memory operation circuit for signed multiplication including multiple columns of operation units provided by the present invention, a multiplication operation of a 2-bit first operand and an N-bit second operand can be implemented. The operation process is as follows:

(1) Disconnect the transmission gates between the operation columns; and precharge the calculation bit lines CBL of each two columns to the intermediate potential.

(2) The N-bit second operand is decomposed into N single-bit numbers, and each single-bit number is pre-stored in the weight storage part of a different column according to the corresponding weight.

(3) synchronously inputting the encoded first operand to the SRAM cells of all selected columns through WLL, WLR, INN and INP; and then performing a multiplication operation of the first operand and one bit of the second operand in each column;

(4) The transmission gates between the operation columns are closed. The product of the 2-bit first operand and the N-bit second operand is reflected in the change of the bit line voltage of the calculated bit line CBL. The change direction of the bit line voltage of CBL reflects the sign of the product, and the change amplitude of CBL reflects the value of the product.

The present invention also includes a CIM chip, which integrates the aforementioned in-memory operation circuit with signed multiplication.

The technical solution provided by the present invention has the following beneficial effects:

The present invention designs a signed multiplication in-memory calculation circuit based on a double-word-line double-bit-line SRAM cell, which stores a 1-bit weight in the SRAM cell, and a 2-bit signed number is divided into a 1-bit sign bit and a 1-bit unsigned number. The 1-bit sign bit is represented by controlling the high and low levels of the double-word lines WLL and WLR, and the 1-bit unsigned number is controlled in combination with the input word lines INN and INP of the newly added calculation part. In the circuit, according to the different values of each signal in the characterization weight and the signed number, the conduction of the charge and discharge path of the calculation word line CBL relative to the power supply and the ground can be controlled, and then the final product result is characterized by the change of the voltage at the point of CBL.

The circuit can realize multiplication operations between different symbol numbers in a single circuit unit, saving circuit area overhead, and the circuit reliability is relatively high.

The solution of the present invention can also represent the high and low bits of the weights in each column by calculating the size of the partially mounted capacitor C, and reflect the calculation result on the voltage of CBL to ensure the accuracy of the calculation result. Based on such a design circuit, it also supports the multiplication of 2-bit signed numbers and multi-bit weights, and the performance is more powerful.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a circuit schematic diagram of an in-memory operation circuit for signed multiplication provided in Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of a computing unit in each column in FIG. 1 .

FIG3 is a circuit diagram of a computing unit including a plurality of SRAM units in the weight storage part provided in Embodiment 1 of the present invention.

FIG. 4 is a circuit diagram of an in-memory operation circuit for signed multiplication including multiple columns of operation units provided in Embodiment 1 of the present invention.

FIG5 is an architecture diagram of a CIM chip provided in Embodiment 2 of the present invention.

FIG. 6 is a signal diagram of a calculation bit line CBL in the multiplication stage of a signed number and a single-bit weight in a test experiment.

FIG. 7 is a signal diagram of the calculation bit line CBL in the multiplication operation phase of the signed number “11” and the 4-bit weight in the test experiment.

FIG. 8 is a signal diagram of the calculation bit line CBL in the multiplication operation stage of the signed number “01” and the 4-bit weight in the test experiment.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

Example 1

The present embodiment provides an in-memory operation circuit with signed multiplication, as shown in FIG1 , which includes at least one column of operation units, and each column of operation units includes a weight storage part and a calculation part. Among them, the weight storage part adopts an SRAM cell with a double word line. In the actual circuit of this embodiment, the SRAM cell can adopt the classic 6T-SRAM cell, or it can adopt other SRAM cells with double word lines obtained by further adding MOS tubes to the 6T-SRAM cell and upgrading it, such as 8T-SRAM, 10T-SRAM and 12T-SRAM, etc.

In the SRAM cell with dual word lines used in this embodiment, at least one inverting latch structure with two storage nodes Q and QB and two transmission tubes located on both sides of the inverting latch structure for connecting the bit lines BL and BLB are included. In the scheme of this embodiment, the source electrodes of the two transmission tubes in the SRAM cell are connected to the storage nodes Q and QB, the drain electrodes are respectively connected to the two bit lines BL and BLB, and the gate electrodes are respectively connected to two independent word lines. In this implementation, the two word lines are respectively recorded as WLL and WLR.

For example, when the weight storage part of this embodiment adopts a 6T-SRAM unit, it includes two NMOS tubes N1 and N2, and two inverters INV0 and INV1. As shown in Figure 2, the circuit connection relationship is: the input end of INV0 and the output end of INV1 are connected to the source of N1 and serve as the storage node Q. The output end of INV0 and the input end of INV1 are connected to the source of N2 and serve as the storage node QB. The drains of N1 and N2 are connected to the bit lines BL and BLB respectively, and the gates of N1 and N2 are connected to the word lines WLL and WLR respectively.

As shown in FIG. 2 , the calculation part of each column of the operation unit in this embodiment is composed of two NMOS transistors N3 and N4, two PMOS transistors P1 and P2, and a capacitor C; the circuit connection relationship is:

The drains of P1 and N3 are connected to the calculation bit line CBL; the gate of N3 is connected to the bit line BL, and the gate of P1 is connected to the bit line BLB; the source of N3 is connected to the drain of N4; the source of P1 is connected to the drain of P2; the gate of N4 is connected to the input word line INN; the gate of P2 is connected to the input word line INP; the source of N4 is connected to VSS; the source of P2 is connected to VDD; one end of capacitor C is connected to the calculation bit line CBL, and the other end is connected to VSS.

Combined with the circuit diagram, it can be seen that in the calculation part of this embodiment, when the storage node Q and the input word line INN are both high, the calculation bit line CBL can be connected to the ground terminal VSS through N3 and N4, thereby forming a discharge path. When the storage node QB and the input word line INP are both high, the calculation bit line CBL can be connected to the power supply terminal VDD through P1 and P2, thereby forming a charging path.

In particular, in order to ensure the consistency of the charge and discharge characteristics in the charging path and the discharging path, the calculation part of this embodiment uses the same width-to-length ratio for transistors N3 and N4; the same width-to-length ratio for transistors P1 and P2.

Based on the above working principle of the calculation part in the circuit, in the in-memory operation circuit with signed multiplication provided in this embodiment, the operation unit of each column can realize the multiplication operation between the signed 2-bit first operand and the unsigned 1-bit second operand. In detail, the operation logic of the circuit scheme to perform the multiplication operation is:

1. The second operand is pre-stored in the SRAM cell, and the calculation bit line CBL is pre-charged to an intermediate potential.

Taking the circuit scheme based on 6T-SRAM shown in FIG2 as an example, if the second operand in the multiplication operation to be performed is "0", the storage node Q is set to a low level and QB is set to a high level through the original data storage function of the 6T-SRAM unit. Conversely, if the second operand in the multiplication operation to be performed is "1", the storage node Q is set to a high level and QB is set to a low level through the original data storage function of the 6T-SRAM unit.

In addition, before the operation, the bit line level of the calculation bit line CBL needs to be precharged to an intermediate potential. In this embodiment, the "intermediate potential" refers to the intermediate potential relative to the power supply voltage VDD and the ground terminal VSS. Specifically, in this embodiment, CBL is precharged to 1/2 VDD in the initial stage.

2. Encode the first input operand through the level status of WLL, WLR, INN and INP.

In this embodiment, the input of the first operand is realized by inputting control signals of different level states to the word lines WLL and WLR in the weight storage part and the input word lines INN and INP in the calculation part. Specifically, combined with the working principle of the circuit, the encoding rules of the second operand in this embodiment are as follows:

(1) When the first operand in the multiplication operation is "+1", WLL, INN and INP are set to low levels and WLR is set to high level.

(2) When the first operand in the multiplication operation is "-1", WLL, INN and INP are set to high levels and WLR is set to low level.

(3) When the first operand in the multiplication operation is "0", WLL and INN are set to low level, and WLR and INP are set to high level.

3. In the in-memory operation circuit with signed multiplication provided in this embodiment, after the input of the first operand and the second operand is completed, the product of the first operand and the second operand is reflected in the change of the bit line voltage of the calculated bit line CBL.

Specifically, in the circuit of this embodiment, the level states of Q, QB, WLL, WLR, INN, INP, etc. will eventually affect the conduction state of each MOS tube between CBL and low-level VSS and high-level VDD. A charging path and a discharging path are formed between CBL and VDD or VSS, which in turn causes the bit line voltage of CBL at the "intermediate potential" to increase or decrease. The change in the bit line voltage on CBL can just represent the final product.

Specifically, during the multiplication operation performed by the circuit of this embodiment, when the bit line voltage of the calculated bit line CBL rises, it indicates that the product is "+1"; when the bit line voltage of the calculated bit line CBL drops, it indicates that the product is "-1"; when the bit line voltage of the calculated bit line CBL remains unchanged, it indicates that the product is "0".

In order to make the principle and performance of the in-memory operation circuit with signed multiplication provided by this embodiment clearer, the operation process of the circuit is described in detail below in combination with six different operation processes of different first operands and second operands:

1. (+1) × 1

First, the second operand "1" is pre-stored in the 6T-SRAM cell, and CBL is pre-charged to VDD/2. At this time, the storage node Q in the 6T-SRAM cell is at a high level, and QB is at a low level.

Then, WLL is set to a low level and WLR is set to a high level. At this time, the N1 tube remains off, the N2 tube is turned on, and the data at the QB end is transmitted to the gate end of the P1 tube through the N2 tube, and the P1 tube is turned on. At the same time, the INN end is set to a low potential, and the INP end is set to a low potential, then the P2 tube is also turned on. At this time, the charging path between CBL and VDD is opened, and because N3 and N4 fail to turn on, the discharge path between CBL and VSS remains closed. Therefore, the bit line voltage on the calculated bit line CBL will gradually increase from VDD/2 to VDD. The bit line voltage of CBL increases, indicating that the product result is (+1).

The operation is completed: (+1)×1= (+1).

2. (-1) × 1

First, the second operand "1" is pre-stored in the 6T-SRAM cell, and CBL is pre-charged to VDD/2. At this time, the storage node Q in the 6T-SRAM cell is at a high level, and QB is at a low level.

Then, WLL is set to a high level and WLR is set to a low level. At this time, N1 tube is turned on, N2 tube remains off, and the data at the Q end is transmitted to the gate end of N3 tube through N1 tube, and N3 tube is turned on. At the same time, the INN end is set to a high potential, and the INP end is set to a high potential, then N4 tube is also turned on. At this time, the discharge circuit between CBL and VSS is turned on; and because P1 and P2 fail to conduct, the charging path between CBL and VDD is closed. Therefore, the bit line voltage on the calculated bit line CBL will gradually decrease from VDD/2 to VSS. The bit line voltage of CBL decreases, indicating that the product result is (-1).

The operation is completed: (+1)×1= (+1).

3. (+1) × 0

First, the second operand "0" is pre-stored in the 6T-SRAM cell, and CBL is pre-charged to VDD/2. At this time, the storage node Q in the 6T-SRAM cell is at a low level, and QB is at a high level.

Then, WLL is set to a low level and WLR is set to a high level. At this time, N2 is turned on and N1 remains off. The data at the QB end is transmitted to the gate end of P1 through N2, and P1 is turned off. At the same time, the INN end is set to a low potential, and the INP end is set to a low potential, and the N4 tube is also turned off. In this state, since both N4 and P1 are turned off, the discharge circuit between CBL and VSS is turned off, and the charging path between CBL and VDD is also turned off. Therefore, if the bit line voltage on the bit line CBL remains unchanged at the current level, the product result is 0.

The operation is completed: (+1)×0=0.

4. (-1) × 0

First, the second operand "0" is pre-stored in the 6T-SRAM cell, and CBL is pre-charged to VDD/2. At this time, the storage node Q in the 6T-SRAM cell is at a low level, and QB is at a high level.

Then, WLL is set to a high level and WLR is set to a low level. At this time, N1 tube is turned on, N2 tube remains off, and the data at the Q end is transmitted to the gate end of N3 tube through N1 tube, and N3 tube is turned off. At the same time, the INN end is set to a high potential, and the INP end is set to a high potential, then P2 tube is also turned off. In this state, since both N3 and P2 are turned off, the discharge circuit between CBL and VSS is turned off, and the charging path between CBL and VDD is also turned off. Therefore, if the bit line voltage on the bit line CBL remains unchanged at the current level, it means that the product result is 0.

The operation is completed: (-1)×0=0.

5.0×1

First, the second operand "1" is pre-stored in the 6T-SRAM cell, and CBL is pre-charged to VDD/2. At this time, the storage node Q in the 6T-SRAM cell is at a high level, and QB is at a low level.

Then, WLL is set to a low level, and WLR is set to a low level. At this time, both N1 and N2 are turned off. At the same time, the INN terminal is set to a low potential, and the INP terminal is set to a high potential. In this state, the discharge circuit between CBL and VSS is turned off, and the charging path between CBL and VDD is also turned off. Therefore, if the bit line voltage on the bit line CBL remains unchanged at the current level, the product result is 0.

The operation is completed: 0×1=0.

6.0×0

First, the second operand "0" is pre-stored in the 6T-SRAM cell, and CBL is pre-charged to VDD/2. At this time, the storage node Q in the 6T-SRAM cell is at a low level, and QB is at a high level.

Then, WLL is set to a low level, and WLR is set to a low level. At this time, both N1 and N2 are turned off. At the same time, the INN terminal is set to a low potential, and the INP terminal is set to a high potential. In this state, the discharge circuit between CBL and VSS is turned off, and the charging path between CBL and VDD is also turned off. Therefore, if the bit line voltage on the bit line CBL remains unchanged at the current level, the product result is 0.

The calculation is completed: 0×0=0.

In combination with the above process, the truth table of the signed multiplication operation process performed by the in-memory operation circuit for signed multiplication provided in this embodiment is summarized as shown in Table 1 below:

Table 1: Truth table of the operation process of the in-memory operation circuit with signed multiplication

In combination with the above truth table, it can be found that the in-memory operation circuit for signed multiplication provided in this embodiment, which includes a weight storage part and a calculation part, can fully realize the multiplication operation of a signed 2-bit number and an unsigned 1-bit number.

In a further optimized solution of the present embodiment, as shown in FIG3 , the weight storage part of each column of operation units includes a plurality of SRAM cells arranged in columns; each SRAM cell is connected to the same group of bit lines BL and BLB; each SRAM cell is also connected to independent word lines WLL and WLR of the corresponding row; each SRAM cell in the same column shares the circuit of the same calculation part.

In the circuit design shown in FIG3 , the SRAM cells in each row of the same column can form a basic unit that can perform a signed multiplication task with the calculation part below, thereby greatly saving the area overhead in the circuit. In addition, the design in which the SRAM cells in the same column share a calculation part also allows different second operands to be pre-stored in different rows during the pre-storage stage, and then different rows are enabled in turn to complete different multiplication operations to improve the operation efficiency. Furthermore, after applying this design to an array containing a large number of SRAM cells, it is also possible to pre-store the second operand of another operation task in other SRAM cells in different rows and columns while a certain SRAM cell participates in the multiplication operation, so as to improve the work efficiency of the circuit in processing large-scale similar logical operation tasks.

In a further optimized solution of this embodiment, as shown in FIG4 , the in-memory operation circuit with signed multiplication may further include multiple columns of operation units, assuming that the number of columns of operation units in the circuit is N, N ≥ 2. At this time, by adjusting the capacitance of the capacitor C mounted on each column of the calculation part, and setting a transmission gate TG for connecting the calculation bit line CBL between adjacent columns of operation units, it is also possible to distinguish the weights of the second operands of the multiplication operations performed in operation units of different columns.

The principle of distinguishing the weight of the second operand is: when the size of the capacitors C mounted in different columns is set to 8C, 4C, 2C, and 1C respectively, their charges remain unchanged at 8Q, 4Q, 2Q, and 1Q respectively. On this basis, the calculation results in the calculations in different columns are reflected on their respective calculation bit lines CBL. Although the bit line voltage of each column has only three states: VDD, VDD/2, and VSS, when the CBLs of different columns with different capacitors are connected through the transmission gate, the capacitors on different columns will share charges, which will cause the bit line voltage on the calculation bit line CBL to finally present more different levels of voltage states. These different levels of voltage can be used to represent the product of the 2-bit first operand and the N-bit second operand.

Based on the circuit scheme in FIG. 4 , the in-memory operation circuit for signed multiplication including multiple columns of operation units provided in this embodiment implements the operation process of multiplying a 2-bit first operand and an N-bit second operand as follows:

(1) Disconnect the transmission gates TG between the operation columns; and precharge the calculation bit lines CBL of each of the two columns to the intermediate potential.

(2) The N-bit second operand is decomposed into N single-bit numbers, and each single-bit number is pre-stored in the weight storage part of a different column according to the corresponding weight.

(3) synchronously inputting the encoded first operand to the SRAM cells of all selected columns through WLL, WLR, INN and INP; and then performing a multiplication operation of the first operand and one bit of the second operand in each column;

(4) The transmission gates between the operation columns are closed. The product of the 2-bit first operand and the N-bit second operand is reflected in the change of the bit line voltage of the calculated bit line CBL. The change direction of the bit line voltage of CBL reflects the sign of the product, and the change amplitude of CBL reflects the value of the product.

Taking the execution of 2bit×2bit multiplication as an example, the operation process requires two columns of operation units, one of which is mounted with a 1C capacitor and the other with a 2C capacitor. At this time, the BLK mounted with a 1C capacitor is the low-order operation column, and the operation unit mounted with a 2C capacitor is the high-order operation column.

Assume that the operation process is "+1×11" and the product result is "+3". At this time in the circuit, the bit line voltages on the CBL of the two operation units are both VDD before charge sharing, and the bit line voltages of the CBL are still VDD after charge sharing, △V=VDD/2.

Assume that the operation process is "+1×10", and the product result is "+2". At this time, in the circuit, the bit line voltage on the CBL of the low-order operation unit is VDD/2 before charge sharing, and the bit line voltage on the CBL of the high-order operation unit is VDD before charge sharing. Considering that the capacitor mounted on the low-order operation unit is 1C and the capacitor mounted on the high-order operation unit is 2C, the bit line voltage of CBL after charge sharing is 5VDD/6, △V=VDD/3.

Assume that the operation process is "+1×01" and the product result is "+2". At this time in the circuit, the bit line voltage on the CBL of the low-order operation unit is VDD before charge sharing, and the bit line voltage on the CBL of the low-order operation unit is VDD/2 before charge sharing. Considering that the capacitor mounted on the low-order operation unit is 1C and the capacitor mounted on the high-order operation unit is 2C, the bit line voltage of CBL after charge sharing is 2VDD/3, △V=VDD/6.

Assume that the operation process is "+1×00" and the product result is "+2". At this time in the circuit, the bit line voltages on the CBL of the two operation units are both VDD/2 before charge sharing, and the bit line voltages after charge sharing are still VDD/2, and △V=0.

It can be seen that when the product result decreases in steps of +3, +2, +1, and 0, the change △V of the bit line voltage on the CBL after charge sharing also decreases in steps of VDD/2, VDD/3, VDD/6, and 0, and the decrease in each step is VDD/6.

The summary rule is: in the charge sharing mechanism of this embodiment, when the product result includes 2 ^M situations, each operation unit can divide the change of the bit line voltage of CBL (from VDD/2 to VDD) into 2 ^M different gradients, and establish a mapping relationship between △V of different gradients and the digital quantities of different product results.

The above only introduces the example of a 2-bit signed number being a positive number. Based on the same principle, when the 2-bit signed number is a negative number, the same rule should also apply. Similarly, when more operation units are used to perform multiplication operations of higher-bit second operands, the relevant rules should also be met.

Therefore, in the present embodiment, after capacitors C of different sizes are mounted on each operation unit, under the charge sharing mechanism of the present embodiment, the multiplication result of the 2-bit signed first operand and the M-bit unsigned second operand will be reflected in the change amount of the bit line voltage of the calculated bit line CBL. By quantifying the change direction and specific value of the bit line voltage on the CBL after charge sharing by the successive approximation ADC, the digital quantity of different operation results can be accurately obtained.

Example 2

On the basis of Example 1, this embodiment further provides a CIM chip, in which the in-memory operation circuit with signed multiplication as in Example 1 is integrated. As shown in FIG5 , the CIM chip includes an N×N SRAM array, and a calculation module consisting of N circuits such as the calculation part in Example 1 is configured below the array; the calculation bit lines CBL of each unit circuit in the calculation module are connected in series in sequence through N-1 transmission gates; and the capacitance value of the capacitor C mounted on each unit circuit is distributed in a stepwise manner of 8, 4, 2, and 1. In addition, the CIM chip also includes various peripheral circuits related to realizing data reading, writing, and holding functions based on the SRAM array,

The CIM chip provided in this embodiment has the same data processing function as the SRAM chip, and can also be used to perform multiplication operations of signed numbers and single-bit or multi-bit numbers. Therefore, it is suitable for performing data processing tasks of neural networks such as CNN and DNN in artificial intelligence.

Performance Testing

In order to further verify the performance of the in-memory operation circuit with signed multiplication provided by the present invention, the technicians formulated an experimental plan and conducted a simulation experiment on the function of the circuit shown in FIG5 :

1. Multiplication of signed numbers and single-bit weights

This embodiment first uses one of the 6T-SRAM units in the circuit and its corresponding calculation part as the experimental object, and performs a multiplication operation of a 2-bit signed number by a 1-bit weight to verify the operation performance of the circuit when performing signed number multiplication (+1×1 and -1×1). The pre-charge voltage of CBL before calculation (2ns before) is set to VDD/2.

The signal changes of the bit line CBL during the experiment are shown in Figure 6. By analyzing the signal flow chart in Figure 6, it can be found that: starting from 2ns, the circuit starts to calculate the 2-bit signed number multiplied by the 1-bit weight. When the 2-bit signed number is '11' (referring to -1), WLL is set to a high potential, WLR is set to a low potential, the sign bit indicates negative, the 1-bit weight is "1", and CBL is discharged to VSS. When the 2-bit signed number is '01' (referring to +1), WLL is set to a low potential, WLR is set to a high potential, the sign bit indicates positive, the 1-bit weight is "1", and CBL is charged to VDD.

2. Multiplication of a signed number (-1) and a 4-bit weight

This experiment further uses the four operation units in the circuit as the operation object to perform a 2-bit signed number multiplied by a 4-bit weight calculation. In the circuit, three transmission gates connect the CBLs of the four operation units based on 6T-SRAM units in the same row. The sizes of the capacitors C mounted in each type are 8C, 4C, 2C, and 1C respectively. In this operation process, VDD is set to 900mV, and the set voltage reached by CBL before 2ns is 450mV.

During the experiment, all calculation tasks from "11" multiplied by "0000" to "1111" were executed in sequence. The circuit started to perform 2-bit signed number multiplied by 4-bit weight calculation at 2ns, and charge sharing started at 2.2ns. The signal flow graph of the obtained CBL is shown in Figure 7.

By observing the data in the figure, we can find that: when the 2-bit signed number is "11" (WLL is set to high potential, WLR is set to low potential, and the sign bit indicates negative), the 4-bit weight is "0000", the four CBLs remain unchanged at 450mV, and the CBL after charge sharing is 448.55mV; the 4-bit weight is "0001", and the CBL after charge sharing is 421.32mV; the 4-bit weight is "0010", and the CBL after charge sharing is 391.05mV; the 4-bit weight is "0011", and the CBL after charge sharing is 358.97mV; the 4-bit weight is "0100", and the CBL after charge sharing is 331.07mV; the 4-bit weight is "0101", and the CBL after charge sharing is 300.72mV; the 4-bit weight is "0110", and the CBL after charge sharing is 268.75mV; The 4-bit weight is "0111", and the CBL after charge sharing is 243.42mV; the 4-bit weight is "1000", and the CBL after charge sharing is 209.92mV; the 4-bit weight is "1001", and the CBL after charge sharing is 181.73mV; the 4-bit weight is "1010", and the CBL after charge sharing is 150.36mV; the 4-bit weight is "1011", and the CBL after charge sharing is 119.17mV; the 4-bit weight is "1100", and the CBL after charge sharing is 91.92mV; the 4-bit weight is "1101", and the CBL after charge sharing is 62.03mV; the 4-bit weight is "1110", and the CBL after charge sharing is 33.25mV; the 4-bit weight is "1111", and the CBL after charge sharing is 1.99mV.

Analysis of the data shows that: during the multi-bit multiplication operation, the fluctuation of the difference between the various operation results is within the allowable error range. The circuit has good linearity during discharge, and the reliability of the circuit operation results is high.

3. Multiplication of a signed number (+1) and a 4-bit weight

This experiment continues to use the four operation units in the circuit as the operation object, and performs a 2-bit signed number multiplied by a 4-bit weight calculation. In the circuit, three transmission gates connect the CBLs of the four operation units based on 6T-SRAM units in the same row together. The sizes of the capacitors C mounted in each type are 8C, 4C, 2C, and 1C respectively. In this operation process, VDD is set to 900mV, and the set voltage reached by CBL before 2ns is 450mV.

During the experiment, all calculation tasks from "01" multiplied by "0000" to "1111" were executed in sequence. The circuit started to perform 2-bit signed number multiplied by 4-bit weight calculation at 2ns, and charge sharing started at 2.2ns: the signal flow graph of the obtained CBL is shown in Figure 8.

Analyzing the data in the figure, we can find that:

When the 2-bit signed number is "01" (WLL is set to low potential, WLR is set to high potential, and the sign bit indicates positive), and the 4-bit weight is "0000", the four CBLs remain unchanged at 450mV, and the CBL after charge sharing is 450mV; the 4-bit weight is "0001", and the CBL after charge sharing is 481.25mV; the 4-bit weight is "0010", and the CBL after charge sharing is 510.02mV; the 4-bit weight is "0011", and the CBL after charge sharing is 539.11mV; the 4-bit weight is "0100", and the CBL after charge sharing is 570.07mV; the 4-bit weight is "0101", and the CBL after charge sharing is 599.48mV; the 4-bit weight is "0110", and the CBL after charge sharing is 630.58mV; the 4-bit weight is "0 4-bit weight is "111", and the CBL after charge sharing is 661.94mV; the 4-bit weight is "1000", and the CBL after charge sharing is 688.31mV; the 4-bit weight is "1001", and the CBL after charge sharing is 719.83mV; the 4-bit weight is "1010", and the CBL after charge sharing is 752.36mV; the 4-bit weight is "1011", and the CBL after charge sharing is 780.66mV; the 4-bit weight is "1100", and the CBL after charge sharing is 811.02mV; the 4-bit weight is "1101", and the CBL after charge sharing is 840.83mV; the 4-bit weight is "1110", and the CBL after charge sharing is 868.52mV; the 4-bit weight is "1111", and the CBL after charge sharing is 898.87mV.

During the multi-bit multiplication operation, the fluctuation of the difference between the various operation results is within the allowable error range. The circuit also has good linearity during charging, and the reliability of the circuit operation results is high.

The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims (9)

1. An in-memory arithmetic circuit with signed multiplication, characterized in that it comprises at least one column of arithmetic units, each column of arithmetic units comprising a weight storage part and a calculation part; wherein, the weight stores the part, it adopts SRAM cell with double word lines; the drains of two transmission pipes in the SRAM unit are respectively connected to two bit lines, and the gates of the two transmission pipes are respectively connected to two word lines WLL and WLR; the computing part comprises two NMOS tubes N3 and N4, two PMOS tubes P1 and P2 and a capacitor C; the circuit connection relation is as follows:

The drains of P1 and N3 are connected to the computation bit line CBL; the gate of N3 is connected with the bit line BL, and the gate of P1 is connected with the bit line BLB; the source electrode of N3 is connected with the drain electrode of N4; the source electrode of the P1 is connected with the drain electrode of the P2; the grid electrode of N4 is connected with an input word line INN; the grid electrode of P2 is connected with an input word line INP; the source electrode of N4 is connected with VSS; the source electrode of P2 is connected with VDD; one end of the capacitor C is connected to the computation bit line CBL, and the other end is connected to VSS;

The operation unit of each column is used for realizing multiplication operation between a signed 2bit first operand and an unsigned second operand; the operation logic for performing the multiplication operation is:

Pre-storing a second operand in the SRAM cell; calculating the bit line CBL to be precharged to an intermediate potential; encoding the input first operand by the level states of WLL, WLR, INN and INP; the product of the first operand and the second operand is reflected in a change in the bit line voltage of the computation bit line CBL;

When the first operand in the multiplication operation is "+1", WLL, INN and INP are set to low level, and WLR is set to high level; when the first operand in the multiplication operation is "-1", WLL, INN and INP are set to high level, and WLR is set to low level; when the first operand in the multiplication operation is "0", WLL and INN are set low, and WLR and INP are set high.

2. The in-memory arithmetic circuit of signed multiplication of claim 1, wherein: the SRAM unit adopts a 6T-SRAM unit or other SRAM units with double word lines, which are obtained by adding MOS tubes on the basis of the 6T-SRAM unit.

3. The in-memory arithmetic circuit of signed multiplication of claim 2, wherein: the 6T-SRAM unit comprises two NMOS transistors N1 and N2 and two inverters INV0 and INV1; the circuit connection relationship is as follows: the input end of the INV0 and the output end of the INV1 are connected with the source electrode of the N1 and serve as a storage node Q; the output end of the INV0 and the input end of the INV1 are connected with the source electrode of the N2 and serve as a storage node QB; the drains of N1 and N2 are connected to bit lines BL and BLB, respectively, and the gates of N1 and N2 are connected to word lines WLL and WLR, respectively.

4. The in-memory arithmetic circuit of signed multiplication of claim 3, wherein: during the multiplication operation, when the bit line voltage of the calculated bit line CBL rises, the product is expressed as "+1"; when the bit line voltage of the calculated bit line CBL drops, the product is represented as "-1"; when the bit line voltage of the calculated bit line CBL remains unchanged, the product is represented as "0".

5. The in-memory arithmetic circuit of signed multiplication of claim 1, wherein: the weight storage part comprises a plurality of SRAM units which are arranged in columns; each SRAM cell is connected to the same set of bit lines BL and BLB; each SRAM cell is also connected to an independent word line WLL and WLR of the corresponding row; the same column of SRAM cells share the same circuitry of the computation portion.

6. The in-memory arithmetic circuit of signed multiplication of claim 1, wherein: in the calculation section, the aspect ratio of the transistors N3 and N4 is the same; the aspect ratio of transistors P1 and P2 is the same.

7. The in-memory arithmetic circuit of signed multiplication of claim 1, wherein: the weight of a second operand of multiplication operation executed in operation units of different columns is distinguished by adjusting the capacitance of a capacitor C in each column of calculation parts; the multiple of the capacitance C in each column relative to the unit capacitance is the weight of the second operand in the operation process.

8. The in-memory arithmetic circuit of signed multiplication of claim 7, wherein: the device comprises N rows of operation units, wherein the multiplying power of capacitance values of capacitors C in each row of operation units is 1, 2, 4, 8, … and 2 ^N-1 respectively; a transmission gate TG for connecting a calculation bit line CBL of each two adjacent columns of operation units is arranged between each two adjacent columns of operation units respectively;

The strategy for implementing multiplication operation of a 2bit first operand and a Nbit second operand based on a multi-column arithmetic unit is as follows:

Disconnecting transmission gates among operation columns; and precharging the computation bit lines CBL of each two columns to an intermediate potential;

Decomposing a second operand of Nbit into N single-bit numbers according to bits, and pre-storing each single-bit number into weight storage parts of different columns according to corresponding weights;

Synchronizing input of the encoded first operand to all selected columns of SRAM cells through WLL, WLR, INN and INP; and then completing multiplication operation of one bit in the first operand and the second operand in each column;

Closing transmission gates among operation columns, wherein the product of the 2bit first operand and the Nbit second operand is reflected on the change of bit line voltage of a calculation bit line CBL; the change direction of the bit line voltage of the CBL reflects the sign of the product, and the change amplitude of the CBL reflects the numerical value of the product.

9. A CIM chip, characterized in that: integrated with an in-memory arithmetic circuit of signed multiplication as claimed in any one of claims 1 to 8.