CN116364137A

CN116364137A - Same-side double-bit-line 8T unit, logic operation circuit and CIM chip

Info

Publication number: CN116364137A
Application number: CN202310345783.6A
Authority: CN
Inventors: 强斌; 赵强
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2023-04-03
Filing date: 2023-04-03
Publication date: 2023-06-30

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an 8T unit, a quantization circuit, a logic operation circuit, a coding circuit, a memory circuit and a CIM chip of double bit lines on the same side. The 8T unit has a data read-write maintaining function and a Boolean logic operation function, and supports independent or parallel operation of AND, OR, AND or OR three types of logic operation; the 8T unit is composed of 2 PMOS tubes P1-P2 and 6 NMOS tubes N1-N6, wherein P1, P2 and N1-N4 form a classical 6TSRAM structure, and the grid electrode of N5 is connected with an inverted storage node QB; the drain electrode of N5 is connected with the source electrode of N6 and connected with a bit line CBL in parallel; the drain electrode of N6 is connected with a bit line RBL; the grid electrode of N6 is connected with a word line RWL1; n5 has its source connected to word line RWL2; the word lines RWL1 and RWL2 are used for inputting one operand required by logic operation, and the bit lines RBL and/or CBL are used for outputting a corresponding operation result. The invention solves the problems of single logical operation function and narrow application scene supported by various existing memory circuit schemes.

Description

Same-side double-bit-line 8T unit, logic operation circuit and CIM chip

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to an 8T unit of a same-side double-bit line, a quantization circuit, a logic operation circuit, a coding circuit, a memory circuit of the 8T unit based on the same-side double-bit line and a CIM chip.

Background

The continuous development of technologies such as face recognition, unmanned, machine translation, voiceprint recognition and intelligent customer service machines brings great convenience to the life of people. These technologies all belong to artificial intelligence (artificial intelligence, AI) technology, and the development of artificial intelligence technology is not separated from the support of big data. Artificial intelligence requires processing massive data in the application process, and the explosively-growing data requires that the processor has a great improvement in computing capacity, and technicians need to greatly improve the performance of the processor to meet the requirement of 'computing age'.

The conventional von neumann architecture separates the processor compute unit from memory, reads data from memory when the processor is operating, and then writes the data back to memory after the processor has processed the data. Most computing systems today are based on von neumann architecture, where there is physical separation between the arithmetic units and the memory units. The power consumption and delay of data round trip between the arithmetic unit and the memory unit are much larger than those required for computation. Therefore, von neumann architecture becomes a bottleneck restricting big data and artificial intelligence applications, and in order to greatly reduce the delay of data and reduce power consumption, it is urgent to search for a new architecture. The computing in-memory (CIM) architecture is a new computing architecture which breaks through the bottleneck problem of von Neumann, integrates an operation unit and a storage unit into a whole, realizes storage and operation in the unit, and does not need to carry out cross-unit transmission of data, so that the data processing speed can be effectively increased, the requirement of big data application can be met, the power consumption can be greatly reduced, and the computing parallelism can be improved.

The SRAM is widely used for the cache closest to the computing unit due to the advantages of high speed, low power consumption and good compatibility of logic circuits, and on the basis, the development of CIM chips with different types of in-memory operation functions is a popular research field. Current research based on SRAM in-memory computation has focused mainly on three parts, the voltage domain, the current domain and the charge domain. To handle different logical operation tasks, a technician developed a series of SRAM cells with complex logical operation functions based on common 6T memory cells. For example, some technicians have developed decoupled 8T SRAM cells that are capable of performing different types of logic operation tasks, but the functions of boolean logic operations that can be performed by conventional decoupled 8T SRAM cells are relatively single and cannot cope with more complex logic operation scenarios.

Disclosure of Invention

In order to solve the problems that the logic operation functions supported by various existing memory operation circuit schemes are single and the application scene is narrow, the invention provides an 8T unit of a same-side double-bit line, a quantization circuit, a logic operation circuit and a coding circuit, a memory operation circuit of the 8T unit based on the same-side double-bit line and a CIM chip.

The invention is realized by adopting the following technical scheme:

an 8T unit with double bit lines on the same side is used as a basic functional unit of an SRAM circuit and has a data read-write holding function and a Boolean logic operation function. This type 8T cell supports separate or parallel operations of the and, or, co-or three types of boolean logic operations. The 8T unit is composed of 2 PMOS tubes P1-P2 and 6 NMOS tubes N1-N6, and the circuit connection relation is as follows:

the sources of P1 and P2 are connected with a power supply VDD; the sources of N1 and N2 are grounded GND. The drains of P1, N1 and N3 are electrically connected with the gates of P2 and N2 and serve as a storage node Q; the drains of P2, N4 are electrically connected to the gates of P1, N5 and serve as the inverted storage node QB. The grid electrodes of N3 and N4 are connected with word lines WL; n3 has its source connected to bit line BL; n4 has its source connected to bit line BLB; the drain electrode of N5 is connected with the source electrode of N6 and connected with a bit line CBL in parallel; the drain electrode of N6 is connected with a bit line RBL; the grid electrode of N6 is connected with a word line RWL1; n5 is connected to word line RWL2.

Wherein, word lines RWL1 and RWL2 are commonly used for inputting one operand required by boolean logic operation, and bit lines RBL and/or CBL are used for outputting corresponding operation result.

In the improved 8T unit containing double bit lines at the same side, a 6T unit consisting of P1, P2 and N1-N4 is used as a basic unit for executing a data read-write holding function. The circuit structure of the 6T cell is a traditional SRAM cell circuit. Wherein P1 and N1 form one inverter, and P2 and N2 form the other inverter; the two inverters constitute a cross-coupled latch structure and form two storage nodes Q and QB for storing and holding data. N3 and N4 are respectively used as transmission pipes between bit lines BL and BLB and a storage node Q, QB; and further realizing the read-write operation of the stored data.

The 8T units formed by P1, P2 and N1-N6 are used as basic units for executing Boolean logic operation, wherein N5 and N6 form a decoupling read port for executing the Boolean logic operation. In the operation of Boolean logic operation, taking data pre-stored in a storage node Q as one operand; two-bit binary numbers representing the level states input to word lines RWL1 and RWL2 are encoded to form another operand. Finally, the operation results of three types of Boolean logic operation operations can be obtained by detecting the bit line voltages of the CBL and/or the RBL. Wherein, the operation result of the OR operation is represented by the bit line voltage of the CBL; representing the operation result of the OR operation by the bit line voltage of the RBL; the result of the exclusive nor operation is characterized by the bit line voltage common to both CBL and RBL.

As a further improvement of the present invention, the operation strategy of the 8T unit to perform the logical and operation is as follows:

(1) Pre-storing:

the first operand Q1 is written into the storage node Q in the data write mode, and then the bit lines BL, BLB are set high, WL is set low, and the data hold state is switched back. Wherein, when Q is high, Q1 is "1"; when Q is low, Q1 is "0".

(2) A pre-charging stage:

the bit line RBL is precharged to a high level.

(3) And (3) a calculation stage:

the second operand Q2 is first input through RWL2 and RWL 1. Wherein when RWL1 is high and RWL2 is low, Q2 is "1". When RWL1 and RWL2 are both high, Q2 is "0" is indicated.

Then, the level of the output bit line RBL is quantized; when RBL keeps high level, it indicates that the AND operation result Z1 is 0; when RBL falls to a low level, it indicates that AND operation result Z1 is "1".

As a further improvement of the present invention, the operation strategy of the 8T unit to perform a logical or operation is as follows:

(1) Pre-storing:

(2) A pre-charging stage:

the bit line RBL is precharged to a high level.

(3) And (3) a calculation stage:

the second operand Q2 is first input through RWL2 and RWL 1. Wherein, when RWL1 is high and RWL2 is low, Q2 is "0"; when RWL1 and RWL2 are both high, Q2 is "1".

Then, the level of the output bit line CBL is quantized; when CBL keeps high level, it shows OR operation result Z2 is 1; when CBL falls low, it indicates that and operation result Z2 is "0".

As a further improvement of the present invention, the operation strategy of the 8T unit to perform a logical exclusive nor operation is as follows:

(1) Pre-storing:

(2) A pre-charging stage:

the bit line CBL is precharged to a high level.

(3) And (3) a calculation stage:

Then, the levels of the bit lines RBL and CBL are outputted by quantization; when RBL and CBL are both low, the result Z3 of the OR operation is 0; when RBL and CBL are both high, it means that the OR operation result Z3 is "1".

The present invention includes a quantization circuit applied to the 8T cells of the same-side double bit lines, and further outputs the operation result corresponding to any one or more logic operation operations of "and", "or", "same or" according to the bit line voltages of the bit lines RBL and/or CBL.

Wherein the quantization circuit comprises three sense amplifiers SA1, SA2 and SA3. The positive input port of SA1 is connected with a reference voltage VREF1 in a normally high level state, the negative input port of SA1 is connected with a bit line RBL, and the output end Z1 of SA1 is used for outputting the operation result of logical AND operation. The negative input port of SA2 is connected with a reference voltage VREF2 in a normally high level state, the positive input port of SA2 is connected with a bit line CBL, and the output end Z2 of SA2 is used for outputting the operation result of logical OR operation. The negative input port of SA3 is connected with the output end Z1 of SA1, the positive input port of SA3 is connected with the output end Z2 of SA2, and the output end Z3 of SA3 is used for outputting the operation result of logical AND operation.

What needs to be specifically stated is: the outputs of Z1 and Z2 can be divided into two paths, one path is directly output, and the other path is used as the input of SA3. Thus, independent output of the results of different types of logic operations by SA1, SA2 and SA3 can be realized as required, or the different types of logic operations can be processed in parallel and synchronously output.

The invention also includes a logic circuit for implementing any one or more boolean logic operations of "and", "or", "same or" either alone or in parallel. The logic operation circuit includes an operation section and an operation output section.

Wherein the operation part comprises at least one 8T unit with the same side double bit line. When more than 1 8T cell is present, each 8T cell is arranged in a column and connected to the same set of bit lines BL, BLB, RBL and CBL, and each row of 8T cells is connected to a set of independent word lines WL, RWL1 and RWL2, respectively.

The arithmetic output section employs the quantization circuit described above. The quantization circuit comprises two input ends and three output ends, wherein the two input ends are respectively connected to bit lines RBL and CBL of the operation part, and the three output ends are respectively used as operation output ports for AND, OR, AND or OR logic operation.

The invention also comprises a coding circuit which is applied to the logic operation circuit; the encoding circuit is used as a front-end circuit for inputting operands required in AND, OR, AND or OR logic operation to the logic operation circuit. The coding circuit at least comprises three coding units, which are respectively: with the coding unit, or with the coding unit. Each coding unit comprises an input end and two output ends, the input end of the coding unit is used for receiving one operand of the logic operation, and the output end of the coding unit is used for inputting corresponding control signals to word lines RWL1 and RWL2 of the 8T unit according to the input operand and a preset coding rule.

Wherein, the coding rule with the coding unit is: (1) When the input operand is "1", the control signal output to RWL1 is high, and the control signal output to RWL2 is low. (2) When the input operand is "0", the control signals output to RWL1 and RWL2 are both high.

Or the coding rule of the coding unit is: (1) When the input operand is "0", the control signal output to RWL1 is low, and the control signal output to RWL2 is high. (2) When the input operand is "1", the control signals output to RWL1 and RWL2 are both low.

The coding rule of the same or coding unit is as follows: (1) When the input operand is "1", the control signal output to RWL1 is high, and the control signal output to RWL2 is low. (2) When the input operand is "0", the control signals output to RWL1 and RWL2 are both low.

The invention also comprises a memory circuit based on the 8T unit of the same side double bit line, which is a large-scale integrated circuit with a conventional SRAM memory function and a complex Boolean logic operation function. The memory circuit includes: the memory array, the word line group, the bit line group, the word line driver, the pre-charge circuit, the time sequence control module, the mode switching circuit, the coding circuit and the quantization output circuit.

The memory array is formed by arranging N multiplied by M double-bit-line 8T units on the same side in an array mode of N rows and M columns. The word line group includes three types of word lines WL, RWL1, and RWL2, and the number of each type of word line is N. Each 8T cell in the same row in the memory array is connected to the same set of word lines WL, RWL1, and RWL 2. The bit line group includes four types of bit lines BL, BLB, RBL and CBL, and the number of each bit line is M. All 8T cells in the same column in the memory array are connected to the same set of bit lines BL, BLB, RBL and CBL.

The word line driver is used to control the turn-on of the respective word lines WL, RWL1, and RWL 2. The precharge circuit is used for performing precharge operation on the designated bit line at different stages of performing data storage or logic operation. The timing control module is used for generating various clock signals required for executing data read-write holding operation or logic operation.

The mode switching circuit is used for switching the working mode of the memory circuit, and the working mode of the memory circuit comprises a data storage mode and a logic operation mode. The logical operation modes are classified into an AND operation mode, an OR operation mode, an AND operation mode and an OR operation mode.

The coding circuit adopts the scheme. The encoding circuit outputs corresponding control signals to the word lines RWL1 and RWL2 according to operands required to complete the operation in the logical operation mode.

The quantization output circuit includes a data reading section and an operation output section. The data reading section is connected to the bit lines BL and BLB for outputting the storage data of each storage node according to the level states of BL and BLB. The arithmetic output section employs the quantization circuit as described above and is connected to the bit lines RBL and CBL. The operation output part is used for outputting the operation result of the corresponding Boolean logic operation according to the bit line voltage of the bit lines RBL and/or CBL.

The invention also includes a CIM chip packaged by the memory circuit of the 8T unit based on the same side double-bit line.

The technical scheme provided by the invention has the following beneficial effects:

the invention utilizes the classical 8T SRAM circuit structure, combines and newly designs the input signal coding logic and the bit line voltage analog-to-digital conversion logic by adding special control word lines and the decoupling double bit lines on the same side, and simultaneously realizes the AND operation or the OR operation or the AND operation in the Boolean logic operation. Compared with the traditional decoupling 8T SRAM unit circuit with only a single Boolean logic operation function, the 8T unit SRAM with double bit lines on the same side can realize a plurality of different types of Boolean logic operations, supports synchronous execution of the plurality of different types of Boolean logic operations, and has more powerful functions.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:

fig. 1 is a circuit diagram of an 8T cell with double bit lines on the same side as that provided in embodiment 1 of the present invention.

Fig. 2 is a circuit diagram of a quantization circuit for an identical-side double-bit line 8T cell design provided in embodiment 2 of the present invention.

Fig. 3 is a circuit diagram of a logic operation circuit combining the 8T cell and quantization circuit designs of the double bit line on the same side in embodiment 3 of the present invention.

Fig. 4 is a functional block diagram of a logic operation circuit including an encoding circuit provided in embodiment 3 of the present invention.

Fig. 5 is a circuit diagram of an 8T cell memory circuit based on a double bit line on the same side according to embodiment 4 of the present invention.

Fig. 6 is a timing waveform diagram corresponding to each signal when the circuit of fig. 5 is simulated for and operation, or operation, and nor operation in a simulation experiment.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Example 1

The present embodiment provides an 8T cell with double bit lines on the same side, which is used as a basic functional unit of an SRAM circuit, and has a data read/write holding function and a boolean logic operation function. This type 8T cell supports separate or parallel operations of the and, or, co-or three types of boolean logic operations. As shown in fig. 1, the 8T unit is composed of 2 PMOS transistors P1 to P2 and 6 NMOS transistors N1 to N6, and the circuit connection relationship is as follows:

In the 8T cell including the double bit lines on the same side after the improvement of the embodiment, the 6T cell composed of P1, P2, N1 to N4 is used as the basic cell for executing the data read-write holding function. The circuit structure of the 6T unit formed by the six MOS tubes is a classical SRAM unit circuit. Wherein P1 and N1 form one inverter, and P2 and N2 form the other inverter; the two inverters constitute a cross-coupled latch structure and form two storage nodes Q and QB for storing and holding data. P1 and P2 are used as pull-up circuit structures in the writing operation; the NMOS transistors N1 and N2 serve as a pull-down circuit structure at the time of the write operation. N3 and N4 are respectively used as transmission pipes between bit lines BL and BLB and a storage node Q, QB; data read/write operations on the data stored in the storage node Q, QB can be implemented by using N3, N4 and BL, BLB.

Based on the classical 6T structure, 8T units formed by P1, P2 and N1-N6 are used as basic units for executing Boolean logic operation. Where N5 and N6 together constitute a decoupled read port that performs Boolean logic operations. When the 8T unit provided by the embodiment executes Boolean logic operation, the data pre-stored in the storage node Q is used as one operand; two-bit binary numbers representing the level states input to word lines RWL1 and RWL2 are encoded to form another operand. Finally, the operation results of three types of Boolean logic operation operations can be obtained by detecting the bit line voltages of the CBL and/or the RBL.

Specifically, in the 8T cell modified in this embodiment, the operation result of the or operation is characterized by the bit line voltage of the CBL; representing the operation result of the OR operation by the bit line voltage of the RBL; the result of the exclusive nor operation is characterized by the bit line voltage common to both CBL and RBL.

In order to make the scheme of the embodiment clearer, the advantages are more obvious, and the working principle and the operation method of the same-side double-bit-line 8T unit provided by the embodiment are respectively explained in detail in the following sequence of a data storage function and a logic operation function:

1. Data storage function

1. Data retention state

The operation principle of the same-side dual-bit line 8T memory cell in the data retention state of the present embodiment is as follows: setting two bit lines BL, BLB related to data read-write to high level; the word line WL is set to low so that the transfer transistors N3, N4 are turned off. Next, word line RWL2 for performing boolean logic operation in the decoupled read port is set high, turning off the paths of bit line CBL and bit line RBL to ground. Finally, word line RWL1 is set low, and bit line CBL and bit line RBL are isolated.

At this time, the storage nodes Q, QB of the 8T units store corresponding data, and the stored data is locked in a coupling structure formed by two inverters, thereby realizing data retention.

Meanwhile, in the data holding state, the storage node Q is electrically connected to the gate of N5 in the decoupled read port, so that the data stored in the storage node Q can be used as one of the operands required in the process of performing the boolean logic operation later.

2. Data read operation

The procedure for performing data reading operation on the same-side dual-bit line 8T memory cell provided in this embodiment is as follows: setting bit lines BL, BLB to high level and WL to high level, and then, NMOS transistors N3, N4 are in an on state; bit line BL and bit line BLB are electrically connected to storage node Q, QB within the 8T cell via NMOS transistors N3, N4, respectively; the storage node Q or QB causes the bit line BL or BLB to be electrically connected to VSS through transistors N1, N2 in the 8T cell, the bit line BL or BLB being discharged; the data stored in the storage node can be read out by taking the voltage drop of the bit line BL or BLB.

3. Data write operation

The procedure for performing the data writing operation of the 8T memory cell with double bit lines on the same side provided in this embodiment is as follows: first, the bit line BL or BLB is set to a corresponding high level or low level, respectively, according to the memory data to be written. Then, the word line WL is set to a high level. At this time, the NMOS transistors N3, N4 are in an on state; bit line BL and bit line BLB are electrically coupled to storage nodes Q and QB within the 8T cell via NMOS transistors N3, N4, respectively.

If the original data in Q or QB is "0" and the data to be written is "1", the storage node Q or QB in the 8T cell causes the bit line BL or the bit line BLB to be connected to the power supply VDD through P1, P2, and the storage node Q or QB in the 8T cell is written with a high level, i.e., data "1". If the original data in Q or QB is "1" and the data to be written is "0", the stored data Q or QB in the 8T cell causes the bit line BL or the bit line BLB to be electrically connected to the ground VSS through N1, N2, and the storage node Q or QB in the 8T cell is written with a low level, i.e., data "0".

2. Boolean logic function

In the dual-bit-line 8T memory cell of the present embodiment, the bit lines BL and BLB need to be set high and WL is set low when performing the boolean logic operation, so that the 8T cell is in the data retention state. At this time, the NMOS transistors N3, N4 are in an off state; the stored data Q in the SRAM is electrically connected to the gate of the NMOS transistor N5 in the decoupled read port. In this state, when the storage node Q in the 8T cell is high (i.e., the stored data is "1"), the NMOS transistor N5 in the decoupled read port is in an on state; when the storage node Q in the 8T cell is low (i.e., the stored data is "0"), the NMOS transistor N5 in the decoupled read port is in an off state.

In the same-side dual-bit 8T memory cell of this embodiment, word line RWL2 in the decoupled read port is electrically connected to the source of NMOS transistor N5. Thus, when the word line RWL2 is high, the decoupled read port is in an off state. When word line RWL2 is low, the decoupled read port is in an on state. In addition, the word line RWL1 in the decoupled read port is electrically connected to the gate of the NMOS transistor N6; thus, when the word line RWL1 is high, the NMOS transistor N6 in the decoupled read port is in an on state. When the word line RWL1 is low, the NMOS transistor N6 in the decoupled read port is in an off state. Further, when the NMOS transistor N6 in the decoupled read port is in an off state, the bit line CLB and the bit line RBL are in an isolated state. When the NMOS transistor N6 in the decoupled read port is in an on state, the bit line CLB and the bit line RBL are in a connected state.

Based on the above circuit operation principle, the present embodiment regards the data stored in the storage node Q as one of the operands in performing the boolean logic operation. Then, by a special encoding rule, a combination of different level states of the word lines RWL1 and RWL2 is used as another operand that can produce different outputs. The result of the boolean logic operation between the two operands may be presented via different level states of the bit lines CBL and/or RBL.

For ease of description, in the subsequent analysis of the different boolean logic operations, the data stored in storage node Q is collectively referred to as a first operand (OP 1), while the data commonly encoded by RWL1 and RWL2 is referred to as a second operand (OP 2).

4. AND operation

The operation strategy for performing logical and operation by the same-side double-bit line 8T cell provided in this embodiment is as follows:

(1) Pre-storing:

(2) A pre-charging stage:

the bit line RBL is precharged to a high level.

(3) And (3) a calculation stage:

When the 8T unit of the present embodiment performs a logical and operation, the original storage node Q is at a high level when the first operand is "1". At this time, if RWL1 is at high level and RWL2 is at low level, i.e., the second operand is "1", then N5 and N6 are both kept on, at this time, the bit line voltage of RBL will drop to low level, indicating that the operation result is "1", i.e., the following operation is implemented: 1and 1=1.

When the first operand is "1", the original storage node Q is high. At this time, if RWL 1and RWL2 are both high, i.e., the second operand is "0", the decoupled read port is in the off state; at this time, the bit line voltage of the RBL remains high, which indicates that the operation result is "0", that is, the following operation is implemented: 1and 0=0.

When the first operand is "0", the original storage node Q is low. At this time, no matter what level state RWL 1and RWL2 are, N5 is kept off, and at this time, the bit line voltage of RBL remains high, which indicates that the operation result is "0". Namely, the following operation is realized: 0and 1=0, and 0and 0=0.

Up to this point, the process of performing the logical and operation in this embodiment is completely error-free. The logic truth table statistics during the logical AND operation are as follows:

Table 1: logic truth table for performing AND operation on 8T units of double bit lines on the same side

5. OR operation

The operation strategy for performing logical or operation for the same-side dual-bit 8T cell provided in this embodiment is as follows:

(1) Pre-storing:

the first operand Q1 is written into the storage node Q in the data write mode, and then the bit lines BL, BLB are set high, WL is set low, and the data hold state is switched back. Wherein, when Q is low, Q1 is "1"; when Q is high, Q1 is "0".

(2) A pre-charging stage:

bit line CBL and bit line RBL are precharged to a high level.

(3) And (3) a calculation stage:

When the 8T unit of this embodiment performs a logical or operation, the original storage node Q is high when the first operand is "0". At this time, if RWL1 is at high level and RWL2 is at low level, i.e., the second operand is "0", then N5 and N6 are both kept on, at this time, the bit line voltage of CBL will drop to low level, indicating that the operation result is "0", i.e., the following operation is implemented: 0OR 0=0.

When the first operand is "0", the original storage node Q is high. At this time, if RWL1 and RWL2 are both high, i.e., the second operand is "1", the decoupled read port is in the off state; at this time, the bit line voltage of CBL remains high, which indicates that the operation result is "1", that is, the following operation is implemented: 0OR 1=1.

When the first operand is "1", the original storage node Q is low. At this time, no matter what level state RWL1 and RWL2 are, N5 is kept off, and at this time, the bit line voltage of CBL remains high, which indicates that the operation result is "1". Namely, the following operation is realized: 1 or0=1, and 1 or1=1.

Up to this point, the process of performing the logical or operation in this embodiment is completely error-free. The logic truth table statistics during a logical OR operation are as follows:

table 2: logic truth table for performing OR operation on 8T units of double bit lines on the same side

6. Exclusive nor operation

The operation strategy for performing logical or operation by the 8T cells of the same-side double bit line provided in this embodiment is as follows:

(1) Pre-storing:

(2) A pre-charging stage:

the bit lines RBL and CBL are precharged to a high level.

(3) And (3) a calculation stage:

Then, the level of the output bit line RBL and the level of the bit line CBL are quantized; when RBL is kept at a high level and CBL is kept at a high level, the calculation result Z1 is 0 and the calculation result Z2 is 1, which means that the AND operation result Z3 is 1; when the RBL falls to a low level and when the CBL remains to a low level, the calculation result Z1 is "1" and the calculation result Z2 is "0", meaning that the exclusive nor calculation result Z3 is "0".

When the 8T unit of this embodiment performs a logical exclusive nor operation, the original storage node Q is high when the first operand is "1". At this time, if RWL1 is at a high level and RWL2 is at a low level, i.e., the second operand is "0", then N5 and N6 are both kept in the on state, and at this time, the bit line voltage of RBL and the bit line voltage of CBL are reduced to a low level, and the calculation result Z1 is "1" and the calculation result Z2 is "0", which means that the exclusive nor calculation result Z3 is "0", i.e., the following operations are implemented: 1XNOR 0=0.

When the first operand is "1", the original storage node Q is high. At this time, if RWL1 and RWL2 are both high, i.e., the second operand is "1", the decoupled read port is in the off state; at this time, the bit line voltage of RBL and the bit line voltage of CBL both remain at high level, and the calculation result Z1 is "0" and the calculation result Z2 is "1", which means that the "exclusive nor" calculation result is "1", that is, the following operations are implemented: 1XNOR1 = 1.

When the first operand is "0", the original storage node Q is low. At this time, if RWL1 is high and RWL2 is low, i.e., the second operand is "0", the decoupled read port is in the off state; at this time, the bit line voltage of RBL and the bit line voltage of CBL both remain at high level, and the calculation result Z1 is "0" and the calculation result Z2 is "1", which means that the "exclusive nor" calculation result is "1", that is, the following operations are implemented: 0XNOR 0=1.

Wherein, when the first operand is "0", the second operand is "1", and the invalid state is defined. So far, the logic truth table statistics in the process of executing the logical AND operation in the embodiment are as follows:

table 3: logic truth table for performing exclusive nor operation on 8T cells of same-side double bit line

In summary, the two-bit line 8T cell on the same side provided in this embodiment can implement the and, or, and or logic operation in boolean logic operation independently or in parallel by combining the special codes of the word line signals RWL1 and RWL2 through a special circuit structure design. Compared with the traditional decoupling 8T SRAM unit circuit with a single Boolean logic operation function, the 8T unit with double bit lines on the same side can realize richer Boolean logic operation functions, support parallel processing of different types of Boolean logic operations in the same circuit, and have stronger logic operation performance.

Example 2

The present embodiment provides a quantization circuit designed mainly for the same-side double-bit line 8T cell in embodiment 1. The method mainly solves the problem of how to perform analog-to-digital conversion on the level states of the bit lines RBL and CBL so as to output corresponding AND operation, OR operation and the correlation of the operation results of the AND operation.

The quantization circuit designed by the embodiment has very ingenious structural design, and three kinds of operations can be synchronously output by only using the three sense amplifiers SA1, SA2 and SA 3. Specifically, as shown in fig. 2, the circuit connection relationship of this type of quantization circuit is as follows:

The positive input port of SA1 is connected with a reference voltage VREF1 in a normally high level state, the negative input port of SA1 is connected with a bit line RBL, and the output end Z1 of SA1 is used for outputting the operation result of logical AND operation. The negative input port of SA2 is connected with a reference voltage VREF2 in a normally high level state, the positive input port of SA2 is connected with a bit line CBL, and the output end Z2 of SA2 is used for outputting the operation result of logical OR operation. The negative input port of SA3 is connected with the output end Z1 of SA1, the positive input port of SA3 is connected with the output end Z2 of SA2, and the output end Z3 of SA3 is used for outputting the operation result of logical AND operation. In this embodiment, when the power supply is 1.2V, the reference voltage VREF1 and the reference voltage VREF2 are both set to 1V.

What needs to be specifically stated is: the outputs of Z1 and Z2 in the quantization circuit of this embodiment may be divided into two paths, one path is directly output, and the other path is used as the input of SA 3. Thus, the purposes of independently outputting the results of different types of logic operations by SA1, SA2 and SA3 or processing the different types of logic operations in parallel and synchronously outputting the results can be realized according to the needs.

Example 3

In combination with the solutions in embodiments 1 and 2, the present embodiment further provides a logic operation circuit for implementing any one or more boolean logic operation operations of "and", "or", "same or" alone or in parallel.

The logic operation circuit includes an operation section and an operation output section. Wherein the operation part includes at least one 8T cell of the same-side double bit line as in embodiment 1. When more than 1 8T cell is shown in fig. 3, the individual 8T cells are arranged in columns and connected to the same set of bit lines BL, BLB, RBL and CBL, and the individual 8T cells of each row are connected to a set of independent word lines WL, RWL1 and RWL2, respectively.

The arithmetic output section adopts the scheme of the quantization circuit provided in embodiment 2. The quantization circuit comprises two input ends and three output ends, wherein the two input ends are respectively connected to bit lines RBL and CBL of the operation part, and the three output ends are respectively used as operation output ports for AND, OR, AND or OR logic operation.

When the circuit is applied to execute logic operation, the method mainly comprises the following steps:

(1) An 8T unit is selected in which a first operand is pre-stored, or a corresponding second operand is pre-stored to a designated 8T unit.

(2) The bit lines RBL and CBL are precharged to a high level and then the encoded second operand is input to the 8T cell through the word lines RWL1 and RWL2.

(3) The bit line voltages of the bit lines RBL and CBL are sampled through a quantization circuit, mode conversion is completed, and the operation result of corresponding AND, OR, AND or OR logic operation is output.

Considering that the encoding rule of the second operand is complex when the logic operation circuit provided in the embodiment performs the operation, and that the "numerical value" of the second operand corresponding to the same two-bit binary code actually has a difference in different types of operation processes, the embodiment designs a special encoding circuit for the logic operation circuit.

As shown in fig. 4, the encoding circuit is mainly used in combination with the aforementioned logic operation circuit, and the encoding circuit is used as a pre-circuit for inputting the second operand required in the and, or logic operation to the logic operation circuit. The coding circuit provided in this embodiment includes at least three coding units, which are respectively: with the coding unit, or with the coding unit. Each coding unit comprises an input end and two output ends, the input end of the coding unit is used for receiving a second operand of the logic operation, and the output end of the coding unit is used for respectively inputting corresponding control signals to word lines RWL1 and RWL2 of the 8T unit according to a preset coding rule and the input second operand.

Or the coding rule of the coding unit is: (1) When the input operand is "0", the control signal output to RWL1 is high, and the control signal output to RWL2 is low. (2) When the input operand is "1", the control signals output to RWL1 and RWL2 are both high.

The coding rule of the same or coding unit is as follows: (1) When the input operand is "0", the control signal output to RWL1 is high, and the control signal output to RWL2 is low. (2) When the input operand is "1", the control signals output to RWL1 and RWL2 are both high.

Example 4

Based on the foregoing embodiments, the present embodiment further provides a memory circuit based on an 8T cell with double bit lines on the same side, which is a large scale integrated circuit with a conventional SRAM memory function and a complex boolean logic operation function. The integrated circuit includes a core memory array of 8T cells on the same side, double bit lines, and associated peripheral circuits.

As shown in fig. 5, according to the functional module division, the memory circuit provided in this embodiment includes: the memory array, the word line group, the bit line group, the word line driver, the pre-charge circuit, the time sequence control module, the mode switching circuit, the coding circuit and the quantization output circuit.

The memory array is formed by arranging N multiplied by M double-bit-line 8T units on the same side in an array mode of N rows and M columns. The word line group includes three types of word lines WL, RWL1, and RWL2, and the number of each type of word line is N. Each 8T cell in the same row in the memory array is connected to the same set of word lines WL, RWL1, and RWL 2. The word line WL is used to control the switching of the transmission pipes N3, N4 during data storage or logic operation. RWL1 and RWL2 are used as input ports for the second operand in the process of executing the logical operation task.

The bit line group includes four types of bit lines BL, BLB, RBL and CBL, and the number of each bit line is M. All 8T cells in the same column in the memory array are connected to the same set of bit lines BL, BLB, RBL and CBL. In the four types of bit lines, BL and BLB are used for performing read-write operation on the stored data in the storage node Q, QB, and RBL and CBL are used for outputting analog signals corresponding to operation results of various Boolean logic operations.

The quantization output circuit includes a data reading section and an operation output section. The data reading section is connected to the bit lines BL and BLB for outputting the storage data of each storage node according to the level states of BL and BLB. The operation output section adopts the quantization circuit as in embodiment 2 and is connected to the bit lines RBL and CBL. The operation output section is used for converting the bit line voltage of the bit line RBL and/or CBL into a digital quantity corresponding to the operation result of the Boolean logic operation.

In addition, it is to be noted that: in practical application, the memory circuit of the 8T cell with double bit lines on the same side in this embodiment may be further packaged into a CIM chip based on 9T1C-SRAM, and generated and sold as a chip.

Simulation experiment

To verify the effectiveness of the solution provided by the present invention, the present experiment simulates the integrated circuit design solution of example 4. The simulation conditions are as follows: the process library adopts a central international 65 nanometer process; corner: TT; temperature:27 ℃; VDD:1.2; the simulation cell array size is 32X1. The simulation process performs functional verification on the AND operation, OR operation, AND operation and OR operation respectively, and a time sequence waveform diagram of the verification process is shown in fig. 6.

From the signals in fig. 6, it can be derived that: the circuit designed by the embodiment successively completes AND operation, OR operation, AND operation and OR operation in Boolean logic operation, and compared with the existing various schemes, the memory circuit of the 8T unit based on the same-side double-bit line provided by the embodiment can realize various Boolean logic operation functions, and has stronger performance.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. An ipsilateral double-bit line 8T cell, characterized in that: the 8T unit is used as a basic functional unit of the SRAM circuit and has a data read-write maintaining function and a Boolean logic operation function, and the 8T unit supports independent or parallel operation of three Boolean logic operations of AND, OR, AND or OR; the 8T unit is composed of 2 PMOS tubes P1-P2 and 6 NMOS tubes N1-N6, and the circuit connection relation is as follows:

the sources of P1 and P2 are connected with a power supply VDD; the drains of P1, N1 and N3 are electrically connected with the gates of P2 and N2 and serve as a storage node Q; the drain electrodes of P2, N2 and N4 are electrically connected with the grid electrodes of P1, N1 and N5 and serve as an inverted storage node QB; the sources of N1 and N2 are grounded to GND; the grid electrodes of N3 and N4 are connected with word lines WL; n3 has its source connected to bit line BL; n4 has its source connected to bit line BLB; the drain electrode of N5 is connected with the source electrode of N6 and connected with a bit line CBL in parallel; the drain electrode of N6 is connected with a bit line RBL; the grid electrode of N6 is connected with a word line RWL1; n5 has its source connected to word line RWL2;

2. The ipsilateral double bit line 8T cell of claim 1, wherein: in the case of the 8T cell in question,

the 6T unit formed by P1, P2 and N1-N4 is used as a basic unit for executing the data read-write holding function; the 8T units formed by P1, P2 and N1-N6 are used together as basic units for executing Boolean logic operation, wherein N5 and N6 form a decoupling read port for executing the Boolean logic operation; in the operation of Boolean logic operation, taking data pre-stored in a storage node Q as one operand; encoding the two-bit binary numbers input to the level state representation on word lines RWL1 and RWL2 to form another operand; finally, representing the operation result of the OR operation through the bit line voltage of the CBL; representing the operation result of the OR operation by the bit line voltage of the RBL; the result of the exclusive nor operation is characterized by the bit line voltage common to both CBL and RBL.

3. The ipsilateral double bit line 8T cell of claim 2, wherein: the operation strategy of the 8T unit for executing the logical AND operation is as follows:

(1) Pre-storing:

writing a first operand Q1 into a storage node Q in a data writing mode, setting bit lines BL and BLB to be high level, setting WL to be low level, and switching back to a data holding state; wherein, when Q is high, Q1 is "1"; when Q is low, Q1 is "0";

(2) A pre-charging stage:

precharging the bit line RBL to a high level;

(3) And (3) a calculation stage:

inputting a second operand Q2 through RWL2 and RWL 1; wherein, when RWL1 is high and RWL2 is low, Q2 is "1"; when RWL1 and RWL2 are both high, Q2 is "0"; then, the level of the output bit line RBL is quantized; when RBL keeps high level, it indicates that the AND operation result Z1 is 0; when RBL falls to a low level, it indicates that AND operation result Z1 is "1".

4. The ipsilateral double bit line 8T cell of claim 2, wherein: the operation strategy of the 8T unit for executing the logical OR operation is as follows:

(1) Pre-storing:

(2) A pre-charging stage:

precharging the bit line RBL to a high level;

(3) And (3) a calculation stage:

inputting a second operand Q2 through RWL2 and RWL 1; wherein, when RWL1 is low and RWL2 is high, Q2 is "0"; when RWL1 and RWL2 are both low, Q2 is "1"; then, the level of the output bit line CBL is quantized; when CBL is kept high, the OR operation result Z2 is 0; when CBL falls to a low level, it indicates that and operation result Z2 is "1".

5. The ipsilateral double bit line 8T cell of claim 2, wherein: the operation strategy of the 8T unit for executing the logical AND operation is as follows:

(1) Pre-storing:

(2) A pre-charging stage:

precharging the bit line RBL to a high level;

(3) And (3) a calculation stage:

inputting a second operand Q2 through RWL2 and RWL 1; wherein, when RWL1 is high and RWL2 is low, Q2 is "1"; when RWL1 and RWL2 are both high, Q2 is "0"; then, the levels of the bit lines RBL and CBL are outputted by quantization; when RBL and CBL are both low, the result Z3 of the OR operation is 0; when RBL and CBL are both high, it means that the OR operation result Z3 is "1".

6. A quantization circuit applied to the 8T cell of the same-side double bit line as claimed in any one of claims 1 to 5, and further synchronously outputting an operation result corresponding to any one or more logic operation operations of "and", "or", "same or" according to the bit line voltage of the bit line RBL and/or CBL; the method is characterized in that:

the quantization circuit includes three sense amplifiers SA1, SA2, and SA3; the positive input port of the SA1 is connected with a reference voltage VREF1 in a normally high level state, the negative input port of the SA1 is connected with a bit line RBL, and the output end Z1 of the SA1 is used for outputting the operation result of logical AND operation; the negative input port of SA2 is connected with a reference voltage VREF2 in a normally high level state, the positive input port of SA2 is connected with a bit line CBL, and the output end Z2 of SA2 is used for outputting the operation result of logical OR operation; the negative input port of SA3 is connected with the output end Z1 of SA1, the positive input port of SA3 is connected with the output end Z2 of SA2, and the output end Z3 of SA3 is used for outputting the operation result of logical AND operation.

7. A logic circuit for implementing any one or more boolean logic operations of and, or, either alone or in parallel; the logic operation circuit includes:

An arithmetic section comprising at least one of the ipsilateral double bit line 8T cells as claimed in any one of claims 1 to 5; when more than 1 8T units are arranged, each 8T unit is arranged in columns and connected to the same group of bit lines BL, BLB, RBL and CBL, and each row of 8T units is connected with a group of independent word lines WL, RWL1 and RWL2 respectively;

an operation output section employing the quantization circuit according to claim 6; the quantization circuit comprises two input ends and three output ends, wherein the two input ends are respectively connected to bit lines RBL and CBL of the operation part, and the three output ends are respectively used as operation output ports for AND, OR, AND or OR logic operation.

8. An encoding circuit, which is applied to the logic operation circuit according to claim 7, wherein the encoding circuit is used as a front-end circuit for inputting operands required in AND, OR, AND or OR logic operations to the logic operation circuit; the coding circuit at least comprises three coding units, which are respectively: with coding unit, or coding unit, co-or coding unit: each coding unit comprises an input end and two output ends, wherein the input end of the coding unit is used for receiving one operand of logic operation, and the output end of the coding unit is used for inputting corresponding control signals to word lines RWL1 and RWL2 of the 8T unit according to a preset coding rule and the input operand;

The coding rule of the and coding unit is as follows: (1) When the input operand is '1', the control signal output to RWL1 is high level, and the control signal output to RWL2 is low level; (2) When the input operand is 0, the control signals output to RWL1 and RWL2 are both high level;

the coding rule of the or coding unit is as follows: (1) When the input operand is 0, the control signal output to RWL1 is low level, and the control signal output to RWL2 is high level; (2) When the input operand is '1', the control signals output to RWL1 and RWL2 are both low level;

the coding rule of the same or coding unit is as follows: (1) When the input operand is '1', the control signal output to RWL1 is high level, and the control signal output to RWL2 is low level; (2) When the input operand is "0", the control signals output to RWL1 and RWL2 are both low.

9. A memory circuit of an 8T cell based on a same-side double bit line, characterized in that: the integrated circuit is a large-scale integrated circuit with a conventional SRAM storage function and a complex Boolean logic operation function; the memory circuit includes:

a memory array, which is formed by arranging n×m double-bit-line 8T cells on the same side according to claim 1 in an array manner of N rows and M columns;

A word line group including three types of word lines WL, RWL1, and RWL2, the number of each type of word line being N; each 8T unit of the same row in the memory array is connected to the same group of word lines WL, RWL1 and RWL 2;

a bit line group including four types of bit lines BL, BLB, RBL and CBL, the number of each bit line being M; all 8T cells in the same column in the memory array are connected to the same set of bit lines BL, BLB, RBL and CBL;

a word line driver for controlling the turn-on of each of the word lines WL, RWL1, and RWL 2;

a precharge circuit for performing precharge operation on a specified bit line at different stages of performing data storage or logic operation;

a timing control module for generating respective clock signals required for performing a data read-write holding operation or a logic operation;

a mode switching circuit for switching an operation mode of the memory circuit, the operation mode of the memory circuit including a data storage mode and a logic operation mode; the logic operation modes are divided into an AND operation mode, an OR operation mode and a AND operation mode;

an encoding circuit employing the encoding circuit according to claim 8; the coding circuit outputs corresponding control signals to word lines RWL1 and RWL2 according to operands required to finish operation in a logic operation mode; and

A quantization output circuit including a data reading section and an operation output section; the data reading part is connected to bit lines BL and BLB and is used for outputting storage data of each storage node according to the level states of BL and BLB; the operation output section employs the quantization circuit according to claim 6, and is connected to the bit lines RBL and CBL; the operation output part is used for outputting the operation result of the corresponding Boolean logic operation according to the bit line voltage of the bit lines RBL and/or CBL.

10. A CIM chip, characterized in that: packaged with the memory circuit of the ipsilateral double-bit line-based 8T cell of claim 9.