CN217280038U

CN217280038U - Low-power consumption circuit suitable for SRAM

Info

Publication number: CN217280038U
Application number: CN202221003972.2U
Authority: CN
Inventors: 不公告发明人
Original assignee: Sichuan Chuang'an Microelectronics Co ltd
Current assignee: Sichuan Chuang'an Microelectronics Co ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-08-23
Anticipated expiration: 2032-04-27

Abstract

The utility model discloses a low power consumption circuit suitable for SRAM, comprising an SRAM memory array; an address decoding module; a read-write data processing module; a pre-charging module; an internal clock and control signal generation module; and the low-power consumption module outputs control signals to the address decoding module, the internal clock and control signal generating module and the read-write data processing module. The utility model has the advantages of through the low-power consumption mode, reducible leakage current that comes from between memory cell and the pre-charge circuit can make the pre-charge circuit stop work in order to reduce sensitive amplifier stand-by power consumption, can fix each module internal signal in order to reduce the consumption that the device upset action produced. Therefore, the standby power consumption of the SRAM circuit can be greatly reduced in the low power consumption mode.

Description

Low-power consumption circuit suitable for SRAM

Technical Field

The utility model relates to a SRAM circuit, concretely relates to low-power consumption circuit suitable for SRAM.

Background

Sram (static Random Access memory) sram, generally loses stored data after power is turned off. SRAM is the memory device with the fastest read/write speed at present, and is commonly used for the first-level buffer and the second-level buffer of a processor.

In order to meet the requirement of high-speed read-write characteristics of the SRAM, some modules in the conventional SRAM circuit structure are kept in a working state even in a circuit standby state, which results in high standby power consumption of the SRAM as a whole.

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to solve at least the above problems and to provide at least the advantages which will be described later.

An object of the utility model is to provide a low-power consumption circuit suitable for SRAM is for solving the too high problem of current SRAM circuit stand-by power consumption.

To achieve these objects and other advantages in accordance with the purpose of the invention, there is provided a low power consumption circuit for an SRAM, comprising:

the SRAM memory array is used for storing data;

the address decoding module is used for decoding, generating rows and columns and sending the rows and the columns to the SRAM memory array;

the read-write data processing module is used for outputting data in the SRAM memory array and transmitting the data to the SRAM memory array for storage;

the pre-charging module is used for pre-charging a data transmission line between the SRAM storage array and the read-write data processing module;

the internal clock and control signal generating module outputs control signals to the address decoding module, the read-write data processing module and the pre-charging module;

and the low-power consumption module outputs control signals to the address decoding module, the internal clock and control signal generating module and the read-write data processing module.

In one possible design, the address decoding module comprises a decoding and address saving module, an external decoding signal is connected to the decoding and address saving module through a not gate K1, a not gate K2 and a not gate K3 in sequence, and the output of the decoding and address saving module is connected to an SRAM memory array;

receiving signals sent by an internal clock and control signal generation module, wherein after the signals pass through a NOT gate K4, one path of the signals is connected to the negative electrode of a power supply of a NOT gate K3, and the other path of the signals passes through a NOT gate K5 and is connected to the positive electrode of the power supply of the NOT gate K3;

and receiving a signal sent by the low-power-consumption module, wherein after the signal passes through the NOT gate K6, one path of the signal is connected to the positive electrode of a power supply of the NOT gate K1, and the other path of the signal is connected to the negative electrode of the power supply of the NOT gate K1 through the NOT gate K7.

In one possible design, a disable circuit is arranged between the not gate K3 and the decoding and address saving module in parallel, the disable circuit includes a not gate K8 and a not gate K9, an input end of the not gate K8 is connected with the decoding and address saving module, an output end of the not gate K3 is connected to an output end of the not gate K9, a power supply anode of the not gate K9 is connected to an output end of the not gate K4, and a power supply cathode of the not gate K9 is connected to an output end of the not gate K5.

In one possible design, the decoding and address saving module respectively outputs a row selection signal and a column selection signal to the SRAM memory array, the row selection signal of the decoding and address saving module is connected to the SRAM memory array through an and gate U1, and an output terminal of an not gate K7 is connected to another input terminal of an and gate U1 after passing through an odd number of not gates; the column selection signal of the decoding and address saving module is connected to the SRAM memory array through an AND gate U2, and the output end of an NOT gate K7 is connected to the other input end of the AND gate U2 after passing through an odd number of NOT gates.

In one possible design, the pre-charging module includes a field effect switch PM1, a field effect switch PM2, and a field effect switch PM3, the sources of the field effect switch PM1 and the field effect switch PM2 are connected to the positive power supply VDD, the drain of the field effect switch PM1 is connected to the data transmission line BL on the read-write data processing module, the drain of the field effect switch PM2 is connected to the data transmission line BLB on the read-write data processing module, the source of the field effect switch PM3 is connected to the data transmission line BL, and the drain thereof is connected to the data transmission line BLB;

the control end of the internal clock and control signal generation module and the control end of the low-power consumption module are respectively connected with two input ends of an AND gate U3, and the output end of an AND gate U3 is connected with the gates of a field effect switch PM1, a field effect switch PM2 and a field effect switch PM 3;

the field effect switch PM4, the field effect switch PM5, the field effect switch PM6, the field effect switch PM7, the field effect switch NM8 and the field effect switch NM9 are further included, a source electrode of the field effect switch PM4 is connected to a power supply positive electrode VDD through the field effect switch PM6, a drain electrode of the field effect switch PM4 is connected to the data transmission line BL, and a grid electrode of the field effect switch PM is connected to the data transmission line BLB; a source electrode of the field effect switch PM5 is connected to the power supply positive electrode VDD via the field effect switch PM7, a drain electrode thereof is connected to the data transfer line BLB, and a gate electrode thereof is connected to the data transfer line BL; the source of the field effect switch NM8 is connected to the negative power VSS, the drain thereof is connected to the data line BL, the source of the field effect switch NM9 is connected to the negative power VSS, the drain thereof is connected to the data line BLB, and the gates of the field effect switch PM6, the field effect switch PM7, the field effect switch NM8 and the field effect switch NM9 are connected to the control terminal of the low power module through a not gate K10 to receive the control signal of the low power module.

In one possible design, the control terminal of the low power consumption module is connected to the and gate U3 through two series-connected not gates; the control end of the internal clock and control signal generation module is connected to an AND gate U3 through two series NOT gates; the not gate K10 is connected to the gates of the field effect switch NM8 and the field effect switch NM9 via two series connected not gates.

In one possible design, the internal clock and control signal generation module includes an internal pulse clock generation logic and a module control signal generation logic, the input terminal of the internal pulse clock generation logic is an external clock signal, the output terminal of the internal pulse clock generation logic is connected to one input terminal of the and gate U4, the other input terminal of the and gate U4 is connected to the preprocessing module through the signal processing logic, the output terminal of the and gate U4 is connected to the input terminal of the module control signal generation logic, and the outputs of the module control signal generation logic and the signal processing logic are both connected to the address decoding module through the and gate U5; the module control signal generation logic and the signal processing logic output are connected to the read-write data processing module through an AND gate U6; both the module control signal generation logic and the signal processing logic outputs are connected to the precharge module via and gate U7.

In one possible design, an even number of not gates in series are provided between the internal pulse clock generation logic and the module control signal generation logic.

In one possible design, the input of the internal pulse clock generation logic is provided with a signal amplifier; the input end of the signal processing logic is provided with a signal amplifier.

The utility model discloses at least, include following beneficial effect: the device is provided with low-power-consumption modules, and when the device is in standby, the circuit of each module is effectively controlled, and the power consumption is reduced mainly from the following aspects:

1. reducing the standby power consumption of the SRAM memory array: when a low power consumption control Signal (SLP) is effective, because the generation of an internal clock signal is interrupted, an address decoding module control signal cannot be generated, the address decoding module control signal is always kept in an invalid state, when the address signal reaches an address latch module, because the address latch module cannot enter a data transmission state according to the control signal, the address decoding cannot be carried out, an SRAM array for storing data cannot be selected, a data storage unit switch MOSFET cannot be started, an Nch inside the data storage module and a Pch for pre-charging cannot be started simultaneously, and the Leak current can be greatly reduced;

2. reduce precharge loop power consumption: when the low power consumption control Signal (SLP) is active, the precharge control signal is fixed to an inactive state in a standby state, the data transfer signal line BL/BLB precharge circuit is turned off, and the data transfer signal line (BLT/BLB) is fixed to a VSS potential. Because the two data transmission signal lines are fixed to the VSS, the sensitive amplifying circuit stops working, and the standby power consumption of the pre-charging circuit is effectively reduced.

3. The standby power consumption of the read-write data processing module is reduced: and controlling a data latch control signal LA in the read-write data processing module so as to control the data latch circuit to enter an invalid state, wherein data is fixed to 0 and is transmitted to an output port through the data latch module for data output because the data transmission signal lines BL/BLB are all at VSS potential. Because the control signals of the modules are fixed, the overturning action of the MOSFET can be effectively reduced, and the standby power consumption of the IO module is effectively reduced.

4. Reduce internal clock and control signal generation module power consumption: the SLP signal and the clock signal CLK are acted together to fix the internal clock signal in an invalid state, and the internal clock signal is fixed, so that the generation circuits, the sequential circuits and the like of the control signals of the other modules keep the original potential and do not perform the turning action.

In summary, in the low power mode, the leakage current between the memory cells and the precharge circuit can be reduced, the precharge circuit can be disabled to reduce the standby power consumption of the sense amplifier, and the internal signal of each block can be fixed to reduce the power consumption caused by the flip operation of the device. Therefore, the standby power consumption of the SRAM circuit can be greatly reduced in the low power consumption mode.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.

Drawings

FIG. 1 is a schematic block diagram of the present invention;

FIG. 2 is a schematic circuit diagram of an address decoding module;

FIG. 3 is a schematic circuit diagram of a pre-charge module;

FIG. 4 is a schematic circuit diagram of an internal clock and control signal generation module;

FIG. 5 is a schematic diagram of the circuit structure of the internal pulse clock generation logic;

FIG. 6 is a schematic diagram of a circuit configuration of the module control signal generation logic;

FIG. 7 is a schematic diagram of a circuit structure of a low power consumption control module;

FIG. 8 is a schematic structural diagram of an SRAM array;

FIG. 9 is a schematic circuit diagram of an SRAM cell;

FIG. 10 is a schematic diagram of a circuit structure of a read/write data processing unit;

FIG. 11 is a timing diagram of signals associated with the low power mode of the SRAM;

FIG. 12 is a logic truth table for SRAM signals;

FIG. 13 is a graph comparing the power consumption of the SRAM memory array in the low power mode with that in the normal mode;

fig. 14 is a graph comparing the whole standby power consumption of the SRAM in the low power consumption mode with that in the normal mode.

Detailed Description

The invention will be further described with reference to the accompanying drawings and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited to the description. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

Referring to fig. 1, a low power consumption circuit for SRAM includes:

the SRAM memory array is used for storing data;

the address decoding module is used for decoding, generating rows and columns and sending the rows and columns to the SRAM storage array;

The low-power consumption control module: and the functions of grading and delaying signals are realized. Realized by an inverter combination.

In the conventional SRAM, the internal clock and control signal generation block receives the external clock signal CLK, and generates the internal pulse clock signal CLK1 when the rising edge of the external clock signal comes. Control signals of the following respective blocks are generated through a series of logic circuits according to the internal pulse clock signal CLK 1:

CLKA address decoding module control signal

When the address decoding module control signal CLKA is effective (high level), the address decoding channel switch MOSFET is started, the address decoding module starts to work, a ROW selection signal (ROW) and a column selection signal (COL) for SRAM memory array address selection are generated, and a memory cell to be read/written is selected. When the address decoding module control signal CLKA is invalid (low level), the address decoding channel switch MOSFET is closed, and the address decoding module enters a standby state. The address selection ROW selection signal (ROW) and the column selection signal (COL) of the SRAM memory array are fixed and point to the SRAM memory cell which carries out the data reading and writing operation at the last time.

PRE precharge module control signal

When the PRE-charge module control signal PRE is active (low level), the PRE-charge circuit starts to work, and when the SRAM circuit does not perform data read/write operation, the data transmission signal line BL/BLB is pulled up to VDD to prepare for the next cycle of data read/write operation. When the PRE-charge module control signal PRE is invalid (high level), the PRE-charge circuit stops working, the data of the SRAM memory unit is transmitted to the read-write data processing module for storage through the data transmission signal line BL/BLB, or the data to be written stored in the read-write data processing module is transmitted to the appointed SRAM memory unit for storage through the data transmission signal line BL/BLB.

Read-write data processing module control signal LA

When the read-write data processing module control signal LA is effective (high level), the data latch unit switch in the read-write data processing module is closed, and data can be transmitted to the output port by the data processing module or transmitted to the SRAM storage unit by the data processing module for data storage. When the read-write data processing module control signal LA is invalid (low level), a data latch unit switch in the read-write data processing module is turned on, the data of the storage unit is locked, and the data is output to an output port for data output.

In a first aspect, the standby power consumption of the existing SRAM circuit is analyzed:

1. standby power consumption of the SRAM memory array:

in the normal mode, when data read-write operation is performed on a target memory cell according to an address selection signal in each period, each memory cell in the SRAM memory array has 3 states: neither COL nor ROW is selected; only ROW is selected; COL and ROW are both selected. During a cycle, both the COL and ROW are selected to have only one memory cell. However, the number of SRAM memory cells to be selected only ROW is different depending on the difference in SRAM capacity, and the larger the number of BITs (BIT number) of the SRAM, the larger the number of SRAM to be selected only ROW. For the memory cells only with the selected ROW, because the ROW is selected, the switch NFETs on the two sides of the memory cells are turned on, meanwhile, because the COLs are not selected, the pre-charging loop corresponding to the data transmission signal line BL/BLB is not turned off, and the NFETs and the PFETs are turned on simultaneously, so that larger leakage current is generated.

As shown in the leakage current diagram of the SRAM memory array, when PRE01 is at low level, PM1/PM2/PM3 is turned on, the channel connecting BL/BLB and VDD is turned on, and the potential of BL/BLB is pulled up to VDD. Due to the structural characteristics of the SRAM memory cell, one NFET of NM8/NM9 is turned on, and when ROW is high and NM6/NM7 is turned on, VDD → NM6 → NM9 → VSS or VDD → NM7 → NM8 → VSS channel is turned on, which generates a large amount of through current and has large standby power consumption.

2. Standby power consumption of the sense amplifier:

in the conventional SRAM structure, the high-capacity requirement of the SRAM is considered, a large number of repeated SRAM storage units exist in the design process of an SRAM circuit and a layout, and due to the fact that the size of a chip needs to be considered, the MOSFET size of an SRAM standard unit provided by each process manufacturer is small, and the driving capability is low. The voltage differential amplification of the BL/BLB by the sense amplifier must be added in the SRAM circuit design. Due to the characteristic that the sense amplifier needs to work in a saturation region, in order to ensure the sense amplifier to work normally, bias current needs to be provided for the sense amplifier all the time, and therefore the sense amplifier can generate a large amount of Leak current in a standby state.

3. Pre-charge loop standby power consumption

As described in the introduction of the PRE-charge module control signal, in the standby state of the SRAM circuit, in order to ensure fast reading and writing of data in the SRAM memory array, the PRE-charge circuit of the data transmission signal line BL/BLB is always in an operating state, and the potential of the data transmission signal line BL/BLB is maintained at VDD, which results in larger power consumption.

4. Standby power consumption of other modules

Other modules such as internal clock and control signal generation modules, address decoding modules, etc. generate less leakage current than the standby leakage current generated by the SRAM memory array and sense amplifier due to the smaller overall number.

In summary, the standby power consumption of the SRAM mainly comes from the standby power consumption generated by the SRAM memory array, the sense amplifier, and the precharge circuit, and in order to solve the problem of high static power consumption of the circuit, the design proposes to add a low power consumption mode control Signal (SLP) to the circuit to participate in the generation of part of the control signals, add a logic circuit for low power consumption control, and add a low power consumption mode to the circuit, thereby reducing the standby power consumption of the SRAM.

In a second aspect, the improvement is:

the device is mainly improved in that a low-power-consumption module is added, and the low-power-consumption module outputs a control signal to an internal clock and control signal generation module, a pre-charging module and an address decoding module; and the internal clock and control signal generation module, the pre-charge module and the address decoding module are improved correspondingly.

1. An address decoding module: the concrete structure is as follows:

as shown in fig. 2, the address decoding module includes a decoding and address saving module, the external decoding signal is connected to the decoding and address saving module through the not gate K1, the not gate K2 and the not gate K3 in sequence, and the output of the decoding and address saving module is connected to the SRAM memory array;

and receiving a signal sent by the low-power-consumption module, wherein after the signal passes through a NOT gate K6, one path of the signal is connected to the positive electrode of a power supply of a NOT gate K1, and the other path of the signal is connected to the negative electrode of the power supply of a NOT gate K1 through a NOT gate K7.

The device comprises a NOT gate K8, a NOT gate K9, a decoding and address saving module, a forbidding loop, a NOT gate K9, a NOT gate K4 and a NOT gate K5, wherein the forbidding loop is arranged between the NOT gate K3 and the decoding and address saving module in parallel and comprises the NOT gate K8 and the NOT gate K9, the input end of the NOT gate K8 is connected with the decoding and address saving module, the output end of the NOT gate K9 is connected to the output end of the NOT gate K3, the positive electrode of a power supply of the NOT gate K9 is connected to the output end of the NOT gate K4, and the negative electrode of the power supply of the NOT gate K9 is connected to the output end of the NOT gate K5.

The decoding and address saving module respectively outputs a row selection signal and a column selection signal to the SRAM memory array, the row selection signal of the decoding and address saving module is connected to the SRAM memory array through an AND gate U1, and the output end of a NOT gate K7 is connected to the other input end of the AND gate U1 after passing through an odd number of NOTs; the column selection signal of the decoding and address saving module is connected to the SRAM memory array through an AND gate U2, and the output end of an NOT gate K7 is connected to the other input end of the AND gate U2 after passing through an odd number of NOT gates. The decoding and address saving module is the prior art, and 2-4 decoders and latches (Latch) can be selected.

In the address decoding module, when the low power consumption mode control signal SLPA is active (low level), the TRINV2 is turned off, the output ROW selection signal ROW and the output column selection signal Col are fixed to low level, and the SRAM memory array cannot be selected. When the address decoding module low power consumption mode control signal SLPA is invalid (high level), the TRINV2 is turned on, and the SRAM circuit can normally perform read-write data operation. When the SLPA is low, the output signals (the row selection signal and the column selection signal) can be realized as a result of being low regardless of whether the address signal and the clock signal are high or low.

When the low power consumption mode control signal SLP is inactive (high level), the SLPA0 is fixed to high level, the SLPA1 is fixed to low level, and the TRINV2 is in a state of being always on. When CLKA is valid, TRINV0 and TRINV1 are closed, the input address signal is latched and simultaneously the address is transmitted to a decoding and address storing module to decode the input address signal to obtain a ROW selection signal ROW and a column selection signal COL so as to position the SRAM storage unit needing to be operated. When the low power mode control signal SLP is active (low level), the SLPA0 is fixed to low level, the SLPA1 is fixed to high level, the TRINV2 is turned off, and the address signal cannot be transmitted to the inside of the address decoding module. Meanwhile, because the SLPA2 is fixed to a low level, the ROW selection signal ROW and the column selection signal COL are both fixed to a low level, which can effectively reduce the standby power consumption of the address decoding module. Meanwhile, as the ROW selection signal ROW and the column selection signal COL are fixed to be low level, the switch NFETs of all the SRAM storage units are turned off, and data misoperation can be effectively avoided.

2. A pre-charging module:

as shown in fig. 3, the precharge module includes a field effect switch PM1, a field effect switch PM2, and a field effect switch PM3, the sources of the field effect switch PM1 and the field effect switch PM2 are both connected to the positive power supply VDD, the drain of the field effect switch PM1 is connected to the data transmission line BL on the read-write data processing module, the drain of the field effect switch PM2 is connected to the data transmission line BLB on the read-write data processing module, the source of the field effect switch PM3 is connected to the data transmission line BL, and the drain thereof is connected to the data transmission line BLB;

the field effect switch PM4, the field effect switch PM5, the field effect switch PM6, the field effect switch PM7, the field effect switch NM8 and the field effect switch NM9 are further included, a source electrode of the field effect switch PM4 is connected to a power supply positive electrode VDD through the field effect switch PM6, a drain electrode of the field effect switch PM4 is connected to the data transmission line BL, and a grid electrode of the field effect switch PM is connected to the data transmission line BLB; a source of the field effect switch PM5 is connected to the power supply positive electrode VDD via the field effect switch PM7, a drain thereof is connected to the data transfer line BLB, and a gate thereof is connected to the data transfer line BL; the source of the field effect switch NM8 is connected to the negative power VSS, the drain thereof is connected to the data line BL, the source of the field effect switch NM9 is connected to the negative power VSS, the drain thereof is connected to the data line BLB, and the gates of the field effect switch PM6, the field effect switch PM7, the field effect switch NM8 and the field effect switch NM9 are connected to the control terminal of the low power module through a not gate K10 to receive the control signal of the low power module.

The control end of the low-power consumption module is connected to an AND gate U3 through two series NOT gates; the control end of the internal clock and control signal generation module is connected to an AND gate U3 through two series NOT gates; the not gate K10 is connected to the gates of the field effect switch NM8 and the field effect switch NM9 via two series connected not gates. The inverter circuit has a transition region between high and low level transitions, i.e., between load stop and saturation, which is an amplification region (linear region), and the inverter can be used as an amplifier. Therefore, the NOT gate can amplify the signal and can play a role in enhancing the driving.

When the precharge module low power mode control signal SLPP is active (high level), the precharge circuit control signal PRE is fixed to the high level, the precharge circuit PFETs are turned off, and the precharge circuit does not operate. The data transmission signal line is fixed to a low level, the data transmission signal line BL/BLB high level maintaining circuit is closed, and the power consumption of the pre-charging loop is reduced.

When the low power mode control signal SLP is inactive (high level), the SLPP and SLPP0 are fixed at high level, the precharge module receives the precharge module control signal PRE generated by the internal clock and control signal generation module, and turns on the charging circuit when the circuit is not in operation. SLPP1 is fixed at low level, PM5/PM6 is started, and PM4/PM3 maintains high level signals in data transmission signal lines during circuit operation, so that stability of data read-write operation is effectively guaranteed, and the data read-write operation is accelerated. SLPP2 is fixed to high level, NM7/NM8 is in off state, and has no influence on data reading and writing. When the low power consumption mode control signal SLP is active (low level), the SLPP0 is fixed to the low level, the PRE01 is simultaneously fixed to the high level, the PM1/PM2/PM3 are turned off, and the precharge circuit is turned off. SLPP2 is fixed at high level, NM7/NM8 is turned on, and pulls down the data transfer signal line BL/BLB voltage to low level. The standby power consumption of the pre-charging circuit is effectively reduced. SLPP1 is fixed to high level, PM5/PM6 is turned off, the data transmission signal line is pulled down to low level, and PM4/PM3 are turned on but do not generate standby power consumption due to the floating of the source. When SLPP is low, PM1, PM2 and PM3 are completely turned off, PM6 and PM7 are also turned off, charging action is guaranteed to be inhibited, and BL and BLB are pulled to be low.

3. An internal clock and control signal generation module: the concrete structure is as follows:

as shown in fig. 4, the internal clock and control signal generation module includes an internal pulse clock generation logic and a module control signal generation logic, the input terminal of the internal pulse clock generation logic is an external clock signal, the output terminal of the internal pulse clock generation logic is connected to one input terminal of an and gate U4, the other input terminal of an and gate U4 is connected to the preprocessing module through a signal processing logic, the output terminal of an and gate U4 is connected to the input terminal of the module control signal generation logic, and the outputs of the module control signal generation logic and the signal processing logic are both connected to the address decoding module through an and gate U5; the module control signal generation logic and the signal processing logic output are both connected to the precharge module through an AND gate U6; the module control signal generation logic and signal processing logic outputs are both connected to the read-write data processing module via an and gate U7.

And an even number of NOT gates connected in series are arranged between the internal pulse clock generation logic and the module control signal generation logic. The input end of the internal pulse clock generating logic is provided with a signal amplifier; the input end of the signal processing logic is provided with a signal amplifier. The signal amplification here is also an even number of not gates connected in series, and the specific functions have been explained above and are not described in detail.

When the internal clock and control signal generation module low power consumption mode control signal SLPC is active (low level), the internal pulse clock generation related logic circuit is turned off, the internal clock signal is fixed to the low level, the clock pulse signal cannot be generated inside the circuit, the address decoding module control signal is fixed to the low level, the precharge module control signal is controlled to the high level, the SRAM circuit cannot operate, and the power consumption of the related module is reduced. When the internal clock and control signal generation module low power mode control signal SLPC is inactive (high level), the low power mode control signal SLPC does not affect generation of other signals.

When the low power mode control signal SLP is inactive (high level), the SRAM is in the normal operation mode, SLPE is high level, the internal clock CLK1 is determined only by the external input clock CLK, the control signals of the respective blocks can be generated normally, and the entire SRAM circuit can perform normal read/write operations. When the low power mode control signal SLP is inactive (low level), the SLP fixes the SLPE to a low level via the signal processing logic, and the internal clock CLK1 signal is fixed to a low level. The internal clock pulse cannot be generated, the subsequent module control signal generation signal maintains the original state, each signal is not inverted, and the internal circuit does not operate even if the external input clock signal CLK changes. Meanwhile, since the SLPE is fixed to a low level, the address decoding module control signal CLKA, the precharge module control signal PRE, and the read/write data processing module control signal LA are all controlled to be in an invalid state (low level), and the related circuits are turned off and cannot operate. The standby power consumption can be effectively reduced. When the SLPC is high level, the output signal can be low level as a result regardless of whether the chip select signal SEN and the clock signal are inverted or not.

As in fig. 4, the internal pulse clock generation logic circuit diagram structure is as in fig. 5; the circuit diagram structure of the module control signal generation logic is shown in FIG. 6; the signal processing logic employs a BUFFER register BUFFER, and a specific circuit configuration is not given here for the prior art.

4. The structure of the low power consumption control module is shown in fig. 7, and one input SLP signal is adopted to obtain three control signals, namely, SLPC, SLPA and SLPP, which are respectively input to the internal clock and control signal generation module, the address decoding module and the pre-charging module.

When the SLP is high, the SLPC, SLPA, and SLPP are all high, and when the SLP is low, the SLPC, SLPA, and SLPP are all low.

5. An SRAM memory array and a read/write data processing module, which are not specifically modified, are shown in fig. 8, and fig. 9 is a circuit structure diagram of the SRAM memory cell in fig. 8. The SRAM memory array is not described in detail in the prior art.

Fig. 10 shows a read/write data processing module, where Larch is a latch and BUFFER is a BUFFER register, which is not described in detail for the prior art. The read-write data processing module is the prior art and is not described in detail.

In summary, the timing diagram of the signals related to the low power mode of the SRAM is shown in FIG. 11;

when the SLP is a high level signal, an external clock signal is input, and the input of an address signal is invalid. And the SRAM is switched to a low power consumption mode when the read-write operation is not performed on the SRAM for a long time, so that the standby power consumption of the SRAM can be greatly reduced. The logic truth table of the SRAM signal is shown in FIG. 12.

Experiment: in the prior art, the whole circuit works in a high-speed state no matter whether the SRAM needs to read and write data or not, so that the power consumption is larger. The SRAM designed by the scheme can reduce standby power consumption as much as possible by entering the SRAM low power consumption mode when the system is in standby.

The design scheme based on the low power consumption mode can effectively reduce the standby power consumption of the SRAM memory array, and after the SRAM memory array enters the low power consumption mode, each memory unit does not act and does not have a state that PchNch is simultaneously started, so that only very low leakage current exists, the power consumption is close to 0, and the standby power consumption is greatly reduced. And (4) current comparison results obtained by simulation under the condition of maximum current. FIG. 13 is a graph comparing the power consumption of the SRAM memory array in the low power consumption mode with that in the normal mode;

because the power consumption of the SRAM memory array is the largest source of the overall power consumption of the SRAM, the overall power consumption of the SRAM is greatly improved after the power consumption of the SRAM memory array is greatly reduced. The current comparison result obtained by simulation under the condition of maximum current, as shown in fig. 14, is a comparison graph of the whole standby power consumption of the SRAM in the low power consumption mode and the normal mode.

While the embodiments of the invention have been described above, it is not intended to be limited to the details shown, or described, but rather to cover all modifications, which would come within the scope of the appended claims, and all changes which come within the meaning and range of equivalency of the art are therefore intended to be embraced therein.

Claims

1. A low power consumption circuit for an SRAM, comprising:

the SRAM memory array is used for storing data;

2. The circuit of claim 1, wherein the address decoding module comprises a decoding and address holding module, the external decoding signal is sequentially connected to the decoding and address holding module through a not gate K1, a not gate K2 and a not gate K3, and the output of the decoding and address holding module is connected to the SRAM memory array;

3. The circuit of claim 2, wherein a disable circuit is disposed between the not gate K3 and the decoding and address holding module in parallel, the disable circuit includes a not gate K8 and a not gate K9, an input terminal of the not gate K8 is connected to the decoding and address holding module, an output terminal of the not gate K8 is connected to an output terminal of the not gate K3 through the not gate K9, a power supply anode of the not gate K9 is connected to an output terminal of the not gate K4, and a power supply cathode of the not gate K9 is connected to an output terminal of the not gate K5.

4. The circuit of claim 2, wherein the decoding and address holding module outputs row selection signals and column selection signals to the SRAM memory array, respectively, the row selection signals of the decoding and address holding module are connected to the SRAM memory array through an and gate U1, and an output terminal of the not gate K7 is connected to another input terminal of the and gate U1 after passing through an odd number of not gates; the column selection signal of the decoding and address saving module is connected to the SRAM memory array through an AND gate U2, and the output end of an NOT gate K7 is connected to the other input end of the AND gate U2 after passing through an odd number of NOT gates.

5. The low power consumption circuit applicable to SRAM of claim 1, wherein the precharge module comprises a field effect switch PM1, a field effect switch PM2 and a field effect switch PM3, sources of the field effect switch PM1 and the field effect switch PM2 are connected to a positive power supply VDD, a drain of the field effect switch PM1 is connected to a data transmission line BL on the read-write data processing module, a drain of the field effect switch PM2 is connected to a data transmission line BLB on the read-write data processing module, a source of the field effect switch PM3 is connected to the data transmission line BL, and a drain thereof is connected to the data transmission line BLB;

6. The low power consumption circuit for SRAM as claimed in claim 5, wherein the control terminal of the low power consumption module is connected to AND gate U3 through two series-connected NOT gates; the control end of the internal clock and control signal generation module is connected to an AND gate U3 through two series-connected NOT gates; the not gate K10 is connected to the gates of the field effect switch NM8 and the field effect switch NM9 via two series connected not gates.

7. The low power consumption circuit of claim 1, wherein the internal clock and control signal generation block comprises an internal pulse clock generation logic and a block control signal generation logic, the internal pulse clock generation logic has an input terminal of an external clock signal and an output terminal connected to one input terminal of an and gate U4, the other input terminal of an and gate U4 is connected to the pre-processing block via a signal processing logic, the output terminal of an and gate U4 is connected to the input terminal of the block control signal generation logic, and both the block control signal generation logic and the signal processing logic output are connected to the address decoding block via an and gate U5; the output of the module control signal generation logic and the output of the signal processing logic are both connected to the read-write data processing module through an AND gate U6; both the module control signal generation logic and the signal processing logic outputs are connected to the precharge module via and gate U7.

8. The low power consumption circuit for SRAM of claim 7 wherein an even number of NOT gates in series are provided between said internal pulse clock generation logic and said module control signal generation logic.

9. The low power consumption circuit suitable for the SRAM of claim 7, wherein an input terminal of the internal pulse clock generation logic is provided with a signal amplifier; the input end of the signal processing logic is provided with a signal amplifier.