CN112036562B - Bit cell applied to memory computation and memory computation array device - Google Patents
Bit cell applied to memory computation and memory computation array device Download PDFInfo
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Abstract
The invention provides a bit cell applied to memory computing. The bit cell comprises: a four-pipe memory cell and a peripheral memory circuit; the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit. The invention has set up four-tube memory cell, apply it to the memory array module instead of six-tube memory cell, has simplified the structure of the array device of the memory calculation, the peripheral memory circuit of the invention is used for carrying on the operation of cumulative addition, utilize analog mixed signal capacitive coupling to calculate and finish the neural network cumulative operation of binary system, realize the input activation of 5 values, has improved the computational accuracy, and there is quiescent current to reduce the power consumption and capacitive coupling mechanism has better stability in the course of calculating. Therefore, the invention simplifies the storage and calculation array structure, reduces the power consumption and improves the storage and calculation efficiency and precision.
Description
Technical Field
The present invention relates to the field of memory computing technologies, and in particular, to a bit cell and a memory array device for memory computing.
Background
Deep Convolutional Neural Networks (DCNNs) continue to demonstrate improved inference accuracy, and Deep learning is shifting to edge computation. This development has driven the work of low-resource machine learning algorithms and their accelerated hardware. The most common operation in DCNNs is Multiplication and Accumulation (MAC), which controls power and delay. The MAC operation has high regularity and parallelism, and is therefore very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators.
The current memory array is basically based on six or more tubes of memory cells, and MAC operation is divided into current domain calculation based on a resistance divider, a discharge rate and the like and charge domain calculation based on charge sharing, a capacitance divider and the like. In contrast, charge domain calculation consumes less power due to the absence of quiescent current. And the six-tube structure has larger area and larger power consumption.
How to simplify the storage and calculation array structure, reduce power consumption and improve storage and calculation efficiency and precision becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a bit cell applied to memory computation and a memory computation array device, so as to simplify the memory computation array structure, reduce the power consumption and improve the memory computation efficiency and precision.
In order to achieve the purpose, the invention provides the following scheme:
a bit cell for application to memory computations, the bit cell comprising:
the four-tube storage unit and a peripheral memory circuit are used for carrying out accumulation addition operation on the activation signal and the weight value output by the four-tube storage unit;
the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit;
the word line control end of the four-tube storage unit is connected with a word line, the bit line control end of the four-tube storage unit is connected with a bit line, and the bit bar control end of the four-tube storage unit is connected with a bit bar;
a first activation signal input end of the peripheral memory circuit is connected with a first activation signal line, and a first deactivation signal input end of the peripheral memory circuit is connected with a first deactivation signal line;
a second activation signal input end of the peripheral memory circuit is connected with a second activation signal line, and a second deactivation signal input end of the peripheral memory circuit is connected with a second deactivation signal line;
and the signal output end of the peripheral memory circuit is connected with a signal output line.
Optionally, the four-transistor memory cell includes a transistor T1, a transistor T2, a transistor T3, and a transistor T4;
the input end of the transistor T1 and the input end of the transistor T2 are both connected with a power supply VDD, the output end of the transistor T1 is connected with the control end of the transistor T2, and the control end of the transistor T1 is connected with the output end of the transistor T2;
an input terminal of the transistor T3 is connected to the bit line BL, an output terminal of the transistor T3 is connected to the output terminal of the transistor T1, and a control terminal of the transistor T3 is connected to the word line WL;
the input terminal of the transistor T4 is connected to the inverted bit line BLB, the output terminal of the transistor T4 is connected to the output terminal of the transistor T2, and the control terminal of the transistor T4 is connected to the word line WL.
Optionally, the peripheral memory circuit includes a capacitor C1, a capacitor C2, a transistor T5, a transistor T6, a transistor T7, and a transistor T8;
an input terminal of the transistor T5 is connected to the first activation signal line MWL _ a, and an input terminal of the transistor T6 is connected to the first deactivation signal line MWLB _ a; the output terminal of the transistor T5, the output terminal of the transistor T6, and one end of the capacitor C1 are connected in common;
an input terminal of the transistor T7 is connected to the second activation signal line MWL _ b, and an input terminal of the transistor T8 is connected to the second deactivation signal line MWLB _ b; the output terminal of the transistor T7, the output terminal of the transistor T8, and one end of the capacitor C2 are connected in common;
the other end of the capacitor C1 is connected with the other end of the capacitor C2 and then is connected with a signal output line;
the control end of the transistor T5 and the control end of the transistor T7 are both connected with the weight output end of the four-tube memory cell;
the control terminal of the transistor T6 and the control terminal of the transistor T8 are both connected to the inverted value output terminal of the four-transistor memory cell.
A computing array device, the computing array device comprising:
the device comprises a storage array module, a column decoding module, a row decoding module, an input activation driving module and an analog-to-digital conversion output module; the memory array module comprises
Bit cells applied to memory computation;
the output ends of the n bit lines of the row decoding module are respectively connected with the n bit lines, and the output ends of the n bit reversal lines of the row decoding module are respectively connected with the n bit reversal lines;
the m word line output ends of the row decoding module are respectively connected with the m word lines;
the m first activation signal output ends of the storage array module are respectively connected with the m first activation signal lines, and the m first deactivation signal output ends of the storage array module are respectively connected with the m first deactivation signal lines; the m second activation signal output ends of the storage array module are respectively connected with the m second activation signal lines, and the m second deactivation signal output ends of the storage array module are respectively connected with the m second deactivation signal lines;
n analog signal input ends of the analog-to-digital conversion output module are respectively connected with n signal output lines;
word line control ends of bit cells in m rows of the storage array module are respectively connected with m word lines;
first activation signal input ends of m rows of bit units of the storage array module are respectively connected with m first activation signal lines, first flyback signal input ends of m rows of bit units of the storage array module are respectively connected with m first flyback signal lines, second activation signal input ends of m rows of bit units of the storage array module are respectively connected with m second activation signal lines, and second flyback signal input ends of m rows of bit units of the storage array module are respectively connected with m second flyback signal lines;
bit line control ends of the n rows of bit cells of the storage array module are respectively connected with the n bit lines, and inverted bit line control ends of the n rows of bit cells of the storage array module are respectively connected with the n inverted bit lines;
the signal output ends of the bit cells of the n rows of the memory array module are respectively connected with the n signal output lines.
Optionally, the bit cell comprises:
the four-tube storage unit and a peripheral memory circuit are used for carrying out accumulation addition operation on the activation signal and the weight value output by the four-tube storage unit;
the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit;
the word line control end of the four-tube storage unit is connected with a word line, the bit line control end of the four-tube storage unit is connected with a bit line, and the bit bar control end of the four-tube storage unit is connected with a bit bar;
a first activation signal input end of the peripheral memory circuit is connected with a first activation signal line, and a first deactivation signal input end of the peripheral memory circuit is connected with a first deactivation signal line;
a second activation signal input end of the peripheral memory circuit is connected with a second activation signal line, and a second deactivation signal input end of the peripheral memory circuit is connected with a second deactivation signal line;
and the signal output end of the peripheral memory circuit is connected with a signal output line.
Optionally, the four-transistor memory cell includes a transistor T1, a transistor T2, a transistor T3, and a transistor T4;
the input end of the transistor T1 and the input end of the transistor T2 are both connected with a power supply VDD, the output end of the transistor T1 is connected with the control end of the transistor T2, and the control end of the transistor T1 is connected with the output end of the transistor T2;
an input terminal of the transistor T3 is connected to the bit line BL, an output terminal of the transistor T3 is connected to the output terminal of the transistor T1, and a control terminal of the transistor T3 is connected to the word line WL;
the input terminal of the transistor T4 is connected to the inverted bit line BLB, the output terminal of the transistor T4 is connected to the output terminal of the transistor T2, and the control terminal of the transistor T4 is connected to the word line WL.
Optionally, the peripheral memory circuit includes a capacitor C1, a capacitor C2, a transistor T5, a transistor T6, a transistor T7, and a transistor T8;
an input terminal of the transistor T5 is connected to the first activation signal line MWL _ a, and an input terminal of the transistor T6 is connected to the first deactivation signal line MWLB _ a; the output terminal of the transistor T5, the output terminal of the transistor T6, and one end of the capacitor C1 are connected in common;
an input terminal of the transistor T7 is connected to the second activation signal line MWL _ b, and an input terminal of the transistor T8 is connected to the second deactivation signal line MWLB _ b; the output terminal of the transistor T7, the output terminal of the transistor T8, and one end of the capacitor C2 are connected in common;
the other end of the capacitor C1 is connected with the other end of the capacitor C2 and then is connected with a signal output line;
the control end of the transistor T5 and the control end of the transistor T7 are both connected with the weight output end of the four-tube memory cell;
the control terminal of the transistor T6 and the control terminal of the transistor T8 are both connected to the inverted value output terminal of the four-transistor memory cell.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a bit cell applied to memory calculation, which comprises: the four-tube storage unit and a peripheral memory circuit are used for carrying out accumulation addition operation on the activation signal and the weight value output by the four-tube storage unit; the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit. The invention has set up four-tube memory cell, apply it to the memory array module instead of six-tube memory cell, has simplified the structure of the array device of the memory calculation, the peripheral memory circuit of the invention is used for carrying on the operation of cumulative addition, utilize analog mixed signal capacitive coupling to calculate and finish the neural network cumulative operation of binary system, realize the input activation of 5 values, has improved the computational accuracy, and there is quiescent current to reduce the power consumption and capacitive coupling mechanism has better stability in the course of calculating. Therefore, the invention simplifies the storage and calculation array structure, reduces the power consumption and improves the storage and calculation efficiency and precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a circuit diagram of a bit cell for memory computation according to the present invention;
fig. 2 is a circuit diagram of a storage array apparatus provided in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a bit cell applied to memory computation and a memory computation array device, so as to simplify the memory computation array structure, reduce the power consumption and improve the memory computation efficiency and precision.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
As shown in FIG. 1, the present invention provides a bit cell for use in memory computing, the bit cell comprising: the four-tube storage unit and a peripheral memory circuit are used for carrying out accumulation addition operation on the activation signal and the weight value output by the four-tube storage unit; the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit; the word line control terminals (the control terminals of the transistor T3 and the transistor T4) of the four-transistor memory cell are connected with a word line WL, the bit line control terminal (the input terminal of the transistor T3) of the four-transistor memory cell is connected with a bit line BL, and the inverted bit line control terminal (the input terminal of the transistor T4) of the four-transistor memory cell is connected with an inverted bit line BLB; a first activation signal input terminal (input terminal of the transistor T5) of the peripheral saving circuit is connected to the first activation signal line MWL _ a, and a first deactivation signal input terminal (input terminal of the transistor T6) of the peripheral saving circuit is connected to the first deactivation signal line MWLB _ a; a second activation signal input terminal (input terminal of the transistor T7) of the peripheral saving circuit is connected to a second activation signal line MWL _ b, and a second deactivation signal input terminal (input terminal of the transistor T8) of the peripheral saving circuit is connected to a second deactivation signal line MWLB _ b; the signal output terminal of the peripheral memory circuit (the common terminal of the capacitor C1 and the capacitor C2) is connected to a signal output line.
Wherein the four-transistor memory cell comprises a transistor T1, a transistor T2, a transistor T3, and a transistor T4; the input end of the transistor T1 and the input end of the transistor T2 are both connected with a power supply VDD, the output end of the transistor T1 is connected with the control end of the transistor T2, and the control end of the transistor T1 is connected with the output end of the transistor T2; an input terminal of the transistor T3 is connected to the bit line BL, an output terminal of the transistor T3 is connected to the output terminal of the transistor T1, and a control terminal of the transistor T3 is connected to the word line WL; the input terminal of the transistor T4 is connected to the inverted bit line BLB, the output terminal of the transistor T4 is connected to the output terminal of the transistor T2, and the control terminal of the transistor T4 is connected to the word line WL.
The peripheral memory circuit comprises a capacitor C1, a capacitor C2, a transistor T5, a transistor T6, a transistor T7 and a transistor T8; an input terminal of the transistor T5 is connected to the first activation signal line MWL _ a, and an input terminal of the transistor T6 is connected to the first deactivation signal line MWLB _ a; the output terminal of the transistor T5, the output terminal of the transistor T6, and one end of the capacitor C1 are connected in common; an input terminal of the transistor T7 is connected to the second activation signal line MWL _ b, and an input terminal of the transistor T8 is connected to the second deactivation signal line MWLB _ b; the output terminal of the transistor T7, the output terminal of the transistor T8, and one end of the capacitor C2 are connected in common;
the other end of the capacitor C1 is connected with the other end of the capacitor C2 and then is connected with a signal output line; the control end of the transistor T5 and the control end of the transistor T7 are both connected with the weight output end of the four-tube memory cell; the control terminal of the transistor T6 and the control terminal of the transistor T8 are both connected to the inverted value output terminal of the four-transistor memory cell.
Specifically, as shown in fig. 1, the bit cell (Bitcell) is composed of a basic memory structure (four-transistor memory cell) of 4 transistors (T1, T2, T3, T4) with the addition of two capacitors (C1, C2) and peripheral memory circuits of four pass transistors (T5, T6, T7, T8).
In the bit unit, the capacitor C1 is charged and discharged after being gated by the activation signal line MWL _ a/MWLB _ a through the transistors T5 and T6, the capacitor C2 is charged and discharged after being gated by the activation signal line MWL _ b/MWLB _ b through the transistors T7 and T8, and the four transistors are selected to be conducted by the stored weight values (weight value Q and inverse weight value QB). Charge (one row at a time) is placed on the bit lines and shared by columns. bMAC is divided into two steps: the first step of precharging, in which MWL _ a (i), MWLB _ a (i), MWL _ b (i), MWLB _ b (i), MBL (i) are charged to VRST (middle level) at the same time, and there is no voltage potential on both sides of the capacitor; the second step is charging off, the input driver transmits an activation signal to mwl (i)/mwlb (i), and the result of the input activation being the same as or equal to the weight forms a voltage difference with MBL across the capacitor to generate charge accumulation on the bit line MBL. And the MBL outputs a result after analog-to-digital conversion is carried out through the ADC. The RST is a control signal, the gate of the MOS transistor connected to the VRST (intermediate level) is input, and the precharge and the charge shutdown are controlled by controlling the on/off of the MOS transistor connected to the VRST (intermediate level).
Table 1 is a multiply-accumulate operand table, in which the values of the Input (Input) are represented by combinations of high and low levels on four MWL lines (activation signal lines), and two numbers in each table in the bold frame at the lower right of table 1 represent voltages Vc1 and Vc2 applied to two capacitors. The 5-value Input (Input) improves the accuracy of the calculation very well.
Table 15 value input logic table
Example 2
The present invention also provides a storage array apparatus comprising:
the device comprises a storage array module, a column decoding module, a row decoding module, an input activation driving module and an analog-to-digital conversion output module; the memory array module comprises
Bit cells applied to memory computation; the output ends of the n bit lines of the row decoding module are respectively connected with the n bit lines, and the output ends of the n bit reversal lines of the row decoding module are respectively connected with the n bit reversal lines; the m word line output ends of the row decoding module are respectively connected with the m word lines; the m first activation signal output ends of the storage array module are respectively connected with the m first activation signal lines, and the m first deactivation signal output ends of the storage array module are respectively connected with the m first deactivation signal lines; the m second activation signal output ends of the storage array module are respectively connected with the m second activation signal lines, and the m second deactivation signal output ends of the storage array module are respectively connected with the m second deactivation signal lines; n analog signal input ends of the analog-to-digital conversion output module are respectively connected with n signal output lines; word line control ends of bit cells in m rows of the storage array module are respectively connected with m word lines; first activation signal input ends of m rows of bit units of the storage array module are respectively connected with m first activation signal lines, first flyback signal input ends of m rows of bit units of the storage array module are respectively connected with m first flyback signal lines, second activation signal input ends of m rows of bit units of the storage array module are respectively connected with m second activation signal lines, and second flyback signal input ends of m rows of bit units of the storage array module are respectively connected with m second flyback signal lines; bit line control ends of the n rows of bit cells of the storage array module are respectively connected with the n bit lines, and inverted bit line control ends of the n rows of bit cells of the storage array module are respectively connected with the n inverted bit lines; the signal output ends of the bit cells of the n rows of the memory array module are respectively connected with the n signal output lines.
The storage array device comprises a storage array module, a row decoding module, a column decoding module, an input activation driving module and an analog-to-digital conversion output module, wherein the row decoding module is used for row decoding in read-write operation (R/W) of a storage unit, the column decoding module is used for Address Decoder and R/W BL Control, and the input activation driving module and the analog-to-digital conversion output module are used for input activation driving (MWLDecoder/Driver) of a storage structure. The column decoding module acts on bit lines BL (i) and its inverse signals BLB (i), inputs and activates signals MWL _ a [ i ] and MWL _ b [ i ] and its inverse signals MWLB _ b [ i ], and outputs bit lines MBL (i) to analog-to-digital conversion output module (ADC) for output.
The bit line output MBL of a binary multiply accumulate (bMAC) operation for each column in a memory array module is the sum of a column multiply accumulate calculation, with analog signals on the MBL side, and the array contains one ADC per column in order to digitize these values.
The row decoding module decodes the address signal of the access data, and the column decoding module decodes the access data signal to realize the basic read-write operation of the data stored in the memory array.
The input activation driving module is used for transmitting an input activation signal, and the activation signal is operated with the data (namely the weight) stored in the storage array.
Analog-to-digital converter ADC performs analog-to-digital conversion on the multiply-accumulate bit line mbl (i) signal.
The structure and operation principle of the bit cell are the same as those of embodiment 1, and are not described herein again.
As shown in fig. 2, a row decoding module (c) outputs WL [ i ] signal to select a certain row of a storage array module (i) after decoding, a column decoding module (c) outputs BL [ i ] and BLB [ i ] to select a certain column of the storage array module (i), and the column decoding module (c) and the row decoding module (c) realize reading and writing of weight in a bit cell; the input activation driving module (IV) decodes the input activation signal and outputs 128 groups of MWL signals which are connected to each row of the array (IV); the output signal MBL [ i ] in the storage array module is connected to the analog-to-digital conversion output module (V), and the ADC in the corresponding column in the analog-to-digital conversion output module (V) completes the final result output.
The memory computing device is a structure proposed for a neural network, and the working principle of the memory computing device is to multiply and accumulate input activation and storage weight values in a storage unit. The weights are binarized to +1 and-1 in a Binary Neural Network (BNN), so that the multiplication can be represented by a simple exclusive-nor (XNOR) operation. The present invention relates to a memory computing device that performs binary multiply-accumulate (bMAC) using charge sharing.
As shown in fig. 2, the charge of the storage array device of the present invention (one row at a time) is placed on the bit lines and shared by columns. bMAC is divided into two steps: the first step of precharging, in which MWL _ a (i), MWLB _ a (i), MWL _ b (i), MWLB _ b (i), MBL (i) are charged to VRST (middle level) at the same time, and there is no voltage potential on both sides of the capacitor; the second step is charging off, the input driver transmits an activation signal to mwl (i)/mwlb (i), and the result of the input activation being the same as or equal to the weight forms a voltage difference with MBL across the capacitor to generate charge accumulation on the bit line MBL. And the MBL outputs a result after analog-to-digital conversion is carried out through the ADC.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a bit cell applied to memory calculation, which comprises: a four-pipe memory cell and a peripheral memory circuit; the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit. The storage array module in the storage array device adopts 4-tube units, so that the array structure is optimized, and the array area is reduced; 5-value input is activated, so that the calculation precision is improved; the calculation process of memory calculation is completed through a capacitive coupling charge domain, no static current is generated, power consumption is reduced, and a capacitive coupling mechanism has better stability. Therefore, compared with the prior art, the storage array device has smaller area, higher precision and better stability.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (5)
1. A bit cell for use in memory computing, the bit cell comprising:
the four-tube storage unit and a peripheral memory circuit are used for carrying out accumulation addition operation on the activation signal and the weight value output by the four-tube storage unit;
the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit;
the word line control end of the four-tube storage unit is connected with a word line, the bit line control end of the four-tube storage unit is connected with a bit line, and the bit bar control end of the four-tube storage unit is connected with a bit bar;
a first activation signal input end of the peripheral memory circuit is connected with a first activation signal line, and a first deactivation signal input end of the peripheral memory circuit is connected with a first deactivation signal line;
a second activation signal input end of the peripheral memory circuit is connected with a second activation signal line, and a second deactivation signal input end of the peripheral memory circuit is connected with a second deactivation signal line;
the signal output end of the peripheral memory circuit is connected with a signal output line;
the peripheral memory circuit comprises a capacitor C1, a capacitor C2, a transistor T5, a transistor T6, a transistor T7 and a transistor T8; an input terminal of the transistor T5 is connected to the first activation signal line MWL _ a, and an input terminal of the transistor T6 is connected to the first deactivation signal line MWLB _ a; the output terminal of the transistor T5, the output terminal of the transistor T6, and one end of the capacitor C1 are connected in common; an input terminal of the transistor T7 is connected to the second activation signal line MWL _ b, and an input terminal of the transistor T8 is connected to the second deactivation signal line MWLB _ b; the output terminal of the transistor T7, the output terminal of the transistor T8, and one end of the capacitor C2 are connected in common; the other end of the capacitor C1 is connected with the other end of the capacitor C2 and then is connected with a signal output line; the control end of the transistor T5 and the control end of the transistor T7 are both connected with the weight output end of the four-tube memory cell; the control terminal of the transistor T6 and the control terminal of the transistor T8 are both connected to the inverted value output terminal of the four-transistor memory cell.
2. The bitcell of claim 1, wherein the four-transistor memory cell comprises transistor T1, transistor T2, transistor T3 and transistor T4;
the input end of the transistor T1 and the input end of the transistor T2 are both connected with a power supply VDD, the output end of the transistor T1 is connected with the control end of the transistor T2, and the control end of the transistor T1 is connected with the output end of the transistor T2;
an input terminal of the transistor T3 is connected to the bit line BL, an output terminal of the transistor T3 is connected to the output terminal of the transistor T1, and a control terminal of the transistor T3 is connected to the word line WL;
the input terminal of the transistor T4 is connected to the inverted bit line BLB, the output terminal of the transistor T4 is connected to the output terminal of the transistor T2, and the control terminal of the transistor T4 is connected to the word line WL.
3. An inventory array arrangement, comprising:
the device comprises a storage array module, a column decoding module, a row decoding module, an input activation driving module and an analog-to-digital conversion output module; the memory array module comprises
Bit cells applied to memory computation;
the output ends of the n bit lines of the row decoding module are respectively connected with the n bit lines, and the output ends of the n bit reversal lines of the row decoding module are respectively connected with the n bit reversal lines;
the m word line output ends of the row decoding module are respectively connected with the m word lines;
the m first activation signal output ends of the storage array module are respectively connected with the m first activation signal lines, and the m first deactivation signal output ends of the storage array module are respectively connected with the m first deactivation signal lines; the m second activation signal output ends of the storage array module are respectively connected with the m second activation signal lines, and the m second deactivation signal output ends of the storage array module are respectively connected with the m second deactivation signal lines;
n analog signal input ends of the analog-to-digital conversion output module are respectively connected with n signal output lines;
word line control ends of bit cells in m rows of the storage array module are respectively connected with m word lines;
first activation signal input ends of m rows of bit units of the storage array module are respectively connected with m first activation signal lines, first flyback signal input ends of m rows of bit units of the storage array module are respectively connected with m first flyback signal lines, second activation signal input ends of m rows of bit units of the storage array module are respectively connected with m second activation signal lines, and second flyback signal input ends of m rows of bit units of the storage array module are respectively connected with m second flyback signal lines;
bit line control ends of the n rows of bit cells of the storage array module are respectively connected with the n bit lines, and inverted bit line control ends of the n rows of bit cells of the storage array module are respectively connected with the n inverted bit lines;
the signal output ends of the bit cells of n rows of the storage array module are respectively connected with n signal output lines;
peripheral memory circuitry of the bitcell comprising capacitor C1, capacitor C2, transistor T5, transistor T6, transistor T7 and transistor T8; an input terminal of the transistor T5 is connected to the first activation signal line MWL _ a, and an input terminal of the transistor T6 is connected to the first deactivation signal line MWLB _ a; the output terminal of the transistor T5, the output terminal of the transistor T6, and one end of the capacitor C1 are connected in common; an input terminal of the transistor T7 is connected to the second activation signal line MWL _ b, and an input terminal of the transistor T8 is connected to the second deactivation signal line MWLB _ b; the output terminal of the transistor T7, the output terminal of the transistor T8, and one end of the capacitor C2 are connected in common; the other end of the capacitor C1 is connected with the other end of the capacitor C2 and then is connected with a signal output line; the control end of the transistor T5 and the control end of the transistor T7 are both connected with the weight output end of the four-transistor storage unit of the bit unit; the control terminal of the transistor T6 and the control terminal of the transistor T8 are both connected to the inverted value output terminal of the quad-transistor memory cell of the bit cell.
4. The storage array apparatus of claim 3, wherein the bit cell comprises:
the four-tube storage unit and a peripheral memory circuit are used for carrying out accumulation addition operation on the activation signal and the weight value output by the four-tube storage unit;
the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the counter weight output end of the four-tube storage unit is connected with the counter weight input end of the four-tube storage unit;
the word line control end of the four-tube storage unit is connected with a word line, the bit line control end of the four-tube storage unit is connected with a bit line, and the bit bar control end of the four-tube storage unit is connected with a bit bar;
a first activation signal input end of the peripheral memory circuit is connected with a first activation signal line, and a first deactivation signal input end of the peripheral memory circuit is connected with a first deactivation signal line;
a second activation signal input end of the peripheral memory circuit is connected with a second activation signal line, and a second deactivation signal input end of the peripheral memory circuit is connected with a second deactivation signal line;
and the signal output end of the peripheral memory circuit is connected with a signal output line.
5. The memory array arrangement of claim 4, wherein the four-transistor memory cell comprises transistor T1, transistor T2, transistor T3, and transistor T4;
the input end of the transistor T1 and the input end of the transistor T2 are both connected with a power supply VDD, the output end of the transistor T1 is connected with the control end of the transistor T2, and the control end of the transistor T1 is connected with the output end of the transistor T2;
an input terminal of the transistor T3 is connected to the bit line BL, an output terminal of the transistor T3 is connected to the output terminal of the transistor T1, and a control terminal of the transistor T3 is connected to the word line WL;
the input terminal of the transistor T4 is connected to the inverted bit line BLB, the output terminal of the transistor T4 is connected to the output terminal of the transistor T2, and the control terminal of the transistor T4 is connected to the word line WL.
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| CN112558922A (en) * | 2021-02-20 | 2021-03-26 | 中科院微电子研究所南京智能技术研究院 | Four-transistor memory computing device based on separated word lines |
| CN112558919B (en) * | 2021-02-22 | 2021-05-18 | 中科院微电子研究所南京智能技术研究院 | Memory computing bit unit and memory computing device |
| CN113095496B (en) * | 2021-04-25 | 2022-07-15 | 山东大学 | Circuit and method for improving calculation precision of storage and calculation integrated array |
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