CN112232502B - Same or memory unit and memory array device - Google Patents
Same or memory unit and memory array device Download PDFInfo
- Publication number
- CN112232502B CN112232502B CN202011490153.0A CN202011490153A CN112232502B CN 112232502 B CN112232502 B CN 112232502B CN 202011490153 A CN202011490153 A CN 202011490153A CN 112232502 B CN112232502 B CN 112232502B
- Authority
- CN
- China
- Prior art keywords
- switch tube
- exclusive
- switch
- drain electrode
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
Abstract
The invention provides a same or storage and calculation unit, which comprises: an internal memory cell and an exclusive nor circuit; the bit line input end of the internal storage unit is connected with a bit line, the bit bar line input end of the internal storage unit is connected with a bit bar line, the word line input end of the internal storage unit is connected with a word line, and the weight end of the internal storage unit is connected with the control end of the exclusive nor circuit; the first input end of the exclusive OR operation circuit inputs an input signal, the second input end of the exclusive OR operation circuit inputs the opposite number of the input signal, and the output end of the exclusive OR operation circuit outputs the input signal and a signal obtained after exclusive OR operation is carried out on the weight. The 8-tube storage and calculation unit provided by the invention can realize exclusive OR operation, and meanwhile, the operation can be realized only by carrying out two-line coding on the input signal to obtain the input signal and the opposite number of the input signal, so that the difficulty of time sequence control is reduced.
Description
Technical Field
The present invention relates to the field of memory computing technologies, and in particular, to a peer-to-peer computing unit and a memory array device.
Background
The precision of Convolutional Neural Networks (CNNs) in large-scale recognition tasks is improved unprecedentedly. However, algorithm complexity and memory access limit the energy efficiency and acceleration speed of CNN hardware. To address this problem, in recent algorithms, weights and neuron activations are binarized to be either +1 or-1, making the multiplication between weights and input activations an exclusive-nor operation. The binary coding method makes the algorithm more suitable for being realized by a hardware circuit.
The conventional 8-tube structure sram only realizes the decoupling of input and output, but cannot realize an operation function, and an additional MAC circuit is required, so that an additional area is increased. The storage and calculation unit of the 12-transistor has a large area, and four lines are needed for encoding the input signal, so that the complexity of the input signal encoding module is increased, and the difficulty of the time sequence control of the input signal is also improved.
How to provide a memory cell with an exclusive nor operation function and small difficulty in timing control becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a same-or computing unit and a computing array device, and provides a computing unit with a same-or computing function and low time sequence control difficulty.
In order to achieve the purpose, the invention provides the following scheme:
a peer-to-peer or storage unit, the peer-to-peer or storage unit comprising:
an internal memory cell and an exclusive nor circuit;
the bit line input end of the internal storage unit is connected with a bit line, the bit bar line input end of the internal storage unit is connected with a bit bar line, the word line input end of the internal storage unit is connected with a word line, and the weight end of the internal storage unit is connected with the control end of the exclusive nor circuit;
the first input end of the exclusive OR operation circuit inputs an input signal, the second input end of the exclusive OR operation circuit inputs the opposite number of the input signal, and the output end of the exclusive OR operation circuit outputs the input signal and a signal obtained after exclusive OR operation is carried out on the weight.
Optionally, the exclusive nor operation circuit includes a switch tube T1 and a switch tube T2;
the gates of the switch tube T1 and the switch tube T2 are both used as the control end of the exclusive-nor operation circuit and connected with the weight end of the internal storage unit;
the source electrode of the switch tube T1 is used as the opposite number of the input signal of the second input end of the exclusive-nor operation circuit, the drain electrode of the switch tube T1 is connected with the source electrode of the switch tube T2 in a common point mode, and the connection point of the drain electrode of the switch tube T1 and the source electrode of the switch tube T2 is the output end of the exclusive-nor operation circuit;
the drain of the switch tube T2 is used as the first input end of the exclusive nor operation circuit to input the input signal.
Optionally, the switch transistor T1 is a PMOS transistor, and the switch transistor T2 is an NMOS transistor.
Optionally, the internal storage unit includes: a switching tube T3, a switching tube T4, a switching tube T5, a switching tube T6, a switching tube T7 and a switching tube T8;
the source electrode of the switch tube T3 is used as the bit line input end of the internal memory cell and is connected with the bit line, and the drain electrode of the switch tube T3 is connected with the drain electrode of the switch tube T5;
the source electrode of the switch tube T4 is used as the inverted bit line input end of the internal storage unit and is connected with the inverted bit line, and the drain electrode of the switch tube T4 is connected with the drain electrode of the switch tube T7;
the gates of the switch tube T3 and the switch tube T4 are used as the word line input end of the internal memory cell and are connected with the word line;
the source electrode of the switch tube T5 and the source electrode of the switch tube T7 are both connected with a power supply VDD; the drain electrode of the switch tube T5 is connected with the drain electrode of the switch tube T6 in a concurrent mode, and the connection point of the drain electrode of the switch tube T5 and the drain electrode of the switch tube T6 is used as a weight end of the internal storage unit;
the drain electrode of the switch tube T7 is connected with the drain electrode of the switch tube T8 in a concurrent manner, and the connection point of the drain electrode of the switch tube T7 and the drain electrode of the switch tube T8 is used as a weight-inversing value end of the internal storage unit;
the source electrode of the switch tube T6 and the source electrode of the switch tube T8 are both grounded;
the grid electrode of the switch tube T5 and the grid electrode of the switch tube T6 are both connected with the weight value end, and the grid electrode of the switch tube T7 and the grid electrode of the switch tube T8 are both connected with the weight value end.
Optionally, the switching tube T3, the switching tube T4, the switching tube T6, and the switching tube T8 are NMOS tubes, and the switching tube T5 and the switching tube T7 are PMOS tubes.
A memory array device, the memory array device comprises a memory array, a bit line control module, a word line control module, an input coding module and an ADC module;
the storage array comprises n multiplied by m exclusive OR storage units which are arranged in an array, and each exclusive OR storage unit comprises an internal storage unit and an exclusive OR operation circuit;
bit line input ends of the m rows of the internal storage units are respectively connected with m bit lines, and inverted bit line input ends of the m rows of the internal storage units are respectively connected with m inverted bit lines; the word line input ends of the internal storage units in the n rows are respectively connected with the n word lines;
the bit line control module is respectively connected with m bit lines and m bit bar lines, and the word line control module is respectively connected with n word lines; n signal output ends of the input coding module are respectively connected with first input ends of the n rows of internal storage units, and n inverted signal output ends of the input coding module are respectively connected with second input ends of the n rows of internal storage units;
and the output ends of the m columns of the exclusive OR operation circuits are respectively connected with m ADC modules.
Optionally, an enable switch tube is further disposed between the storage array and the ADC module.
Optionally, the exclusive nor operation circuit includes a switch tube T1 and a switch tube T2;
the gates of the switch tube T1 and the switch tube T2 are both used as the control end of the exclusive-nor operation circuit and connected with the weight end of the internal storage unit;
the source electrode of the switch tube T1 is used as the opposite number of the input signal of the second input end of the exclusive-nor operation circuit, the drain electrode of the switch tube T1 is connected with the source electrode of the switch tube T2 in a common point mode, and the connection point of the drain electrode of the switch tube T1 and the source electrode of the switch tube T2 is the output end of the exclusive-nor operation circuit;
the drain of the switch tube T2 is used as the first input end of the exclusive nor operation circuit to input the input signal.
Optionally, the internal storage unit includes: a switching tube T3, a switching tube T4, a switching tube T5, a switching tube T6, a switching tube T7 and a switching tube T8;
the source electrode of the switch tube T3 is used as the bit line input end of the internal memory cell and is connected with the bit line, and the drain electrode of the switch tube T3 is connected with the drain electrode of the switch tube T5;
the source electrode of the switch tube T4 is used as the inverted bit line input end of the internal storage unit and is connected with the inverted bit line, and the drain electrode of the switch tube T4 is connected with the drain electrode of the switch tube T7;
the gates of the switch tube T3 and the switch tube T4 are used as the word line input end of the internal memory cell and are connected with the word line;
the source electrode of the switch tube T5 and the source electrode of the switch tube T7 are both connected with a power supply VDD; the drain electrode of the switch tube T5 is connected with the drain electrode of the switch tube T6 in a concurrent mode, and the connection point of the drain electrode of the switch tube T5 and the drain electrode of the switch tube T6 is used as a weight end of the internal storage unit;
the drain electrode of the switch tube T7 is connected with the drain electrode of the switch tube T8 in a concurrent manner, and the connection point of the drain electrode of the switch tube T7 and the drain electrode of the switch tube T8 is used as a weight-inversing value end of the internal storage unit;
the source electrode of the switch tube T6 and the source electrode of the switch tube T8 are both grounded;
the grid electrode of the switch tube T5 and the grid electrode of the switch tube T6 are both connected with the weight value end, and the grid electrode of the switch tube T7 and the grid electrode of the switch tube T8 are both connected with the weight value end.
Optionally, the switching tube T2, the switching tube T3, the switching tube T4, the switching tube T6 and the switching tube T8 are NMOS tubes, and the switching tube T1, the switching tube T5 and the switching tube T7 are PMOS tubes.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a peer-to-peer or storage unit, comprising: an internal memory cell and an exclusive nor circuit; the bit line input end of the internal storage unit is connected with a bit line, the bit bar line input end of the internal storage unit is connected with a bit bar line, the word line input end of the internal storage unit is connected with a word line, and the weight end of the internal storage unit is connected with the control end of the exclusive nor circuit; the first input end of the exclusive OR operation circuit inputs an input signal, the second input end of the exclusive OR operation circuit inputs the opposite number of the input signal, and the output end of the exclusive OR operation circuit outputs the input signal and a signal obtained after exclusive OR operation is carried out on the weight. The 8-tube storage and calculation unit provided by the invention can realize exclusive OR operation, and meanwhile, the operation can be realized only by carrying out two-line coding on the input signal to obtain the input signal and the opposite number of the input signal, so that the difficulty of time sequence control is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a simplified circuit diagram of a XNOR cell according to the present invention;
FIG. 2 is a circuit diagram of a XNOR memory cell provided in the present invention;
fig. 3 is a circuit diagram of a storage array apparatus provided in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a same-or computing unit and a computing array device, and provides a computing unit with a same-or computing function and low time sequence control difficulty.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
As shown in fig. 1 and 2, the present invention provides a peer or storage unit, comprising: an internal memory cell and an exclusive nor circuit; the bit line input end of the internal storage unit is connected with a bit line BL, the bit bar line input end of the internal storage unit is connected with a bit bar line BLB, the word line input end of the internal storage unit is connected with a word line WL, and the weight end Q of the internal storage unit is connected with the control end P of the exclusive nor circuit; the first input end of the exclusive OR operation circuit inputs an input signal IN, the second input end of the exclusive OR operation circuit inputs an inverse number INB of the input signal, and the output end OUT of the exclusive OR operation circuit outputs a signal obtained by exclusive OR operation of the input signal and a weight.
The exclusive-nor operation circuit comprises a switch tube T1 and a switch tube T2; the gates of the switch tube T1 and the switch tube T2 are both used as the control end P of the exclusive-nor circuit and connected with the weight end Q of the internal storage unit; the source electrode of the switch tube T1 is used as the inverse number INB of the input signal of the second input end of the exclusive-nor operation circuit, the drain electrode of the switch tube T1 is connected with the source electrode of the switch tube T2 in a point-sharing manner, and the connection point of the drain electrode of the switch tube T1 and the source electrode of the switch tube T2 is the output end OUT of the exclusive-nor operation circuit; the drain of the switch tube T2 is used as the first input end of the exclusive nor operation circuit to input the input signal IN.
The internal storage unit includes: a switching tube T3, a switching tube T4, a switching tube T5, a switching tube T6, a switching tube T7 and a switching tube T8; the source electrode of the switch tube T3 is used as the bit line input end of the internal memory cell and is connected with the bit line BL, and the drain electrode of the switch tube T3 is connected with the drain electrode of the switch tube T5; the source electrode of the switch tube T4 is used as the inverted bit line input end of the internal storage unit and is connected with an inverted bit line BLB, and the drain electrode of the switch tube T4 is connected with the drain electrode of the switch tube T7; the gates of the switch tube T3 and the switch tube T4 are used as the word line input end of the internal memory cell and are connected with the word line WL; the source electrode of the switch tube T5 and the source electrode of the switch tube T7 are both connected with a power supply VDD; the drain electrode of the switch tube T5 is connected with the drain electrode of the switch tube T6 in a concurrent manner, and the connection point of the drain electrode of the switch tube T5 and the drain electrode of the switch tube T6 is used as a weight end Q of the internal storage unit; the drain of the switch tube T7 and the drain of the switch tube T8 are connected in common, and the connection point of the drain of the switch tube T7 and the drain of the switch tube T8 is used as the inversion value terminal of the internal memory cell
(ii) a The source electrode of the switch tube T6 and the source electrode of the switch tube T8 are both grounded GND; the grid of the switch tube T5 and the grid of the switch tube T6 are connected with the weight-inversing end
And the grid electrode of the switch tube T7 and the grid electrode of the switch tube T8 are both connected with the weight terminal Q.
The switch tube T2, the switch tube T3, the switch tube T4, the switch tube T6 and the switch tube T8 are NMOS tubes, and the switch tube T1, the switch tube T5 and the switch tube T7 are PMOS tubes.
The working principle is as follows: fig. 1 is a simplified schematic diagram, and fig. 2 is a schematic structural diagram. In fig. 2, a switch tube T3-a switch tube T8 form a common 6T sram memory cell, and a switch tube T5, a switch tube T6, a switch tube T7, and a switch tube T8 form two inverters connected end to form an internal memory cell. The ring structure realizes the storage of weight values in the weight end Q. The switch tube T3 and the switch tube T4 are pass tubes, which connect the bit line BL to the internal memory cell and realize the read/write controlled by the bit line. As shown in fig. 2, the gates of the switch transistor T1 and the switch transistor T2 are connected, and after connection, as can be seen from fig. 2, the switch transistor T2 has the same level as the control terminal P of the exclusive nor circuit, the drain of the switch transistor T2 is connected to the input signal NB, and the source of the switch transistor T1 is connected to the inverse INB of the input signal. The drain of the switch tube T1 is also connected to the source of the switch tube T2, and the connection point is used as the output terminal OUT of the exclusive nor circuit for outputting signals. And the exclusive OR operation circuit is responsible for carrying out exclusive OR operation on the input data and the weight value. The storage node Q (weight value end) of the 6Tsram is connected to the point P of the exclusive nor circuit (control end of the exclusive nor circuit), and controls the gates of the switch tube T1 and the switch tube T2. The exclusive nor operation is explained in conjunction with table 1.
TABLE 1 XORing List
In the circuit shown in fig. 2, if 1 represents +1 and 0 represents-1, it can be equivalent to the operation of multiplying the weight by the input.
When the weight value of the weight value terminal Q is 1, the switch tube T2 is turned on, the switch tube T1 is turned off, the input signal IN is output, when the weight value of Q is 0, the switch tube T1 is turned on, the switch tube T2 is turned off, and the inverse number INB of IN is output. This may correspond to an exclusive nor operation. When 1 in the circuit represents +1 and 0 represents-1, the multiplication relation of the two can be satisfied. This is also the unit that is needed in the memory computing chip and can be multiplied or XORed.
Example 2
As shown in fig. 3, the present invention also provides a storage array device, which includes a storage array, a bit line control module, a word line control module, an input encoding module, and an ADC module; the storage array comprises n multiplied by m exclusive OR storage units which are arranged in an array, and each exclusive OR storage unit comprises an internal storage unit and an exclusive OR operation circuit; bit line input ends of the m rows of the internal storage units are respectively connected with m bit lines, and inverted bit line input ends of the m rows of the internal storage units are respectively connected with m inverted bit lines; the word line input ends of the internal storage units in the n rows are respectively connected with the n word lines; the bit line control module is respectively connected with m bit lines and m bit bar lines, and the word line control module is respectively connected with n word lines; n signal output ends of the input coding module are respectively connected with first input ends of the n rows of internal storage units, and n inverted signal output ends of the input coding module are respectively connected with second input ends of the n rows of internal storage units; and the output ends of the m columns of the exclusive OR operation circuits are respectively connected with m ADC modules.
The overall size of the storage array is 32 rows and 8 columns, namely the value of n is 32, the value of m is 8, in practical application, the SRAM array can adopt four (or more) storage arrays with 32 rows and 8 columns, each storage array is one piece, namely four pieces, and the storage space of 1KB is realized. The 32 x 8 storage and calculation array is easy to generate, good in calculation effect and capable of achieving higher precision, and the array with larger size can be combined through multiplexing to achieve larger calculation amount.
And an enabling switch tube is also arranged between the storage and calculation array and the ADC module.
The internal memory cell and the exclusive nor circuit in embodiment 2 of the present invention are the internal memory cell and the exclusive nor circuit in embodiment 1, and the structure and principle thereof are not described herein again.
The working principle of the storage and calculation array device is as follows: fig. 3 illustrates the circuit structure of the memory array in the invention. Wherein the bit line control module (BL control module) is connected to all the bit line pairs BL and BLB, e.g., BL [0] and BLB [0] in fig. 3, and performs a corresponding precharge operation during read and write operations. All word lines WL are connected to a word line (e.g. WL [0], WL [1], WL [2] in FIG. 3) control module (WL control module) and control the gating of the corresponding row bit lines, giving an active high signal to the row that needs to be operated. The Input encoding module (Input module) encodes the Input signal and sends the Input signal to the memory array through the Input signal lines (Input signal lines such as IN 0, IN 1, IN 2 IN FIG. 3) and the inverse Input signal lines (inverse Input signal lines are the inverse of the Input signal on the Input signal lines, such as INB 0, INB 1, INB 2 IN FIG. 3) leading out from the module. The storage array performs an exclusive nor operation on the input signal and the weight value stored in the 6t sram cell (internal storage cell). The output OUT of the exclusive nor circuit is connected to an output line OL (e.g., OL [0] in fig. 3) so that the results of each column are superimposed, the result being a voltage signal that all pull-up and pull-down signals act together. And the bottom end of the OL [0] is connected with an NMOS tube as an enabling switch tube, the grid electrode of the NMOS tube is controlled by an enabling signal EN, and under the condition that the enabling switch tube receives the EN enabling signal, a calculation result passes through the NMOS tube (the enabling switch tube) and is transmitted to the ADC to be output as a digital signal result through analog-to-digital conversion.
The same or memory unit of the invention combines the multiplication memory array according to the mode of the figure, the input signal and the opposite number thereof are coded and input by an input module, and the reading and writing of the same or memory unit are realized by controlling two bit lines (BL, BLB) by a Word Line (WL). A word line control module for controlling the word line and the bit line is arranged in the peripheral circuit(WL control module) and a bit line control module (BL control module). The exclusive nor cells share one word line WL for each row and input the same input signal. Each column shares a pair of bit lines BL and BLB, and an output signal OUT of each column is superimposed on an output line OL (OL [0] in fig. 1)]) In the above, the pull-up and pull-down effects of the output signals of the same or storage units in all the columns are superposed into a voltage signal, and the superposed voltage signal is converted into a digital signal through an ADC for output. And the bottom end of each OL is provided with an NMOS tube which is gated by an EN signal, and the signal on the OL is output through the ADC under the condition that the EN signal is enabled,V ref the reference voltage applied when the ADC carries out analog-to-digital conversion.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the great advantage of this circuit is its small area. In order to realize storage and calculation, the traditional memory calculation unit is usually realized by applying 12 or more CMOS (complementary metal oxide semiconductor) tubes, the required calculation function is realized by applying 8 tubes, so that the power consumption of the circuit can be reduced by a simple circuit, and a more objective calculation amount energy ratio can be obtained.
Currently, the common 8-tube is usually based on a 6-tube structure to perform input and output port decoupling, and cannot realize an arithmetic function. The invention realizes the function of the exclusive-nor operation by adding only two MOS tubes (T1 and T2) to the traditional 6-tube sram memory cell. Compared with a 12-tube structure proposed by Shihui Yin in JSSC 2020, the circuit is simpler, an enabling tube of an operation unit is eliminated, and a row of uniform output enabling control is performed at the tail end of an output line instead. The exclusive nor operation is realized on a smaller area.
The exclusive OR operation corresponding relation of the exclusive OR memory unit is as follows:
1*1=1 -1*-1=1 1*-1=-1 -1*1=-1
1XNOR1=1 0XNOR0=1 1XNOR0=0 0XNOR1=0
wherein the symbol "XNOR" denotes an exclusive nor operation.
According to the above correspondence, if the circuit of the present invention uses 1 to represent +1 and 0 to represent-1, the circuit can also implement multiplication.
The invention provides a new memory computing unit applied to a CNN algorithm, so that a weight storage array can also perform exclusive OR operation with an input signal at the same time, and partial convolution operation is completed in the array. Therefore, the energy and the time delay consumed by the data transmission part are saved, and the power consumption of the circuit is reduced while the operation speed is improved. In the existing high-speed digital chip, the power consumption consumed by data transmission can account for about 90% of the whole power consumption, and meanwhile, the problems of delay, limited bandwidth and the like of data transmission also greatly restrict the further improvement of the operation speed of the chip. In the storage array consisting of the same or storage units provided by the invention, only two MOS (metal oxide semiconductor) tubes are added to each unit, and the same or calculation of the weight and the input is completed on the basis of not obviously increasing the area.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. An exclusive nor storage unit, comprising:
an internal memory cell and an exclusive nor circuit;
the bit line input end of the internal storage unit is connected with a bit line, the bit bar line input end of the internal storage unit is connected with a bit bar line, the word line input end of the internal storage unit is connected with a word line, and the weight end of the internal storage unit is connected with the control end of the exclusive nor circuit;
the first input end of the exclusive OR operation circuit inputs an input signal, the second input end of the exclusive OR operation circuit inputs the opposite number of the input signal, and the output end of the exclusive OR operation circuit outputs the input signal and a signal obtained after exclusive OR operation is carried out on a weight value;
the internal storage unit includes: a switching tube T3, a switching tube T4, a switching tube T5, a switching tube T6, a switching tube T7 and a switching tube T8; the source electrode of the switch tube T3 is used as the bit line input end of the internal memory cell and is connected with the bit line, and the drain electrode of the switch tube T3 is connected with the drain electrode of the switch tube T5; the source electrode of the switch tube T4 is used as the inverted bit line input end of the internal storage unit and is connected with the inverted bit line, and the drain electrode of the switch tube T4 is connected with the drain electrode of the switch tube T7; the gates of the switch tube T3 and the switch tube T4 are used as the word line input end of the internal memory cell and are connected with the word line; the source electrode of the switch tube T5 and the source electrode of the switch tube T7 are both connected with a power supply VDD; the drain electrode of the switch tube T5 is connected with the drain electrode of the switch tube T6 in a concurrent mode, and the connection point of the drain electrode of the switch tube T5 and the drain electrode of the switch tube T6 is used as a weight end of the internal storage unit; the drain electrode of the switch tube T7 is connected with the drain electrode of the switch tube T8 in a concurrent manner, and the connection point of the drain electrode of the switch tube T7 and the drain electrode of the switch tube T8 is used as a weight-inversing value end of the internal storage unit; the source electrode of the switch tube T6 and the source electrode of the switch tube T8 are both grounded; the grid electrode of the switch tube T5 and the grid electrode of the switch tube T6 are both connected with the weight value end, and the grid electrode of the switch tube T7 and the grid electrode of the switch tube T8 are both connected with the weight value end.
2. The exclusive-nor memory cell of claim 1, wherein the exclusive-nor operation circuit comprises a switch tube T1 and a switch tube T2;
the gates of the switch tube T1 and the switch tube T2 are both used as the control end of the exclusive-nor operation circuit and connected with the weight end of the internal storage unit;
the source electrode of the switch tube T1 is used as the opposite number of the input signal of the second input end of the exclusive-nor operation circuit, the drain electrode of the switch tube T1 is connected with the source electrode of the switch tube T2 in a common point mode, and the connection point of the drain electrode of the switch tube T1 and the source electrode of the switch tube T2 is the output end of the exclusive-nor operation circuit;
the drain of the switch tube T2 is used as the first input end of the exclusive nor operation circuit to input the input signal.
3. The NOR memory cell of claim 2 wherein the switch transistor T1 is a PMOS transistor and the switch transistor T2 is an NMOS transistor.
4. The XNOR memory cell of claim 1, wherein the switch transistor T3, the switch transistor T4, the switch transistor T6 and the switch transistor T8 are NMOS transistors, and the switch transistor T5 and the switch transistor T7 are PMOS transistors.
5. An inventory array device, comprising an inventory array, a bit line control module, a word line control module, an input encoding module, and an ADC module;
the storage array comprises n multiplied by m exclusive OR storage units which are arranged in an array, and each exclusive OR storage unit comprises an internal storage unit and an exclusive OR operation circuit;
bit line input ends of the m rows of the internal storage units are respectively connected with m bit lines, and inverted bit line input ends of the m rows of the internal storage units are respectively connected with m inverted bit lines; the word line input ends of the internal storage units in the n rows are respectively connected with the n word lines;
the bit line control module is respectively connected with m bit lines and m bit bar lines, and the word line control module is respectively connected with n word lines; n signal output ends of the input coding module are respectively connected with first input ends of the n rows of internal storage units, and n inverted signal output ends of the input coding module are respectively connected with second input ends of the n rows of internal storage units;
the output ends of the m rows of the exclusive OR operation circuits are respectively connected with m ADC modules;
the internal storage unit includes: a switching tube T3, a switching tube T4, a switching tube T5, a switching tube T6, a switching tube T7 and a switching tube T8; the source electrode of the switch tube T3 is used as the bit line input end of the internal memory cell and is connected with the bit line, and the drain electrode of the switch tube T3 is connected with the drain electrode of the switch tube T5; the source electrode of the switch tube T4 is used as the inverted bit line input end of the internal storage unit and is connected with the inverted bit line, and the drain electrode of the switch tube T4 is connected with the drain electrode of the switch tube T7; the gates of the switch tube T3 and the switch tube T4 are used as the word line input end of the internal memory cell and are connected with the word line; the source electrode of the switch tube T5 and the source electrode of the switch tube T7 are both connected with a power supply VDD; the drain electrode of the switch tube T5 is connected with the drain electrode of the switch tube T6 in a concurrent mode, and the connection point of the drain electrode of the switch tube T5 and the drain electrode of the switch tube T6 is used as a weight end of the internal storage unit; the drain electrode of the switch tube T7 is connected with the drain electrode of the switch tube T8 in a concurrent manner, and the connection point of the drain electrode of the switch tube T7 and the drain electrode of the switch tube T8 is used as a weight-inversing value end of the internal storage unit; the source electrode of the switch tube T6 and the source electrode of the switch tube T8 are both grounded; the grid electrode of the switch tube T5 and the grid electrode of the switch tube T6 are both connected with the weight value end, and the grid electrode of the switch tube T7 and the grid electrode of the switch tube T8 are both connected with the weight value end.
6. The array device of claim 5, wherein an enable switch is further disposed between the array and the ADC module.
7. The storage and computation array device of claim 5, wherein the XNOR circuit comprises a switch transistor T1 and a switch transistor T2;
the gates of the switch tube T1 and the switch tube T2 are both used as the control end of the exclusive-nor operation circuit and connected with the weight end of the internal storage unit;
the source electrode of the switch tube T1 is used as the opposite number of the input signal of the second input end of the exclusive-nor operation circuit, the drain electrode of the switch tube T1 is connected with the source electrode of the switch tube T2 in a common point mode, and the connection point of the drain electrode of the switch tube T1 and the source electrode of the switch tube T2 is the output end of the exclusive-nor operation circuit;
the drain of the switch tube T2 is used as the first input end of the exclusive nor operation circuit to input the input signal.
8. The memory-computing array device of claim 5, wherein the switch transistor T2, the switch transistor T3, the switch transistor T4, the switch transistor T6 and the switch transistor T8 are NMOS transistors, and the switch transistor T1, the switch transistor T5 and the switch transistor T7 are PMOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011490153.0A CN112232502B (en) | 2020-12-17 | 2020-12-17 | Same or memory unit and memory array device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011490153.0A CN112232502B (en) | 2020-12-17 | 2020-12-17 | Same or memory unit and memory array device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112232502A CN112232502A (en) | 2021-01-15 |
| CN112232502B true CN112232502B (en) | 2021-03-23 |
Family
ID=74124176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011490153.0A Active CN112232502B (en) | 2020-12-17 | 2020-12-17 | Same or memory unit and memory array device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112232502B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI776645B (en) * | 2021-03-17 | 2022-09-01 | 神盾股份有限公司 | Sum-of-products calculation apparatus |
| CN113642706A (en) * | 2021-08-10 | 2021-11-12 | 中国科学院上海微系统与信息技术研究所 | Neuron network unit, convolution operation module and convolution neural network |
| CN115660057B (en) * | 2022-12-13 | 2023-05-12 | 至讯创新科技(无锡)有限公司 | Control method for realizing convolution operation of NAND flash memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111816234A (en) * | 2020-07-30 | 2020-10-23 | 中科院微电子研究所南京智能技术研究院 | Voltage accumulation memory computing circuit based on SRAM bit line union |
| CN112036562A (en) * | 2020-11-05 | 2020-12-04 | 中科院微电子研究所南京智能技术研究院 | Bit cell applied to memory computation and memory computation array device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212089B1 (en) * | 1996-03-19 | 2001-04-03 | Hitachi, Ltd. | Semiconductor memory device and defect remedying method thereof |
| US5217917A (en) * | 1990-03-20 | 1993-06-08 | Hitachi, Ltd. | Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor |
-
2020
- 2020-12-17 CN CN202011490153.0A patent/CN112232502B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111816234A (en) * | 2020-07-30 | 2020-10-23 | 中科院微电子研究所南京智能技术研究院 | Voltage accumulation memory computing circuit based on SRAM bit line union |
| CN112036562A (en) * | 2020-11-05 | 2020-12-04 | 中科院微电子研究所南京智能技术研究院 | Bit cell applied to memory computation and memory computation array device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112232502A (en) | 2021-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112232502B (en) | Same or memory unit and memory array device | |
| Chen et al. | A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors | |
| CN112151091B (en) | 8T SRAM unit and memory computing device | |
| CN111816231B (en) | Memory computing device with double-6T SRAM structure | |
| CN112992223B (en) | Memory computing unit, memory computing array and memory computing device | |
| US10636481B1 (en) | Memory cell for computing-in-memory applications, memory unit for computing-in-memory applications and computing method thereof | |
| CN113255904B (en) | Voltage margin enhanced capacitive coupling storage integrated unit, subarray and device | |
| CN113035251B (en) | Digital memory computing array device | |
| CN112558919B (en) | Memory computing bit unit and memory computing device | |
| CN111816234A (en) | Voltage accumulation memory computing circuit based on SRAM bit line union | |
| CN112036562B (en) | Bit cell applied to memory computation and memory computation array device | |
| CN114089950B (en) | Multi-bit multiply-accumulate operation unit and in-memory calculation device | |
| CN113257306B (en) | Storage and calculation integrated array and accelerating device based on static random access memory | |
| CN117271436B (en) | SRAM-based current mirror complementary in-memory calculation macro circuit and chip | |
| CN113823343B (en) | Separated computing device based on 6T-SRAM | |
| CN113593618A (en) | Storage and calculation integrated storage array structure suitable for differential SRAM storage unit | |
| Zhang et al. | A 55nm, 0.4 V 5526-TOPS/W compute-in-memory binarized CNN accelerator for AIoT applications | |
| CN114300012B (en) | Decoupling SRAM memory computing device | |
| CN114627930A (en) | Single-bit differential SRAM (static random Access memory) storage and calculation integrated array and device | |
| US10410690B1 (en) | Reference-free multi-level sensing circuit for computing-in-memory applications, reference-free memory unit for computing-in-memory applications and sensing method thereof | |
| Sehgal et al. | Trends in analog and digital intensive compute-in-SRAM designs | |
| CN112233712B (en) | 6T SRAM (static random Access memory) storage device, storage system and storage method | |
| CN112558922A (en) | Four-transistor memory computing device based on separated word lines | |
| JP3731046B2 (en) | Semiconductor associative memory | |
| CN114895869B (en) | Multi-bit memory computing device with symbols |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 5 / F, building 1, Qilin artificial intelligence Industrial Park, 266 Chuangyan Road, Jiangning District, Nanjing City, Jiangsu Province Patentee after: Zhongke Nanjing Intelligent Technology Research Institute Address before: 5 / F, building 1, Qilin artificial intelligence Industrial Park, 266 Chuangyan Road, Jiangning District, Nanjing City, Jiangsu Province Patentee before: Nanjing Institute of intelligent technology, Institute of microelectronics, Chinese Academy of Sciences |