CN114089950B - Multi-bit multiply-accumulate operation unit and in-memory calculation device - Google Patents
Multi-bit multiply-accumulate operation unit and in-memory calculation device Download PDFInfo
- Publication number
- CN114089950B CN114089950B CN202210062863.6A CN202210062863A CN114089950B CN 114089950 B CN114089950 B CN 114089950B CN 202210062863 A CN202210062863 A CN 202210062863A CN 114089950 B CN114089950 B CN 114089950B
- Authority
- CN
- China
- Prior art keywords
- switching tube
- multiply
- switch tube
- bit
- accumulate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/5235—Multiplying only using indirect methods, e.g. quarter square method, via logarithmic domain
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
Abstract
The invention relates to a multi-bit multiply-accumulate operation unit and a memory computing device, wherein the multi-bit multiply-accumulate operation unit comprises: m columns of memory computing units; each column of the memory computing units comprises N memory computing subunits; each memory computing subunit comprises a 6T-SRAM storage unit, a switch tube M7 and a switch tube M8; the first end of the switch tube M7 is connected with the storage unit, the second end of the switch tube M7 is connected with the common end, the third end of the switch tube M7 is connected with the second end of the switch tube M8, the first end of the switch tube M8 is used for inputting a pulse signal, and the third end of the switch tube M8 is used for outputting a read bit line signal. In the multiply-accumulate operation, the invention avoids the influence of read-write interference by additionally adding the switching tubes M7 and M8.
Description
Technical Field
The present invention relates to the field of in-memory computing technologies, and in particular, to a multi-bit multiply-accumulate arithmetic unit and an in-memory computing device.
Background
Deep Convolutional Neural Networks (DCNNs) are rapidly developed in the fields of artificial intelligence and the like, and along with the gradual development of the DCNNs, the problems in the aspects of size, efficiency, energy consumption and the like need to be considered more and more. In the conventional calculation process, the weights are moved between the memory and the arithmetic unit, which is not in accordance with the requirement of low power consumption. Memory Computing (IMC) is increasingly attractive to DCNN acceleration, and conventional memory computing units mostly use voltage or level for computing, and have the problems of read-write interference and low precision due to more single-bit computation.
Disclosure of Invention
The invention aims to provide a multi-bit multiply-accumulate operation unit and a memory computing device, so as to avoid the problem of read-write interference.
To achieve the above object, the present invention provides a multi-bit multiply-accumulate operation unit, comprising:
m columns of memory computing units; each column of the memory computing units comprises N memory computing subunits; wherein M and N are both positive integers greater than or equal to 1;
each memory computing subunit comprises a 6T-SRAM storage unit, a switch tube M7 and a switch tube M8; the first end of the switch tube M7 is connected with the 6T-SRAM memory unit, the second end of the switch tube M7 is connected with the common terminal VSS, the third end of the switch tube M7 is connected with the second end of the switch tube M8, the first end of the switch tube M8 is used for inputting pulse signals, and the third end of the switch tube M8 is used for outputting read bit line signals.
Optionally, the 6T-SRAM memory cell comprises:
a switching tube M1, a switching tube M2, a switching tube M3, a switching tube M4, a switching tube M5 and a switching tube M6;
the second end of the switch tube M1 and the second end of the switch tube M2 are connected to a power supply VDD, the first end of the switch tube M1, the first end of the switch tube M5, the third end of the switch tube M2 and the third end of the switch tube M6 are connected, a connection point is called a Q point, the first end of the switch tube M2, the first end of the switch tube M6, the third end of the switch tube M1 and the third end of the switch tube M5 are connected, a connection point is called a Q 'point, the second end of the switch tube M5 and the second end of the switch tube M6 are connected to a common terminal VSS, the first end of the switch tube M3 and the first end of the switch tube M4 are used for inputting word line signals, the second end of the switch tube M3 is connected to the Q' point, the third end of the switch tube M3 is used for inputting inverted line signals, the third end of the switch tube M4 is connected to the Q point, and the second end of the switch tube M4 is used for inputting bit line signals.
Optionally, when the switching transistor M1 — the switching transistor M8 are both transistors, the transistor M1 and the transistor M2 are both PMOS, and the transistor M3, the transistor M4, the transistor M5, the transistor M6, the transistor M7, and the transistor M8 are all NMOS, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.
Alternatively, M is 4 and N is 64.
The invention also provides a memory computing device, which comprises K multi-bit multiply-accumulate operation units, an input control module, a bit line driving module, a word line driving module and K groups of multiply-accumulate reading computation modules; wherein K is a positive integer greater than or equal to 1;
the input control module, the bit line driving module and the word line driving module are all connected with each multi-bit multiply-accumulate operation unit, the g-th group of multiply-accumulate read calculation modules is connected with the g-th multi-bit multiply-accumulate operation units, and g is a positive integer which is greater than or equal to 1 and less than or equal to K; the input control module is used for converting input data into pulse signals to be output, the bit line driving module is used for outputting inverted bit line signals and bit line signals, the word line driving module is used for outputting word line signals, each multi-bit multiply-accumulate operation unit is used for performing weight storage and product operation of the pulse signals and weights according to the word line signals, the bit line signals and the inverted bit line signals, and product results are output in a bit line reading signal mode;
and the multiply-accumulate reading computation module is used for performing analog-to-digital conversion on the product result output by the multi-bit multiply-accumulate operation unit and then accumulating the product result to obtain a computation result.
Alternatively, K is 8.
Optionally, each multiply-accumulate read-out calculation module includes 4 analog-to-digital conversion units and 1 digital weighting unit, the 4 analog-to-digital conversion units are respectively connected with 4 rows of memory calculation units in each multi-bit multiply-accumulate operation unit correspondingly, and the 4 analog-to-digital conversion units are connected with the digital weighting unit; the 4 analog-to-digital conversion units are used for converting the analog values of all columns in the multiplication result into digital values; the digital weighting unit is used for adding 4 columns of digital values to obtain a calculation result.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention relates to a multi-bit multiply-accumulate operation unit and a memory computing device, wherein the multi-bit multiply-accumulate operation unit comprises: m columns of memory computing units; each column of the memory computing units comprises N memory computing subunits; each memory computing subunit comprises a 6T-SRAM storage unit, a switch tube M7 and a switch tube M8; the first end of the switch tube M7 is connected with the storage unit, the second end of the switch tube M7 is connected with the common end, the third end of the switch tube M7 is connected with the second end of the switch tube M8, the first end of the switch tube M8 is used for inputting a pulse signal, and the third end of the switch tube M8 is used for outputting a read bit line signal. In the multiply-accumulate operation, the invention avoids the influence of read-write interference by additionally adding the switching tubes M7 and M8.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a diagram of a multi-bit multiply-accumulate unit according to the present invention;
FIG. 2 is a diagram of an in-memory computing device according to the present invention;
FIG. 3 is a block diagram of a multiply-accumulate read calculation module according to the present invention;
description of the symbols:
the digital word-line multiplication and accumulation device comprises a 1-multi-bit multiplication and accumulation operation unit, a 2-input control module, a 3-bit line driving module, a 4-word line driving module, a 5-multiplication and accumulation reading calculation module, a 6-memory calculation unit, a 7-memory calculation subunit, an 8-analog-to-digital conversion unit and a 9-digital weighting unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a multi-bit multiply-accumulate operation unit and a memory computing device, so as to avoid the problem of read-write interference.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
The invention discloses a multi-bit multiply-accumulate operation unit 1, the multi-bit multiply-accumulate operation unit 1 includes:
m-column memory calculation units 6; each column of the memory computing units 6 comprises N memory computing subunits 7; wherein M and N are both positive integers greater than or equal to 1; each memory computing subunit 7 comprises a 6T-SRAM storage unit, a switch tube M7 and a switch tube M8; the first end of the switch tube M7 is connected with the 6T-SRAM memory unit, the second end of the switch tube M7 is connected with the common terminal VSS, the third end of the switch tube M7 is connected with the second end of the switch tube M8, the first end of the switch tube M8 is used for inputting pulse signals, and the third end of the switch tube M8 is used for outputting read bit line signals.
As an optional implementation mode, the 6T-SRAM memory cell comprises: a switching tube M1, a switching tube M2, a switching tube M3, a switching tube M4, a switching tube M5 and a switching tube M6.
The second end of the switch tube M1 and the second end of the switch tube M2 are connected to a power supply VDD, the first end of the switch tube M1, the first end of the switch tube M5, the third end of the switch tube M2 and the third end of the switch tube M6 are connected, a connection point is called a Q point, the first end of the switch tube M2, the first end of the switch tube M6, the third end of the switch tube M1 and the third end of the switch tube M5 are connected, a connection point is called a Q 'point, the second end of the switch tube M5 and the second end of the switch tube M6 are connected to a common terminal VSS, the first end of the switch tube M3 and the first end of the switch tube M4 are used for inputting word line signals, the second end of the switch tube M3 is connected to the Q' point, the third end of the switch tube M3 is used for inputting inverted line signals, the third end of the switch tube M4 is connected to the Q point, and the second end of the switch tube M4 is used for inputting bit line signals.
When the switching tubes M1-M8 are all transistors, the transistors M1 and M2 are all PMOS, the transistors M3, M4, M5, M6, M7 and M8 are all NMOS, the first terminal is a gate, the second terminal is a source, and the third terminal is a drain. As shown in fig. 1, the multi-bit multiply-accumulate operation unit 1 includes: 4 columns of memory calculation units 6; each column of said memory calculation units 6 comprises 64 memory calculation subunits 7.
Each of the memory computing sub-units 7 includes a 6T-SRAM memory cell, a transistor M7, and a transistor M8; the gate of the transistor M7 is connected to the 6T-SRAM memory cell, the source of the transistor M7 is connected to the common terminal VSS, and the drain of the transistor M7 is connected to the source of the transistor M8; the drain of the transistor M8 In the row (i + 1) and column (j) memory calculation subunit 7 is used for outputting a read bit line signal RBLj, and the gate of the transistor M8 In the row (i + 1) and column (j) memory calculation subunit 7 is used for inputting a pulse signal In < i >; the gate of the transistor M4 in the column i +1 memory calculation subunit 7 is used to input the word line signal WL < i >, the source of the transistor M4 in the column i +1 memory calculation subunit 7 is used to input the bit line signal BLj, and the drain of the transistor M3 in the column i +1 memory calculation subunit 7 is used to input the bit line signal BLBj, where i is a positive integer greater than or equal to 0 and less than or equal to 63, and j is a positive integer greater than or equal to 1 and less than or equal to 4.
As shown in fig. 1, the multi-bit multiply-accumulate operation unit 1 is composed of 4 columns of memory calculation units 6, which respectively store 4 th, 3 rd, 2 nd, and 1 st bits of 4-bit weight from left to right, and respectively represent 4 different bits of 4-bit weight. The transistor M1-the transistor M6 are used for storing weights, the transistor M7 and the transistor M8 are used for realizing multiplication of pulse signals and the weights, the transistor M1 and the transistor M2 are both PMOS, and the transistor M3-the transistor M8 are both NMOS. When the weight is stored, when the weight is stored in any one of 64 lines, firstly, the voltage of WL < i > corresponding to the line is increased, if the stored weight is 1, the voltage of BLj is 1, and the voltage of BLBj is 0; if the stored weight is 0, let the voltage of BLj be 0 and the voltage of BLBj be 1. When the calculation is carried out, firstly, data is input, the input data is 4-bit data, the size of the data is represented by the difference of the pulse width size, and the input of 4 bits means 15 possibilities of pulse width. The pulses are represented by In < i >, and different pulse widths represent different discharge times, which can cause different voltages In the voltage equalizing module, which is represented by the difference of the voltages of the read bit line signals RBL4, RBL3, RBL2 and RBL1, and the voltage difference is the result of one multiplication operation. Each column of 64 memory computing subunits 7 only has 16 units opened in each computation, which means that one multi-bit multiply-accumulate arithmetic unit 1 carries out 16 operations of 4 bits by 4 bits. The 16 cells all have the effect of discharging the read bit line signal RBLj, and finally the voltage on RBLj represents the result of the summation of the 16 multiplication operations, so that the read bit line signal RBLj represents the result of the 16 multiplication and accumulation operations.
Example 2
As shown in fig. 2, the present invention also discloses a memory computing device, which includes 8 multi-bit multiply-accumulate computing units 1 of embodiment 1, an input control module 2, a bit line driving module 3, a word line driving module 4, and 8 multiply-accumulate reading computing modules 5; the input control module 2, the bit line driving module 3 and the word line driving module 4 are all connected with each multi-bit multiply-accumulate operation unit 1, the g-th group of multiply-accumulate read calculation modules 5 is connected with the g-th multi-bit multiply-accumulate operation units 1, and g is a positive integer greater than or equal to 1 and less than or equal to 8; the input control module 2 is used for converting input data into pulse signals In <0> -In <63> for outputting, the bit line driving module 3 is used for outputting bit bar line signals BLB0<4:1> -BLB7<4:1> and bit line signals BL0<4:1> -BL7<4:1>, the word line driving module 4 is used for outputting word line signals WL <0> -WL <63>, each multi-bit multiply-accumulate operation unit 1 is used for carrying out weight storage and product operation of the pulse signals and the weights according to the word line signals, the bit line signals and the bit bar line signals, and the product result is output In read bit line signals RBL0<4:1> -RBL7<4:1 >; the multiply-accumulate readout calculation module 5 is configured to perform analog-to-digital conversion on the product result output by the multi-bit multiply-accumulate operation unit 1 and then accumulate the result to obtain a calculation result. The read bit line signals are RBL1-RBL4 in embodiment 1, because 8 multi-bit multiply-accumulate units 1 of embodiment 1 are included in embodiment 2, and in order to better distinguish the read bit line signals, the read bit line signals RBL1-RBL4 output by the 1 st multi-bit multiply-accumulate unit 1 are represented by RBL0<4:1>, and so on, the read bit line signals RBL1-RBL4 output by the 8 th multi-bit multiply-accumulate unit 1 are represented by RBL7<4:1 >; the bit line signals BL1-BL4 input by the 1 st multi-bit multiply-accumulate unit 1 are represented by BL0<4:1>, and so on, and the bit line signals BL1-BL4 input by the 8 th multi-bit multiply-accumulate unit 1 are represented by BL7<4:1 >; the bar line signals BLB1-BLB4 inputted from the 1 st multi-bit multiply-accumulate unit 1 are represented by BLB0<4:1>, and so on, and the bar line signals BLB1-BLB4 inputted from the 8 th multi-bit multiply-accumulate unit 1 are represented by BLB7<4:1 >.
As shown in fig. 3, the g-th multiply-accumulate readout calculation module 5 of the present invention includes 4 analog-to-digital conversion units 8 with 6 bits and 1 digital weighting unit 9, where the 4 analog-to-digital conversion units 8 are respectively connected to the 4 columns of memory calculation units 6 in the g-th multi-bit multiply-accumulate operation unit 1, and the 4 analog-to-digital conversion units 8 are all connected to the digital weighting unit 9; the 4 analog-to-digital conversion units 8 are used for receiving read bit line signals RBL1-RBL4 output by the 4 columns of memory calculation units 6, can also be written as RBlg <4:1>, and convert each column of analog values (namely the read bit line signals RBLj) in the multiplication result into a digital value of 6 bit; the digital weighting unit 9 is used for weighting and adding the digital values of 4 columns and 6 bits to obtain a calculation result of 10 bits and outputting the calculation result. That is to say, each of the multiply-accumulate readout calculation modules 5 of the present invention is mainly composed of two parts, the first part is a 4-6-bit analog-to-digital conversion unit 8, which is used to convert 4 analog voltage values output by the multi-bit multiply-accumulate operation unit 1 into 4 6-bit digital values. The second part is a digital weighting unit 9, namely 4 digital values of 6 bits output by the previous part are weighted, actually 8 groups of adders are formed to perform bitwise addition, and the final 10-bit calculation result is output.
The scheme disclosed by the invention has the following advantages:
the memory computing subunit 7 adopts an 8T SRAM structure, so that additional computing units (namely M7 and M8) are improved, the problem of read-write interference can be effectively avoided, and the accuracy of a computing result is improved.
Compared with the traditional read-out calculation module with a pure analog structure, the multiply-accumulate read-out calculation module 5 with a digital and analog mixed structure can effectively improve the calculation precision and greatly reduce the relative area and power consumption.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (6)
1. A memory computing device is characterized by comprising K multi-bit multiply-accumulate operation units, an input control module, a bit line driving module, a word line driving module and K groups of multiply-accumulate reading computation modules; wherein K is a positive integer greater than or equal to 1;
the input control module, the bit line driving module and the word line driving module are all connected with each multi-bit multiply-accumulate operation unit, the g-th group of multiply-accumulate read calculation modules is connected with the g-th multi-bit multiply-accumulate operation units, and g is a positive integer which is greater than or equal to 1 and less than or equal to K; the input control module is used for converting input data into pulse signals to be output, the bit line driving module is used for outputting inverted bit line signals and bit line signals, the word line driving module is used for outputting word line signals, each multi-bit multiply-accumulate operation unit is used for carrying out weight storage and product operation of the pulse signals and weights according to the word line signals, the bit line signals and the inverted bit line signals, and product results are output in a bit line reading signal mode;
the multiply-accumulate reading computation module is used for performing analog-to-digital conversion on the product result output by the multi-bit multiply-accumulate operation unit and then accumulating the product result to obtain a computation result; the multiply-accumulate reading calculation module comprises an analog-to-digital conversion unit and a digital weighting unit;
the multi-bit multiply-accumulate operation unit includes:
m columns of memory computing units; each column of the memory computing units comprises N memory computing subunits; wherein M and N are both positive integers greater than or equal to 1;
each memory computing subunit comprises a 6T-SRAM storage unit, a switch tube M7 and a switch tube M8; the first end of the switch tube M7 is connected with the 6T-SRAM memory unit, the second end of the switch tube M7 is connected with the common terminal VSS, the third end of the switch tube M7 is connected with the second end of the switch tube M8, the first end of the switch tube M8 is used for inputting pulse signals, and the third end of the switch tube M8 is used for outputting read bit line signals.
2. The in-memory computing device of claim 1, wherein the 6T-SRAM memory cell comprises:
a switching tube M1, a switching tube M2, a switching tube M3, a switching tube M4, a switching tube M5 and a switching tube M6;
a second end of the switching tube M1 and a second end of the switching tube M2 are all connected with a power supply VDD, a first end of the switching tube M1, a first end of the switching tube M5, a third end of the switching tube M2 and a third end of the switching tube M6 are connected, a connection point is called a Q point, a first end of the switching tube M2, a first end of the switching tube M6, a third end of the switching tube M1 and a third end of the switching tube M5 are connected, a connection point is called a Q 'point, a second end of the switching tube M5 and a second end of the switching tube M6 are all connected with a common terminal VSS, a first end of the switching tube M3 and a first end of the switching tube M4 are all used for inputting word line signals, a second end of the switching tube M3 is connected with the Q' point, a third end of the switching tube M3 is used for inputting bit line signals, a third end of the switching tube M4 is connected with the Q point, and a second end of the switching tube M4 is used for inputting bit line signals.
3. The memory computing device of claim 2, wherein when the switch M1-switch M8 are both transistors, the transistors M1 and M2 are both PMOS, the transistors M3, M4, M5, M6, M7, and M8 are all NMOS, the first terminal is gate, the second terminal is source, and the third terminal is drain.
4. The in-memory computing device of claim 1, wherein M is 4 and N is 64.
5. The in-memory computing device of claim 1, wherein K is 8.
6. The memory computing device of claim 5, wherein each of the multiply-accumulate read-out computing modules comprises 4 analog-to-digital converting units and 1 digital weighting unit, the 4 analog-to-digital converting units are respectively connected to 4 columns of memory computing units in each of the multi-bit multiply-accumulate computing units, and the 4 analog-to-digital converting units are connected to the digital weighting unit; the 4 analog-to-digital conversion units are used for converting the analog values of all columns in the multiplication result into digital values; the digital weighting unit is used for adding 4 columns of digital values to obtain a calculation result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210062863.6A CN114089950B (en) | 2022-01-20 | 2022-01-20 | Multi-bit multiply-accumulate operation unit and in-memory calculation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210062863.6A CN114089950B (en) | 2022-01-20 | 2022-01-20 | Multi-bit multiply-accumulate operation unit and in-memory calculation device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114089950A CN114089950A (en) | 2022-02-25 |
| CN114089950B true CN114089950B (en) | 2022-05-27 |
Family
ID=80308677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210062863.6A Active CN114089950B (en) | 2022-01-20 | 2022-01-20 | Multi-bit multiply-accumulate operation unit and in-memory calculation device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114089950B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512161B (en) * | 2022-04-19 | 2022-07-05 | 中科南京智能技术研究院 | Memory computing device with symbols |
| CN114647398B (en) * | 2022-05-23 | 2022-08-05 | 中科南京智能技术研究院 | Carry bypass adder-based in-memory computing device |
| CN114783482B (en) * | 2022-06-20 | 2022-09-16 | 中科南京智能技术研究院 | Memory computing device |
| CN114895869B (en) * | 2022-07-13 | 2022-09-23 | 中科南京智能技术研究院 | Multi-bit memory computing device with symbols |
| EP4354435A1 (en) * | 2022-10-11 | 2024-04-17 | Semron GmbH | Analog multiplying unit with binary multipliers |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11574173B2 (en) * | 2019-12-19 | 2023-02-07 | Qualcomm Incorporated | Power efficient near memory analog multiply-and-accumulate (MAC) |
| CN111431536B (en) * | 2020-05-18 | 2023-05-02 | 深圳市九天睿芯科技有限公司 | Subunit, MAC array and bit width reconfigurable analog-digital mixed memory internal computing module |
| CN112151091B (en) * | 2020-09-29 | 2023-03-21 | 中科南京智能技术研究院 | 8T SRAM unit and memory computing device |
| CN113393879B (en) * | 2021-04-27 | 2022-06-10 | 北京航空航天大学 | Nonvolatile memory and SRAM mixed storage integral data fast loading structure |
| CN113823343B (en) * | 2021-11-24 | 2022-02-22 | 中科南京智能技术研究院 | Separated computing device based on 6T-SRAM |
-
2022
- 2022-01-20 CN CN202210062863.6A patent/CN114089950B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114089950A (en) | 2022-02-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114089950B (en) | Multi-bit multiply-accumulate operation unit and in-memory calculation device | |
| CN112151091B (en) | 8T SRAM unit and memory computing device | |
| US20220262424A1 (en) | Compute in memory system | |
| CN109979503B (en) | Static random access memory circuit structure for realizing Hamming distance calculation in memory | |
| CN112992223B (en) | Memory computing unit, memory computing array and memory computing device | |
| CN112558919B (en) | Memory computing bit unit and memory computing device | |
| CN112884140B (en) | Multi-bit memory internal computing unit, array and device | |
| CN112133348B (en) | Storage unit, storage array and memory computing device based on 6T unit | |
| CN112151092B (en) | Storage unit, storage array and in-memory computing device based on 4-pipe storage | |
| CN110176264B (en) | High-low bit merging circuit structure based on internal memory calculation | |
| CN112992232B (en) | Multi-bit positive and negative single-bit memory computing unit, array and device | |
| CN112185447B (en) | 8-pipe double-split control storage unit, storage array and in-memory computing device | |
| CN113255904A (en) | Voltage margin enhanced capacitive coupling storage integrated unit, subarray and device | |
| CN113823343B (en) | Separated computing device based on 6T-SRAM | |
| CN111816234A (en) | Voltage accumulation memory computing circuit based on SRAM bit line union | |
| CN113296734B (en) | Multi-position storage device | |
| CN113467751B (en) | Analog domain memory internal computing array structure based on magnetic random access memory | |
| CN114300012B (en) | Decoupling SRAM memory computing device | |
| CN113077050B (en) | Digital domain computing circuit device for neural network processing | |
| CN114895869B (en) | Multi-bit memory computing device with symbols | |
| CN112558922A (en) | Four-transistor memory computing device based on separated word lines | |
| CN114512161B (en) | Memory computing device with symbols | |
| CN113391786B (en) | Computing device for multi-bit positive and negative weights | |
| CN113971971B (en) | Memory computing unit, array and device with positive and negative computation | |
| CN114882921B (en) | Multi-bit computing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |