CN112259136B - Memory operation circuit and chip structure - Google Patents

Memory operation circuit and chip structure Download PDF

Info

Publication number
CN112259136B
CN112259136B CN202011129148.7A CN202011129148A CN112259136B CN 112259136 B CN112259136 B CN 112259136B CN 202011129148 A CN202011129148 A CN 202011129148A CN 112259136 B CN112259136 B CN 112259136B
Authority
CN
China
Prior art keywords
bit line
pull
switch
unit
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011129148.7A
Other languages
Chinese (zh)
Other versions
CN112259136A (en
Inventor
黄瑞锋
杨昌楷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Haiguang Information Technology Co Ltd
Original Assignee
Haiguang Information Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Haiguang Information Technology Co Ltd filed Critical Haiguang Information Technology Co Ltd
Priority to CN202011129148.7A priority Critical patent/CN112259136B/en
Publication of CN112259136A publication Critical patent/CN112259136A/en
Application granted granted Critical
Publication of CN112259136B publication Critical patent/CN112259136B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Abstract

The application provides a memory operation circuit and a chip structure. The memory operation circuit comprises: a storage unit having a first storage point and a second storage point which are complementary; a first bit line for sensing a data voltage of a first storage point and a second bit line for sensing a data level of a second storage point; the pull-down unit is respectively connected with the first bit line and the second bit line, and the control end of the pull-down unit is used for accessing a first control signal; when the control end of the first bit line is connected with the high level, the high level read by the first bit line is pulled down to be the low level, and the high level read by the second bit line is pulled down to be the low level; the pull-up unit is respectively connected with the first bit line and the second bit line, and the control end of the pull-up unit is used for accessing a second control signal; to pull up the second bit line to a high level when the pull-down unit pulls down the first bit line to a low level, and to pull up the first bit line to a high level when the pull-down unit pulls down the second bit line to a low level.

Description

Memory operation circuit and chip structure
Technical Field
The present application relates to the field of storage technologies, and in particular, to a memory operation circuit and a chip structure.
Background
Fig. 1 is a schematic diagram of a Memory operation circuit in the prior art, which includes a Static Random-Access Memory (SRAM) 100 and an exclusive-or circuit 200. The static random access memory comprises a main Control logic part Control which is used for controlling the read-write state and the pre-decoding of the static random access memory; word line (word line) decode XDEC; a storage Array; and an input-output circuit IO. The circuit working principle is that DO x data is read out, the read data is compared with data (compare data) needing to be compared, if the comparison is the same, 0 is output, and if the comparison is different, 1 is output. DO [ x ] is just an example of an output in SRAM, and in actual operation, each output may be associated with a data to be compared.
The technical scheme is adopted, and the value of the static random access memory is read out firstly and then compared through exclusive-or logic. However, the delay of the exclusive or logic circuit is large.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a memory operation circuit and a chip structure, which can perform an exclusive or operation before reading a data level, and do not need to perform an exclusive or operation after reading, thereby reducing a delay.
The embodiment of the present application provides a memory operation circuit, including:
a storage unit having a first storage point and a second storage point which are complementary;
a first bit line for sensing a data voltage of a first storage point and a second bit line for sensing a data level of a second storage point;
the pull-down unit is respectively connected with the first bit line and the second bit line, and the control end of the pull-down unit is used for accessing a first control signal; when the control end of the first bit line is connected with the high level, the high level read by the first bit line is pulled down to be the low level, and the high level read by the second bit line is pulled down to be the low level;
the pull-up unit is respectively connected with the first bit line and the second bit line, and the control end of the pull-up unit is used for accessing a second control signal; to pull up the second bit line to a high level when the pull-down unit pulls down the first bit line to a low level, and to pull up the first bit line to a high level when the pull-down unit pulls down the second bit line to a low level.
According to the embodiment of the application, the data level can be subjected to exclusive-OR operation before being read out by adopting the pull-up unit and the pull-down unit, the exclusive-OR operation is not required to be carried out after being read out, the delay can be reduced, and the layout area required by a design circuit can be reduced.
Optionally, in the memory operation circuit according to this embodiment of the present application, the pull-down unit includes a first pull-down module and a second pull-down module;
the first pull-down module is connected with the first bit line, and a control end of the first pull-down module is connected with a first control signal;
the second pull-down module is connected with the second bit line, and a control end of the second pull-down module is connected with a first control signal.
According to the embodiment of the application, the high levels of the first bit line and the second bit line are respectively pulled down by respectively adopting the first pull-down module and the second pull-down module, so that the accuracy of low operation can be improved, and mutual interference is avoided.
Optionally, in the memory operation circuit according to this embodiment of the present application, the first pull-down module includes a first NMOS transistor and a second NMOS transistor;
the grid electrode and the drain electrode of the first NMOS tube are both connected with the first bit line, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected to the first control signal;
the second pull-down module comprises a third NMOS tube and a fourth NMOS tube;
the grid electrode and the drain electrode of the third NMOS tube are connected with the second bit line, the source electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is connected to the first control signal.
Optionally, in the memory operation circuit according to this embodiment of the present application, the first pull-down module further includes a first switch, a source of the second NMOS transistor is grounded through the first switch, the first switch is connected to a third control signal, and the first switch is configured to be turned on for a preset duration in a read cycle in which the second NMOS transistor is turned on;
the second pull-down module further comprises a second switch, a source electrode of the fourth NMOS tube is grounded through the second switch, the second switch is connected to a third control signal, and the second switch is used for conducting preset time duration in a reading period in which the fourth NMOS tube is conducted.
The first switch is introduced into the first pull-down module, and the second switch is introduced into the second pull-down module, so that when the first bit line is pulled by the pull-up unit, the first pull-down module cannot pull down the first bit line, and when the second bit line is pulled by the pull-up unit, the second pull-down module cannot pull down the first bit line, and therefore the accuracy of the high-level logic value output by the first bit line or the second bit line can be improved.
Optionally, in the memory operation circuit according to this embodiment of the present application, the first switch and the second switch are both NMOS transistors.
Optionally, in the memory operation circuit according to this embodiment of the present application, the pull-up unit includes a first PMOS transistor, a second PMOS transistor, and a third switch;
the control end of the third switch is connected with the fourth control signal; the input end of the third switch is connected with a preset pull-up voltage, the output end of the third switch is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the first bit line, the grid electrode of the first PMOS tube is connected with the second bit line, the drain electrode of the second PMOS tube is connected with the second bit line, and the grid electrode of the second PMOS tube is connected with the first bit line.
Optionally, in the memory operation circuit according to this embodiment of the present application, the third switch is a PMOS transistor.
Optionally, in the memory operation circuit according to this embodiment of the present application, the fourth control signal is an inverted signal of the third control signal.
Optionally, in the memory operation circuit according to the embodiment of the present application, a voltage difference amplifying unit is further included;
the voltage difference unit is respectively connected with the first bit line and the second bit line and used for pulling the higher voltage and the lower voltage in the first bit line and the second bit line high and low.
In the embodiment of the application, the voltage difference amplifying unit is used for pulling the first bit line BL and the second bit line BLB higher in voltage and pulling the first bit line BL and the second bit line BLB lower in voltage, so that the accuracy of the logic values of the data levels output by the first bit line BL and the second bit line BLB is improved.
Optionally, in the memory operation circuit according to an embodiment of the present application, the voltage difference amplifying unit includes: a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first phase inverter, a second phase inverter, an eighth PMOS tube and a ninth PMOS tube;
the grid electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are connected and accessed with a fifth control signal, the source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected and accessed with a power supply voltage, the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and connected with the input end of the first phase inverter at a point A, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth PMOS tube and connected with the input end of the second phase inverter at a point B; the source electrode of the eighth PMOS tube is connected with the first bit line, the drain electrode of the eighth PMOS tube is connected with a point A, the drain electrode of the ninth PMOS tube is connected with the second bit line, the source electrode of the ninth PMOS tube is connected with a point B, the point A is connected with the input end of the second phase inverter, the point B is connected with the output end of the first phase inverter, and the grid electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and is connected with a sixth control signal.
Optionally, in the memory operation circuit according to this embodiment of the present application, the memory operation circuit further includes a fifth NMOS transistor, a drain of the fifth NMOS transistor is connected to negative terminals of the first inverter and the second inverter, a source of the fifth NMOS transistor is grounded, and a gate of the fifth NMOS transistor is connected to an inverted signal of a fifth control signal.
Optionally, in the memory operation circuit according to the embodiment of the present application, the memory operation circuit further includes a word line; the storage unit comprises a latch, a sixth NMOS transistor and a seventh NMOS transistor;
the latch comprises the first storage point and the second storage point;
the word line is respectively connected with the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, the first end of the sixth NMOS tube is connected with the first bit line, and the second end of the sixth NMOS tube is connected with the first storage point; the first end of the seventh NMOS tube is connected with the second bit line, and the second end of the seventh NMOS tube is connected with the second storage point.
Optionally, in the memory operation circuit according to the embodiment of the present application, the memory operation circuit further includes a first bit line switch and a second bit line switch;
the first bit line comprises a first upper half section and a first lower half section, and the second bit line comprises a second upper half section and a second lower half section;
the storage unit is connected with the first upper half section and the second upper half section, the first lower half section is respectively connected with the pull-up unit and the pull-down unit, and the second lower half section is respectively connected with the pull-up unit and the pull-down unit;
the first end of the first bit line switch is connected with the first upper half section, the second end of the first bit line switch is connected with the first lower half section, the first end of the second bit line switch is connected with the second upper half section, the second end of the second bit line switch is connected with the second lower half section, and the control ends of the first bit line switch and the second bit line switch are respectively connected with bit line control signals.
Optionally, in the memory operation circuit according to this embodiment of the present application, the first bit line switch and the second bit line switch are both PMOS transistors.
Optionally, in the memory operation circuit according to an embodiment of the present application, the memory operation circuit further includes an output unit, the output unit is respectively connected to the first bit line and the second bit line, and the output unit is configured to output a value corresponding to the voltage of the first bit line.
In a second aspect, an embodiment of the present application further provides a chip structure, including any one of the memory operation circuits described above.
As can be seen from the above, the memory operation circuit and the chip structure provided in the embodiment of the present application use the pull-down unit to pull down the high level read by the first bit line BL to the low level when the first control signal is at the high level, pull down the high level read by the second bit line BLB to the low level, and use the pull-up unit to pull up the second bit line BLB to the high level when the pull-down unit pulls down the first bit line BL to the low level, and use the pull-up unit to pull up the first bit line to the high level when the pull-down unit pulls down the second bit line BLB to the low level, so as to implement the xor operation between the first control signal and the data level of the first storage point read by the first bit line, output the low level, that is, 0, and output the high level when the first control signal is different from the data level read by the first bit line, namely 1, the exclusive or operation can be carried out before the data level is read out, the exclusive or operation is not required to be carried out after the data level is read out, the delay can be reduced, and the layout area required by the design circuit can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a first structure of a memory operation circuit in the prior art.
Fig. 2 is a first structural diagram of a memory operation circuit according to some embodiments of the present disclosure.
Fig. 3 is a second structure diagram of a memory operation circuit according to some embodiments of the present application.
Fig. 4 is a schematic diagram of a third structure of a memory operation circuit according to some embodiments of the present application.
Fig. 5 is a schematic diagram of a fourth structure of a memory operation circuit according to some embodiments of the present disclosure.
Fig. 6 is a schematic diagram of a fifth structure of a memory operation circuit according to some embodiments of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that the terms "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory operation circuit according to some embodiments of the present application. The memory operation circuit comprises: word line WL, first bit line BL, second bit line BLB, memory cell 101, pull-down cell 102, and pull-up cell 103. The memory cell 101 is connected to the word line WL, the first bit line BL and the second bit line BLB, the pull-down cell 102 is connected to the first bit line BL and the second bit line BLB, and the pull-up cell 103 is connected to the first bit line BL and the second bit line BLB.
The memory cell 101 has a first storage point and a second storage point complementary to each other, so as to store complementary data levels. The memory cell 101 reads a data level of the first storage point through the first bit line BL and a data level of the second storage point through the second bit line BLB under the control of the word line WL.
Wherein, the control end of the pull-down unit 102 is used for accessing a first control signal Cdata; for pulling down the high level read out by the first bit line BL to a low level when its control terminal is switched in a high level, and for pulling down the high level read out by the second bit line BLB to a low level.
Wherein, the control end of the pull-up unit 103 is used for accessing the second control signal. The pull-up unit 103 is configured to pull up the second bit line BLB to a high level when the pull-down unit 102 pulls down the first bit line BL to a low level, and is configured to pull up the first bit line BL to a high level when the pull-down unit 102 pulls down the second bit line BLB to a low level, under the control of the second control signal.
Compared with the prior art shown in fig. 1, in the embodiment of the present invention, when the first control signal is at a high level, the pull-down unit is adopted to pull down the high level read by the first bit line BL to a low level, pull down the high level read by the second bit line BLB to a low level, and when the pull-down unit pulls down the first bit line BL to a low level, the pull-up unit is adopted to pull up the second bit line BLB to a high level, and when the pull-down unit pulls down the second bit line BLB to a low level, the pull-up unit is adopted to pull up the first bit line to a high level, so as to implement an exclusive or operation between the first control signal and the data level of the first storage point read by the first bit line, when the first control signal is the same as the data level read by the first bit line, the low level, that is 0, and when the first control signal is different from the data level read by the first bit line, the high level, that is 1, therefore, the XOR operation can be carried out before the data level is read out, the XOR operation does not need to be carried out after the data level is read out, the delay can be reduced, and the layout area required by the design circuit is reduced.
Referring to fig. 3, fig. 3 is a circuit structure diagram of a memory operation circuit according to some embodiments of the present application. The memory cell 101 includes a latch 1011, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The latch 1011 includes a first storage point Q and the second storage point QB; a word line WL is respectively connected to a gate of a sixth NMOS transistor N6 and a gate of the seventh NMOS transistor N7, a first end of the sixth NMOS transistor N6 is connected to the first bit line BL, and a second end of the sixth NMOS transistor N6 is connected to the first storage point Q; a first terminal of the seventh NMOS transistor N7 is connected to the second bit line BLB, and a second terminal of the seventh NMOS transistor N7 is connected to the second storage point QB. Wherein, the first end is a source electrode, the second end is a drain electrode, the first end is a drain electrode, and the first end is a source electrode. When the voltage of the word line WL is at a high level, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned on, such that the first bit line BL reads the data level of the first storage node Q and the second bit line BLB reads the data level of the second storage node QB.
The latch 1011 is a latch commonly known in the prior art, and is formed by connecting two inverters, and the latch 1011 includes a PMOS transistor P01, a PMOS transistor P02, an NMOS transistor N01, and an NMOS transistor N02. The source electrode of the PMOS tube P01 is connected with the source electrode of the PMOS tube P02 and is connected to the common voltage VDD, the drain electrode of the PMOS tube P01 is connected with the drain electrode of the NMOS tube N01, and the source electrode of the NMOS tube N01 is grounded. The gates of the PMOS transistor P01 and the NMOS transistor N01 are connected to the first storage node Q. The drain of the PMOS transistor P02 is connected to the drain of the NMOS transistor N02, the source of the NMOS transistor N02 is grounded, the gate of the PMOS transistor P02 and the gate of the NMOS transistor N02 are connected to the second storage point QB, the first storage point Q is connected to the drain of the PMOS transistor P02 and the drain of the NMOS transistor N02, and the second storage point QB is connected to the drain of the PMOS transistor P01 and the drain of the NMOS transistor N01.
The pull-down unit 102 includes a first pull-down module 1021 and a second pull-down module 1022. The first pull-down module 1021 is connected to the first bit line BL, and the second pull-down module 1022 is connected to the second bit line BLB. The control terminal of the first pull-down module 1021 is connected to the first control signal Cdata, and the control terminal of the second pull-down module 1022 is connected to the first control signal Cdata. The first pull-down module 1021 is used for pulling down the high level read by the first bit line BL to a low level when the control terminal thereof is switched to the high level. The first pull-down module 1021 is used to pull down the high level read out by the second bit line BLB to a low level when its control terminal is switched in a high level. According to the embodiment of the application, the high levels of the first bit line and the second bit line are respectively pulled down by respectively adopting the first pull-down module and the second pull-down module, so that the accuracy of low operation can be improved, and mutual interference is avoided.
It is understood that, in some embodiments, the first pull-down module 1021 may include a first NMOS transistor N1 and a second NMOS transistor N2, the gate of the first NMOS transistor N1 is connected to the first bit line BL, the drain of the first NMOS transistor N1 is connected to the first bit line BL, the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is grounded. The second pull-down module 1022 may include a third NMOS transistor N3 and a fourth NMOS transistor N4, a gate of the third NMOS transistor N3 is connected to the second bit line BLB, a drain of the third NMOS transistor N3 is connected to the second bit line BLB, a source of the third NMOS transistor N3 is connected to a drain of the fourth NMOS transistor N4, and a source of the fourth NMOS transistor N4 is grounded. The gates of the second NMOS transistor N2 and the fourth NMOS transistor N4 are respectively connected to a first control signal Cdata.
It is understood that, in some embodiments, the first pull-down module 1021 may further include a first switch T1, the source of the second NMOS transistor N2 is grounded through the first switch T1, and a control terminal of the first switch is connected to the third control signal SA _ P. The first switch T1 is used for conducting for a preset time in a reading period when the second NMOS transistor is conducted; wherein the preset duration is less than the one reading period. The first switch T1 may be an NMOS transistor or a PMOS transistor, and of course, in the embodiment shown in fig. 3, the first switch T1 is a PMOS transistor.
Correspondingly, the second pull-down module 1022 further includes a second switch T2, the source of the fourth NMOS transistor N4 is grounded through the second switch T2, the second switch T2 is connected to the third control signal SA _ P, and the second switch T2 is configured to be turned on for a preset time duration in a reading period in which the fourth NMOS transistor N4 is turned on. Wherein the preset duration is less than the one reading period. The second switch T2 may be an NMOS transistor or a PMOS transistor, and of course, in the embodiment shown in fig. 3, the second switch T2 is a PMOS transistor.
In the embodiment of the present application, the first switch is introduced into the first pull-down module 1021, and the second switch is introduced into the second pull-down module 1022, so that when the first bit line is pulled by the pull-up unit, the first pull-down module does not pull down the first bit line, and when the second bit line is pulled by the pull-up unit, the second pull-down module does not pull down the first bit line, so that the accuracy of the high-level logic value output by the first bit line or the second bit line can be improved.
The pull-up unit 103 includes a third switch T3, a first PMOS transistor P1, and a second PMOS transistor P2. The input end of the third switch T3 is connected to the supply voltage VDD, the output end of the third switch is connected to the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2, the drain of the first PMOS transistor P1 is connected to the first bit line BL, the drain of the second PMOS transistor P2 is connected to the second bit line BLB, the gate of the first PMOS transistor P1 is connected to the second bit line, and the gate of the second PMOS transistor P2 is connected to the first bit line BL. The control end of the first switch is connected to a fourth control signal SAB _ P. The third switch T3 may be an NMOS transistor or a PMOS transistor, and in the embodiment shown in fig. 3, it is a PMOS transistor, and correspondingly, the fourth control signal SAB _ P is an inverted signal of the third control signal SA _ P.
In some embodiments, the memory operation circuit may further include an output unit 104, the output unit 104 is respectively connected to the first bit line BL and the second bit line BLB, and the output unit 104 may output a corresponding value, 0 or 1, by using a digital logic circuit to operate the voltages output by the first bit line BL and the second bit line BLB.
The specific operation principle of the memory operation circuit is described in detail below.
When the word line WL is at a low level, neither the first bit line BL nor the second bit line BLB reads a data level from the memory cell 101.
S1, when the word line WL is at high level, the word line WL turns on the sixth NMOS transistor N6 and the seventh NMOS transistor N7 of the memory cell 101, the first bit line BL reads the data level from the first storage point Q of the latch 1011 through the sixth NMOS transistor N6, and the second bit line BLB reads the data level from the second storage point QB of the latch 1011 through the seventh NMOS transistor N7. For example, the first storage point Q is at a high level, the second storage point QB is at a low level, the first bit line BL is pulled up to a high level by the first storage point Q, and the second bit line BLB is pulled down to a lower level by the second storage point QB.
If the first control signal Cdate is maintained at a high level during a read period for reading a data level of the memory cell 101, when the third control signal SA _ P of the first switch T1 is at a high level, the first NMOS transistor N1, the second NMOS transistor N2, and the first switch T1 of the first pull-down module 1021 are all turned on, and thus, a high level of the DL point of the first bit line BL is pulled down to a low level by the first pull-down module 1021. Correspondingly, since the second switch T2 is turned on to be almost off to a small degree when the second bit line BLB is at a low level, the pull-down action of the second pull-down module 1022 is small, when the DL point is gradually pulled down to a low level, the second PMOS transistor P2 is gradually turned on, and correspondingly, the third switch T3 is kept on under the control of the fourth control signal SAB _ P, so that the voltage at the DLB point is pulled up to a high level by the pull-up unit 103 from a low level. Accordingly, it can be derived that, in one read period in which the first control signal Cdata is maintained at a high level, the voltage output from the first bit line is at a low level (logic value is 0) as opposed to the stored data voltage (logic value is 1) of the first storage point Q.
If the first control signal Cdate is maintained at a low level during a read cycle for reading a data level of the memory cell 101, both the first pull-down module 1021 and the second pull-down module 1022 are turned off, and thus, the second bit line BLB is pulled down to a lower level by the second storage point QB since the first bit line BL is pulled up to a high level by the first storage point Q. Therefore, the voltage output from the first bit line BL is high (logic value is 1).
S2, when the word line WL is at high level, the word line WL turns on the sixth NMOS transistor N6 and the seventh NMOS transistor N7 of the memory cell 101, the first bit line BL reads the data level from the first storage point Q of the latch 1011 through the sixth NMOS transistor N6, and the second bit line BLB reads the data level from the second storage point QB of the latch 1011 through the seventh NMOS transistor N7. For example, the first storage point Q is low, the second storage point QB is high, the first bit line BL is pulled low by the first storage point Q to be low, and the second bit line BLB is pulled high by the second storage point QB. Of course, in order to ensure that the voltage at the DLB point of the second bit line BLB is pulled up sufficiently, the pull-up capability of the third switch T3 and the first PMOS transistor P1 is stronger than the pull-down capability of the MOS transistors of the second pull-down module 1022, i.e., the size of the third switch T3 and the first PMOS transistor P1 needs to be larger than the size of the MOS transistors of the second pull-down module 1022.
If the first control signal Cdate is kept at a high level during a read cycle for reading the data level of the memory cell 101, when the third control signal SA _ P is at a high level, the third NMOS transistor N3, the fourth NMOS transistor N4, and the second switch T2 of the second pull-down module 2021 are all turned on, so that the high level at the DLB point of the second bit line BLB is pulled down to a lower level by the second pull-down module 1022. Correspondingly, when the first bit line is at a low level, the first NMOS transistor is turned on to a small degree and is almost turned off, so that the pull-down action of the second pull-down module 1022 is small. When the DLB point of the second bit line BLB is gradually pulled down to a low level, the first PMOS transistor P1 is gradually opened, and correspondingly, the third switch T3 is kept opened under the control of the fourth control signal SAB _ P, so that the voltage of the DL point of the first bit line BL is pulled up to a high level by the pull-up unit 103 from a low level. Accordingly, it can be derived that, in one read cycle in which the first control signal Cdate is maintained at a high level, the voltage output from the first bit line BL is at a high level (logic value of 1) opposite to the stored data voltage (logic value of 1) of the first storage point Q. Of course, in order to ensure that the voltage at the DLB point of the first bit line BLB is pulled up to be high enough, the pull-up capability of the third switch T3 and the second PMOS transistor P2 is stronger than the pull-down capability of each MOS transistor of the first pull-down module 1021, i.e., the size of the third switch T3 and the second PMOS transistor P2 needs to be larger than that of each MOS transistor of the second pull-down module 1022.
If the first control signal Cdate is maintained at a low level during a read cycle for reading a data level of the memory cell 101, both the first pull-down module 1021 and the second pull-down module 1022 are turned off, and thus, the second bit line BLB is pulled up to a high level by the second storage point QB since the first bit line BL is pulled down to a low level by the first storage point Q. Therefore, the voltage output from the first bit line BL is low (logic value is 0).
Thus, from the above two steps, the following truth table can be obtained:
Cdata Q output of
0 1 1
0 0 0
1 0 1
1 1 0
It can be seen that the memory operation circuit outputs a logic value of 0 when the first control signal is the same as the logic value of the first storage point, and outputs a logic value of 1 when the second control signal is the same as the logic value of the first storage point.
It is understood that in some embodiments, the memory operation circuit further includes a first bitline switch Q1 and a second bitline switch Q2; the first bit line BL includes a first upper half and a first lower half, and the second bit line BLB includes a second upper half and a second lower half. The memory cell 101 is connected to the first upper half section and the second upper half section, the first lower half section is respectively connected to the pull-up unit 103 and the pull-down unit 102, and the second lower half section is respectively connected to the pull-up unit 103 and the pull-down unit 102; the first end of the first bit line switch is connected with the first upper half section, the second end of the first bit line switch is connected with the first lower half section, the first end of the second bit line switch is connected with the second upper half section, the second end of the second bit line switch is connected with the second lower half section, and the control ends of the first bit line switch and the second bit line switch are respectively connected with a bit line control signal YMUX. The first bitline switch Q1 and the second bitline switch Q2 may be NMOS transistors or PMOS transistors. After the word line WL is turned off (or after the enabling is finished), the bit line control signal YMUX is also turned off, and since the bit line control signal YMUX controls the first bit line switch Q1 and the second bit line switch Q2 to be PMOS, the word line WL is 1pulse and the bit line control signal YMUX is 0 pulse. So that the values of the subsequent first bit line BL and second bit line BLB are not affected by the values of the pull-up cell and the pull-down cell.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a memory operation circuit according to some embodiments of the present application. The memory operation circuit comprises: a word line WL, a first bit line BL, a second bit line BLB, a memory cell 201, a pull-down unit 202, a pull-up unit 203, a voltage difference amplifying unit 204, and an output unit 205. The memory cell 201 is connected to the word line WL, the first bit line BL and the second bit line BLB, the pull-down cell 202 is connected to the first bit line BL and the second bit line BLB, and the pull-up cell 203 is connected to the first bit line BL and the second bit line BLB. The voltage difference amplifying unit 204 is respectively connected to the first bit line BL and the second bit line BLB. The output unit 205 is connected to the first bit line BL and the second bit line BLB, respectively.
Referring to fig. 5, fig. 5 is a specific circuit structure diagram of a memory operation circuit in some embodiments of the present application.
The memory unit 201, the pull-down unit 202, the pull-up unit 203, and the output unit 205 have the same structure and function as those of the corresponding structure in the above embodiments, and therefore, a repeated description is not required.
The voltage difference amplifying unit 204 is configured to pull up the first bit line BL and the second bit line BLB with higher voltage and pull down the second bit line BLB with lower voltage. The voltage difference amplifying unit 204 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first inverter 2041, a second inverter 2042, an eighth PMOS transistor P8, and a ninth PMOS transistor P9.
The gates of the third PMOS transistor P3, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected to a fifth control signal RCG, the sources of the fourth PMOS transistor P5 and the fifth PMOS transistor P6 are connected to a supply voltage VDD, the source of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4 and to the input of the first inverter F1 at point a, and the drain of the third PMOS transistor P3 is connected to the drain of the fifth PMOS transistor P5 and to the input of the second inverter 2042 at point B; the source of the eighth PMOS transistor P9 is connected to the first bit line BL, the drain of the eighth PMOS transistor P8 is connected to a point a, the drain of the ninth PMOS transistor P9 is connected to the second bit line BLB, the source of the ninth PMOS transistor P9 is connected to a point B, the point a is connected to the input end of the second inverter 2042, the point B is connected to the output end of the first inverter 2041, and the gate of the eighth PMOS transistor P8 is connected to the gate of the ninth PMOS transistor P9 and receives a sixth control signal.
It is understood that, in some embodiments, the voltage difference amplifying unit 204 further includes a fifth NMOS transistor N5, a drain of the fifth NMOS transistor N5 is connected to negative terminals of the first inverter 2041 and the second inverter 2042, a source of the fifth NMOS transistor N5 is grounded, and a gate of the fifth NMOS transistor N5 is connected to the inverted signal SAEN of the sixth control signal. It is to be understood that the fifth control signal can be obtained by inverting the sixth control signal through the inverter F1.
The first inverter 2041 includes a PMOS transistor P03 and an NMOS transistor N03, and the second inverter 2042 includes a PMOS transistor P04 and an NMOS transistor N04. The source electrode of the PMOS tube P03 is connected with the source electrode of the PMOS tube P04 and is connected to the common voltage VDD, the drain electrode of the PMOS tube P03 is connected with the drain electrode of the NMOS tube N03, and the source electrode of the NMOS tube N03 is grounded. The gates of the PMOS transistor P03 and the NMOS transistor N03 are connected to the first storage node Q. The drain of the PMOS transistor P04 is connected to the drain of the NMOS transistor N04, the source of the NMOS transistor N04 is grounded, the gate of the PMOS transistor P04 and the gate of the NMOS transistor N04 are connected to the point B, the point a is connected to the drain of the PMOS transistor P04 and the drain of the NMOS transistor N04, and the point B is connected to the drain of the PMOS transistor P03 and the drain of the NMOS transistor N03.
It is understood that in some embodiments, the memory operation circuit further includes a first bitline switch Q1 and a second bitline switch Q2; the first bit line BL includes a first upper half and a first lower half, and the second bit line BLB includes a second upper half and a second lower half. The memory cell 201 is connected to the first upper half section and the second upper half section, the first lower half section is respectively connected to the pull-up unit 203 and the pull-down unit 202, and the second lower half section is respectively connected to the pull-up unit 203 and the pull-down unit 202; the first end of the first bit line switch is connected with the first upper half section, the second end of the first bit line switch is connected with the first lower half section, the first end of the second bit line switch is connected with the second upper half section, the second end of the second bit line switch is connected with the second lower half section, and the control ends of the first bit line switch and the second bit line switch are respectively connected with a bit line control signal YMUX. The first bitline switch Q1 and the second bitline switch Q2 may be NMOS transistors or PMOS transistors.
In the embodiment of the present application, the voltage difference amplifying unit 204 is used to pull up the voltage of the first bit line BL and the second bit line BLB higher and pull down the voltage of the first bit line BL and the second bit line BLB lower, so as to improve the accuracy of the logic values of the data levels output by the first bit line BL and the second bit line BLB.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a memory operation circuit according to some embodiments of the present application. The memory operation circuit comprises: a plurality of word lines WL, a bit line BL, a second bit line BLB, a plurality of memory cells 301, a pull-down cell 302, a pull-up cell 303, a voltage difference amplifying cell 304, and an output cell 305.
The plurality of memory cells 301 are respectively connected with the plurality of word lines WL in a one-to-one correspondence, each memory cell 301 is respectively connected with the first bit line BL and the second bit line BLB, the pull-down cell 302 is respectively connected with the first bit line BL and the second bit line BLB, and the pull-up cell 303 is respectively connected with the first bit line BL and the second bit line BLB. The voltage difference amplifying unit 304 is connected to the first bit line BL and the second bit line BLB, respectively. The output unit 305 is connected to the first bit line BL and the second bit line BLB, respectively.
The plurality of memory cells 301, the pull-down unit 302, the pull-up unit 303, the voltage difference amplifying unit 304, and the output unit 305 are respectively the same as the corresponding structures in any of the above embodiments, and thus, a description thereof will not be repeated. The data level of the first storage point and the data level of the second storage point of the plurality of memory cells 301 are sequentially read by the first bit line BL and the second bit line BLB under the control of the plurality of word lines WL.
Of course, if the data levels stored in the plurality of memory cells 301 need to be xored with the first control signal, the first control signal is kept in a high state all the time.
The embodiment of the present application further provides a chip structure, where the chip structure includes the memory operation circuit in any of the above embodiments.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (15)

1. A memory arithmetic circuit, comprising:
a storage unit having a first storage point and a second storage point which are complementary;
a first bit line for sensing a data voltage of a first storage point and a second bit line for sensing a data level of a second storage point;
the pull-down unit is respectively connected with the first bit line and the second bit line, and the control end of the pull-down unit is used for accessing a first control signal; when the control end of the first bit line is connected with the high level, the high level read by the first bit line is pulled down to be the low level, and the high level read by the second bit line is pulled down to be the low level;
the pull-up unit is respectively connected with the first bit line and the second bit line, and the control end of the pull-up unit is used for accessing a second control signal; to pull up the second bit line to a high level when the pull-down unit pulls down the first bit line to a low level, and to pull up the first bit line to a high level when the pull-down unit pulls down the second bit line to a low level;
the device also comprises a first bit line switch and a second bit line switch;
the first bit line comprises a first upper half section and a first lower half section, and the second bit line comprises a second upper half section and a second lower half section;
the storage unit is connected with the first upper half section and the second upper half section, the first lower half section is respectively connected with the pull-up unit and the pull-down unit, and the second lower half section is respectively connected with the pull-up unit and the pull-down unit;
the first end of the first bit line switch is connected with the first upper half section, the second end of the first bit line switch is connected with the first lower half section, the first end of the second bit line switch is connected with the second upper half section, the second end of the second bit line switch is connected with the second lower half section, and the control ends of the first bit line switch and the second bit line switch are respectively connected with bit line control signals.
2. The memory operation circuit of claim 1, wherein the pull-down unit comprises a first pull-down module and a second pull-down module;
the first pull-down module is connected with the first bit line, and a control end of the first pull-down module is connected with a first control signal;
the second pull-down module is connected with the second bit line, and a control end of the second pull-down module is connected with a first control signal.
3. The memory operation circuit of claim 2, wherein the first pull-down module comprises a first NMOS transistor and a second NMOS transistor;
the grid electrode and the drain electrode of the first NMOS tube are both connected with the first bit line, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected to the first control signal;
the second pull-down module comprises a third NMOS tube and a fourth NMOS tube;
the grid electrode and the drain electrode of the third NMOS tube are connected with the second bit line, the source electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is connected to the first control signal.
4. The memory operation circuit of claim 3, wherein the first pull-down module further comprises a first switch, the source of the second NMOS transistor is grounded through the first switch, the first switch is connected to a third control signal, and the first switch is configured to be turned on for a preset duration in one reading cycle in which the second NMOS transistor is turned on;
the second pull-down module further comprises a second switch, a source electrode of the fourth NMOS tube is grounded through the second switch, the second switch is connected to a third control signal, and the second switch is used for conducting preset time duration in a reading period in which the fourth NMOS tube is conducted.
5. The memory arithmetic circuit of claim 4, wherein the first switch and the second switch are both NMOS transistors.
6. The memory arithmetic circuit of claim 4, wherein the pull-up unit comprises a first PMOS transistor, a second PMOS transistor, and a third switch;
the control end of the third switch is connected with a fourth control signal; the input end of the third switch is connected with a preset pull-up voltage, the output end of the third switch is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the first bit line, the grid electrode of the first PMOS tube is connected with the second bit line, the drain electrode of the second PMOS tube is connected with the second bit line, and the grid electrode of the second PMOS tube is connected with the first bit line.
7. The memory arithmetic circuit of claim 6, wherein the third switch is a PMOS transistor.
8. The memory arithmetic circuit of claim 6 wherein the fourth control signal is an inverse of the third control signal.
9. The memory arithmetic circuit according to any one of claims 1 to 8, further comprising a voltage difference value amplifying unit;
the voltage difference unit is respectively connected with the first bit line and the second bit line and used for pulling the higher voltage and the lower voltage in the first bit line and the second bit line high and low.
10. The memory operation circuit of claim 9, wherein the voltage difference amplifying unit comprises: a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first phase inverter, a second phase inverter, an eighth PMOS tube and a ninth PMOS tube;
the grid electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are connected and accessed with a fifth control signal, the source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected and accessed with a power supply voltage, the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and connected with the input end of the first phase inverter at a point A, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth PMOS tube and connected with the input end of the second phase inverter at a point B; the source electrode of the eighth PMOS tube is connected with the first bit line, the drain electrode of the eighth PMOS tube is connected with a point A, the drain electrode of the ninth PMOS tube is connected with the second bit line, the source electrode of the ninth PMOS tube is connected with a point B, the point A is connected with the input end of the second phase inverter, the point B is connected with the output end of the first phase inverter, and the grid electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and is connected with a sixth control signal.
11. The memory operation circuit of claim 10, further comprising a fifth NMOS transistor, wherein a drain of the fifth NMOS transistor is connected to negative terminals of the first and second inverters, a source of the fifth NMOS transistor is grounded, and a gate of the fifth NMOS transistor is connected to an inverted signal of a sixth control signal.
12. The memory arithmetic circuit according to any one of claims 1 to 8, further comprising a word line; the storage unit comprises a latch, a sixth NMOS transistor and a seventh NMOS transistor;
the latch comprises the first storage point and the second storage point;
the word line is respectively connected with the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, the first end of the sixth NMOS tube is connected with the first bit line, and the second end of the sixth NMOS tube is connected with the first storage point; the first end of the seventh NMOS tube is connected with the second bit line, and the second end of the seventh NMOS tube is connected with the second storage point.
13. The memory arithmetic circuit of claim 1, wherein the first bit line switch and the second bit line switch are both PMOS transistors.
14. The memory operation circuit according to claim 1, further comprising an output unit, the output unit being connected to the first bit line and the second bit line, respectively, and the output unit being configured to output a value corresponding to the voltage of the first bit line.
15. A chip architecture comprising the memory operation circuit of any one of claims 1 to 14.
CN202011129148.7A 2020-10-20 2020-10-20 Memory operation circuit and chip structure Active CN112259136B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011129148.7A CN112259136B (en) 2020-10-20 2020-10-20 Memory operation circuit and chip structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011129148.7A CN112259136B (en) 2020-10-20 2020-10-20 Memory operation circuit and chip structure

Publications (2)

Publication Number Publication Date
CN112259136A CN112259136A (en) 2021-01-22
CN112259136B true CN112259136B (en) 2021-09-07

Family

ID=74263269

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011129148.7A Active CN112259136B (en) 2020-10-20 2020-10-20 Memory operation circuit and chip structure

Country Status (1)

Country Link
CN (1) CN112259136B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113316751A (en) * 2021-04-16 2021-08-27 尼奥耐克索斯有限私人贸易公司 Low-loss operation circuit and operation method thereof
CN117437944B (en) * 2023-12-20 2024-03-08 长鑫存储技术有限公司 Memory device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2842816B2 (en) * 1995-10-16 1999-01-06 日本電気アイシーマイコンシステム株式会社 Semiconductor storage device
US7286385B2 (en) * 2005-07-27 2007-10-23 International Business Machines Corporation Differential and hierarchical sensing for memory circuits
JP2007280505A (en) * 2006-04-06 2007-10-25 Toshiba Corp Semiconductor memory device
US9378780B1 (en) * 2015-06-16 2016-06-28 National Tsing Hua University Sense amplifier
CN109902822B (en) * 2019-03-07 2021-04-06 北京航空航天大学合肥创新研究院 Memory computing system and method based on Sgimenk track storage
CN110414677B (en) * 2019-07-11 2021-09-03 东南大学 Memory computing circuit suitable for full-connection binarization neural network
CN111341363B (en) * 2020-02-19 2021-11-23 中山大学 STT-MTJ (spin transfer torque-magnetic tunnel junction) based storage and calculation integrated system, chip and control method
CN111429956B (en) * 2020-03-11 2022-04-05 浙江大学 Multi-mode calculable SRAM unit circuit and control method thereof
CN111724840B (en) * 2020-04-29 2022-05-17 福州大学 Circuit based on magnetic tunnel junction and device based on magnetic tunnel junction

Also Published As

Publication number Publication date
CN112259136A (en) 2021-01-22

Similar Documents

Publication Publication Date Title
US7502273B2 (en) Two-port SRAM with a high speed sensing scheme
US8116149B2 (en) Circuit and method for small swing memory signals
US7613032B2 (en) Semiconductor memory device and control method thereof
WO2006121531A1 (en) Dual-port static random access memory having improved cell stability and write margin
CN112259136B (en) Memory operation circuit and chip structure
US8693264B2 (en) Memory device having sensing circuitry with automatic latching of sense amplifier output node
CN112863571A (en) Near-threshold ultralow-leakage latch type memory unit and read-write control circuit thereof
CN111433848A (en) Input buffer circuit
JPH09106677A (en) Row decoder with level converter
US8400820B2 (en) Adjustable impedance SRAM memory device
CN104637532A (en) SRAM storage unit array, SRAM memory and control method thereof
US7821817B2 (en) Semiconductor storage device
CN114093400B (en) Low-leakage single-bit memory computing unit and device
US7136317B1 (en) DRAM with self-resetting data path for reduced power consumption
CN213519272U (en) Reading circuit of memory
US8837244B2 (en) Memory output circuit
CN114093396A (en) Data reading method and reading circuit of memory
US8675427B2 (en) Implementing RC and coupling delay correction for SRAM
US6836446B2 (en) Semiconductor memory device
CN105336360A (en) Control circuit of SRAM array and SRAM
CN112259137B (en) Memory operation circuit and chip structure
CN116631473B (en) Memory unit, memory, electronic product and data writing method
CN212724727U (en) Wide voltage SRAM timing tracking circuit
KR100655810B1 (en) Semiconductor apparatus having memory
CN116913342B (en) Memory circuit with in-memory Boolean logic operation function, and module and chip thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Industrial incubation-3-8, North 2-204, No. 18, Haitai West Road, Huayuan Industrial Zone, Binhai New Area, Tianjin 300450

Applicant after: Haiguang Information Technology Co., Ltd

Address before: 100082 industrial incubation-3-8, North 2-204, 18 Haitai West Road, Huayuan Industrial Zone, Haidian District, Beijing

Applicant before: Haiguang Information Technology Co., Ltd

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant