CN212724727U - Wide voltage SRAM timing tracking circuit - Google Patents

Abstract

The invention provides a wide-voltage SRAM timing tracking circuit, and belongs to the technical field of special integrated circuit design. The discharge switching operation with the time sequence tracking capability is realized by adopting the discharge switching module and the configurable SRAM time sequence logic module, the copy bit lines are controlled to discharge in turn by enabling the copy word lines in turn, and therefore a periodic clock pulse signal is generated, and the period of the signal is the sum of the discharge delays of the copy bit lines. The wide-voltage SRAM timing tracking circuit provided by the invention effectively reduces SAE enabling delay variation of the sense amplifier and improves the process deviation resistance of the circuit; the discharge switching module dynamically adjusts the word line voltage of the copy unit, and the process deviation resistance of the circuit is further improved; the discharge switching module can detect constant discharge threshold voltage and improve the voltage tracking performance of the circuit.

Description

Wide voltage SRAM timing tracking circuit

Technical Field

The invention belongs to the technical field of special integrated circuit design, and particularly relates to a wide-voltage SRAM timing tracking circuit.

Background

With the advent of the mobile internet era, the market has placed ever higher demands on the processing power and endurance of mobile devices. An embedded Static Random Access Memory (SRAM) is one of mainstream memories of a mobile processor chip, and in order to achieve two design goals of high performance and low power consumption, a wide voltage SRAM design with a low to near threshold region is gradually becoming a research hotspot in the industry. The timing tracking circuit is one of the key modules of the embedded SRAM, and determines the performance and stability of the SRAM. However, the ever-decreasing operating voltages and ever-shrinking process nodes introduce significant process variation, making wide voltage SRAM timing tracking circuit designs a significant design challenge.

The wide voltage SRAM timing tracking circuit design has two problems: firstly, as the power supply voltage is reduced, the delay variation (SAE) caused by local process variation is increased sharply, and the read performance of the SRAM is deteriorated. Secondly, the design margins under different voltages are different, and the voltage tracking performance of the traditional copy bit line circuit is poor. A discharge switching type time sequence tracking technology suitable for a wide voltage SRAM and a circuit structure of a discharge switching module are provided in a broad voltage SRAM time sequence tracking circuit research and implementation thesis of 2018 of southeast university, the circuit adopts a bilateral symmetry structure, mutual influence between the level of a node m in a left circuit structure and the level of a node n in a right circuit structure is achieved, accordingly, cyclic turnover of internal signals in a periodic mode is achieved, and the process deviation resistance and the voltage tracking performance of the circuit are improved. However, the circuit structure of the discharge switching module is complex, and the enabling of the copy word line needs to be realized through mutual influence between node voltages, so that the risk of time delay caused by the process is also promoted. Therefore, it is necessary to design an SRAM timing tracking circuit with a simple and clear circuit structure and a discharge switching capability to improve the process deviation resistance and the voltage tracking performance of the circuit.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a wide-voltage SRAM (static random access memory) timing tracking circuit, which adopts a discharge switching module and a configurable SRAM timing logic module to realize discharge switching operation with timing tracking capability, effectively reduces the enabling delay variation of a sense amplifier SAE (sense amplifier enable) and improves the anti-process deviation capability of the circuit; the discharge switching module dynamically adjusts the word line voltage of the copy unit, and the process deviation resistance of the circuit is further improved; the discharge switching module can detect constant discharge threshold voltage and improve the voltage tracking performance of the circuit.

In order to solve the technical problems, the invention provides the following technical scheme:

the invention provides a wide voltage SRAM timing tracking circuit which is suitable for a copy bit line discharge circuit, wherein the copy bit line discharge circuit takes a first copy word line and a second copy word line as discharge control signals, so that the first copy bit line and the second copy bit line are discharged in turn through the copy bit line discharge circuit. The timing tracking circuit includes: the device comprises a discharge switching module and a configurable SRAM sequential logic module.

The discharging switching module takes a start signal, a first copy bit line and a second copy bit line as input signals, and takes a clock pulse, a first copy word line and a second copy word line as output signals.

The discharge switching module includes: the dynamic random access memory comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, a first NAND gate, a first dynamic circuit and a second dynamic circuit.

Furthermore, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all P-type MOS tubes, and the first NMOS tube, the second NMOS tube and the third NMOS tube are all N-type MOS tubes.

Further, the first nand gate is a two-input nand gate.

The source electrode of the first PMOS tube is connected with working voltage, the grid electrode of the first PMOS tube and the input end of the first phase inverter are both connected with a first pre-charge signal, and the drain electrode of the first PMOS tube and the grid electrode of the third PMOS tube are both connected with a first copy bit line; the source electrode of the second PMOS tube is connected with working voltage, the grid electrode of the second PMOS tube and the input end of the second phase inverter are both connected with a second pre-charge signal, and the drain electrode of the second PMOS tube and the grid electrode of the fourth PMOS tube are both connected with a second copy bit line; the source electrode of the third PMOS tube is connected with working voltage, and the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the third NMOS tube are connected to the same point; the source electrode of the fourth PMOS tube is connected with working voltage, and the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube and the input end of the third inverter are connected to the same point; a source electrode of the fifth PMOS tube and a source electrode of the sixth PMOS tube are both connected with working voltage, a grid electrode of the fifth PMOS tube is connected with the output end of the third phase inverter, a grid electrode of the sixth PMOS tube is connected with a start signal, and a drain electrode of the fifth PMOS tube, a drain electrode of the sixth PMOS tube and a drain electrode of the third NMOS tube are connected to a node A; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected with the output end of the second phase inverter, and the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is grounded; the first input end of the first NAND gate is connected with a start signal, the second input end of the first NAND gate, the input end of the sixth inverter and the output end of the seventh inverter are connected with a node A, and the output end of the first NAND gate, the input end of the fourth inverter and the output end of the fifth inverter are connected with a node B; the output end of the fourth inverter is connected with the first copy word line; the output end of the fifth inverter is connected with the first pre-charging signal; the output end of the sixth inverter is connected with the second copy word line; the output end of the seventh inverter is connected with the second pre-charging signal; the first input end of the first dynamic circuit and the first input end of the second dynamic circuit are both connected with a start signal, the second input end of the first dynamic circuit is connected with a node B, and the output end of the first dynamic circuit is connected with the source electrode of a PMOS tube in the fourth phase inverter; the second input end of the second dynamic circuit is connected with the node A, and the output end of the second dynamic circuit is connected with the source electrode of the PMOS tube in the sixth inverter; the first pre-charging signal is used as an output clock pulse of the discharging switching module after passing through the buffer.

When the sequential circuit does not start working, the starting signal is in a low level, the copy bit line discharging circuit is in a reset state, and the discharging switching module enables the first copy bit line and the second copy bit line to be charged to a high level. When the start signal is high, the discharge switching module first enables the first replica word line while making the second replica word line low, the first replica bit line is discharged, and then the second replica bit line is charged to high. When the first replica bit line is discharged, the discharge switching module makes the first replica word line become low level, and simultaneously enables the second replica word line, the second replica bit line is discharged, and then the first replica bit line is recharged to high level.

By means of the alternate cyclic discharging, the discharging switching module generates a periodic clock pulse, and the signal period of the clock pulse is the sum of the time delay of the first copy bit line and the second copy bit line which are discharged once respectively.

The configurable SRAM sequential logic module takes the clock pulse output by the discharge switching module as a clock signal of the sequential logic module, and outputs a sensitive amplifier signal and a word line signal. The configurable SRAM sequential logic module comprises: a single pulse generating circuit and a pulse shifting circuit. The single pulse generating circuit uses a clock pulse as a clock signal of the circuit, and the output signal is a pulse signal whose high-level pulse width coincides with the period of the clock pulse. The input signal of the pulse shift circuit is a pulse signal, and a sense amplifier signal and a word line signal are generated and output in a pure shift register mode.

The single pulse generating circuit includes: the first register, the second register, the eighth inverter and the first AND gate.

Further, the first and gate is a two-input and gate.

The data input end of the first register is connected with the working voltage, the data output end of the first register is connected with the data input end of the second register and the first input end of the first AND gate, and the clock pulse is the clock signal of the first register and the second register; the data output end of the second register is connected with the input end of the eighth inverter, the output end of the eighth inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate outputs a pulse signal.

The pulse shift circuit includes: the register comprises a configuration circuit, a register module, a first OR gate, a third register and a fourth register.

Further, the first or gate is a two input or gate.

The register module is composed of 32 registers connected in series. The pulse signal is an input signal of the register module, the clock pulse is a clock signal of the register module, the first output signal, the second output signal and the … … thirty-second output signal are output signals of the register module, and the output signals are input signals of the configuration circuit.

The configuration circuit is composed of transmission gates, selects any one of the first output signal, the second output signal and the … … thirty-second output signal as the configuration signal through the configuration signal, and is respectively input to the data input end of the third register and the first input end of the first OR gate through the configuration circuit. The clock pulse is the clock signal of the third register, and the output signal of the third register is the sense amplifier signal. The inverse signal of the word line signal is connected to the data input end of the fourth register, the second input end of the first OR gate is connected to the pulse signal, the output signal of the first OR gate is the clock signal of the fourth register, and the output signal of the fourth register is the word line signal.

The single pulse generating circuit generates a pulse signal with the same period as a clock pulse, and the pulse signal is input into the pulse shifting circuit, and the pulse shifting circuit generates a sensitive amplifier signal and a word line signal in a pure shift register mode. In the register module of the pulse shift circuit, because no additional combinational logic exists between the shift registers, the Setup timing violation does not occur. The configuration circuit selects the number of the shift registers in the register module to control the enabling time of the word line signal. The configuration circuit is composed of transmission gates, selects any one of the first output signal, the second output signal and the … … thirty-second output signal through the configuration signal and outputs the selected signal, wherein the output signal is the configuration signal. Therefore, when the number of the selected shift registers of the configuration circuit is M, the enabling time of the word line signal is M clock pulse periods, the sense amplifier signal is enabled within one clock pulse period after the word line signal is turned off, and the delay of the sense amplifier signal is 1 clock pulse period. By generating periodic clock pulses, the original asynchronous SRAM time sequence design is synchronized and digitized, various configurable pulse signals can be flexibly designed, the enabling time of each signal can be accurately controlled, and the problem of overlapping of control signals in the asynchronous SRAM time sequence design can be avoided.

The discharge switching module provided by the invention adopts the first dynamic circuit to dynamically reduce the word line voltage of the first copy unit, and adopts the second dynamic circuit to dynamically reduce the word line voltage of the second copy unit.

The first dynamic circuit has two input ends and one output end, the first input end is connected with the start signal, the second input end is connected with the input end of the fourth phase inverter, and the output end is connected with the source electrode of the P-type MOS tube in the fourth phase inverter.

The second dynamic circuit has two input ends and an output end, the first input end is connected with the start signal, the second input end is connected with the input end of the sixth phase inverter, and the output end is connected with the source electrode of the P-type MOS tube in the sixth phase inverter.

The first dynamic circuit and the second dynamic circuit have the same circuit configuration, and each dynamic circuit includes: the ninth inverter, the second NAND gate, the seventh PMOS tube, the eighth PMOS tube, the fourth NMOS tube, the first capacitor, the second capacitor and the third capacitor.

Furthermore, the seventh PMOS tube and the eighth PMOS tube are both P-type MOS tubes, and the fourth NMOS tube is an N-type MOS tube.

Further, the second nand gate is a two-input nand gate.

The source electrode of the seventh PMOS tube is connected with the working voltage, the drain electrode of the seventh PMOS tube is connected with the output end of the dynamic circuit, and the grid electrode of the seventh PMOS tube is connected with the output end of the ninth phase inverter; the source electrode of the eighth PMOS tube is connected with one end of the first capacitor and the drain electrode of the seventh PMOS tube, and the other end of the first capacitor is grounded; the drain electrode of the eighth PMOS tube is connected with one end of the second capacitor and the drain electrode of the fourth NMOS tube, and the other end of the second capacitor is grounded; the grid of the eighth PMOS tube and the grid of the fourth NMOS tube are connected with the output end of the second NAND gate; the source electrode of the fourth NMOS tube is grounded; the input end of the ninth inverter is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with a start signal; the second input end of the second NAND gate is the second input end of the dynamic circuit and is connected with the input end of the phase inverter which takes the copy word line as an output signal; one end of the third capacitor is connected with the output end of the inverter which takes the copy word line as an output signal, and the other end of the third capacitor is grounded.

Furthermore, the output end of the fourth inverter and one end of the third capacitor which are connected with the first dynamic circuit are both connected with the first copy word line.

Furthermore, the output end of the sixth inverter connected with the second dynamic circuit and one end of the third capacitor are both connected with the second copy word line.

When the starting signal is in a low level, the whole time sequence module is in a reset state, and the power supply voltage of a fourth inverter taking the first copy word line as an output signal and the power supply voltage of a sixth inverter taking the second copy word line as an output signal are both charged to the working power supply voltage; when the start signal is high, the timing module starts to operate.

The first dynamic circuit works specifically as follows: when the first copy word line is enabled, the first copy word line voltage is lower than the working power supply voltage; when the first copy word line is closed, the power supply voltage of the fourth inverter is charged to the working power supply voltage, and the whole timing module returns to the initial state.

The second dynamic circuit works specifically as follows: when the second copy word line is enabled, the second copy word line voltage is lower than the working power supply voltage; when the second copy word line is turned off, the power supply voltage of the sixth inverter is charged to the working power supply voltage, and the whole timing module returns to the initial state.

The discharge switching module provided by the invention is also provided with a first copy bit line constant discharge threshold voltage detection circuit and a second copy bit line constant discharge threshold voltage detection circuit.

Further, the first replica bit line constant discharge threshold voltage detection circuit includes: the PMOS transistor comprises a first PMOS transistor, a third PMOS transistor, a first NMOS transistor and a first phase inverter. When the first copy bit line and the first precharge signal are changed into high level, the first copy bit line starts to discharge, when the first copy bit line discharges to the threshold voltage of the third PMOS tube, the third PMOS tube is conducted, so that the drain electrode of the third PMOS tube is changed into high level, and the detection threshold value of the first copy bit line is the threshold voltage of the third PMOS tube.

Further, the second replica bit line constant discharge threshold voltage detection circuit includes: a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a second phase inverter. When the second copy bit line and the second precharge signal are changed to high level, the second copy bit line starts to discharge, and when the second copy bit line discharges to the threshold voltage of the fourth PMOS tube, the fourth PMOS tube is conducted, so that the drain electrode of the fourth PMOS tube is changed to high level, and the detection threshold value of the second copy bit line is the threshold voltage of the fourth PMOS tube.

Compared with the prior art, the wide voltage SRAM timing tracking circuit provided by the invention has the following benefits:

1. the wide-voltage SRAM timing tracking circuit provided by the invention has a discharge switching type timing tracking circuit structure, discharges through K copied discharge units, effectively reduces the delay variation of Sense Amplifier Enable (SAE), and improves the process deviation resistance of the circuit. At 0.6V TT25 ℃, when the K value is 32, the time delay change sigma of SAE is reduced to 0.55ns from 1.88ns of the traditional scheme, and the time delay change sigma is reduced by 70%.

2. A dynamic circuit is designed in the discharge switching module to dynamically adjust the word line voltage of the copy unit, so that the influence of an extra inverter delay chain is eliminated, and extra delay deviation is not introduced, thereby improving the process change resistance.

3. A constant discharge threshold voltage detection circuit is designed in the discharge switching module, so that discharge voltage differences under different voltages are basically consistent, design redundancy under high voltage is eliminated, and voltage tracking performance is improved.

Drawings

Fig. 1 is a schematic diagram of a wide voltage SRAM timing tracking circuit according to the present invention.

Fig. 2 is a schematic diagram of a discharge switching type operation process of a wide voltage SRAM timing tracking circuit according to the present invention.

Fig. 3 is a circuit structure diagram and an operation waveform diagram of a discharge switching module in the wide voltage SRAM timing tracking circuit according to the present invention.

FIG. 4 is a configurable SRAM sequential logic circuit diagram in the wide voltage SRAM sequential tracking circuit of the present invention.

FIG. 5 is a diagram showing a statistical distribution of SAE delay in a conventional scheme and a wide voltage SRAM timing tracking circuit according to the present invention.

Fig. 6 is a waveform diagram of the operation of the configurable SRAM sequential logic module circuit in the wide voltage SRAM sequential tracking circuit according to the present invention.

Fig. 7 is a schematic diagram of a circuit structure for dynamically reducing the word line voltage of the replica unit in the wide voltage SRAM timing tracking circuit according to the present invention.

FIG. 8 is a waveform diagram illustrating dynamic switching of the word line voltage of the replica cell in the wide voltage SRAM timing tracking circuit according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to examples.

Example 1. The invention provides a wide voltage SRAM timing tracking circuit which is suitable for copying a bit line discharge circuit. In the preferred embodiment, the replica bit line discharge circuit adopts a traditional column-type replica bit line circuit and 128bit cells/BL, so that no additional layout area is increased, and the capacitance of the single-side bit line is completely consistent with that of the traditional scheme. Fig. 1 illustrates a circuit configuration of a discharge switching module, a configurable SRAM sequential logic module, and a replica bit line discharge circuit. Wherein, a column copy bit line discharge circuit comprises: 2K Replica bit line discharge cells (RC) and J-bank redundancy cells (Dummy Cell, DC). Each replica bitline discharge cell RC has two inputs connected to the first replica wordline WL1, a second input connected to the second replica wordline WL2, a first output connected to the first replica bitline signal RBL1, and a second output connected to the second replica bitline signal RBL 2.

As can be seen from fig. 1, the replica bit line discharge circuit takes the first replica word line WL1 and the second replica word line WL2 as discharge control signals, so that the first replica bit line RBL1 and the second replica bit line RBL2 are alternately discharged by the replica bit line discharge circuit.

In the preferred embodiment, the second input terminals of the 1 st to K-th replica bit line discharge cells RC are set to be connected to the low level, that is, the second replica word line WL2 is connected to the low level; the first input terminal of the K +1 th to 2K th replica bit line discharging unit RC is set to be connected to a low level, i.e., the first replica word line WL1 is connected to a low level. The word line signals input to the remaining J groups of redundancy cells DC are all constantly at a low level.

Further, each of the replica bit line discharge cells RC is a word line separation type discharge cell. The word line separation type discharge cell adopts a '6T' structure. The word line separation type discharge cell has the first replica word line WL1 separated from the second replica word line WL 2. The internal nodes of the replica discharge cells RC are all connected to a high level, and the discharge path of the first replica bit line RBL1 and the discharge path of the second replica bit line RBL2 do not interfere with each other.

As shown in fig. 1, the discharging switching module takes a START signal START, a first replica bit line RBL1 and a second replica bit line RBL2 as input signals, and takes a clock pulse CK, a first replica word line WL1 and a second replica word line WL2 as output signals.

The operation steps of the discharge switching module are shown in fig. 2. When the sequential circuit does not work, the starting signal is in a low level, the copy bit line discharging circuit is in a reset state, and the discharging switching module enables the first copy bit line RBL1 and the second copy bit line RBL2 to be charged to a high level. The replica bit line discharge circuit is in a reset state, and the start signal is at a low level. First, when the START signal START is high, the discharging switching module first enables the first copy word line WL1 while the second copy word line WL2 becomes low, and the first copy bit line RBL1 is discharged through the 1 st to K-th copy bit line discharging units RC while the second copy bit line RBL2 is charged to high. In the second step, when the discharge of the first copy bit line RBL1 is completed, the discharge switching module makes the first copy word line WL1 go low while enabling the second copy word line WL2, and the second copy bit line RBL2 is discharged through the K +1 th to 2K th copy bit line discharge cells RC while the first copy bit line RBL1 is recharged to high. The third step is similar to the first step, and the fourth step is similar to the second step. Therefore, the discharge switching module generates a periodic clock pulse CK having a period of a sum of times of discharging the first replica bit line RBL1 and the second replica bit line RBL2 once each.

Example 2. The circuit of the discharge switching model proposed by the present invention is shown on the left side of fig. 3.

The discharge switching module includes: the inverter comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMMOS tube P6, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a first inverter INV _1, a second inverter INV _2, a third inverter INV _3, a fourth inverter INV _4, a fifth inverter INV _5, a sixth inverter INV _6, a seventh inverter INV _7, a first NAND gate NAND _1, a first dynamic circuit and a second dynamic circuit.

Furthermore, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are all P-type MOS transistors, and the first NMOS transistor N1, the second NMOS transistor N2 and the third NMOS transistor N3 are all N-type MOS transistors.

Further, the first NAND gate NAND _1 is a two-input NAND gate.

The source of the first PMOS transistor P1 is connected to a working voltage, the gate of the first PMOS transistor P1 and the input terminal of the first inverter INV _1 are both connected to the first precharge signal PRE1, and the drain of the first PMOS transistor P1 and the gate of the third PMOS transistor P3 are both connected to the first replica bit line RBL 1; the source of the second PMOS transistor P2 is connected to the operating voltage, the gate of the second PMOS transistor P2 and the input of the second inverter INV _2 are both connected to the second precharge signal PRE2, and the drain of the second PMOS transistor P2 and the gate of the fourth PMOS transistor P4 are both connected to the second replica bit line RBL 2; the source electrode of the third PMOS tube P3 is connected with the working voltage, and the drain electrode of the third PMOS tube P3, the drain electrode of the first NMOS tube N1 and the gate electrode of the third NMOS tube N3 are connected to the same point; the source electrode of the fourth PMOS tube P4 is connected with the working voltage, and the drain electrode of the fourth PMOS tube P4, the drain electrode of the second NMOS tube N2 and the input end of the third inverter INV _3 are connected to the same point; a source electrode of the fifth PMOS tube P5 and a source electrode of the sixth PMOS tube P6 are both connected with working voltage, a grid electrode of the fifth PMOS tube P5 is connected with an output end of the third inverter INV _3, a grid electrode of the sixth PMOS tube P6 is connected with a start signal, and a drain electrode of the fifth PMOS tube P5, a drain electrode of the sixth PMOS tube P6 and a drain electrode of the third NMOS tube N3 are connected with a node A; the grid electrode of the first NMOS tube N1 is connected with the output end of the first inverter INV _1, and the source electrode of the first NMOS tube N1 is grounded; the grid electrode of the second NMOS tube N2 is connected with the output end of the second inverter INV _2, and the source electrode of the second NMOS tube N2 is grounded; the source electrode of the third NMOS tube N3 is grounded; a first input end of the first NAND gate NAND _1 is connected with the START signal START, a second input end of the first NAND gate NAND _1, an input end of the sixth inverter INV _6 and an output end of the seventh inverter INV _7 are connected to the node a, and an output end of the first NAND gate NAND _1, an input end of the fourth inverter INV _4 and an output end of the fifth inverter INV _5 are connected to the node B; the output end of the fourth inverter INV _4 is connected to the first copy word line WL 1; the output end of the fifth inverter INV _5 is connected with the first PRE-charge signal PRE 1; the output end of the sixth inverter INV _6 is connected to the second copy word line WL 2; the output end of the seventh inverter INV _7 is connected to the second precharge signal PRE 2; a first input end of the first dynamic circuit and a first input end of the second dynamic circuit are both connected with a START signal START, a second input end of the first dynamic circuit is connected with a node B, and an output end of the first dynamic circuit is connected with a source electrode of a PMOS (P-channel metal oxide semiconductor) tube in the fourth inverter INV _ 4; the second input end of the second dynamic circuit is connected with the node A, and the output end of the second dynamic circuit is connected with the source electrode of the PMOS tube in the sixth inverter INV _ 6; the first precharge signal PRE1 passes through the buffer and then serves as the output clock CK of the discharge switching module.

In the preferred embodiment, the operation waveform of the discharging switching module is shown on the right side of fig. 3. First, when the replica bit line discharge circuit does not START operating, the START signal START is at a low level, the replica bit line discharge circuit is in a reset state, and both the first replica bit line RBL1 and the second replica bit line RBL2 are charged to a high level, which includes the following specific processes:

when the START signal START is low, the node B is high, the first replica word line WL1 output from the fourth inverter INV _4 and the first precharge signal PRE1 output from the fifth inverter are low, the sixth PMOS transistor P6 is turned on, so that the node a is high, and the second replica word line WL2 output from the sixth inverter INV _6 and the second precharge signal PRE2 output from the seventh inverter are also low. When the first PRE-charge signal PRE1 and the second PRE-charge signal PRE2 are both low, the first PMOS transistor P1 and the second PMOS transistor P2 are both turned on, and the first replica bit line RBL1 and the second replica bit line RBL2 are both charged to high.

After the discharging switching module makes the first replica bit line RBL1 and the second replica bit line RBL2 both charge to a high level, when the START signal START is at a high level, the discharging switching module STARTs to operate, and the specific steps are as follows:

in step S1, the first replica word line WL1 is enabled, the first replica bit line RBL1 starts discharging, the first replica word line WL1 is turned off, and the first replica bit line RBL1 ends discharging:

the node a is high, the first copy word line WL1 output through the first NAND gate NAND _1 and the fourth inverter INV _4 is high, and the first copy bit line RBL1 is discharged;

when the first replica bit line RBL1 discharges to the threshold voltage of the third PMOS transistor P3, the third PMOS transistor P3 is turned on, so that the drain of the third PMOS transistor P3 becomes high, the third NMOS transistor N3 is turned on, so that the node a becomes low, and the second replica word line WL2 is enabled;

meanwhile, the node a becomes low level so that the first copy word line WL1 is low level, the first copy bit line RBL1 ends discharging, and the first copy bit line RBL1 is recharged to high level.

In step S2, the second replica word line WL2 is enabled, the second replica bit line RBL2 starts discharging, the second replica word line WL2 is turned off, and the second replica bit line RBL2 ends discharging:

the second replica word line WL2 is high, and the second replica bit line RBL2 discharges;

when the second replica bit line RBL2 discharges to the threshold voltage of the fourth PMOS transistor P4, the fourth PMOS transistor P4 is turned on, so that the drain of the fourth PMOS transistor P4 becomes high, at this time, the fifth PMOS transistor P5 is turned on, so that the node a becomes high, at this time, the first replica word line WL1 is enabled;

meanwhile, the node a becomes high level so that the second replica word line WL2 is low level, the second replica bit line RBL2 ends discharging, and the second replica bit line RBL2 is recharged to high level.

Through steps S1 and S2, discharge rotation switching is realized, the discharge switching module generates a periodic clock pulse, and the signal period of the clock pulse CK is the sum of the delay times of discharging the first replica bit line RBL1 and the second replica bit line RBL2 once each.

As can be seen from the signal waveforms shown in fig. 3, the discharge switching pattern implements pull-down and pull-UP control of the level of the node a by charging and discharging the first replica bit line RBL1 and the second replica bit line RBL2, i.e., alternation of the a _ DN waveform and the a _ UP waveform in the figure, so that the internal signal is cyclically inverted in a periodic manner. By means of this alternate cyclic discharge, the discharge switching module generates a periodic clock pulse CK. Since the first replica bit line RBL1 and the second replica bit line RBL2 are both discharged simultaneously by K replica discharge cells RC, a delay deviation of the discharge of the first replica bit line RBL1 and the discharge of the second replica bit line RBL2 is greatly reduced, and a signal period of the clock pulse CK is a sum of delays of the discharge of the first replica bit line RBL1 and the discharge of the second replica bit line RBL2 each once, so that the delay deviation of the clock pulse CK is also greatly reduced.

Example 3. The circuit structure of the configurable SRAM sequential logic module according to the present invention is shown in fig. 4. The configurable SRAM sequential logic module takes the clock pulse CK output by the discharge switching module as a clock signal of the sequential logic module, and outputs a sense amplifier signal SAE and a word line signal WL. The configurable SRAM sequential logic module comprises: a single pulse generating circuit and a pulse shifting circuit. The single PULSE generating circuit takes the clock PULSE CK as a clock signal of the circuit, the output signal is a PULSE signal PULSE, and the high-level PULSE width of the PULSE signal PULSE is consistent with the period of the clock PULSE CK. The input signal of the pulse shift circuit is a pulse signal CK, and a sense amplifier signal SAE and a word line signal WL are generated and output in a pure shift register mode.

The single pulse generating circuit includes: the first register R _1, the second register R _2, the eighth inverter INV _8, AND the first AND gate AND _ 1.

Further, the first AND gate AND _1 is a two-input AND gate.

The data input end D of the first register R _1 is connected with the working voltage, the data output end Q of the first register R _1 is connected with the data input end D of the second register R _2 AND the first input end of the first AND gate AND _1, AND the clock pulse CK is a clock signal of the first register R _1 AND the second register R _ 2; the data output end Q of the second register R _2 is connected to the input end of the eighth inverter INV _8, the output end of the eighth inverter INV _8 is connected to the second input end of the first AND gate AND _1, AND the output end of the first AND gate AND _1 outputs the PULSE signal PULSE.

The pulse shift circuit includes: the register comprises a configuration circuit, a register module, a first OR gate OR _1, a third register R _3 and a fourth register R _ 4.

Further, the first OR gate OR _1 is a two-input OR gate.

The register module is composed of 32 registers connected in series. The PULSE signal PULSE is an input signal of the register module, the clock PULSE CK is a clock signal of the register module, and the first output signal Q1, the second output signal Q2, … …, the thirty-second output signal Q32 are output signals of the register module, which serve as input signals of the configuration circuit.

The configuration circuit is constituted by a transmission gate, selects any one of the first output signal Q1, the second output signal Q2, … …, the thirty-second output signal Q32 as the configuration signal Conf _ out by the configuration signal, and is input to the data input terminal D of the third register R _3 and the first input terminal of the first OR gate OR _1 by the configuration circuit, respectively. The clock CK is a clock signal of the third register R _3, and an output signal of the third register R _3 is a sense amplifier signal SAE. The inverse signal of the word line signal WL is connected to the data input terminal of the fourth register R _4, the second input terminal of the first OR gate OR _1 is connected to the pulse signal, the output signal of the first OR gate OR _1 is the clock signal of the fourth register R _4, and the output signal of the fourth register R _4 is the word line signal WL.

The single PULSE generating circuit generates a PULSE signal PULSE with the high level PULSE width same as the period of the clock PULSE CK, and inputs the PULSE signal PULSE into the PULSE shifting circuit, and the PULSE shifting circuit adopts a pure shift register mode to generate a sense amplifier signal SAE and a word line signal WL. In the register module of the pulse shift circuit, because no additional combinational logic exists between the shift registers, the Setup timing violation does not occur. The number of the shift registers in the register module is selected by the configuration circuit to control the enabling time of the word line signal WL. The configuration circuit is composed of transmission gates, and selects and outputs any one of the first output signal Q1, the second output signal Q2, … …, and the thirty-second output signal Q32 by a configuration signal, which is the configuration signal Conf _ out. Therefore, when the number of the selected shift registers of the configuration circuit is M, the enable time of the word line signal WL is M clock CK cycles, the sense amplifier signal SAE is enabled in one clock CK cycle after the word line signal WL is turned off, the delay of the sense amplifier signal SAE is 1 clock CK cycle, the waveform of the sense amplifier signal SAE is shown in fig. 5, and the operating waveform of the configuration circuit is shown in fig. 6. By generating the periodic clock pulse CK, the original asynchronous SRAM time sequence design is synchronized and digitized, various configurable pulse signals can be flexibly designed, the enabling time of each signal can be accurately controlled, and the problem of overlapping of control signals in the asynchronous SRAM time sequence design can be avoided.

Example 4. The discharge switching module provided by the invention adopts the first dynamic circuit to dynamically reduce the word line voltage of the first copy unit, adopts the second dynamic circuit to dynamically reduce the word line voltage of the second copy unit, and has a structure shown in fig. 7.

The first dynamic circuit has two input ends and an output end, the first input end is connected with the START signal START, the second input end is connected with the input end of the fourth inverter INV _4, and the output end is connected with the source electrode of the PMOS tube in the fourth inverter INV _ 4.

The second dynamic circuit has two input ends and an output end, the first input end is connected with the START signal START, the second input end is connected with the input end of the sixth inverter INV _6, and the output end is connected with the source electrode of the PMOS tube in the sixth inverter INV _ 6.

The first dynamic circuit and the second dynamic circuit have the same circuit configuration, and each dynamic circuit includes: the third inverter INV _9, the second NAND gate NAND _2, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the fourth NMOS transistor N4, the first capacitor C1, the second capacitor C2, and the third capacitor C4.

Furthermore, the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are both PMOS transistors, and the fourth NMOS transistor N4 is an NMOS transistor.

Further, the second NAND gate NAND _2 is a two-input NAND gate.

The source electrode of the seventh PMOS tube P7 is connected with the working voltage, the drain electrode of the seventh PMOS tube P7 is connected with the output end of the dynamic circuit, and the grid electrode of the seventh PMOS tube P7 is connected with the output end of the ninth inverter INV _ 9; the source electrode of the eighth PMOS tube P8 is connected with one end of the first capacitor C1 and the drain electrode of the seventh PMOS tube P7, and the other end of the first capacitor C1 is grounded; the drain electrode of the eighth PMOS transistor P8 is connected to one end of the second capacitor C2 and the drain electrode of the fourth NMOS transistor N4, and the other end of the second capacitor C2 is grounded; the gate of the eighth PMOS transistor P8 and the gate of the fourth NMOS transistor N4 are connected to the output terminal of the second NAND gate NAND _ 2; the source electrode of the fourth NMOS transistor N4 is grounded; the input end of the ninth inverter INV _9 is connected to the output end of the second NAND gate NAND _ 2; the first input end of the second NAND gate NAND _2 is connected with a START signal START; the second input end of the second NAND gate NAND _2 is the second input end of the dynamic circuit and is connected with the input end of the inverter which takes the copy word line as an output signal; one end of the third capacitor C3 is connected to the output end of the inverter which uses the copy word line as the output signal, and the other end of the third capacitor C3 is connected to the ground.

Further, the output end of the fourth inverter INV _4 and one end of the third capacitor C3, which are connected to the first dynamic circuit, are both connected to the first replica word line WL 1;

further, an output end of the sixth inverter INV _6 and one end of the third capacitor C3, which are connected to the second dynamic circuit, are both connected to the second replica word line WL 2.

When the START signal START is low, the entire timing module is in a reset state, the power supply voltage of the fourth inverter INV _4 with the first replica word line WL1 as an output signal and the sixth inverter INV _6 with the second replica word line WL2 as an output signal are charged to high level, and simultaneously the first capacitor C1 is charged and the second capacitor C2 is discharged through the fourth NMOS transistor N4; when the start signal is high, the timing module starts to operate.

Taking the first dynamic circuit as an example, the working condition of the dynamic circuit is specifically explained: when the first replica word line WL1 is enabled, the input WLB1 of the fourth inverter INV _4 is at low level, the output of the second NAND gate NAND _2 is at high level and turns off the seventh PMOS transistor P7, meanwhile, the eighth PMOS transistor P8 is turned on and the fourth nmos transistor N4 is turned off, at this time, since no charge is stored in the second capacitor C2 and the third capacitor C3, charge sharing is performed among the first capacitor C1, the second capacitor C2 and the third capacitor C3, so that the supply voltage of the fourth inverter INV _4 is lower than the operating supply voltage, and the voltage of the first replica word line 1 is lower than the operating supply voltage; when the first replica word line WL1 is at a low level, the WLB1 of the fourth inverter INV _4 is at a high level, the NAND gate NAND _2 outputs at a low level and turns on the seventh PMOS transistor P7, so that the power supply voltage of the fourth inverter INV _4 is charged to the working power supply voltage, the first capacitor C1 is charged, the second capacitor C2 and the third capacitor C3 are both discharged, and the whole timing module returns to the initial state.

The second dynamic circuit operates as the first dynamic circuit.

Fig. 8 is a waveform diagram of the discharge switching module according to the present invention for implementing dynamic switching of the word line voltage of the replica cell. The discharge switching circuit enables the first replica word line WL1 and the second replica word line WL2 alternately, when the first replica word line WL1 is enabled, the supply voltage of the fourth inverter is dynamically lowered while the supply voltage of the sixth inverter is charged to the operating power supply voltage; conversely, when the second replica word line WL2 is enabled, the supply voltage of the sixth inverter is dynamically lowered while the supply voltage of the fourth inverter is charged to the operating supply voltage. Therefore, whether the first replica word line WL1 is enabled or the second replica word line WL2 is enabled, the word line voltage is dynamically reduced from 600mV to 520 mV. The dynamic reduction principle of the first replica word line WL1 voltage and the second replica word line WL2 voltage is charge sharing, that is, the word line voltage is determined by the size ratio among the first capacitor C1, the second capacitor C2 and the third capacitor C3, so the size ratio of the first capacitor C1 and the second capacitor C2 can be adjusted to change the value of the word line voltage according to the practical application requirement.

Example 5. In the conventional circuit, the replica bit lines are connected by inverters, and the discharge voltage difference of the replica bit lines at a high voltage is different from that of the replica bit lines at a low voltage because the number of discharge cells needs to be changed to reduce the difference. Therefore, the discharging switching module provided by the invention can realize the constant discharging threshold voltage detection of the first copy bit line RBL1 and the constant discharging threshold voltage detection of the second copy bit line RBL2, so that the discharging voltage difference of the first copy bit line RBL1 and the discharging voltage difference of the second copy bit line RBL2 are kept constant under the condition of voltage change.

The first replica bit line constant discharge threshold voltage detection circuit includes: a first PMOS transistor P1, a third PMOS transistor P3, a first NMOS transistor N1, and a first inverter INV _ 1. When the first replica bit line RBL1 and the first precharge signal PRE1 become high level, the first replica bit line RBL1 starts to discharge, and when the first replica bit line RBL1 discharges to the threshold voltage of the third PMOS transistor P3, the third PMOS transistor P3 is turned on, so that the drain of the third PMOS transistor P3 becomes high level, and the discharge voltage difference of the first replica bit line RBL1 is the threshold voltage of the third PMOS transistor P3, and since the threshold voltage of the third PMOS transistor P3 does not substantially change with the voltage change, the discharge voltage difference of the first replica bit line RBL1 is constant.

The second replica bit line constant discharge threshold voltage detection circuit includes: a second PMOS transistor P2, a fourth PMOS transistor P4, a second NMOS transistor N2, and a second inverter INV _ 2. When the second replica bit line RBL2 and the second precharge signal PRE2 become high level, the second replica bit line RBL2 starts to discharge, and when the second replica bit line RBL2 discharges to the threshold voltage of the fourth PMOS transistor P4, the fourth PMOS transistor P4 is turned on, so that the drain of the fourth PMOS transistor P4 becomes high level, and the discharge voltage difference of the second replica bit line RBL2 is the threshold voltage of the fourth PMOS transistor P4, and since the threshold voltage of the fourth PMOS transistor P4 does not substantially change with the voltage change, the discharge voltage difference of the second replica bit line RBL2 is constant.

Therefore, when the voltage changes, the structure of the discharge circuit and the number of discharge units in the discharge circuit do not need to be changed, the discharge voltage difference under the high voltage is basically consistent with the discharge voltage difference under the low voltage, the design redundancy under the high voltage is eliminated, and the voltage tracking performance is improved.

The above embodiments and examples are specific supports for the technical idea of the wide voltage SRAM timing tracking circuit proposed by the present invention, and the protection scope of the present invention cannot be limited thereby, and any equivalent changes or equivalent changes made on the basis of the technical scheme according to the technical idea proposed by the present invention still belong to the protection scope of the technical scheme of the present invention.

Claims (5)

1. A wide voltage SRAM timing tracking circuit adapted to a replica bit line discharge circuit that uses a first replica word line and a second replica word line as discharge control signals to cause the first replica bit line and the second replica bit line to be alternately discharged by the replica bit line discharge circuit, the wide voltage SRAM timing tracking circuit comprising: the device comprises a discharge switching module and a configurable SRAM sequential logic module;

the discharging switching module takes a starting signal, a first copy bit line and a second copy bit line as input signals, and takes a clock pulse, a first copy word line and a second copy word line as output signals; the configurable SRAM sequential logic module takes the clock pulse output by the discharge switching module as a clock signal and takes a sensitive amplifier signal and a word line signal as output signals;

the discharge switching module includes: the dynamic transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, a first NAND gate, a first dynamic circuit and a second dynamic circuit;

furthermore, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all P-type MOS tubes, and the first NMOS tube, the second NMOS tube and the third NMOS tube are all N-type MOS tubes;

further, the first nand gate is a two-input nand gate;

the source electrode of the first PMOS tube is connected with working voltage, the grid electrode of the first PMOS tube and the input end of the first phase inverter are both connected with a first pre-charge signal, and the drain electrode of the first PMOS tube and the grid electrode of the third PMOS tube are both connected with a first copy bit line; the source electrode of the second PMOS tube is connected with working voltage, the grid electrode of the second PMOS tube and the input end of the second phase inverter are both connected with a second pre-charge signal, and the drain electrode of the second PMOS tube and the grid electrode of the fourth PMOS tube are both connected with a second copy bit line; the source electrode of the third PMOS tube is connected with working voltage, and the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the third NMOS tube are connected to the same point; the source electrode of the fourth PMOS tube is connected with working voltage, and the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube and the input end of the third inverter are connected to the same point; a source electrode of the fifth PMOS tube and a source electrode of the sixth PMOS tube are both connected with working voltage, a grid electrode of the fifth PMOS tube is connected with the output end of the third phase inverter, a grid electrode of the sixth PMOS tube is connected with a start signal, and a drain electrode of the fifth PMOS tube, a drain electrode of the sixth PMOS tube and a drain electrode of the third NMOS tube are connected to a node A; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected with the output end of the second phase inverter, and the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is grounded; the first input end of the first NAND gate is connected with a start signal, the second input end of the first NAND gate, the input end of the sixth inverter and the output end of the seventh inverter are connected with a node A, and the output end of the first NAND gate, the input end of the fourth inverter and the output end of the fifth inverter are connected with a node B; the output end of the fourth inverter is connected with the first copy word line; the output end of the fifth inverter is connected with the first pre-charging signal; the output end of the sixth inverter is connected with the second copy word line; the output end of the seventh inverter is connected with the second pre-charging signal; the first input end of the first dynamic circuit and the first input end of the second dynamic circuit are both connected with a start signal, the second input end of the first dynamic circuit is connected with a node B, and the output end of the first dynamic circuit is connected with the source electrode of a PMOS tube in the fourth phase inverter; the second input end of the second dynamic circuit is connected with the node A, and the output end of the second dynamic circuit is connected with the source electrode of the PMOS tube in the sixth inverter; the first pre-charging signal is used as an output clock pulse of the discharging switching module after passing through the buffer.

2. The wide voltage SRAM timing tracking circuit of claim 1, wherein the configurable SRAM timing logic module comprises: a single pulse generating circuit and a pulse shifting circuit;

the single-pulse generating circuit takes the clock pulse output by the discharge switching module as a clock signal of the circuit, takes the pulse signal as an output signal, and the high-level pulse width of the pulse signal is consistent with the period of the clock pulse;

the single pulse generating circuit includes: the first register, the second register, the eighth inverter and the first AND gate; the data input end of the first register is connected with the working voltage, the data output end of the first register is connected with the data input end of the second register and the first input end of the first AND gate, and the clock pulse is the clock signal of the first register and the second register; the data output end of the second register is connected with the input end of an eighth inverter, the output end of the eighth inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate outputs a pulse signal;

further, the first and gate is a two-input and gate;

the input signal of the pulse shift circuit is a pulse signal, and a sense amplifier signal and a word line signal are generated and output in a pure shift register mode;

the pulse shift circuit includes: the circuit comprises a configuration circuit, a register module, a first OR gate, a third register and a fourth register; the register module consists of 32 registers connected in series; the pulse signal is an input signal of the register module, the clock pulse is a clock signal of the register module, the first output signal, the second output signal and the … … thirty-second output signal are output signals of the register module, and the output signals are used as input signals of the configuration circuit;

further, the first or gate is a two-input or gate;

the configuration circuit is composed of transmission gates, any one of a first output signal, a second output signal and an … … thirty-second output signal is selected as a configuration signal through the configuration signal, and the configuration signal is respectively input to a data input end of the third register and a first input end of the first OR gate; the clock pulse is a clock signal of the third register, and an output signal of the third register is a sensitive amplifier signal; the inverted signal of the word line signal is connected to the input end of the fourth register, the second input end of the first OR gate is connected with the pulse signal, the output signal of the first OR gate is the clock signal of the fourth register, and the output signal of the fourth register is the word line signal.

3. The wide voltage SRAM timing tracking circuit of claim 1,

the first dynamic circuit is provided with two input ends and an output end, the first input end is connected with a start signal, the second input end is connected with the input end of the fourth phase inverter, and the output end is connected with the source electrode of a PMOS tube in the fourth phase inverter;

the second dynamic circuit is provided with two input ends and an output end, the first input end is connected with a start signal, the second input end is connected with the input end of the sixth phase inverter, and the output end is connected with the source electrode of a PMOS tube in the sixth phase inverter;

the first dynamic circuit and the second dynamic circuit have the same circuit configuration, and each dynamic circuit includes: the ninth inverter, the second NAND gate, the seventh PMOS tube, the eighth PMOS tube, the fourth NMOS tube, the first capacitor, the second capacitor and the third capacitor;

further, the second nand gate is a two-input nand gate;

the source electrode of the seventh PMOS tube is connected with the working voltage, the drain electrode of the seventh PMOS tube is connected with the output end of the dynamic circuit, and the grid electrode of the seventh PMOS tube is connected with the output end of the ninth phase inverter; the source electrode of the eighth PMOS tube is connected with one end of the first capacitor and the drain electrode of the seventh PMOS tube, and the other end of the first capacitor is grounded; the drain electrode of the eighth PMOS tube is connected with one end of the second capacitor and the drain electrode of the fourth NMOS tube, and the other end of the second capacitor is grounded; the grid of the eighth PMOS tube and the grid of the fourth NMOS tube are connected with the output end of the second NAND gate; the source electrode of the fourth NMOS tube is grounded; the input end of the ninth inverter is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with a start signal; the second input end of the second NAND gate is the second input end of the dynamic circuit and is connected with the input end of the phase inverter which takes the copy word line as an output signal; one end of the third capacitor is connected with the output end of the inverter which takes the copy word line as an output signal, and the other end of the third capacitor is grounded;

furthermore, the output end of a fourth inverter connected with the first dynamic circuit and one end of a third capacitor are both connected with the first copy word line;

furthermore, the output end of the sixth inverter connected with the second dynamic circuit and one end of the third capacitor are both connected with the second copy word line.

4. The wide voltage SRAM timing tracking circuit of claim 1 wherein the discharge switching module has a first replica bit line constant discharge threshold voltage detection circuit comprising: the PMOS transistor comprises a first PMOS transistor, a third PMOS transistor, a first NMOS transistor and a first phase inverter.

5. The wide voltage SRAM timing tracking circuit of claim 1,

the discharge switching module has a second replica bit line constant discharge threshold voltage detection circuit comprising: a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a second phase inverter.

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