CN111445936A

CN111445936A - Wide voltage SRAM timing tracking circuit

Info

Publication number: CN111445936A
Application number: CN202010500489.4A
Authority: CN
Inventors: 王镇; 顾东志; 杨亮亮
Original assignee: Nanjing Bosin Electronic Technology Co ltd
Current assignee: Nanjing Bosin Electronic Technology Co ltd
Priority date: 2019-08-13
Filing date: 2020-06-04
Publication date: 2020-07-24

Abstract

The invention provides a wide-voltage SRAM timing tracking circuit, and belongs to the technical field of special integrated circuit design. The discharge switching operation with the time sequence tracking capability is realized by adopting the discharge switching module and the configurable SRAM time sequence logic module, the copy bit lines are controlled to discharge in turn by enabling the copy word lines in turn, and therefore a periodic clock pulse signal is generated, and the period of the signal is the sum of the discharge delays of the copy bit lines. The wide-voltage SRAM timing tracking circuit provided by the invention effectively reduces SAE enabling delay variation of the sense amplifier and improves the process deviation resistance of the circuit; the discharge switching module dynamically adjusts the word line voltage of the copy unit, and the process deviation resistance of the circuit is further improved; the discharge switching module can detect constant discharge threshold voltage and improve the voltage tracking performance of the circuit.

Description

Wide voltage SRAM timing tracking circuit

Technical Field

The invention belongs to the technical field of special integrated circuit design, and particularly relates to a wide-voltage SRAM timing tracking circuit.

Background

With the advent of the mobile internet era, the market has placed ever higher demands on the processing power and endurance of mobile devices. An embedded Static Random Access Memory (SRAM) is one of mainstream memories of a mobile processor chip, and in order to achieve two design goals of high performance and low power consumption, a wide voltage SRAM design with a low to near threshold region is gradually becoming a research hotspot in the industry. The timing tracking circuit is one of the key modules of the embedded SRAM, and determines the performance and stability of the SRAM. However, the ever-decreasing operating voltages and ever-shrinking process nodes introduce significant process variation, making wide voltage SRAM timing tracking circuit designs a significant design challenge.

The wide voltage SRAM timing tracking circuit design has two problems: firstly, as the power supply voltage is reduced, the delay variation (SAE) caused by local process variation is increased sharply, and the read performance of the SRAM is deteriorated. Secondly, the design margins under different voltages are different, and the voltage tracking performance of the traditional copy bit line circuit is poor. A discharge switching type time sequence tracking technology suitable for a wide voltage SRAM and a circuit structure of a discharge switching module are provided in a broad voltage SRAM time sequence tracking circuit research and implementation thesis of 2018 of southeast university, the circuit adopts a bilateral symmetry structure, mutual influence between the level of a node m in a left circuit structure and the level of a node n in a right circuit structure is achieved, accordingly, cyclic turnover of internal signals in a periodic mode is achieved, and the process deviation resistance and the voltage tracking performance of the circuit are improved. However, the circuit structure of the discharge switching module is complex, and the enabling of the copy word line needs to be realized through mutual influence between node voltages, so that the risk of time delay caused by the process is also promoted. Therefore, it is necessary to design an SRAM timing tracking circuit with a simple and clear circuit structure and a discharge switching capability to improve the process deviation resistance and the voltage tracking performance of the circuit.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a wide-voltage SRAM (static random access memory) timing tracking circuit, which adopts a discharge switching module and a configurable SRAM timing logic module to realize discharge switching operation with timing tracking capability, effectively reduces the enabling delay variation of a sense amplifier SAE (sense amplifier enable) and improves the anti-process deviation capability of the circuit; the discharge switching module dynamically adjusts the word line voltage of the copy unit, and the process deviation resistance of the circuit is further improved; the discharge switching module can detect constant discharge threshold voltage and improve the voltage tracking performance of the circuit.

In order to solve the technical problems, the invention provides the following technical scheme:

the invention provides a wide voltage SRAM timing tracking circuit which is suitable for a copy bit line discharge circuit, wherein the copy bit line discharge circuit takes a first copy word line and a second copy word line as discharge control signals, so that the first copy bit line and the second copy bit line are discharged in turn through the copy bit line discharge circuit. The timing tracking circuit includes: the device comprises a discharge switching module and a configurable SRAM sequential logic module.

The discharging switching module takes a start signal, a first copy bit line and a second copy bit line as input signals, and takes a clock pulse, a first copy word line and a second copy word line as output signals.

The discharge switching module includes: the dynamic random access memory comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, a first NAND gate, a first dynamic circuit and a second dynamic circuit.

Furthermore, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all P-type MOS tubes, and the first NMOS tube, the second NMOS tube and the third NMOS tube are all N-type MOS tubes.

Further, the first nand gate is a two-input nand gate.

The source electrode of the first PMOS tube is connected with working voltage, the grid electrode of the first PMOS tube and the input end of the first phase inverter are both connected with a first pre-charge signal, and the drain electrode of the first PMOS tube and the grid electrode of the third PMOS tube are both connected with a first copy bit line; the source electrode of the second PMOS tube is connected with working voltage, the grid electrode of the second PMOS tube and the input end of the second phase inverter are both connected with a second pre-charge signal, and the drain electrode of the second PMOS tube and the grid electrode of the fourth PMOS tube are both connected with a second copy bit line; the source electrode of the third PMOS tube is connected with working voltage, and the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the third NMOS tube are connected to the same point; the source electrode of the fourth PMOS tube is connected with working voltage, and the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube and the input end of the third inverter are connected to the same point; a source electrode of the fifth PMOS tube and a source electrode of the sixth PMOS tube are both connected with working voltage, a grid electrode of the fifth PMOS tube is connected with the output end of the third phase inverter, a grid electrode of the sixth PMOS tube is connected with a start signal, and a drain electrode of the fifth PMOS tube, a drain electrode of the sixth PMOS tube and a drain electrode of the third NMOS tube are connected to a node A; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected with the output end of the second phase inverter, and the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is grounded; the first input end of the first NAND gate is connected with a start signal, the second input end of the first NAND gate, the input end of the sixth inverter and the output end of the seventh inverter are connected with a node A, and the output end of the first NAND gate, the input end of the fourth inverter and the output end of the fifth inverter are connected with a node B; the output end of the fourth inverter is connected with the first copy word line; the output end of the fifth inverter is connected with the first pre-charging signal; the output end of the sixth inverter is connected with the second copy word line; the output end of the seventh inverter is connected with the second pre-charging signal; the first input end of the first dynamic circuit and the first input end of the second dynamic circuit are both connected with a start signal, the second input end of the first dynamic circuit is connected with a node B, and the output end of the first dynamic circuit is connected with the source electrode of a PMOS tube in the fourth phase inverter; the second input end of the second dynamic circuit is connected with the node A, and the output end of the second dynamic circuit is connected with the source electrode of the PMOS tube in the sixth inverter; the first pre-charging signal is used as an output clock pulse of the discharging switching module after passing through the buffer.

When the sequential circuit does not start working, the starting signal is in a low level, the copy bit line discharging circuit is in a reset state, and the discharging switching module enables the first copy bit line and the second copy bit line to be charged to a high level. When the start signal is high, the discharge switching module first enables the first replica word line while making the second replica word line low, the first replica bit line is discharged, and then the second replica bit line is charged to high. When the first replica bit line is discharged, the discharge switching module makes the first replica word line become low level, and simultaneously enables the second replica word line, the second replica bit line is discharged, and then the first replica bit line is recharged to high level.

By means of the alternate cyclic discharging, the discharging switching module generates a periodic clock pulse, and the signal period of the clock pulse is the sum of the time delay of the first copy bit line and the second copy bit line which are discharged once respectively.

The configurable SRAM sequential logic module takes the clock pulse output by the discharge switching module as a clock signal of the sequential logic module, and outputs a sensitive amplifier signal and a word line signal. The configurable SRAM sequential logic module comprises: a single pulse generating circuit and a pulse shifting circuit. The single pulse generating circuit uses a clock pulse as a clock signal of the circuit, and the output signal is a pulse signal whose high-level pulse width coincides with the period of the clock pulse. The input signal of the pulse shift circuit is a pulse signal, and a sense amplifier signal and a word line signal are generated and output in a pure shift register mode.

The single pulse generating circuit includes: the first register, the second register, the eighth inverter and the first AND gate.

Further, the first and gate is a two-input and gate.

The data input end of the first register is connected with the working voltage, the data output end of the first register is connected with the data input end of the second register and the first input end of the first AND gate, and the clock pulse is the clock signal of the first register and the second register; the data output end of the second register is connected with the input end of the eighth inverter, the output end of the eighth inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate outputs a pulse signal.

The pulse shift circuit includes: the register comprises a configuration circuit, a register module, a first OR gate, a third register and a fourth register.

Further, the first or gate is a two input or gate.

The register module is composed of 32 registers connected in series. The pulse signal is an input signal of the register module, the clock pulse is a clock signal of the register module, the first output signal, the second output signal and the … … thirty-second output signal are output signals of the register module, and the output signals are input signals of the configuration circuit.

The configuration circuit is composed of transmission gates, selects any one of the first output signal, the second output signal and the … … thirty-second output signal as the configuration signal through the configuration signal, and is respectively input to the data input end of the third register and the first input end of the first OR gate through the configuration circuit. The clock pulse is the clock signal of the third register, and the output signal of the third register is the sense amplifier signal. The inverse signal of the word line signal is connected to the data input end of the fourth register, the second input end of the first OR gate is connected to the pulse signal, the output signal of the first OR gate is the clock signal of the fourth register, and the output signal of the fourth register is the word line signal.

The single pulse generating circuit generates a pulse signal with the same period as a clock pulse, and the pulse signal is input into the pulse shifting circuit, and the pulse shifting circuit generates a sensitive amplifier signal and a word line signal in a pure shift register mode. In the register module of the pulse shift circuit, because no additional combinational logic exists between the shift registers, the Setup timing violation does not occur. The configuration circuit selects the number of the shift registers in the register module to control the enabling time of the word line signal. The configuration circuit is composed of transmission gates, selects any one of the first output signal, the second output signal and the … … thirty-second output signal through the configuration signal and outputs the selected signal, wherein the output signal is the configuration signal. Therefore, when the number of the selected shift registers of the configuration circuit is M, the enabling time of the word line signal is M clock pulse periods, the sense amplifier signal is enabled within one clock pulse period after the word line signal is turned off, and the delay of the sense amplifier signal is 1 clock pulse period. By generating periodic clock pulses, the original asynchronous SRAM time sequence design is synchronized and digitized, various configurable pulse signals can be flexibly designed, the enabling time of each signal can be accurately controlled, and the problem of overlapping of control signals in the asynchronous SRAM time sequence design can be avoided.

The discharge switching module provided by the invention adopts the first dynamic circuit to dynamically reduce the word line voltage of the first copy unit, and adopts the second dynamic circuit to dynamically reduce the word line voltage of the second copy unit.

The first dynamic circuit has two input ends and one output end, the first input end is connected with the start signal, the second input end is connected with the input end of the fourth phase inverter, and the output end is connected with the source electrode of the P-type MOS tube in the fourth phase inverter.

The second dynamic circuit has two input ends and an output end, the first input end is connected with the start signal, the second input end is connected with the input end of the sixth phase inverter, and the output end is connected with the source electrode of the P-type MOS tube in the sixth phase inverter.

The first dynamic circuit and the second dynamic circuit have the same circuit configuration, and each dynamic circuit includes: the ninth inverter, the second NAND gate, the seventh PMOS tube, the eighth PMOS tube, the fourth NMOS tube, the first capacitor, the second capacitor and the third capacitor.

Furthermore, the seventh PMOS tube and the eighth PMOS tube are both P-type MOS tubes, and the fourth NMOS tube is an N-type MOS tube.

Further, the second nand gate is a two-input nand gate.

The source electrode of the seventh PMOS tube is connected with the working voltage, the drain electrode of the seventh PMOS tube is connected with the output end of the dynamic circuit, and the grid electrode of the seventh PMOS tube is connected with the output end of the ninth phase inverter; the source electrode of the eighth PMOS tube is connected with one end of the first capacitor and the drain electrode of the seventh PMOS tube, and the other end of the first capacitor is grounded; the drain electrode of the eighth PMOS tube is connected with one end of the second capacitor and the drain electrode of the fourth NMOS tube, and the other end of the second capacitor is grounded; the grid of the eighth PMOS tube and the grid of the fourth NMOS tube are connected with the output end of the second NAND gate; the source electrode of the fourth NMOS tube is grounded; the input end of the ninth inverter is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with a start signal; the second input end of the second NAND gate is the second input end of the dynamic circuit and is connected with the input end of the phase inverter which takes the copy word line as an output signal; one end of the third capacitor is connected with the output end of the inverter which takes the copy word line as an output signal, and the other end of the third capacitor is grounded.

Furthermore, the output end of the fourth inverter and one end of the third capacitor which are connected with the first dynamic circuit are both connected with the first copy word line.

Furthermore, the output end of the sixth inverter connected with the second dynamic circuit and one end of the third capacitor are both connected with the second copy word line.

When the starting signal is in a low level, the whole time sequence module is in a reset state, and the power supply voltage of a fourth inverter taking the first copy word line as an output signal and the power supply voltage of a sixth inverter taking the second copy word line as an output signal are both charged to the working power supply voltage; when the start signal is high, the timing module starts to operate.

The first dynamic circuit works specifically as follows: when the first copy word line is enabled, the first copy word line voltage is lower than the working power supply voltage; when the first copy word line is closed, the power supply voltage of the fourth inverter is charged to the working power supply voltage, and the whole timing module returns to the initial state.

The second dynamic circuit works specifically as follows: when the second copy word line is enabled, the second copy word line voltage is lower than the working power supply voltage; when the second copy word line is turned off, the power supply voltage of the sixth inverter is charged to the working power supply voltage, and the whole timing module returns to the initial state.

The discharge switching module provided by the invention is also provided with a first copy bit line constant discharge threshold voltage detection circuit and a second copy bit line constant discharge threshold voltage detection circuit.

Further, the first replica bit line constant discharge threshold voltage detection circuit includes: the PMOS transistor comprises a first PMOS transistor, a third PMOS transistor, a first NMOS transistor and a first phase inverter. When the first copy bit line and the first precharge signal are changed into high level, the first copy bit line starts to discharge, when the first copy bit line discharges to the threshold voltage of the third PMOS tube, the third PMOS tube is conducted, so that the drain electrode of the third PMOS tube is changed into high level, and the detection threshold value of the first copy bit line is the threshold voltage of the third PMOS tube.

Further, the second replica bit line constant discharge threshold voltage detection circuit includes: a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a second phase inverter. When the second copy bit line and the second precharge signal are changed to high level, the second copy bit line starts to discharge, and when the second copy bit line discharges to the threshold voltage of the fourth PMOS tube, the fourth PMOS tube is conducted, so that the drain electrode of the fourth PMOS tube is changed to high level, and the detection threshold value of the second copy bit line is the threshold voltage of the fourth PMOS tube.

Compared with the prior art, the wide voltage SRAM timing tracking circuit provided by the invention has the following benefits:

1. the wide-voltage SRAM timing tracking circuit provided by the invention has a discharge switching type timing tracking circuit structure, discharges through K copied discharge units, effectively reduces the delay variation of Sense Amplifier Enable (SAE), and improves the process deviation resistance of the circuit. At 0.6V TT25 ℃, when the K value is 32, the time delay change sigma of SAE is reduced to 0.55ns from 1.88ns of the traditional scheme, and the time delay change sigma is reduced by 70%.

2. A dynamic circuit is designed in the discharge switching module to dynamically adjust the word line voltage of the copy unit, so that the influence of an extra inverter delay chain is eliminated, and extra delay deviation is not introduced, thereby improving the process change resistance.

3. A constant discharge threshold voltage detection circuit is designed in the discharge switching module, so that discharge voltage differences under different voltages are basically consistent, design redundancy under high voltage is eliminated, and voltage tracking performance is improved.

Drawings

Fig. 1 is a schematic diagram of a wide voltage SRAM timing tracking circuit according to the present invention.

Fig. 2 is a schematic diagram of a discharge switching type operation process of a wide voltage SRAM timing tracking circuit according to the present invention.

Fig. 3 is a circuit structure diagram and an operation waveform diagram of a discharge switching module in the wide voltage SRAM timing tracking circuit according to the present invention.

FIG. 4 is a configurable SRAM sequential logic circuit diagram in the wide voltage SRAM sequential tracking circuit of the present invention.

FIG. 5 is a diagram showing a statistical distribution of SAE delay in a conventional scheme and a wide voltage SRAM timing tracking circuit according to the present invention.

Fig. 6 is a waveform diagram of the operation of the configurable SRAM sequential logic module circuit in the wide voltage SRAM sequential tracking circuit according to the present invention.

Fig. 7 is a schematic diagram of a circuit structure for dynamically reducing the word line voltage of the replica unit in the wide voltage SRAM timing tracking circuit according to the present invention.

FIG. 8 is a waveform diagram illustrating dynamic switching of the word line voltage of the replica cell in the wide voltage SRAM timing tracking circuit according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to examples.

The circuit structure of the discharge switching module, the configurable SRAM timing logic module and the Replica bit line discharge circuit is shown in FIG. 1, wherein the one-column Replica bit line discharge circuit comprises 2K Replica bit line discharge units (Replica cells, RC) and J-group redundancy units (Dummy cells, DC), each Replica bit line discharge unit RC is provided with two input ends and two output ends, a first input end is connected with a first Replica word line W L1, a second input end is connected with a second Replica word line W L, a first output end is connected with a first Replica bit line signal RB L1, and a second output end is connected with a second Replica bit line RB L.

As can be seen from fig. 1, the replica bit line discharge circuit takes the first replica word line W L1 and the second replica word line W L2 as discharge control signals, so that the first replica bit line RB L1 and the second replica bit line RB L2 are alternately discharged by the replica bit line discharge circuit.

In the preferred embodiment, the second input terminal of the 1 st to K-th replica bit line discharge cells RC is set to be connected to a low level, i.e., the second replica word line W L2 is connected to a low level, the first input terminal of the K +1 th to 2K-th replica bit line discharge cells RC is set to be connected to a low level, i.e., the first replica word line W L1 is connected to a low level, and the input word line signals of the remaining J groups of redundancy cells DC are all set to be constant at a low level.

The internal nodes of the replica discharge cells RC are connected to a high level, and a discharge channel of the first replica bit line RB L1 and a discharge channel of the second replica bit line RB L are not interfered with each other.

As shown in fig. 1, the discharging switching module takes a START signal START, a first replica bit line RB L1 and a second replica bit line RB L2 as input signals, and takes a clock pulse CK, a first replica word line W L1 and a second replica word line W L2 as output signals.

The operation steps of the discharge switching module are shown in fig. 2. when the timing circuit does not START operating, the START signal is low, the replica bit line discharge circuit is in a reset state, the discharge switching module causes both the first replica bit line RB L1 and the second replica bit line RB L to be charged to a high level, the replica bit line discharge circuit is in a reset state, and the START signal is low, the first step, when the START signal START is high, the discharge switching module first enables the first replica word line W L while the second replica word line W L is low, the first replica bit line RB L21 is discharged through the 1 st to K th replica bit line discharge cells RC while the second replica bit line RB L is charged to a high level, the discharge switching module causes the first replica word line W L to be low while enabling the second replica word line W L RB, the second replica bit line L RB 2 is discharged through the K +1 to 2K replica bit line RB L, the first replica bit line W L is discharged through the low level while the second replica bit line RB 4832 is enabled, the second replica bit line discharge unit RB L is discharged through the first replica bit line discharge pulse L, the discharge switching module is performed once again, and the discharge switching of the first replica bit line RB 24 is performed similarly to the fourth replica bit line discharge switching module.

Example 2. The circuit of the discharge switching model proposed by the present invention is shown on the left side of fig. 3.

The discharge switching module includes: the inverter comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMMOS tube P6, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a first inverter INV _1, a second inverter INV _2, a third inverter INV _3, a fourth inverter INV _4, a fifth inverter INV _5, a sixth inverter INV _6, a seventh inverter INV _7, a first NAND gate NAND _1, a first dynamic circuit and a second dynamic circuit.

Furthermore, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are all P-type MOS transistors, and the first NMOS transistor N1, the second NMOS transistor N2 and the third NMOS transistor N3 are all N-type MOS transistors.

Further, the first NAND gate NAND _1 is a two-input NAND gate.

The dynamic NAND-type dynamic PMOS transistor comprises a first PMOS transistor P, a second PMOS transistor P, a third PMOS transistor P, a fifth PMOS transistor P, a seventh PMOS, a seventh NMOS, a fifth PMOS, a seventh NMOS, a sixth NMOS, a seventh NMOS, a fifth PMOS, a sixth NMOS, a fifth PMOS, a sixth NMOS, a fifth NMOS, a sixth NMOS, a fifth NMOS, a sixth, a fifth NMOS, a sixth, a NMOS, a dynamic NAND, a fifth NMOS, a sixth, a fifth NMOS, a fifth NMOS, a sixth, a fifth, a dynamic NMOS, a fifth, a sixth, a fifth, a sixth, a fifth, a sixth, a fifth, a dynamic NMOS, a dynamic NAND, a fifth, a dynamic NMOS, a fifth, a sixth, a fifth, a dynamic NMOS, a sixth, a fifth, a dynamic NMOS, a dynamic NAND, a fifth, a dynamic NMOS, a dynamic NAND, a dynamic NMOS, a dynamic NAND, a dynamic NMOS, a dynamic NAND, a dynamic NMOS, a dynamic NAND, a dynamic inverter, a dynamic NAND, a dynamic NMOS, a dynamic inverter, a dynamic NMOS, a dynamic NAND.

First, when the replica bit line discharging circuit does not START operating, the START signal START is low, the replica bit line discharging circuit is in a reset state, and both the first replica bit line RB L1 and the second replica bit line RB L2 are charged to a high level, which includes the following specific processes:

when the START signal START is low, the node B is high, the first replica word line W L1 output from the fourth inverter INV _4 and the first precharge signal PRE1 output from the fifth inverter are low, the sixth PMOS transistor P6 is turned on, so that the node a is high, the second replica word line W L2 output from the sixth inverter INV _6 and the second precharge signal PRE2 output from the seventh inverter are also low, when the first precharge signal PRE1 and the second precharge signal PRE2 are both low, the first PMOS transistor P1 and the second PMOS transistor P2 are both turned on, and the first replica bit line L1 RB 1 and the second replica bit line RB L2 are both charged to high.

After the discharging switching module makes the first replica bit line RB L1 and the second replica bit line RB L2 both charge to a high level, when the START signal START is at a high level, the discharging switching module STARTs to operate, and the specific steps are as follows:

in step S1, the first replica word line W L1 is enabled, the first replica bit line RB L1 starts discharging, the first replica word line W L1 is turned off, and the first replica bit line RB L1 ends discharging:

the node a is high, the first copy word line W L1 output through the first NAND gate NAND _1 and the fourth inverter INV _4 is high, and the first copy bit line RB L1 discharges;

when the first replica bit line RB L1 discharges to the threshold voltage of the third PMOS transistor P3, the third PMOS transistor P3 is turned on, so that the drain of the third PMOS transistor P3 becomes high, the third NMOS transistor N3 is turned on, so that the node a becomes low, and the second replica word line W L2 is enabled;

meanwhile, the node a becomes low level so that the first replica word line W L1 is low level, the first replica bit line RB L1 ends discharging, and the first replica bit line RB L1 is recharged to high level.

In step S2, the second replica word line W L2 is enabled, the second replica bit line RB L2 starts discharging, the second replica word line W L2 is turned off, and the second replica bit line RB L2 ends discharging:

the second replica word line W L2 is high and the second replica bit line RB L2 discharges;

when the second replica bit line RB L2 discharges to the threshold voltage of the fourth PMOS transistor P4, the fourth PMOS transistor P4 is turned on, so that the drain of the fourth PMOS transistor P4 becomes high, at this time, the fifth PMOS transistor P5 is turned on, so that the node a becomes high, at this time, the first replica word line W L1 is enabled;

meanwhile, the node a becomes high so that the second replica word line W L2 is low, the second replica bit line RB L2 ends discharging, and the second replica bit line RB L2 is recharged to high.

Through the steps S1 and S2, the discharging rotation switching is realized, the discharging switching module generates a periodic clock pulse, and the signal period of the clock pulse CK is the sum of the time delays of the first replica bit line RB L1 and the second replica bit line RB L2 which are each discharged once.

It can be seen from the signal waveforms shown in fig. 3 that the discharge switching model achieves the control of pulling down and pulling UP the level of the node a by charging and discharging the first replica bit line RB L1 and the second replica bit line RB L2, i.e., the alternation of the a _ DN waveform and the a _ UP waveform in the figure, so that the internal signal cyclically flips in a periodic manner, by this way of alternately cyclically discharging, the discharge switching module generates a periodic clock pulse CK, and since the first replica bit line RB L1 and the second replica bit line RB L2 are both simultaneously discharged by the K replica discharge cells RC, the delay deviation of the discharge of the first replica bit line RB L1 and the discharge of the second replica bit line RB L2 is greatly reduced, and the signal period of the clock pulse CK is the sum of the delays of the discharges of the first replica bit line RB L1 and the second replica bit line RB L2, respectively, so the delay deviation of the clock pulse is also greatly reduced.

Embodiment 3. the circuit structure of the configurable SRAM sequential logic module according to the present invention is shown in fig. 4. the configurable SRAM sequential logic module uses the clock pulse CK output by the discharge switching module as the clock signal of the sequential logic module to output the sense amplifier signal SAE and the word line signal W L. the configurable SRAM sequential logic module includes a single pulse generating circuit and a pulse shifting circuit, the single pulse generating circuit uses the clock pulse CK as the clock signal of the circuit, the output signal is the pulse signal PU L SE, the high level pulse width of the pulse signal PU L SE is consistent with the period of the clock pulse CK, the input signal of the pulse shifting circuit is the pulse signal CK, and the sense amplifier signal SAE and the word line signal W L are generated and output by using a pure shift register.

The single pulse generating circuit includes: the first register R _1, the second register R _2, the eighth inverter INV _8, AND the first AND gate AND _ 1.

Further, the first AND gate AND _1 is a two-input AND gate.

The data input end D of the first register R _1 is connected with the working voltage, the data output end Q of the first register R _1 is connected with the data input end D of the second register R _2 AND the first input end of the first AND gate AND _1, the clock pulse CK is the clock signal of the first register R _1 AND the second register R _2, the data output end Q of the second register R _2 is connected with the input end of the eighth inverter INV _8, the output end of the eighth inverter INV _8 is connected with the second input end of the first AND gate AND _1, AND the output end of the first AND gate AND _1 outputs the pulse signal PU L SE.

The pulse shift circuit includes: the register comprises a configuration circuit, a register module, a first OR gate OR _1, a third register R _3 and a fourth register R _ 4.

Further, the first OR gate OR _1 is a two-input OR gate.

The pulse signal PU L SE is the input signal of the register module, the clock pulse CK is the clock signal of the register module, the first output signal Q1, the second output signal Q2, the … … thirty-second output signal Q32 are all the output signals of the register module, and the output signals are the input signals of the configuration circuit.

The configuration circuit is composed of transmission gates, any one of the first output signal Q1, the second output signal Q2, … … and the thirty-second output signal Q32 is selected as the configuration signal Conf _ out by the configuration signal, and is respectively input to the data input end D of the third register R _3 and the first input end of the first OR gate OR _1 by the configuration circuit, the clock pulse CK is a clock signal of the third register R _3, the output signal of the third register R _3 is a sense amplifier signal SAE, the inverted signal of the word line signal W L is connected to the data input end of the fourth register R _4, the second input end of the first OR gate OR _1 is a pulse signal, the output signal of the first OR gate OR _1 is a clock signal of the fourth register R _4, and the output signal of the fourth register R _4 is the word line signal W L.

The single pulse generating circuit generates a pulse signal PU L SE with high level pulse width same as clock pulse CK period, and inputs the pulse signal PU L SE into the pulse shift circuit, the pulse shift circuit adopts a pure shift register mode to generate a sense amplifier signal SAE and a word line signal W L. in a register module of the pulse shift circuit, due to no extra combination logic between the shift registers, a Setup timing violation does not occur, the configuration circuit selects the number of the shift registers in the register module to control the enabling time of the word line signal W L. the configuration circuit is composed of transmission gates, selects any one of a first output signal Q1, a second output signal Q2 and a thirty-second output signal Q32 of … … to output by configuration signals, the output signals are configuration signals Conf _ out, therefore, when the number of the shift registers selected by the configuration circuit is M, the enabling time of the word line signal W L is M clock pulse CK periods, the sense amplifier signal SAE is enabled within one clock pulse CK period after the W L is closed, the sense amplifier is configured as a clock pulse CK 1, the waveform of the SRAM is designed to avoid the asynchronous control of the asynchronous clock pulse signals, and the asynchronous control of the clock pulse CK signal is designed as shown in the asynchronous timing control circuit.

Example 4. The discharge switching module provided by the invention adopts the first dynamic circuit to dynamically reduce the word line voltage of the first copy unit, adopts the second dynamic circuit to dynamically reduce the word line voltage of the second copy unit, and has a structure shown in fig. 7.

The first dynamic circuit has two input ends and an output end, the first input end is connected with the START signal START, the second input end is connected with the input end of the fourth inverter INV _4, and the output end is connected with the source electrode of the PMOS tube in the fourth inverter INV _ 4.

The second dynamic circuit has two input ends and an output end, the first input end is connected with the START signal START, the second input end is connected with the input end of the sixth inverter INV _6, and the output end is connected with the source electrode of the PMOS tube in the sixth inverter INV _ 6.

The first dynamic circuit and the second dynamic circuit have the same circuit configuration, and each dynamic circuit includes: the third inverter INV _9, the second NAND gate NAND _2, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the fourth NMOS transistor N4, the first capacitor C1, the second capacitor C2, and the third capacitor C4.

Furthermore, the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are both PMOS transistors, and the fourth NMOS transistor N4 is an NMOS transistor.

Further, the second NAND gate NAND _2 is a two-input NAND gate.

The source electrode of the seventh PMOS tube P7 is connected with the working voltage, the drain electrode of the seventh PMOS tube P7 is connected with the output end of the dynamic circuit, and the grid electrode of the seventh PMOS tube P7 is connected with the output end of the ninth inverter INV _ 9; the source electrode of the eighth PMOS tube P8 is connected with one end of the first capacitor C1 and the drain electrode of the seventh PMOS tube P7, and the other end of the first capacitor C1 is grounded; the drain electrode of the eighth PMOS transistor P8 is connected to one end of the second capacitor C2 and the drain electrode of the fourth NMOS transistor N4, and the other end of the second capacitor C2 is grounded; the gate of the eighth PMOS transistor P8 and the gate of the fourth NMOS transistor N4 are connected to the output terminal of the second NAND gate NAND _ 2; the source electrode of the fourth NMOS transistor N4 is grounded; the input end of the ninth inverter INV _9 is connected to the output end of the second NAND gate NAND _ 2; the first input end of the second NAND gate NAND _2 is connected with a START signal START; the second input end of the second NAND gate NAND _2 is the second input end of the dynamic circuit and is connected with the input end of the inverter which takes the copy word line as an output signal; one end of the third capacitor C3 is connected to the output end of the inverter which uses the copy word line as the output signal, and the other end of the third capacitor C3 is connected to the ground.

Further, an output end of the fourth inverter INV _4 and one end of the third capacitor C3, which are connected to the first dynamic circuit, are both connected to the first replica word line W L1;

further, an output end of the sixth inverter INV _6 and one end of the third capacitor C3, which are connected to the second dynamic circuit, are both connected to the second replica word line W L2.

When the START signal START is low, the whole timing module is in a reset state, the power supply voltage of the fourth inverter INV _4 using the first replica word line W L1 as an output signal and the sixth inverter INV _6 using the second replica word line W L2 as an output signal is charged to high, the first capacitor C1 is charged, the second capacitor C2 is discharged through the fourth NMOS transistor N4, and when the START signal START is high, the timing module STARTs to operate.

Taking the first dynamic circuit as an example, the operation of the dynamic circuit is specifically described, when the first replica word line W L is enabled, the input W L B1 of the fourth inverter INV _4 is at a low level, the output of the second NAND gate NAND _2 is at a high level and turns off the seventh PMOS transistor P7, while the eighth PMOS transistor P8 is turned on and the fourth nmos transistor N4 is turned off, at this time, since no charge is stored on the second capacitor C2 and the third capacitor C3, charge sharing is performed among the first capacitor C1, the second capacitor C2 and the third capacitor C3, so that the supply voltage of the fourth inverter INV _4 is lower than the operating supply voltage, so that the voltage of the first replica word line W L is lower than the operating supply voltage, when the first replica word line W L is at a low level, the input W L B2 of the fourth inverter INV _4 is at a high level, the output of the second NAND gate NAND 2 is at a low level and turns on the seventh replica word line W7, so that the entire operating voltage of the fourth inverter INV _4 and the entire PMOS transistor P638 are charged back to the initial time sequence, and the entire time sequence of the charge back to the entire PMOS transistor C638.

The second dynamic circuit operates as the first dynamic circuit.

FIG. 8 is a waveform diagram illustrating the dynamic switching of the word line voltage of the replica cell by the discharge switching module according to the present invention, the discharge switching circuit enables the first replica word line W L and the second replica word line W L2 to be alternately enabled, when the first replica word line W L is enabled, the supply voltage of the fourth inverter is dynamically decreased, and at the same time, the supply voltage of the sixth inverter is charged to the operating power voltage, whereas, when the second replica word line W L2 is enabled, the supply voltage of the sixth inverter is dynamically decreased, and at the same time, the supply voltage of the fourth inverter is charged to the operating power voltage, so that, no matter whether the first replica word line W L is enabled or the second replica word line W L is enabled, the word line voltage is dynamically decreased from 600mV to 520mV, the dynamic decrease principle of the first replica word line W L voltage and the second replica word line W L voltage is charge sharing, that the word line voltage is dynamically decreased from 600mV to 520mV, to 520, to 3, which may be adjusted according to the magnitude of the first capacitor C1, and the word line voltage of the second replica word line C5392, thus the word line voltage may be adjusted according to the magnitude of the first capacitor C1.

Embodiment 5. the conventional circuit is connected with the replica bit lines by inverters, and the difference between the discharge voltage of the replica bit line at a high voltage and the discharge voltage of the replica bit line at a low voltage is deviated because the number of discharge cells needs to be changed to reduce the deviation, therefore, the discharge switching module provided by the invention can realize the constant discharge threshold voltage detection of the first replica bit line RB L1 and the constant discharge threshold voltage detection of the second replica bit line RB L2, so that the difference between the discharge voltage of the first replica bit line RB L1 and the discharge voltage of the second replica bit line RB L2 is kept constant under the condition of voltage change.

The first replica bit line constant discharge threshold voltage detection circuit comprises a first PMOS tube P1, a third PMOS tube P3, a first NMOS tube N1 and a first inverter INV _1, wherein when the first replica bit line RB L1 and a first precharge signal PRE1 become high level, the first replica bit line RB L1 starts to discharge, when the first replica bit line RB L1 discharges to the threshold voltage of the third PMOS tube P3, the third PMOS tube P3 is conducted, so that the drain of the third PMOS tube P3 becomes high level, the discharge voltage difference of the first replica bit line RB L1 is the threshold voltage of the third PMOS tube P3, and the discharge voltage difference of the first replica bit line RB L1 is constant because the threshold voltage of the third PMOS tube P3 basically does not change along with the voltage change.

The second replica bit line constant discharge threshold voltage detection circuit comprises a second PMOS pipe P2, a fourth PMOS pipe P4, a second NMOS pipe N2 and a second inverter INV _2, when the second replica bit line RB L2 and a second precharge signal PRE2 become high level, the second replica bit line RB L2 starts to discharge, when the second replica bit line RB L2 discharges to the threshold voltage of the fourth PMOS pipe P4, the fourth PMOS pipe P4 is conducted, so that the drain of the fourth PMOS pipe P4 becomes high level, the discharge voltage difference of the second replica bit line RB L2 is the threshold voltage of the fourth PMOS pipe P4, and the discharge voltage difference of the second replica bit line RB L2 is constant because the threshold voltage of the fourth PMOS pipe P4 basically does not change along with the voltage change.

Therefore, when the voltage changes, the structure of the discharge circuit and the number of discharge units in the discharge circuit do not need to be changed, the discharge voltage difference under the high voltage is basically consistent with the discharge voltage difference under the low voltage, the design redundancy under the high voltage is eliminated, and the voltage tracking performance is improved.

The above embodiments and examples are specific supports for the technical idea of the wide voltage SRAM timing tracking circuit proposed by the present invention, and the protection scope of the present invention cannot be limited thereby, and any equivalent changes or equivalent changes made on the basis of the technical scheme according to the technical idea proposed by the present invention still belong to the protection scope of the technical scheme of the present invention.

Claims

1. A wide voltage SRAM timing tracking circuit adapted to a replica bit line discharge circuit that uses a first replica word line and a second replica word line as discharge control signals to cause the first replica bit line and the second replica bit line to be alternately discharged by the replica bit line discharge circuit, the wide voltage SRAM timing tracking circuit comprising: the device comprises a discharge switching module and a configurable SRAM sequential logic module;

the discharging switching module takes a starting signal, a first copy bit line and a second copy bit line as input signals, and takes a clock pulse, a first copy word line and a second copy word line as output signals; the configurable SRAM sequential logic module takes the clock pulse output by the discharge switching module as a clock signal and takes a sensitive amplifier signal and a word line signal as output signals;

the discharge switching module includes: the dynamic transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, a first NAND gate, a first dynamic circuit and a second dynamic circuit;

furthermore, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all P-type MOS tubes, and the first NMOS tube, the second NMOS tube and the third NMOS tube are all N-type MOS tubes;

further, the first nand gate is a two-input nand gate;

2. The wide voltage SRAM timing tracking circuit of claim 1,

when the start signal is at a low level, the discharge switching module enables the first copy bit line and the second copy bit line to be charged to a high level, specifically as follows;

when the starting signal is at a low level, the node B is at a high level, the first replica word line output by the fourth inverter and the first precharge signal output by the fifth inverter are at a low level, the sixth PMOS tube is conducted, so that the node A is at a high level, and the second replica word line output by the sixth inverter and the second precharge signal output by the seventh inverter are also at a low level; when the first pre-charge signal and the second pre-charge signal are both low level, the first PMOS transistor and the second PMOS transistor are both conducted, and the first copy bit line and the second copy bit line are both charged to high level.

3. The wide voltage SRAM timing tracking circuit of claim 1,

after the first replica bit line and the second replica bit line are charged to a high level by the discharging switching module, when a start signal is at a high level, the discharging switching module starts to work, and the specific steps are as follows:

in step S1, the first replica word line is enabled, the first replica bit line starts to discharge, the first replica word line is turned off, and the first replica bit line ends to discharge:

the node A is high level, the first copy word line output by the first NAND gate and the fourth inverter is high level, and the first copy bit line discharges;

when the first copy bit line discharges to the threshold voltage of the third PMOS tube, the third PMOS tube is conducted, so that the drain electrode of the third PMOS tube becomes high level, the third NMOS tube is conducted at the moment, so that the node A becomes low level, and the second copy word line is enabled at the moment;

at the same time, the node a becomes low so that the first replica word line is low, the first replica bit line ends discharging, and the first replica bit line is recharged to high;

in step S2, the second replica word line is enabled, the second replica bit line starts to discharge, the second replica word line is closed, and the second replica bit line ends to discharge:

the second copy word line is at high level, and the second copy bit line is discharged;

when the second copy bit line discharges to the threshold voltage of the fourth PMOS tube, the fourth PMOS tube is conducted, so that the drain electrode of the fourth PMOS tube becomes high level, the fifth PMOS tube is conducted at the moment, so that the node A becomes high level, and the first copy word line is enabled at the moment;

at the same time, the node a becomes high so that the second replica word line is low, the second replica bit line ends discharging, and the second replica bit line is recharged to high;

4. The wide voltage SRAM timing tracking circuit of claim 1, wherein the configurable SRAM timing logic module comprises: a single pulse generating circuit and a pulse shifting circuit;

the single-pulse generating circuit takes the clock pulse output by the discharge switching module as a clock signal of the circuit, takes the pulse signal as an output signal, and the high-level pulse width of the pulse signal is consistent with the period of the clock pulse;

the single pulse generating circuit includes: the first register, the second register, the eighth inverter and the first AND gate; the data input end of the first register is connected with the working voltage, the data output end of the first register is connected with the data input end of the second register and the first input end of the first AND gate, and the clock pulse is the clock signal of the first register and the second register; the data output end of the second register is connected with the input end of an eighth inverter, the output end of the eighth inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate outputs a pulse signal;

further, the first and gate is a two-input and gate;

the input signal of the pulse shift circuit is a pulse signal, and a sense amplifier signal and a word line signal are generated and output in a pure shift register mode;

the pulse shift circuit includes: the circuit comprises a configuration circuit, a register module, a first OR gate, a third register and a fourth register; the register module consists of 32 registers connected in series; the pulse signal is an input signal of the register module, the clock pulse is a clock signal of the register module, the first output signal, the second output signal and the … … thirty-second output signal are output signals of the register module, and the output signals are used as input signals of the configuration circuit;

further, the first or gate is a two-input or gate;

the configuration circuit is composed of transmission gates, any one of a first output signal, a second output signal and an … … thirty-second output signal is selected as a configuration signal through the configuration signal, and the configuration signal is respectively input to a data input end of the third register and a first input end of the first OR gate; the clock pulse is a clock signal of the third register, and an output signal of the third register is a sensitive amplifier signal; the inverted signal of the word line signal is connected to the input end of the fourth register, the second input end of the first OR gate is connected with the pulse signal, the output signal of the first OR gate is the clock signal of the fourth register, and the output signal of the fourth register is the word line signal.

5. The wide voltage SRAM timing tracking circuit of claim 1,

the first dynamic circuit is provided with two input ends and an output end, the first input end is connected with a start signal, the second input end is connected with the input end of the fourth phase inverter, and the output end is connected with the source electrode of a PMOS tube in the fourth phase inverter;

the second dynamic circuit is provided with two input ends and an output end, the first input end is connected with a start signal, the second input end is connected with the input end of the sixth phase inverter, and the output end is connected with the source electrode of a PMOS tube in the sixth phase inverter;

the first dynamic circuit and the second dynamic circuit have the same circuit configuration, and each dynamic circuit includes: the ninth inverter, the second NAND gate, the seventh PMOS tube, the eighth PMOS tube, the fourth NMOS tube, the first capacitor, the second capacitor and the third capacitor;

further, the second nand gate is a two-input nand gate;

the source electrode of the seventh PMOS tube is connected with the working voltage, the drain electrode of the seventh PMOS tube is connected with the output end of the dynamic circuit, and the grid electrode of the seventh PMOS tube is connected with the output end of the ninth phase inverter; the source electrode of the eighth PMOS tube is connected with one end of the first capacitor and the drain electrode of the seventh PMOS tube, and the other end of the first capacitor is grounded; the drain electrode of the eighth PMOS tube is connected with one end of the second capacitor and the drain electrode of the fourth NMOS tube, and the other end of the second capacitor is grounded; the grid of the eighth PMOS tube and the grid of the fourth NMOS tube are connected with the output end of the second NAND gate; the source electrode of the fourth NMOS tube is grounded; the input end of the ninth inverter is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with a start signal; the second input end of the second NAND gate is the second input end of the dynamic circuit and is connected with the input end of the phase inverter which takes the copy word line as an output signal; one end of the third capacitor is connected with the output end of the inverter which takes the copy word line as an output signal, and the other end of the third capacitor is grounded;

furthermore, the output end of a fourth inverter connected with the first dynamic circuit and one end of a third capacitor are both connected with the first copy word line;

6. The wide voltage SRAM timing tracking circuit of any one of claims 1 or 5,

the first dynamic circuit dynamically reduces the first copy word line voltage, and the second dynamic circuit dynamically reduces the second copy word line voltage;

when the starting signal is at a low level, the whole time sequence module is in a reset state, and the power supply voltage of the inverter taking the copy word line as the output signal is charged to the working power supply voltage; when the starting signal is at a high level, the time sequence module starts to work;

the first dynamic circuit works specifically as follows: when the first copy word line is enabled, the first copy word line voltage is lower than the working power supply voltage; when the first copy word line is closed, the power supply voltage of the fourth inverter is charged to the working power supply voltage, and the whole time sequence module returns to the initial state;

7. The wide voltage SRAM timing tracking circuit of claim 1 wherein the discharge switching module has a first replica bit line constant discharge threshold voltage detection circuit comprising: the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a third PMOS transistor, a first NMOS (N-channel metal oxide semiconductor) transistor and a first phase inverter;

when the first copy bit line and the first pre-charge signal are changed into high level, the first copy bit line starts to discharge, when the first copy bit line discharges to the threshold voltage of the third PMOS tube, the third PMOS tube is conducted, so that the drain electrode of the third PMOS tube is changed into high level, and the detection threshold value of the first copy bit line is the threshold voltage of the third PMOS tube; at this time, the discharging voltage difference of the first copy bit line is the threshold voltage of the third PMOS tube.

8. The wide voltage SRAM timing tracking circuit of claim 1,

the discharge switching module has a second replica bit line constant discharge threshold voltage detection circuit comprising: the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the second phase inverter;

when the second copy bit line and the second precharge signal are changed into high levels, the second copy bit line starts to discharge, and when the second copy bit line discharges to the threshold voltage of the fourth PMOS tube, the fourth PMOS tube is conducted, so that the drain electrode of the fourth PMOS tube is changed into high levels, and the detection threshold value of the second copy bit line is the threshold voltage of the fourth PMOS tube; at this time, the discharging voltage difference of the second copy bit line is the threshold voltage of the fourth PMOS tube.